arch/x86/kernel/cpu/microcode/amd_early.c

   1 /*
   2  * Copyright (C) 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Author: Jacob Shin <jacob.shin@amd.com>
   5  * Fixes: Borislav Petkov <bp@suse.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/earlycpio.h>
  13 #include <linux/initrd.h>
  14
  15 #include <asm/cpu.h>
  16 #include <asm/setup.h>
  17 #include <asm/microcode_amd.h>
  18
  19 /*
  20  * This points to the current valid container of microcode patches which we will
  21  * save from the initrd before jettisoning its contents.
  22  */
  23 static u8 *container;
  24 static size_t container_size;
  25
  26 static u32 ucode_new_rev;
  27 u8 amd_ucode_patch[PATCH_MAX_SIZE];
  28 static u16 this_equiv_id;
  29
  30 static struct cpio_data ucode_cpio;
  31
  32 /*
  33  * Microcode patch container file is prepended to the initrd in cpio format.
  34  * See Documentation/x86/early-microcode.txt
  35  */
  36 static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
  37
  38 static struct cpio_data __init find_ucode_in_initrd(void)
  39 {
  40         long offset = 0;
  41         char *path;
  42         void *start;
  43         size_t size;
  44
  45 #ifdef CONFIG_X86_32
  46         struct boot_params *p;
  47
  48         /*
  49          * On 32-bit, early load occurs before paging is turned on so we need
  50          * to use physical addresses.
  51          */
  52         p       = (struct boot_params *)__pa_nodebug(&boot_params);
  53         path    = (char *)__pa_nodebug(ucode_path);
  54         start   = (void *)p->hdr.ramdisk_image;
  55         size    = p->hdr.ramdisk_size;
  56 #else
  57         path    = ucode_path;
  58         start   = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
  59         size    = boot_params.hdr.ramdisk_size;
  60 #endif
  61
  62         return find_cpio_data(path, start, size, &offset);
  63 }
  64
  65 static size_t compute_container_size(u8 *data, u32 total_size)
  66 {
  67         size_t size = 0;
  68         u32 *header = (u32 *)data;
  69
  70         if (header[0] != UCODE_MAGIC ||
  71             header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
  72             header[2] == 0)                            /* size */
  73                 return size;
  74
  75         size = header[2] + CONTAINER_HDR_SZ;
  76         total_size -= size;
  77         data += size;
  78
  79         while (total_size) {
  80                 u16 patch_size;
  81
  82                 header = (u32 *)data;
  83
  84                 if (header[0] != UCODE_UCODE_TYPE)
  85                         break;
  86
  87                 /*
  88                  * Sanity-check patch size.
  89                  */
  90                 patch_size = header[1];
  91                 if (patch_size > PATCH_MAX_SIZE)
  92                         break;
  93
  94                 size       += patch_size + SECTION_HDR_SIZE;
  95                 data       += patch_size + SECTION_HDR_SIZE;
  96                 total_size -= patch_size + SECTION_HDR_SIZE;
  97         }
  98
  99         return size;
 100 }
 101
 102 /*
 103  * Early load occurs before we can vmalloc(). So we look for the microcode
 104  * patch container file in initrd, traverse equivalent cpu table, look for a
 105  * matching microcode patch, and update, all in initrd memory in place.
 106  * When vmalloc() is available for use later -- on 64-bit during first AP load,
 107  * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
 108  * load_microcode_amd() to save equivalent cpu table and microcode patches in
 109  * kernel heap memory.
 110  */
 111 static void apply_ucode_in_initrd(void *ucode, size_t size, bool save_patch)
 112 {
 113         struct equiv_cpu_entry *eq;
 114         size_t *cont_sz;
 115         u32 *header;
 116         u8  *data, **cont;
 117         u8 (*patch)[PATCH_MAX_SIZE];
 118         u16 eq_id = 0;
 119         int offset, left;
 120         u32 rev, eax, ebx, ecx, edx;
 121         u32 *new_rev;
 122
 123 #ifdef CONFIG_X86_32
 124         new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
 125         cont_sz = (size_t *)__pa_nodebug(&container_size);
 126         cont    = (u8 **)__pa_nodebug(&container);
 127         patch   = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
 128 #else
 129         new_rev = &ucode_new_rev;
 130         cont_sz = &container_size;
 131         cont    = &container;
 132         patch   = &amd_ucode_patch;
 133 #endif
 134
 135         data   = ucode;
 136         left   = size;
 137         header = (u32 *)data;
 138
 139         /* find equiv cpu table */
 140         if (header[0] != UCODE_MAGIC ||
 141             header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
 142             header[2] == 0)                            /* size */
 143                 return;
 144
 145         eax = 0x00000001;
 146         ecx = 0;
 147         native_cpuid(&eax, &ebx, &ecx, &edx);
 148
 149         while (left > 0) {
 150                 eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
 151
 152                 *cont = data;
 153
 154                 /* Advance past the container header */
 155                 offset = header[2] + CONTAINER_HDR_SZ;
 156                 data  += offset;
 157                 left  -= offset;
 158
 159                 eq_id = find_equiv_id(eq, eax);
 160                 if (eq_id) {
 161                         this_equiv_id = eq_id;
 162                         *cont_sz = compute_container_size(*cont, left + offset);
 163
 164                         /*
 165                          * truncate how much we need to iterate over in the
 166                          * ucode update loop below
 167                          */
 168                         left = *cont_sz - offset;
 169                         break;
 170                 }
 171
 172                 /*
 173                  * support multiple container files appended together. if this
 174                  * one does not have a matching equivalent cpu entry, we fast
 175                  * forward to the next container file.
 176                  */
 177                 while (left > 0) {
 178                         header = (u32 *)data;
 179                         if (header[0] == UCODE_MAGIC &&
 180                             header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
 181                                 break;
 182
 183                         offset = header[1] + SECTION_HDR_SIZE;
 184                         data  += offset;
 185                         left  -= offset;
 186                 }
 187
 188                 /* mark where the next microcode container file starts */
 189                 offset    = data - (u8 *)ucode;
 190                 ucode     = data;
 191         }
 192
 193         if (!eq_id) {
 194                 *cont = NULL;
 195                 *cont_sz = 0;
 196                 return;
 197         }
 198
 199         if (check_current_patch_level(&rev, true))
 200                 return;
 201
 202         while (left > 0) {
 203                 struct microcode_amd *mc;
 204
 205                 header = (u32 *)data;
 206                 if (header[0] != UCODE_UCODE_TYPE || /* type */
 207                     header[1] == 0)                  /* size */
 208                         break;
 209
 210                 mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
 211
 212                 if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id) {
 213
 214                         if (!__apply_microcode_amd(mc)) {
 215                                 rev = mc->hdr.patch_id;
 216                                 *new_rev = rev;
 217
 218                                 if (save_patch)
 219                                         memcpy(patch, mc,
 220                                                min_t(u32, header[1], PATCH_MAX_SIZE));
 221                         }
 222                 }
 223
 224                 offset  = header[1] + SECTION_HDR_SIZE;
 225                 data   += offset;
 226                 left   -= offset;
 227         }
 228 }
 229
 230 static bool __init load_builtin_amd_microcode(struct cpio_data *cp,
 231                                               unsigned int family)
 232 {
 233 #ifdef CONFIG_X86_64
 234         char fw_name[36] = "amd-ucode/microcode_amd.bin";
 235
 236         if (family >= 0x15)
 237                 snprintf(fw_name, sizeof(fw_name),
 238                          "amd-ucode/microcode_amd_fam%.2xh.bin", family);
 239
 240         return get_builtin_firmware(cp, fw_name);
 241 #else
 242         return false;
 243 #endif
 244 }
 245
 246 void __init load_ucode_amd_bsp(unsigned int family)
 247 {
 248         struct cpio_data cp;
 249         void **data;
 250         size_t *size;
 251
 252 #ifdef CONFIG_X86_32
 253         data =  (void **)__pa_nodebug(&ucode_cpio.data);
 254         size = (size_t *)__pa_nodebug(&ucode_cpio.size);
 255 #else
 256         data = &ucode_cpio.data;
 257         size = &ucode_cpio.size;
 258 #endif
 259
 260         cp = find_ucode_in_initrd();
 261         if (!cp.data) {
 262                 if (!load_builtin_amd_microcode(&cp, family))
 263                         return;
 264         }
 265
 266         *data = cp.data;
 267         *size = cp.size;
 268
 269         apply_ucode_in_initrd(cp.data, cp.size, true);
 270 }
 271
 272 #ifdef CONFIG_X86_32
 273 /*
 274  * On 32-bit, since AP's early load occurs before paging is turned on, we
 275  * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
 276  * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
 277  * save_microcode_in_initrd_amd() BSP's patch is copied to amd_ucode_patch,
 278  * which is used upon resume from suspend.
 279  */
 280 void load_ucode_amd_ap(void)
 281 {
 282         struct microcode_amd *mc;
 283         size_t *usize;
 284         void **ucode;
 285
 286         mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
 287         if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
 288                 __apply_microcode_amd(mc);
 289                 return;
 290         }
 291
 292         ucode = (void *)__pa_nodebug(&container);
 293         usize = (size_t *)__pa_nodebug(&container_size);
 294
 295         if (!*ucode || !*usize)
 296                 return;
 297
 298         apply_ucode_in_initrd(*ucode, *usize, false);
 299 }
 300
 301 static void __init collect_cpu_sig_on_bsp(void *arg)
 302 {
 303         unsigned int cpu = smp_processor_id();
 304         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
 305
 306         uci->cpu_sig.sig = cpuid_eax(0x00000001);
 307 }
 308
 309 static void __init get_bsp_sig(void)
 310 {
 311         unsigned int bsp = boot_cpu_data.cpu_index;
 312         struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
 313
 314         if (!uci->cpu_sig.sig)
 315                 smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
 316 }
 317 #else
 318 void load_ucode_amd_ap(void)
 319 {
 320         unsigned int cpu = smp_processor_id();
 321         struct equiv_cpu_entry *eq;
 322         struct microcode_amd *mc;
 323         u32 rev, eax;
 324         u16 eq_id;
 325
 326         /* Exit if called on the BSP. */
 327         if (!cpu)
 328                 return;
 329
 330         if (!container)
 331                 return;
 332
 333         /*
 334          * 64-bit runs with paging enabled, thus early==false.
 335          */
 336         if (check_current_patch_level(&rev, false))
 337                 return;
 338
 339         eax = cpuid_eax(0x00000001);
 340         eq  = (struct equiv_cpu_entry *)(container + CONTAINER_HDR_SZ);
 341
 342         eq_id = find_equiv_id(eq, eax);
 343         if (!eq_id)
 344                 return;
 345
 346         if (eq_id == this_equiv_id) {
 347                 mc = (struct microcode_amd *)amd_ucode_patch;
 348
 349                 if (mc && rev < mc->hdr.patch_id) {
 350                         if (!__apply_microcode_amd(mc))
 351                                 ucode_new_rev = mc->hdr.patch_id;
 352                 }
 353
 354         } else {
 355                 if (!ucode_cpio.data)
 356                         return;
 357
 358                 /*
 359                  * AP has a different equivalence ID than BSP, looks like
 360                  * mixed-steppings silicon so go through the ucode blob anew.
 361                  */
 362                 apply_ucode_in_initrd(ucode_cpio.data, ucode_cpio.size, false);
 363         }
 364 }
 365 #endif
 366
 367 int __init save_microcode_in_initrd_amd(void)
 368 {
 369         unsigned long cont;
 370         int retval = 0;
 371         enum ucode_state ret;
 372         u8 *cont_va;
 373         u32 eax;
 374
 375         if (!container)
 376                 return -EINVAL;
 377
 378 #ifdef CONFIG_X86_32
 379         get_bsp_sig();
 380         cont    = (unsigned long)container;
 381         cont_va = __va(container);
 382 #else
 383         /*
 384          * We need the physical address of the container for both bitness since
 385          * boot_params.hdr.ramdisk_image is a physical address.
 386          */
 387         cont    = __pa(container);
 388         cont_va = container;
 389 #endif
 390
 391         /*
 392          * Take into account the fact that the ramdisk might get relocated and
 393          * therefore we need to recompute the container's position in virtual
 394          * memory space.
 395          */
 396         if (relocated_ramdisk)
 397                 container = (u8 *)(__va(relocated_ramdisk) +
 398                              (cont - boot_params.hdr.ramdisk_image));
 399         else
 400                 container = cont_va;
 401
 402         if (ucode_new_rev)
 403                 pr_info("microcode: updated early to new patch_level=0x%08x\n",
 404                         ucode_new_rev);
 405
 406         eax   = cpuid_eax(0x00000001);
 407         eax   = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
 408
 409         ret = load_microcode_amd(smp_processor_id(), eax, container, container_size);
 410         if (ret != UCODE_OK)
 411                 retval = -EINVAL;
 412
 413         /*
 414          * This will be freed any msec now, stash patches for the current
 415          * family and switch to patch cache for cpu hotplug, etc later.
 416          */
 417         container = NULL;
 418         container_size = 0;
 419
 420         return retval;
 421 }
 422
 423 void reload_ucode_amd(void)
 424 {
 425         struct microcode_amd *mc;
 426         u32 rev;
 427
 428         /*
 429          * early==false because this is a syscore ->resume path and by
 430          * that time paging is long enabled.
 431          */
 432         if (check_current_patch_level(&rev, false))
 433                 return;
 434
 435         mc = (struct microcode_amd *)amd_ucode_patch;
 436
 437         if (mc && rev < mc->hdr.patch_id) {
 438                 if (!__apply_microcode_amd(mc)) {
 439                         ucode_new_rev = mc->hdr.patch_id;
 440                         pr_info("microcode: reload patch_level=0x%08x\n",
 441                                 ucode_new_rev);
 442                 }
 443         }
 444 }