arch/x86/kernel/cpu/mtrr/generic.c

   1 /*
   2  * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
   3  * because MTRRs can span up to 40 bits (36bits on most modern x86)
   4  */
   5 #define DEBUG
   6
   7 #include <linux/module.h>
   8 #include <linux/init.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11
  12 #include <asm/processor-flags.h>
  13 #include <asm/cpufeature.h>
  14 #include <asm/tlbflush.h>
  15 #include <asm/mtrr.h>
  16 #include <asm/msr.h>
  17 #include <asm/pat.h>
  18
  19 #include "mtrr.h"
  20
  21 struct fixed_range_block {
  22         int base_msr;           /* start address of an MTRR block */
  23         int ranges;             /* number of MTRRs in this block  */
  24 };
  25
  26 static struct fixed_range_block fixed_range_blocks[] = {
  27         { MSR_MTRRfix64K_00000, 1 }, /* one   64k MTRR  */
  28         { MSR_MTRRfix16K_80000, 2 }, /* two   16k MTRRs */
  29         { MSR_MTRRfix4K_C0000,  8 }, /* eight  4k MTRRs */
  30         {}
  31 };
  32
  33 static unsigned long smp_changes_mask;
  34 static int mtrr_state_set;
  35 u64 mtrr_tom2;
  36
  37 struct mtrr_state_type mtrr_state;
  38 EXPORT_SYMBOL_GPL(mtrr_state);
  39
  40 /*
  41  * BIOS is expected to clear MtrrFixDramModEn bit, see for example
  42  * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
  43  * Opteron Processors" (26094 Rev. 3.30 February 2006), section
  44  * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
  45  * to 1 during BIOS initalization of the fixed MTRRs, then cleared to
  46  * 0 for operation."
  47  */
  48 static inline void k8_check_syscfg_dram_mod_en(void)
  49 {
  50         u32 lo, hi;
  51
  52         if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
  53               (boot_cpu_data.x86 >= 0x0f)))
  54                 return;
  55
  56         rdmsr(MSR_K8_SYSCFG, lo, hi);
  57         if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
  58                 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
  59                        " not cleared by BIOS, clearing this bit\n",
  60                        smp_processor_id());
  61                 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
  62                 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
  63         }
  64 }
  65
  66 /* Get the size of contiguous MTRR range */
  67 static u64 get_mtrr_size(u64 mask)
  68 {
  69         u64 size;
  70
  71         mask >>= PAGE_SHIFT;
  72         mask |= size_or_mask;
  73         size = -mask;
  74         size <<= PAGE_SHIFT;
  75         return size;
  76 }
  77
  78 /*
  79  * Check and return the effective type for MTRR-MTRR type overlap.
  80  * Returns 1 if the effective type is UNCACHEABLE, else returns 0
  81  */
  82 static int check_type_overlap(u8 *prev, u8 *curr)
  83 {
  84         if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) {
  85                 *prev = MTRR_TYPE_UNCACHABLE;
  86                 *curr = MTRR_TYPE_UNCACHABLE;
  87                 return 1;
  88         }
  89
  90         if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) ||
  91             (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) {
  92                 *prev = MTRR_TYPE_WRTHROUGH;
  93                 *curr = MTRR_TYPE_WRTHROUGH;
  94         }
  95
  96         if (*prev != *curr) {
  97                 *prev = MTRR_TYPE_UNCACHABLE;
  98                 *curr = MTRR_TYPE_UNCACHABLE;
  99                 return 1;
 100         }
 101
 102         return 0;
 103 }
 104
 105 /*
 106  * Error/Semi-error returns:
 107  * 0xFF - when MTRR is not enabled
 108  * *repeat == 1 implies [start:end] spanned across MTRR range and type returned
 109  *              corresponds only to [start:*partial_end].
 110  *              Caller has to lookup again for [*partial_end:end].
 111  */
 112 static u8 __mtrr_type_lookup(u64 start, u64 end, u64 *partial_end, int *repeat)
 113 {
 114         int i;
 115         u64 base, mask;
 116         u8 prev_match, curr_match;
 117
 118         *repeat = 0;
 119         if (!mtrr_state_set)
 120                 return 0xFF;
 121
 122         if (!(mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED))
 123                 return 0xFF;
 124
 125         /* Make end inclusive end, instead of exclusive */
 126         end--;
 127
 128         /* Look in fixed ranges. Just return the type as per start */
 129         if ((start < 0x100000) &&
 130             (mtrr_state.have_fixed) &&
 131             (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) {
 132                 int idx;
 133
 134                 if (start < 0x80000) {
 135                         idx = 0;
 136                         idx += (start >> 16);
 137                         return mtrr_state.fixed_ranges[idx];
 138                 } else if (start < 0xC0000) {
 139                         idx = 1 * 8;
 140                         idx += ((start - 0x80000) >> 14);
 141                         return mtrr_state.fixed_ranges[idx];
 142                 } else {
 143                         idx = 3 * 8;
 144                         idx += ((start - 0xC0000) >> 12);
 145                         return mtrr_state.fixed_ranges[idx];
 146                 }
 147         }
 148
 149         /*
 150          * Look in variable ranges
 151          * Look of multiple ranges matching this address and pick type
 152          * as per MTRR precedence
 153          */
 154         prev_match = 0xFF;
 155         for (i = 0; i < num_var_ranges; ++i) {
 156                 unsigned short start_state, end_state, inclusive;
 157
 158                 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
 159                         continue;
 160
 161                 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
 162                        (mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
 163                 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
 164                        (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
 165
 166                 start_state = ((start & mask) == (base & mask));
 167                 end_state = ((end & mask) == (base & mask));
 168                 inclusive = ((start < base) && (end > base));
 169
 170                 if ((start_state != end_state) || inclusive) {
 171                         /*
 172                          * We have start:end spanning across an MTRR.
 173                          * We split the region into either
 174                          *
 175                          * - start_state:1
 176                          * (start:mtrr_end)(mtrr_end:end)
 177                          * - end_state:1
 178                          * (start:mtrr_start)(mtrr_start:end)
 179                          * - inclusive:1
 180                          * (start:mtrr_start)(mtrr_start:mtrr_end)(mtrr_end:end)
 181                          *
 182                          * depending on kind of overlap.
 183                          *
 184                          * Return the type of the first region and a pointer
 185                          * to the start of next region so that caller will be
 186                          * advised to lookup again after having adjusted start
 187                          * and end.
 188                          *
 189                          * Note: This way we handle multiple overlaps as well.
 190                          */
 191                         if (start_state)
 192                                 *partial_end = base + get_mtrr_size(mask);
 193                         else
 194                                 *partial_end = base;
 195
 196                         if (unlikely(*partial_end <= start)) {
 197                                 WARN_ON(1);
 198                                 *partial_end = start + PAGE_SIZE;
 199                         }
 200
 201                         end = *partial_end - 1; /* end is inclusive */
 202                         *repeat = 1;
 203                 }
 204
 205                 if ((start & mask) != (base & mask))
 206                         continue;
 207
 208                 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
 209                 if (prev_match == 0xFF) {
 210                         prev_match = curr_match;
 211                         continue;
 212                 }
 213
 214                 if (check_type_overlap(&prev_match, &curr_match))
 215                         return curr_match;
 216         }
 217
 218         if (mtrr_tom2) {
 219                 if (start >= (1ULL<<32) && (end < mtrr_tom2))
 220                         return MTRR_TYPE_WRBACK;
 221         }
 222
 223         if (prev_match != 0xFF)
 224                 return prev_match;
 225
 226         return mtrr_state.def_type;
 227 }
 228
 229 /*
 230  * Returns the effective MTRR type for the region
 231  * Error return:
 232  * 0xFF - when MTRR is not enabled
 233  */
 234 u8 mtrr_type_lookup(u64 start, u64 end)
 235 {
 236         u8 type, prev_type;
 237         int repeat;
 238         u64 partial_end;
 239
 240         type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
 241
 242         /*
 243          * Common path is with repeat = 0.
 244          * However, we can have cases where [start:end] spans across some
 245          * MTRR range. Do repeated lookups for that case here.
 246          */
 247         while (repeat) {
 248                 prev_type = type;
 249                 start = partial_end;
 250                 type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
 251
 252                 if (check_type_overlap(&prev_type, &type))
 253                         return type;
 254         }
 255
 256         return type;
 257 }
 258
 259 /* Get the MSR pair relating to a var range */
 260 static void
 261 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
 262 {
 263         rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 264         rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 265 }
 266
 267 /* Fill the MSR pair relating to a var range */
 268 void fill_mtrr_var_range(unsigned int index,
 269                 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
 270 {
 271         struct mtrr_var_range *vr;
 272
 273         vr = mtrr_state.var_ranges;
 274
 275         vr[index].base_lo = base_lo;
 276         vr[index].base_hi = base_hi;
 277         vr[index].mask_lo = mask_lo;
 278         vr[index].mask_hi = mask_hi;
 279 }
 280
 281 static void get_fixed_ranges(mtrr_type *frs)
 282 {
 283         unsigned int *p = (unsigned int *)frs;
 284         int i;
 285
 286         k8_check_syscfg_dram_mod_en();
 287
 288         rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
 289
 290         for (i = 0; i < 2; i++)
 291                 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
 292         for (i = 0; i < 8; i++)
 293                 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
 294 }
 295
 296 void mtrr_save_fixed_ranges(void *info)
 297 {
 298         if (cpu_has_mtrr)
 299                 get_fixed_ranges(mtrr_state.fixed_ranges);
 300 }
 301
 302 static unsigned __initdata last_fixed_start;
 303 static unsigned __initdata last_fixed_end;
 304 static mtrr_type __initdata last_fixed_type;
 305
 306 static void __init print_fixed_last(void)
 307 {
 308         if (!last_fixed_end)
 309                 return;
 310
 311         pr_debug("  %05X-%05X %s\n", last_fixed_start,
 312                  last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
 313
 314         last_fixed_end = 0;
 315 }
 316
 317 static void __init update_fixed_last(unsigned base, unsigned end,
 318                                      mtrr_type type)
 319 {
 320         last_fixed_start = base;
 321         last_fixed_end = end;
 322         last_fixed_type = type;
 323 }
 324
 325 static void __init
 326 print_fixed(unsigned base, unsigned step, const mtrr_type *types)
 327 {
 328         unsigned i;
 329
 330         for (i = 0; i < 8; ++i, ++types, base += step) {
 331                 if (last_fixed_end == 0) {
 332                         update_fixed_last(base, base + step, *types);
 333                         continue;
 334                 }
 335                 if (last_fixed_end == base && last_fixed_type == *types) {
 336                         last_fixed_end = base + step;
 337                         continue;
 338                 }
 339                 /* new segments: gap or different type */
 340                 print_fixed_last();
 341                 update_fixed_last(base, base + step, *types);
 342         }
 343 }
 344
 345 static void prepare_set(void);
 346 static void post_set(void);
 347
 348 static void __init print_mtrr_state(void)
 349 {
 350         unsigned int i;
 351         int high_width;
 352
 353         pr_debug("MTRR default type: %s\n",
 354                  mtrr_attrib_to_str(mtrr_state.def_type));
 355         if (mtrr_state.have_fixed) {
 356                 pr_debug("MTRR fixed ranges %sabled:\n",
 357                         ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) &&
 358                          (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ?
 359                          "en" : "dis");
 360                 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
 361                 for (i = 0; i < 2; ++i)
 362                         print_fixed(0x80000 + i * 0x20000, 0x04000,
 363                                     mtrr_state.fixed_ranges + (i + 1) * 8);
 364                 for (i = 0; i < 8; ++i)
 365                         print_fixed(0xC0000 + i * 0x08000, 0x01000,
 366                                     mtrr_state.fixed_ranges + (i + 3) * 8);
 367
 368                 /* tail */
 369                 print_fixed_last();
 370         }
 371         pr_debug("MTRR variable ranges %sabled:\n",
 372                  mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis");
 373         high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4;
 374
 375         for (i = 0; i < num_var_ranges; ++i) {
 376                 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
 377                         pr_debug("  %u base %0*X%05X000 mask %0*X%05X000 %s\n",
 378                                  i,
 379                                  high_width,
 380                                  mtrr_state.var_ranges[i].base_hi,
 381                                  mtrr_state.var_ranges[i].base_lo >> 12,
 382                                  high_width,
 383                                  mtrr_state.var_ranges[i].mask_hi,
 384                                  mtrr_state.var_ranges[i].mask_lo >> 12,
 385                                  mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
 386                 else
 387                         pr_debug("  %u disabled\n", i);
 388         }
 389         if (mtrr_tom2)
 390                 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
 391 }
 392
 393 /* Grab all of the MTRR state for this CPU into *state */
 394 void __init get_mtrr_state(void)
 395 {
 396         struct mtrr_var_range *vrs;
 397         unsigned long flags;
 398         unsigned lo, dummy;
 399         unsigned int i;
 400
 401         vrs = mtrr_state.var_ranges;
 402
 403         rdmsr(MSR_MTRRcap, lo, dummy);
 404         mtrr_state.have_fixed = (lo >> 8) & 1;
 405
 406         for (i = 0; i < num_var_ranges; i++)
 407                 get_mtrr_var_range(i, &vrs[i]);
 408         if (mtrr_state.have_fixed)
 409                 get_fixed_ranges(mtrr_state.fixed_ranges);
 410
 411         rdmsr(MSR_MTRRdefType, lo, dummy);
 412         mtrr_state.def_type = (lo & 0xff);
 413         mtrr_state.enabled = (lo & 0xc00) >> 10;
 414
 415         if (amd_special_default_mtrr()) {
 416                 unsigned low, high;
 417
 418                 /* TOP_MEM2 */
 419                 rdmsr(MSR_K8_TOP_MEM2, low, high);
 420                 mtrr_tom2 = high;
 421                 mtrr_tom2 <<= 32;
 422                 mtrr_tom2 |= low;
 423                 mtrr_tom2 &= 0xffffff800000ULL;
 424         }
 425
 426         print_mtrr_state();
 427
 428         mtrr_state_set = 1;
 429
 430         /* PAT setup for BP. We need to go through sync steps here */
 431         local_irq_save(flags);
 432         prepare_set();
 433
 434         pat_init();
 435
 436         post_set();
 437         local_irq_restore(flags);
 438 }
 439
 440 /* Some BIOS's are messed up and don't set all MTRRs the same! */
 441 void __init mtrr_state_warn(void)
 442 {
 443         unsigned long mask = smp_changes_mask;
 444
 445         if (!mask)
 446                 return;
 447         if (mask & MTRR_CHANGE_MASK_FIXED)
 448                 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
 449         if (mask & MTRR_CHANGE_MASK_VARIABLE)
 450                 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
 451         if (mask & MTRR_CHANGE_MASK_DEFTYPE)
 452                 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
 453
 454         printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
 455         printk(KERN_INFO "mtrr: corrected configuration.\n");
 456 }
 457
 458 /*
 459  * Doesn't attempt to pass an error out to MTRR users
 460  * because it's quite complicated in some cases and probably not
 461  * worth it because the best error handling is to ignore it.
 462  */
 463 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
 464 {
 465         if (wrmsr_safe(msr, a, b) < 0) {
 466                 printk(KERN_ERR
 467                         "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
 468                         smp_processor_id(), msr, a, b);
 469         }
 470 }
 471
 472 /**
 473  * set_fixed_range - checks & updates a fixed-range MTRR if it
 474  *                   differs from the value it should have
 475  * @msr: MSR address of the MTTR which should be checked and updated
 476  * @changed: pointer which indicates whether the MTRR needed to be changed
 477  * @msrwords: pointer to the MSR values which the MSR should have
 478  */
 479 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
 480 {
 481         unsigned lo, hi;
 482
 483         rdmsr(msr, lo, hi);
 484
 485         if (lo != msrwords[0] || hi != msrwords[1]) {
 486                 mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
 487                 *changed = true;
 488         }
 489 }
 490
 491 /**
 492  * generic_get_free_region - Get a free MTRR.
 493  * @base: The starting (base) address of the region.
 494  * @size: The size (in bytes) of the region.
 495  * @replace_reg: mtrr index to be replaced; set to invalid value if none.
 496  *
 497  * Returns: The index of the region on success, else negative on error.
 498  */
 499 int
 500 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
 501 {
 502         unsigned long lbase, lsize;
 503         mtrr_type ltype;
 504         int i, max;
 505
 506         max = num_var_ranges;
 507         if (replace_reg >= 0 && replace_reg < max)
 508                 return replace_reg;
 509
 510         for (i = 0; i < max; ++i) {
 511                 mtrr_if->get(i, &lbase, &lsize, &ltype);
 512                 if (lsize == 0)
 513                         return i;
 514         }
 515
 516         return -ENOSPC;
 517 }
 518
 519 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
 520                              unsigned long *size, mtrr_type *type)
 521 {
 522         u32 mask_lo, mask_hi, base_lo, base_hi;
 523         unsigned int hi;
 524         u64 tmp, mask;
 525
 526         /*
 527          * get_mtrr doesn't need to update mtrr_state, also it could be called
 528          * from any cpu, so try to print it out directly.
 529          */
 530         get_cpu();
 531
 532         rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
 533
 534         if ((mask_lo & 0x800) == 0) {
 535                 /*  Invalid (i.e. free) range */
 536                 *base = 0;
 537                 *size = 0;
 538                 *type = 0;
 539                 goto out_put_cpu;
 540         }
 541
 542         rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
 543
 544         /* Work out the shifted address mask: */
 545         tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
 546         mask = size_or_mask | tmp;
 547
 548         /* Expand tmp with high bits to all 1s: */
 549         hi = fls64(tmp);
 550         if (hi > 0) {
 551                 tmp |= ~((1ULL<<(hi - 1)) - 1);
 552
 553                 if (tmp != mask) {
 554                         printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
 555                         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
 556                         mask = tmp;
 557                 }
 558         }
 559
 560         /*
 561          * This works correctly if size is a power of two, i.e. a
 562          * contiguous range:
 563          */
 564         *size = -mask;
 565         *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
 566         *type = base_lo & 0xff;
 567
 568 out_put_cpu:
 569         put_cpu();
 570 }
 571
 572 /**
 573  * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
 574  *                    differ from the saved set
 575  * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
 576  */
 577 static int set_fixed_ranges(mtrr_type *frs)
 578 {
 579         unsigned long long *saved = (unsigned long long *)frs;
 580         bool changed = false;
 581         int block = -1, range;
 582
 583         k8_check_syscfg_dram_mod_en();
 584
 585         while (fixed_range_blocks[++block].ranges) {
 586                 for (range = 0; range < fixed_range_blocks[block].ranges; range++)
 587                         set_fixed_range(fixed_range_blocks[block].base_msr + range,
 588                                         &changed, (unsigned int *)saved++);
 589         }
 590
 591         return changed;
 592 }
 593
 594 /*
 595  * Set the MSR pair relating to a var range.
 596  * Returns true if changes are made.
 597  */
 598 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
 599 {
 600         unsigned int lo, hi;
 601         bool changed = false;
 602
 603         rdmsr(MTRRphysBase_MSR(index), lo, hi);
 604         if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
 605             || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
 606                 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
 607
 608                 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 609                 changed = true;
 610         }
 611
 612         rdmsr(MTRRphysMask_MSR(index), lo, hi);
 613
 614         if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
 615             || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
 616                 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
 617                 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 618                 changed = true;
 619         }
 620         return changed;
 621 }
 622
 623 static u32 deftype_lo, deftype_hi;
 624
 625 /**
 626  * set_mtrr_state - Set the MTRR state for this CPU.
 627  *
 628  * NOTE: The CPU must already be in a safe state for MTRR changes.
 629  * RETURNS: 0 if no changes made, else a mask indicating what was changed.
 630  */
 631 static unsigned long set_mtrr_state(void)
 632 {
 633         unsigned long change_mask = 0;
 634         unsigned int i;
 635
 636         for (i = 0; i < num_var_ranges; i++) {
 637                 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
 638                         change_mask |= MTRR_CHANGE_MASK_VARIABLE;
 639         }
 640
 641         if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
 642                 change_mask |= MTRR_CHANGE_MASK_FIXED;
 643
 644         /*
 645          * Set_mtrr_restore restores the old value of MTRRdefType,
 646          * so to set it we fiddle with the saved value:
 647          */
 648         if ((deftype_lo & 0xff) != mtrr_state.def_type
 649             || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
 650
 651                 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
 652                              (mtrr_state.enabled << 10);
 653                 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
 654         }
 655
 656         return change_mask;
 657 }
 658
 659
 660 static unsigned long cr4;
 661 static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
 662
 663 /*
 664  * Since we are disabling the cache don't allow any interrupts,
 665  * they would run extremely slow and would only increase the pain.
 666  *
 667  * The caller must ensure that local interrupts are disabled and
 668  * are reenabled after post_set() has been called.
 669  */
 670 static void prepare_set(void) __acquires(set_atomicity_lock)
 671 {
 672         unsigned long cr0;
 673
 674         /*
 675          * Note that this is not ideal
 676          * since the cache is only flushed/disabled for this CPU while the
 677          * MTRRs are changed, but changing this requires more invasive
 678          * changes to the way the kernel boots
 679          */
 680
 681         raw_spin_lock(&set_atomicity_lock);
 682
 683         /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
 684         cr0 = read_cr0() | X86_CR0_CD;
 685         write_cr0(cr0);
 686         wbinvd();
 687
 688         /* Save value of CR4 and clear Page Global Enable (bit 7) */
 689         if (cpu_has_pge) {
 690                 cr4 = __read_cr4();
 691                 __write_cr4(cr4 & ~X86_CR4_PGE);
 692         }
 693
 694         /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
 695         count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
 696         __flush_tlb();
 697
 698         /* Save MTRR state */
 699         rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 700
 701         /* Disable MTRRs, and set the default type to uncached */
 702         mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
 703         wbinvd();
 704 }
 705
 706 static void post_set(void) __releases(set_atomicity_lock)
 707 {
 708         /* Flush TLBs (no need to flush caches - they are disabled) */
 709         count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
 710         __flush_tlb();
 711
 712         /* Intel (P6) standard MTRRs */
 713         mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 714
 715         /* Enable caches */
 716         write_cr0(read_cr0() & ~X86_CR0_CD);
 717
 718         /* Restore value of CR4 */
 719         if (cpu_has_pge)
 720                 __write_cr4(cr4);
 721         raw_spin_unlock(&set_atomicity_lock);
 722 }
 723
 724 static void generic_set_all(void)
 725 {
 726         unsigned long mask, count;
 727         unsigned long flags;
 728
 729         local_irq_save(flags);
 730         prepare_set();
 731
 732         /* Actually set the state */
 733         mask = set_mtrr_state();
 734
 735         /* also set PAT */
 736         pat_init();
 737
 738         post_set();
 739         local_irq_restore(flags);
 740
 741         /* Use the atomic bitops to update the global mask */
 742         for (count = 0; count < sizeof mask * 8; ++count) {
 743                 if (mask & 0x01)
 744                         set_bit(count, &smp_changes_mask);
 745                 mask >>= 1;
 746         }
 747
 748 }
 749
 750 /**
 751  * generic_set_mtrr - set variable MTRR register on the local CPU.
 752  *
 753  * @reg: The register to set.
 754  * @base: The base address of the region.
 755  * @size: The size of the region. If this is 0 the region is disabled.
 756  * @type: The type of the region.
 757  *
 758  * Returns nothing.
 759  */
 760 static void generic_set_mtrr(unsigned int reg, unsigned long base,
 761                              unsigned long size, mtrr_type type)
 762 {
 763         unsigned long flags;
 764         struct mtrr_var_range *vr;
 765
 766         vr = &mtrr_state.var_ranges[reg];
 767
 768         local_irq_save(flags);
 769         prepare_set();
 770
 771         if (size == 0) {
 772                 /*
 773                  * The invalid bit is kept in the mask, so we simply
 774                  * clear the relevant mask register to disable a range.
 775                  */
 776                 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
 777                 memset(vr, 0, sizeof(struct mtrr_var_range));
 778         } else {
 779                 vr->base_lo = base << PAGE_SHIFT | type;
 780                 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
 781                 vr->mask_lo = -size << PAGE_SHIFT | 0x800;
 782                 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
 783
 784                 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
 785                 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
 786         }
 787
 788         post_set();
 789         local_irq_restore(flags);
 790 }
 791
 792 int generic_validate_add_page(unsigned long base, unsigned long size,
 793                               unsigned int type)
 794 {
 795         unsigned long lbase, last;
 796
 797         /*
 798          * For Intel PPro stepping <= 7
 799          * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
 800          */
 801         if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
 802             boot_cpu_data.x86_model == 1 &&
 803             boot_cpu_data.x86_mask <= 7) {
 804                 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
 805                         pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
 806                         return -EINVAL;
 807                 }
 808                 if (!(base + size < 0x70000 || base > 0x7003F) &&
 809                     (type == MTRR_TYPE_WRCOMB
 810                      || type == MTRR_TYPE_WRBACK)) {
 811                         pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
 812                         return -EINVAL;
 813                 }
 814         }
 815
 816         /*
 817          * Check upper bits of base and last are equal and lower bits are 0
 818          * for base and 1 for last
 819          */
 820         last = base + size - 1;
 821         for (lbase = base; !(lbase & 1) && (last & 1);
 822              lbase = lbase >> 1, last = last >> 1)
 823                 ;
 824         if (lbase != last) {
 825                 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
 826                 return -EINVAL;
 827         }
 828         return 0;
 829 }
 830
 831 static int generic_have_wrcomb(void)
 832 {
 833         unsigned long config, dummy;
 834         rdmsr(MSR_MTRRcap, config, dummy);
 835         return config & (1 << 10);
 836 }
 837
 838 int positive_have_wrcomb(void)
 839 {
 840         return 1;
 841 }
 842
 843 /*
 844  * Generic structure...
 845  */
 846 const struct mtrr_ops generic_mtrr_ops = {
 847         .use_intel_if           = 1,
 848         .set_all                = generic_set_all,
 849         .get                    = generic_get_mtrr,
 850         .get_free_region        = generic_get_free_region,
 851         .set                    = generic_set_mtrr,
 852         .validate_add_page      = generic_validate_add_page,
 853         .have_wrcomb            = generic_have_wrcomb,
 854 };