arch/x86/kernel/cpu/mtrr/generic.c

   1 /*
   2  * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
   3  * because MTRRs can span up to 40 bits (36bits on most modern x86)
   4  */
   5 #define DEBUG
   6
   7 #include <linux/module.h>
   8 #include <linux/init.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11
  12 #include <asm/processor-flags.h>
  13 #include <asm/cpufeature.h>
  14 #include <asm/tlbflush.h>
  15 #include <asm/mtrr.h>
  16 #include <asm/msr.h>
  17 #include <asm/pat.h>
  18
  19 #include "mtrr.h"
  20
  21 struct fixed_range_block {
  22         int base_msr;           /* start address of an MTRR block */
  23         int ranges;             /* number of MTRRs in this block  */
  24 };
  25
  26 static struct fixed_range_block fixed_range_blocks[] = {
  27         { MSR_MTRRfix64K_00000, 1 }, /* one   64k MTRR  */
  28         { MSR_MTRRfix16K_80000, 2 }, /* two   16k MTRRs */
  29         { MSR_MTRRfix4K_C0000,  8 }, /* eight  4k MTRRs */
  30         {}
  31 };
  32
  33 static unsigned long smp_changes_mask;
  34 static int mtrr_state_set;
  35 u64 mtrr_tom2;
  36
  37 struct mtrr_state_type mtrr_state;
  38 EXPORT_SYMBOL_GPL(mtrr_state);
  39
  40 /*
  41  * BIOS is expected to clear MtrrFixDramModEn bit, see for example
  42  * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
  43  * Opteron Processors" (26094 Rev. 3.30 February 2006), section
  44  * "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
  45  * to 1 during BIOS initalization of the fixed MTRRs, then cleared to
  46  * 0 for operation."
  47  */
  48 static inline void k8_check_syscfg_dram_mod_en(void)
  49 {
  50         u32 lo, hi;
  51
  52         if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
  53               (boot_cpu_data.x86 >= 0x0f)))
  54                 return;
  55
  56         rdmsr(MSR_K8_SYSCFG, lo, hi);
  57         if (lo & K8_MTRRFIXRANGE_DRAM_MODIFY) {
  58                 printk(KERN_ERR FW_WARN "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
  59                        " not cleared by BIOS, clearing this bit\n",
  60                        smp_processor_id());
  61                 lo &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
  62                 mtrr_wrmsr(MSR_K8_SYSCFG, lo, hi);
  63         }
  64 }
  65
  66 /* Get the size of contiguous MTRR range */
  67 static u64 get_mtrr_size(u64 mask)
  68 {
  69         u64 size;
  70
  71         mask >>= PAGE_SHIFT;
  72         mask |= size_or_mask;
  73         size = -mask;
  74         size <<= PAGE_SHIFT;
  75         return size;
  76 }
  77
  78 /*
  79  * Check and return the effective type for MTRR-MTRR type overlap.
  80  * Returns 1 if the effective type is UNCACHEABLE, else returns 0
  81  */
  82 static int check_type_overlap(u8 *prev, u8 *curr)
  83 {
  84         if (*prev == MTRR_TYPE_UNCACHABLE || *curr == MTRR_TYPE_UNCACHABLE) {
  85                 *prev = MTRR_TYPE_UNCACHABLE;
  86                 *curr = MTRR_TYPE_UNCACHABLE;
  87                 return 1;
  88         }
  89
  90         if ((*prev == MTRR_TYPE_WRBACK && *curr == MTRR_TYPE_WRTHROUGH) ||
  91             (*prev == MTRR_TYPE_WRTHROUGH && *curr == MTRR_TYPE_WRBACK)) {
  92                 *prev = MTRR_TYPE_WRTHROUGH;
  93                 *curr = MTRR_TYPE_WRTHROUGH;
  94         }
  95
  96         if (*prev != *curr) {
  97                 *prev = MTRR_TYPE_UNCACHABLE;
  98                 *curr = MTRR_TYPE_UNCACHABLE;
  99                 return 1;
 100         }
 101
 102         return 0;
 103 }
 104
 105 /*
 106  * Error/Semi-error returns:
 107  * 0xFF - when MTRR is not enabled
 108  * *repeat == 1 implies [start:end] spanned across MTRR range and type returned
 109  *              corresponds only to [start:*partial_end].
 110  *              Caller has to lookup again for [*partial_end:end].
 111  */
 112 static u8 __mtrr_type_lookup(u64 start, u64 end, u64 *partial_end, int *repeat)
 113 {
 114         int i;
 115         u64 base, mask;
 116         u8 prev_match, curr_match;
 117
 118         *repeat = 0;
 119         if (!mtrr_state_set)
 120                 return 0xFF;
 121
 122         if (!mtrr_state.enabled)
 123                 return 0xFF;
 124
 125         /* Make end inclusive end, instead of exclusive */
 126         end--;
 127
 128         /* Look in fixed ranges. Just return the type as per start */
 129         if (mtrr_state.have_fixed && (start < 0x100000)) {
 130                 int idx;
 131
 132                 if (start < 0x80000) {
 133                         idx = 0;
 134                         idx += (start >> 16);
 135                         return mtrr_state.fixed_ranges[idx];
 136                 } else if (start < 0xC0000) {
 137                         idx = 1 * 8;
 138                         idx += ((start - 0x80000) >> 14);
 139                         return mtrr_state.fixed_ranges[idx];
 140                 } else if (start < 0x1000000) {
 141                         idx = 3 * 8;
 142                         idx += ((start - 0xC0000) >> 12);
 143                         return mtrr_state.fixed_ranges[idx];
 144                 }
 145         }
 146
 147         /*
 148          * Look in variable ranges
 149          * Look of multiple ranges matching this address and pick type
 150          * as per MTRR precedence
 151          */
 152         if (!(mtrr_state.enabled & 2))
 153                 return mtrr_state.def_type;
 154
 155         prev_match = 0xFF;
 156         for (i = 0; i < num_var_ranges; ++i) {
 157                 unsigned short start_state, end_state;
 158
 159                 if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
 160                         continue;
 161
 162                 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
 163                        (mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
 164                 mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
 165                        (mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
 166
 167                 start_state = ((start & mask) == (base & mask));
 168                 end_state = ((end & mask) == (base & mask));
 169
 170                 if (start_state != end_state) {
 171                         /*
 172                          * We have start:end spanning across an MTRR.
 173                          * We split the region into
 174                          * either
 175                          * (start:mtrr_end) (mtrr_end:end)
 176                          * or
 177                          * (start:mtrr_start) (mtrr_start:end)
 178                          * depending on kind of overlap.
 179                          * Return the type for first region and a pointer to
 180                          * the start of second region so that caller will
 181                          * lookup again on the second region.
 182                          * Note: This way we handle multiple overlaps as well.
 183                          */
 184                         if (start_state)
 185                                 *partial_end = base + get_mtrr_size(mask);
 186                         else
 187                                 *partial_end = base;
 188
 189                         if (unlikely(*partial_end <= start)) {
 190                                 WARN_ON(1);
 191                                 *partial_end = start + PAGE_SIZE;
 192                         }
 193
 194                         end = *partial_end - 1; /* end is inclusive */
 195                         *repeat = 1;
 196                 }
 197
 198                 if ((start & mask) != (base & mask))
 199                         continue;
 200
 201                 curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
 202                 if (prev_match == 0xFF) {
 203                         prev_match = curr_match;
 204                         continue;
 205                 }
 206
 207                 if (check_type_overlap(&prev_match, &curr_match))
 208                         return curr_match;
 209         }
 210
 211         if (mtrr_tom2) {
 212                 if (start >= (1ULL<<32) && (end < mtrr_tom2))
 213                         return MTRR_TYPE_WRBACK;
 214         }
 215
 216         if (prev_match != 0xFF)
 217                 return prev_match;
 218
 219         return mtrr_state.def_type;
 220 }
 221
 222 /*
 223  * Returns the effective MTRR type for the region
 224  * Error return:
 225  * 0xFF - when MTRR is not enabled
 226  */
 227 u8 mtrr_type_lookup(u64 start, u64 end)
 228 {
 229         u8 type, prev_type;
 230         int repeat;
 231         u64 partial_end;
 232
 233         type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
 234
 235         /*
 236          * Common path is with repeat = 0.
 237          * However, we can have cases where [start:end] spans across some
 238          * MTRR range. Do repeated lookups for that case here.
 239          */
 240         while (repeat) {
 241                 prev_type = type;
 242                 start = partial_end;
 243                 type = __mtrr_type_lookup(start, end, &partial_end, &repeat);
 244
 245                 if (check_type_overlap(&prev_type, &type))
 246                         return type;
 247         }
 248
 249         return type;
 250 }
 251
 252 /* Get the MSR pair relating to a var range */
 253 static void
 254 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
 255 {
 256         rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 257         rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 258 }
 259
 260 /* Fill the MSR pair relating to a var range */
 261 void fill_mtrr_var_range(unsigned int index,
 262                 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
 263 {
 264         struct mtrr_var_range *vr;
 265
 266         vr = mtrr_state.var_ranges;
 267
 268         vr[index].base_lo = base_lo;
 269         vr[index].base_hi = base_hi;
 270         vr[index].mask_lo = mask_lo;
 271         vr[index].mask_hi = mask_hi;
 272 }
 273
 274 static void get_fixed_ranges(mtrr_type *frs)
 275 {
 276         unsigned int *p = (unsigned int *)frs;
 277         int i;
 278
 279         k8_check_syscfg_dram_mod_en();
 280
 281         rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]);
 282
 283         for (i = 0; i < 2; i++)
 284                 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]);
 285         for (i = 0; i < 8; i++)
 286                 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]);
 287 }
 288
 289 void mtrr_save_fixed_ranges(void *info)
 290 {
 291         if (cpu_has_mtrr)
 292                 get_fixed_ranges(mtrr_state.fixed_ranges);
 293 }
 294
 295 static unsigned __initdata last_fixed_start;
 296 static unsigned __initdata last_fixed_end;
 297 static mtrr_type __initdata last_fixed_type;
 298
 299 static void __init print_fixed_last(void)
 300 {
 301         if (!last_fixed_end)
 302                 return;
 303
 304         pr_debug("  %05X-%05X %s\n", last_fixed_start,
 305                  last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
 306
 307         last_fixed_end = 0;
 308 }
 309
 310 static void __init update_fixed_last(unsigned base, unsigned end,
 311                                      mtrr_type type)
 312 {
 313         last_fixed_start = base;
 314         last_fixed_end = end;
 315         last_fixed_type = type;
 316 }
 317
 318 static void __init
 319 print_fixed(unsigned base, unsigned step, const mtrr_type *types)
 320 {
 321         unsigned i;
 322
 323         for (i = 0; i < 8; ++i, ++types, base += step) {
 324                 if (last_fixed_end == 0) {
 325                         update_fixed_last(base, base + step, *types);
 326                         continue;
 327                 }
 328                 if (last_fixed_end == base && last_fixed_type == *types) {
 329                         last_fixed_end = base + step;
 330                         continue;
 331                 }
 332                 /* new segments: gap or different type */
 333                 print_fixed_last();
 334                 update_fixed_last(base, base + step, *types);
 335         }
 336 }
 337
 338 static void prepare_set(void);
 339 static void post_set(void);
 340
 341 static void __init print_mtrr_state(void)
 342 {
 343         unsigned int i;
 344         int high_width;
 345
 346         pr_debug("MTRR default type: %s\n",
 347                  mtrr_attrib_to_str(mtrr_state.def_type));
 348         if (mtrr_state.have_fixed) {
 349                 pr_debug("MTRR fixed ranges %sabled:\n",
 350                          mtrr_state.enabled & 1 ? "en" : "dis");
 351                 print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
 352                 for (i = 0; i < 2; ++i)
 353                         print_fixed(0x80000 + i * 0x20000, 0x04000,
 354                                     mtrr_state.fixed_ranges + (i + 1) * 8);
 355                 for (i = 0; i < 8; ++i)
 356                         print_fixed(0xC0000 + i * 0x08000, 0x01000,
 357                                     mtrr_state.fixed_ranges + (i + 3) * 8);
 358
 359                 /* tail */
 360                 print_fixed_last();
 361         }
 362         pr_debug("MTRR variable ranges %sabled:\n",
 363                  mtrr_state.enabled & 2 ? "en" : "dis");
 364         if (size_or_mask & 0xffffffffUL)
 365                 high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
 366         else
 367                 high_width = ffs(size_or_mask>>32) + 32 - 1;
 368         high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
 369
 370         for (i = 0; i < num_var_ranges; ++i) {
 371                 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
 372                         pr_debug("  %u base %0*X%05X000 mask %0*X%05X000 %s\n",
 373                                  i,
 374                                  high_width,
 375                                  mtrr_state.var_ranges[i].base_hi,
 376                                  mtrr_state.var_ranges[i].base_lo >> 12,
 377                                  high_width,
 378                                  mtrr_state.var_ranges[i].mask_hi,
 379                                  mtrr_state.var_ranges[i].mask_lo >> 12,
 380                                  mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
 381                 else
 382                         pr_debug("  %u disabled\n", i);
 383         }
 384         if (mtrr_tom2)
 385                 pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
 386 }
 387
 388 /* Grab all of the MTRR state for this CPU into *state */
 389 void __init get_mtrr_state(void)
 390 {
 391         struct mtrr_var_range *vrs;
 392         unsigned long flags;
 393         unsigned lo, dummy;
 394         unsigned int i;
 395
 396         vrs = mtrr_state.var_ranges;
 397
 398         rdmsr(MSR_MTRRcap, lo, dummy);
 399         mtrr_state.have_fixed = (lo >> 8) & 1;
 400
 401         for (i = 0; i < num_var_ranges; i++)
 402                 get_mtrr_var_range(i, &vrs[i]);
 403         if (mtrr_state.have_fixed)
 404                 get_fixed_ranges(mtrr_state.fixed_ranges);
 405
 406         rdmsr(MSR_MTRRdefType, lo, dummy);
 407         mtrr_state.def_type = (lo & 0xff);
 408         mtrr_state.enabled = (lo & 0xc00) >> 10;
 409
 410         if (amd_special_default_mtrr()) {
 411                 unsigned low, high;
 412
 413                 /* TOP_MEM2 */
 414                 rdmsr(MSR_K8_TOP_MEM2, low, high);
 415                 mtrr_tom2 = high;
 416                 mtrr_tom2 <<= 32;
 417                 mtrr_tom2 |= low;
 418                 mtrr_tom2 &= 0xffffff800000ULL;
 419         }
 420
 421         print_mtrr_state();
 422
 423         mtrr_state_set = 1;
 424
 425         /* PAT setup for BP. We need to go through sync steps here */
 426         local_irq_save(flags);
 427         prepare_set();
 428
 429         pat_init();
 430
 431         post_set();
 432         local_irq_restore(flags);
 433 }
 434
 435 /* Some BIOS's are messed up and don't set all MTRRs the same! */
 436 void __init mtrr_state_warn(void)
 437 {
 438         unsigned long mask = smp_changes_mask;
 439
 440         if (!mask)
 441                 return;
 442         if (mask & MTRR_CHANGE_MASK_FIXED)
 443                 pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
 444         if (mask & MTRR_CHANGE_MASK_VARIABLE)
 445                 pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
 446         if (mask & MTRR_CHANGE_MASK_DEFTYPE)
 447                 pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
 448
 449         printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
 450         printk(KERN_INFO "mtrr: corrected configuration.\n");
 451 }
 452
 453 /*
 454  * Doesn't attempt to pass an error out to MTRR users
 455  * because it's quite complicated in some cases and probably not
 456  * worth it because the best error handling is to ignore it.
 457  */
 458 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
 459 {
 460         if (wrmsr_safe(msr, a, b) < 0) {
 461                 printk(KERN_ERR
 462                         "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
 463                         smp_processor_id(), msr, a, b);
 464         }
 465 }
 466
 467 /**
 468  * set_fixed_range - checks & updates a fixed-range MTRR if it
 469  *                   differs from the value it should have
 470  * @msr: MSR address of the MTTR which should be checked and updated
 471  * @changed: pointer which indicates whether the MTRR needed to be changed
 472  * @msrwords: pointer to the MSR values which the MSR should have
 473  */
 474 static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
 475 {
 476         unsigned lo, hi;
 477
 478         rdmsr(msr, lo, hi);
 479
 480         if (lo != msrwords[0] || hi != msrwords[1]) {
 481                 mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
 482                 *changed = true;
 483         }
 484 }
 485
 486 /**
 487  * generic_get_free_region - Get a free MTRR.
 488  * @base: The starting (base) address of the region.
 489  * @size: The size (in bytes) of the region.
 490  * @replace_reg: mtrr index to be replaced; set to invalid value if none.
 491  *
 492  * Returns: The index of the region on success, else negative on error.
 493  */
 494 int
 495 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
 496 {
 497         unsigned long lbase, lsize;
 498         mtrr_type ltype;
 499         int i, max;
 500
 501         max = num_var_ranges;
 502         if (replace_reg >= 0 && replace_reg < max)
 503                 return replace_reg;
 504
 505         for (i = 0; i < max; ++i) {
 506                 mtrr_if->get(i, &lbase, &lsize, &ltype);
 507                 if (lsize == 0)
 508                         return i;
 509         }
 510
 511         return -ENOSPC;
 512 }
 513
 514 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
 515                              unsigned long *size, mtrr_type *type)
 516 {
 517         unsigned int mask_lo, mask_hi, base_lo, base_hi;
 518         unsigned int tmp, hi;
 519
 520         /*
 521          * get_mtrr doesn't need to update mtrr_state, also it could be called
 522          * from any cpu, so try to print it out directly.
 523          */
 524         get_cpu();
 525
 526         rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
 527
 528         if ((mask_lo & 0x800) == 0) {
 529                 /*  Invalid (i.e. free) range */
 530                 *base = 0;
 531                 *size = 0;
 532                 *type = 0;
 533                 goto out_put_cpu;
 534         }
 535
 536         rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
 537
 538         /* Work out the shifted address mask: */
 539         tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
 540         mask_lo = size_or_mask | tmp;
 541
 542         /* Expand tmp with high bits to all 1s: */
 543         hi = fls(tmp);
 544         if (hi > 0) {
 545                 tmp |= ~((1<<(hi - 1)) - 1);
 546
 547                 if (tmp != mask_lo) {
 548                         printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
 549                         add_taint(TAINT_FIRMWARE_WORKAROUND);
 550                         mask_lo = tmp;
 551                 }
 552         }
 553
 554         /*
 555          * This works correctly if size is a power of two, i.e. a
 556          * contiguous range:
 557          */
 558         *size = -mask_lo;
 559         *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
 560         *type = base_lo & 0xff;
 561
 562 out_put_cpu:
 563         put_cpu();
 564 }
 565
 566 /**
 567  * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
 568  *                    differ from the saved set
 569  * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
 570  */
 571 static int set_fixed_ranges(mtrr_type *frs)
 572 {
 573         unsigned long long *saved = (unsigned long long *)frs;
 574         bool changed = false;
 575         int block = -1, range;
 576
 577         k8_check_syscfg_dram_mod_en();
 578
 579         while (fixed_range_blocks[++block].ranges) {
 580                 for (range = 0; range < fixed_range_blocks[block].ranges; range++)
 581                         set_fixed_range(fixed_range_blocks[block].base_msr + range,
 582                                         &changed, (unsigned int *)saved++);
 583         }
 584
 585         return changed;
 586 }
 587
 588 /*
 589  * Set the MSR pair relating to a var range.
 590  * Returns true if changes are made.
 591  */
 592 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
 593 {
 594         unsigned int lo, hi;
 595         bool changed = false;
 596
 597         rdmsr(MTRRphysBase_MSR(index), lo, hi);
 598         if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
 599             || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
 600                 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
 601
 602                 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
 603                 changed = true;
 604         }
 605
 606         rdmsr(MTRRphysMask_MSR(index), lo, hi);
 607
 608         if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
 609             || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
 610                 (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
 611                 mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 612                 changed = true;
 613         }
 614         return changed;
 615 }
 616
 617 static u32 deftype_lo, deftype_hi;
 618
 619 /**
 620  * set_mtrr_state - Set the MTRR state for this CPU.
 621  *
 622  * NOTE: The CPU must already be in a safe state for MTRR changes.
 623  * RETURNS: 0 if no changes made, else a mask indicating what was changed.
 624  */
 625 static unsigned long set_mtrr_state(void)
 626 {
 627         unsigned long change_mask = 0;
 628         unsigned int i;
 629
 630         for (i = 0; i < num_var_ranges; i++) {
 631                 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
 632                         change_mask |= MTRR_CHANGE_MASK_VARIABLE;
 633         }
 634
 635         if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
 636                 change_mask |= MTRR_CHANGE_MASK_FIXED;
 637
 638         /*
 639          * Set_mtrr_restore restores the old value of MTRRdefType,
 640          * so to set it we fiddle with the saved value:
 641          */
 642         if ((deftype_lo & 0xff) != mtrr_state.def_type
 643             || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
 644
 645                 deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
 646                              (mtrr_state.enabled << 10);
 647                 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
 648         }
 649
 650         return change_mask;
 651 }
 652
 653
 654 static unsigned long cr4;
 655 static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
 656
 657 /*
 658  * Since we are disabling the cache don't allow any interrupts,
 659  * they would run extremely slow and would only increase the pain.
 660  *
 661  * The caller must ensure that local interrupts are disabled and
 662  * are reenabled after post_set() has been called.
 663  */
 664 static void prepare_set(void) __acquires(set_atomicity_lock)
 665 {
 666         unsigned long cr0;
 667
 668         /*
 669          * Note that this is not ideal
 670          * since the cache is only flushed/disabled for this CPU while the
 671          * MTRRs are changed, but changing this requires more invasive
 672          * changes to the way the kernel boots
 673          */
 674
 675         raw_spin_lock(&set_atomicity_lock);
 676
 677         /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
 678         cr0 = read_cr0() | X86_CR0_CD;
 679         write_cr0(cr0);
 680         wbinvd();
 681
 682         /* Save value of CR4 and clear Page Global Enable (bit 7) */
 683         if (cpu_has_pge) {
 684                 cr4 = read_cr4();
 685                 write_cr4(cr4 & ~X86_CR4_PGE);
 686         }
 687
 688         /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
 689         __flush_tlb();
 690
 691         /* Save MTRR state */
 692         rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 693
 694         /* Disable MTRRs, and set the default type to uncached */
 695         mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
 696         wbinvd();
 697 }
 698
 699 static void post_set(void) __releases(set_atomicity_lock)
 700 {
 701         /* Flush TLBs (no need to flush caches - they are disabled) */
 702         __flush_tlb();
 703
 704         /* Intel (P6) standard MTRRs */
 705         mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 706
 707         /* Enable caches */
 708         write_cr0(read_cr0() & 0xbfffffff);
 709
 710         /* Restore value of CR4 */
 711         if (cpu_has_pge)
 712                 write_cr4(cr4);
 713         raw_spin_unlock(&set_atomicity_lock);
 714 }
 715
 716 static void generic_set_all(void)
 717 {
 718         unsigned long mask, count;
 719         unsigned long flags;
 720
 721         local_irq_save(flags);
 722         prepare_set();
 723
 724         /* Actually set the state */
 725         mask = set_mtrr_state();
 726
 727         /* also set PAT */
 728         pat_init();
 729
 730         post_set();
 731         local_irq_restore(flags);
 732
 733         /* Use the atomic bitops to update the global mask */
 734         for (count = 0; count < sizeof mask * 8; ++count) {
 735                 if (mask & 0x01)
 736                         set_bit(count, &smp_changes_mask);
 737                 mask >>= 1;
 738         }
 739
 740 }
 741
 742 /**
 743  * generic_set_mtrr - set variable MTRR register on the local CPU.
 744  *
 745  * @reg: The register to set.
 746  * @base: The base address of the region.
 747  * @size: The size of the region. If this is 0 the region is disabled.
 748  * @type: The type of the region.
 749  *
 750  * Returns nothing.
 751  */
 752 static void generic_set_mtrr(unsigned int reg, unsigned long base,
 753                              unsigned long size, mtrr_type type)
 754 {
 755         unsigned long flags;
 756         struct mtrr_var_range *vr;
 757
 758         vr = &mtrr_state.var_ranges[reg];
 759
 760         local_irq_save(flags);
 761         prepare_set();
 762
 763         if (size == 0) {
 764                 /*
 765                  * The invalid bit is kept in the mask, so we simply
 766                  * clear the relevant mask register to disable a range.
 767                  */
 768                 mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
 769                 memset(vr, 0, sizeof(struct mtrr_var_range));
 770         } else {
 771                 vr->base_lo = base << PAGE_SHIFT | type;
 772                 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
 773                 vr->mask_lo = -size << PAGE_SHIFT | 0x800;
 774                 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
 775
 776                 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
 777                 mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
 778         }
 779
 780         post_set();
 781         local_irq_restore(flags);
 782 }
 783
 784 int generic_validate_add_page(unsigned long base, unsigned long size,
 785                               unsigned int type)
 786 {
 787         unsigned long lbase, last;
 788
 789         /*
 790          * For Intel PPro stepping <= 7
 791          * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
 792          */
 793         if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
 794             boot_cpu_data.x86_model == 1 &&
 795             boot_cpu_data.x86_mask <= 7) {
 796                 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
 797                         pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
 798                         return -EINVAL;
 799                 }
 800                 if (!(base + size < 0x70000 || base > 0x7003F) &&
 801                     (type == MTRR_TYPE_WRCOMB
 802                      || type == MTRR_TYPE_WRBACK)) {
 803                         pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
 804                         return -EINVAL;
 805                 }
 806         }
 807
 808         /*
 809          * Check upper bits of base and last are equal and lower bits are 0
 810          * for base and 1 for last
 811          */
 812         last = base + size - 1;
 813         for (lbase = base; !(lbase & 1) && (last & 1);
 814              lbase = lbase >> 1, last = last >> 1)
 815                 ;
 816         if (lbase != last) {
 817                 pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
 818                 return -EINVAL;
 819         }
 820         return 0;
 821 }
 822
 823 static int generic_have_wrcomb(void)
 824 {
 825         unsigned long config, dummy;
 826         rdmsr(MSR_MTRRcap, config, dummy);
 827         return config & (1 << 10);
 828 }
 829
 830 int positive_have_wrcomb(void)
 831 {
 832         return 1;
 833 }
 834
 835 /*
 836  * Generic structure...
 837  */
 838 const struct mtrr_ops generic_mtrr_ops = {
 839         .use_intel_if           = 1,
 840         .set_all                = generic_set_all,
 841         .get                    = generic_get_mtrr,
 842         .get_free_region        = generic_get_free_region,
 843         .set                    = generic_set_mtrr,
 844         .validate_add_page      = generic_validate_add_page,
 845         .have_wrcomb            = generic_have_wrcomb,
 846 };