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perf_counter: Rename perf_counter_hw_event => perf_counter_attr
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_counter.c
1 /*
2 * Performance counter x86 architecture code
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 *
10 * For licencing details see kernel-base/COPYING
11 */
12
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
22
23 #include <asm/apic.h>
24 #include <asm/stacktrace.h>
25 #include <asm/nmi.h>
26
27 static u64 perf_counter_mask __read_mostly;
28
29 struct cpu_hw_counters {
30 struct perf_counter *counters[X86_PMC_IDX_MAX];
31 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
32 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
33 unsigned long interrupts;
34 int enabled;
35 };
36
37 /*
38 * struct x86_pmu - generic x86 pmu
39 */
40 struct x86_pmu {
41 const char *name;
42 int version;
43 int (*handle_irq)(struct pt_regs *, int);
44 void (*disable_all)(void);
45 void (*enable_all)(void);
46 void (*enable)(struct hw_perf_counter *, int);
47 void (*disable)(struct hw_perf_counter *, int);
48 unsigned eventsel;
49 unsigned perfctr;
50 u64 (*event_map)(int);
51 u64 (*raw_event)(u64);
52 int max_events;
53 int num_counters;
54 int num_counters_fixed;
55 int counter_bits;
56 u64 counter_mask;
57 u64 max_period;
58 u64 intel_ctrl;
59 };
60
61 static struct x86_pmu x86_pmu __read_mostly;
62
63 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
64 .enabled = 1,
65 };
66
67 /*
68 * Intel PerfMon v3. Used on Core2 and later.
69 */
70 static const u64 intel_perfmon_event_map[] =
71 {
72 [PERF_COUNT_CPU_CYCLES] = 0x003c,
73 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
74 [PERF_COUNT_CACHE_REFERENCES] = 0x4f2e,
75 [PERF_COUNT_CACHE_MISSES] = 0x412e,
76 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
77 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
78 [PERF_COUNT_BUS_CYCLES] = 0x013c,
79 };
80
81 static u64 intel_pmu_event_map(int event)
82 {
83 return intel_perfmon_event_map[event];
84 }
85
86 static u64 intel_pmu_raw_event(u64 event)
87 {
88 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
89 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
90 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
91 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
92 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
93
94 #define CORE_EVNTSEL_MASK \
95 (CORE_EVNTSEL_EVENT_MASK | \
96 CORE_EVNTSEL_UNIT_MASK | \
97 CORE_EVNTSEL_EDGE_MASK | \
98 CORE_EVNTSEL_INV_MASK | \
99 CORE_EVNTSEL_COUNTER_MASK)
100
101 return event & CORE_EVNTSEL_MASK;
102 }
103
104 /*
105 * AMD Performance Monitor K7 and later.
106 */
107 static const u64 amd_perfmon_event_map[] =
108 {
109 [PERF_COUNT_CPU_CYCLES] = 0x0076,
110 [PERF_COUNT_INSTRUCTIONS] = 0x00c0,
111 [PERF_COUNT_CACHE_REFERENCES] = 0x0080,
112 [PERF_COUNT_CACHE_MISSES] = 0x0081,
113 [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x00c4,
114 [PERF_COUNT_BRANCH_MISSES] = 0x00c5,
115 };
116
117 static u64 amd_pmu_event_map(int event)
118 {
119 return amd_perfmon_event_map[event];
120 }
121
122 static u64 amd_pmu_raw_event(u64 event)
123 {
124 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
125 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
126 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
127 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
128 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
129
130 #define K7_EVNTSEL_MASK \
131 (K7_EVNTSEL_EVENT_MASK | \
132 K7_EVNTSEL_UNIT_MASK | \
133 K7_EVNTSEL_EDGE_MASK | \
134 K7_EVNTSEL_INV_MASK | \
135 K7_EVNTSEL_COUNTER_MASK)
136
137 return event & K7_EVNTSEL_MASK;
138 }
139
140 /*
141 * Propagate counter elapsed time into the generic counter.
142 * Can only be executed on the CPU where the counter is active.
143 * Returns the delta events processed.
144 */
145 static u64
146 x86_perf_counter_update(struct perf_counter *counter,
147 struct hw_perf_counter *hwc, int idx)
148 {
149 int shift = 64 - x86_pmu.counter_bits;
150 u64 prev_raw_count, new_raw_count;
151 s64 delta;
152
153 /*
154 * Careful: an NMI might modify the previous counter value.
155 *
156 * Our tactic to handle this is to first atomically read and
157 * exchange a new raw count - then add that new-prev delta
158 * count to the generic counter atomically:
159 */
160 again:
161 prev_raw_count = atomic64_read(&hwc->prev_count);
162 rdmsrl(hwc->counter_base + idx, new_raw_count);
163
164 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
165 new_raw_count) != prev_raw_count)
166 goto again;
167
168 /*
169 * Now we have the new raw value and have updated the prev
170 * timestamp already. We can now calculate the elapsed delta
171 * (counter-)time and add that to the generic counter.
172 *
173 * Careful, not all hw sign-extends above the physical width
174 * of the count.
175 */
176 delta = (new_raw_count << shift) - (prev_raw_count << shift);
177 delta >>= shift;
178
179 atomic64_add(delta, &counter->count);
180 atomic64_sub(delta, &hwc->period_left);
181
182 return new_raw_count;
183 }
184
185 static atomic_t active_counters;
186 static DEFINE_MUTEX(pmc_reserve_mutex);
187
188 static bool reserve_pmc_hardware(void)
189 {
190 int i;
191
192 if (nmi_watchdog == NMI_LOCAL_APIC)
193 disable_lapic_nmi_watchdog();
194
195 for (i = 0; i < x86_pmu.num_counters; i++) {
196 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
197 goto perfctr_fail;
198 }
199
200 for (i = 0; i < x86_pmu.num_counters; i++) {
201 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
202 goto eventsel_fail;
203 }
204
205 return true;
206
207 eventsel_fail:
208 for (i--; i >= 0; i--)
209 release_evntsel_nmi(x86_pmu.eventsel + i);
210
211 i = x86_pmu.num_counters;
212
213 perfctr_fail:
214 for (i--; i >= 0; i--)
215 release_perfctr_nmi(x86_pmu.perfctr + i);
216
217 if (nmi_watchdog == NMI_LOCAL_APIC)
218 enable_lapic_nmi_watchdog();
219
220 return false;
221 }
222
223 static void release_pmc_hardware(void)
224 {
225 int i;
226
227 for (i = 0; i < x86_pmu.num_counters; i++) {
228 release_perfctr_nmi(x86_pmu.perfctr + i);
229 release_evntsel_nmi(x86_pmu.eventsel + i);
230 }
231
232 if (nmi_watchdog == NMI_LOCAL_APIC)
233 enable_lapic_nmi_watchdog();
234 }
235
236 static void hw_perf_counter_destroy(struct perf_counter *counter)
237 {
238 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
239 release_pmc_hardware();
240 mutex_unlock(&pmc_reserve_mutex);
241 }
242 }
243
244 static inline int x86_pmu_initialized(void)
245 {
246 return x86_pmu.handle_irq != NULL;
247 }
248
249 /*
250 * Setup the hardware configuration for a given attr_type
251 */
252 static int __hw_perf_counter_init(struct perf_counter *counter)
253 {
254 struct perf_counter_attr *attr = &counter->attr;
255 struct hw_perf_counter *hwc = &counter->hw;
256 int err;
257
258 if (!x86_pmu_initialized())
259 return -ENODEV;
260
261 err = 0;
262 if (!atomic_inc_not_zero(&active_counters)) {
263 mutex_lock(&pmc_reserve_mutex);
264 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
265 err = -EBUSY;
266 else
267 atomic_inc(&active_counters);
268 mutex_unlock(&pmc_reserve_mutex);
269 }
270 if (err)
271 return err;
272
273 /*
274 * Generate PMC IRQs:
275 * (keep 'enabled' bit clear for now)
276 */
277 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
278
279 /*
280 * Count user and OS events unless requested not to.
281 */
282 if (!attr->exclude_user)
283 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
284 if (!attr->exclude_kernel)
285 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
286
287 if (!hwc->sample_period)
288 hwc->sample_period = x86_pmu.max_period;
289
290 atomic64_set(&hwc->period_left, hwc->sample_period);
291
292 /*
293 * Raw event type provide the config in the event structure
294 */
295 if (perf_event_raw(attr)) {
296 hwc->config |= x86_pmu.raw_event(perf_event_config(attr));
297 } else {
298 if (perf_event_id(attr) >= x86_pmu.max_events)
299 return -EINVAL;
300 /*
301 * The generic map:
302 */
303 hwc->config |= x86_pmu.event_map(perf_event_id(attr));
304 }
305
306 counter->destroy = hw_perf_counter_destroy;
307
308 return 0;
309 }
310
311 static void intel_pmu_disable_all(void)
312 {
313 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
314 }
315
316 static void amd_pmu_disable_all(void)
317 {
318 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
319 int idx;
320
321 if (!cpuc->enabled)
322 return;
323
324 cpuc->enabled = 0;
325 /*
326 * ensure we write the disable before we start disabling the
327 * counters proper, so that amd_pmu_enable_counter() does the
328 * right thing.
329 */
330 barrier();
331
332 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
333 u64 val;
334
335 if (!test_bit(idx, cpuc->active_mask))
336 continue;
337 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
338 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
339 continue;
340 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
341 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
342 }
343 }
344
345 void hw_perf_disable(void)
346 {
347 if (!x86_pmu_initialized())
348 return;
349 return x86_pmu.disable_all();
350 }
351
352 static void intel_pmu_enable_all(void)
353 {
354 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
355 }
356
357 static void amd_pmu_enable_all(void)
358 {
359 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
360 int idx;
361
362 if (cpuc->enabled)
363 return;
364
365 cpuc->enabled = 1;
366 barrier();
367
368 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
369 u64 val;
370
371 if (!test_bit(idx, cpuc->active_mask))
372 continue;
373 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
374 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
375 continue;
376 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
377 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
378 }
379 }
380
381 void hw_perf_enable(void)
382 {
383 if (!x86_pmu_initialized())
384 return;
385 x86_pmu.enable_all();
386 }
387
388 static inline u64 intel_pmu_get_status(void)
389 {
390 u64 status;
391
392 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
393
394 return status;
395 }
396
397 static inline void intel_pmu_ack_status(u64 ack)
398 {
399 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
400 }
401
402 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
403 {
404 int err;
405 err = checking_wrmsrl(hwc->config_base + idx,
406 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
407 }
408
409 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
410 {
411 int err;
412 err = checking_wrmsrl(hwc->config_base + idx,
413 hwc->config);
414 }
415
416 static inline void
417 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
418 {
419 int idx = __idx - X86_PMC_IDX_FIXED;
420 u64 ctrl_val, mask;
421 int err;
422
423 mask = 0xfULL << (idx * 4);
424
425 rdmsrl(hwc->config_base, ctrl_val);
426 ctrl_val &= ~mask;
427 err = checking_wrmsrl(hwc->config_base, ctrl_val);
428 }
429
430 static inline void
431 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
432 {
433 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
434 intel_pmu_disable_fixed(hwc, idx);
435 return;
436 }
437
438 x86_pmu_disable_counter(hwc, idx);
439 }
440
441 static inline void
442 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
443 {
444 x86_pmu_disable_counter(hwc, idx);
445 }
446
447 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
448
449 /*
450 * Set the next IRQ period, based on the hwc->period_left value.
451 * To be called with the counter disabled in hw:
452 */
453 static int
454 x86_perf_counter_set_period(struct perf_counter *counter,
455 struct hw_perf_counter *hwc, int idx)
456 {
457 s64 left = atomic64_read(&hwc->period_left);
458 s64 period = hwc->sample_period;
459 int err, ret = 0;
460
461 /*
462 * If we are way outside a reasoable range then just skip forward:
463 */
464 if (unlikely(left <= -period)) {
465 left = period;
466 atomic64_set(&hwc->period_left, left);
467 ret = 1;
468 }
469
470 if (unlikely(left <= 0)) {
471 left += period;
472 atomic64_set(&hwc->period_left, left);
473 ret = 1;
474 }
475 /*
476 * Quirk: certain CPUs dont like it if just 1 event is left:
477 */
478 if (unlikely(left < 2))
479 left = 2;
480
481 if (left > x86_pmu.max_period)
482 left = x86_pmu.max_period;
483
484 per_cpu(prev_left[idx], smp_processor_id()) = left;
485
486 /*
487 * The hw counter starts counting from this counter offset,
488 * mark it to be able to extra future deltas:
489 */
490 atomic64_set(&hwc->prev_count, (u64)-left);
491
492 err = checking_wrmsrl(hwc->counter_base + idx,
493 (u64)(-left) & x86_pmu.counter_mask);
494
495 return ret;
496 }
497
498 static inline void
499 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
500 {
501 int idx = __idx - X86_PMC_IDX_FIXED;
502 u64 ctrl_val, bits, mask;
503 int err;
504
505 /*
506 * Enable IRQ generation (0x8),
507 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
508 * if requested:
509 */
510 bits = 0x8ULL;
511 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
512 bits |= 0x2;
513 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
514 bits |= 0x1;
515 bits <<= (idx * 4);
516 mask = 0xfULL << (idx * 4);
517
518 rdmsrl(hwc->config_base, ctrl_val);
519 ctrl_val &= ~mask;
520 ctrl_val |= bits;
521 err = checking_wrmsrl(hwc->config_base, ctrl_val);
522 }
523
524 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
525 {
526 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
527 intel_pmu_enable_fixed(hwc, idx);
528 return;
529 }
530
531 x86_pmu_enable_counter(hwc, idx);
532 }
533
534 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
535 {
536 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
537
538 if (cpuc->enabled)
539 x86_pmu_enable_counter(hwc, idx);
540 else
541 x86_pmu_disable_counter(hwc, idx);
542 }
543
544 static int
545 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
546 {
547 unsigned int event;
548
549 if (!x86_pmu.num_counters_fixed)
550 return -1;
551
552 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
553
554 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_INSTRUCTIONS)))
555 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
556 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_CPU_CYCLES)))
557 return X86_PMC_IDX_FIXED_CPU_CYCLES;
558 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_BUS_CYCLES)))
559 return X86_PMC_IDX_FIXED_BUS_CYCLES;
560
561 return -1;
562 }
563
564 /*
565 * Find a PMC slot for the freshly enabled / scheduled in counter:
566 */
567 static int x86_pmu_enable(struct perf_counter *counter)
568 {
569 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
570 struct hw_perf_counter *hwc = &counter->hw;
571 int idx;
572
573 idx = fixed_mode_idx(counter, hwc);
574 if (idx >= 0) {
575 /*
576 * Try to get the fixed counter, if that is already taken
577 * then try to get a generic counter:
578 */
579 if (test_and_set_bit(idx, cpuc->used_mask))
580 goto try_generic;
581
582 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
583 /*
584 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
585 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
586 */
587 hwc->counter_base =
588 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
589 hwc->idx = idx;
590 } else {
591 idx = hwc->idx;
592 /* Try to get the previous generic counter again */
593 if (test_and_set_bit(idx, cpuc->used_mask)) {
594 try_generic:
595 idx = find_first_zero_bit(cpuc->used_mask,
596 x86_pmu.num_counters);
597 if (idx == x86_pmu.num_counters)
598 return -EAGAIN;
599
600 set_bit(idx, cpuc->used_mask);
601 hwc->idx = idx;
602 }
603 hwc->config_base = x86_pmu.eventsel;
604 hwc->counter_base = x86_pmu.perfctr;
605 }
606
607 perf_counters_lapic_init();
608
609 x86_pmu.disable(hwc, idx);
610
611 cpuc->counters[idx] = counter;
612 set_bit(idx, cpuc->active_mask);
613
614 x86_perf_counter_set_period(counter, hwc, idx);
615 x86_pmu.enable(hwc, idx);
616
617 return 0;
618 }
619
620 static void x86_pmu_unthrottle(struct perf_counter *counter)
621 {
622 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
623 struct hw_perf_counter *hwc = &counter->hw;
624
625 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
626 cpuc->counters[hwc->idx] != counter))
627 return;
628
629 x86_pmu.enable(hwc, hwc->idx);
630 }
631
632 void perf_counter_print_debug(void)
633 {
634 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
635 struct cpu_hw_counters *cpuc;
636 unsigned long flags;
637 int cpu, idx;
638
639 if (!x86_pmu.num_counters)
640 return;
641
642 local_irq_save(flags);
643
644 cpu = smp_processor_id();
645 cpuc = &per_cpu(cpu_hw_counters, cpu);
646
647 if (x86_pmu.version >= 2) {
648 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
649 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
650 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
651 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
652
653 pr_info("\n");
654 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
655 pr_info("CPU#%d: status: %016llx\n", cpu, status);
656 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
657 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
658 }
659 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
660
661 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
662 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
663 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
664
665 prev_left = per_cpu(prev_left[idx], cpu);
666
667 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
668 cpu, idx, pmc_ctrl);
669 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
670 cpu, idx, pmc_count);
671 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
672 cpu, idx, prev_left);
673 }
674 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
675 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
676
677 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
678 cpu, idx, pmc_count);
679 }
680 local_irq_restore(flags);
681 }
682
683 static void x86_pmu_disable(struct perf_counter *counter)
684 {
685 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
686 struct hw_perf_counter *hwc = &counter->hw;
687 int idx = hwc->idx;
688
689 /*
690 * Must be done before we disable, otherwise the nmi handler
691 * could reenable again:
692 */
693 clear_bit(idx, cpuc->active_mask);
694 x86_pmu.disable(hwc, idx);
695
696 /*
697 * Make sure the cleared pointer becomes visible before we
698 * (potentially) free the counter:
699 */
700 barrier();
701
702 /*
703 * Drain the remaining delta count out of a counter
704 * that we are disabling:
705 */
706 x86_perf_counter_update(counter, hwc, idx);
707 cpuc->counters[idx] = NULL;
708 clear_bit(idx, cpuc->used_mask);
709 }
710
711 /*
712 * Save and restart an expired counter. Called by NMI contexts,
713 * so it has to be careful about preempting normal counter ops:
714 */
715 static int intel_pmu_save_and_restart(struct perf_counter *counter)
716 {
717 struct hw_perf_counter *hwc = &counter->hw;
718 int idx = hwc->idx;
719 int ret;
720
721 x86_perf_counter_update(counter, hwc, idx);
722 ret = x86_perf_counter_set_period(counter, hwc, idx);
723
724 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
725 intel_pmu_enable_counter(hwc, idx);
726
727 return ret;
728 }
729
730 static void intel_pmu_reset(void)
731 {
732 unsigned long flags;
733 int idx;
734
735 if (!x86_pmu.num_counters)
736 return;
737
738 local_irq_save(flags);
739
740 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
741
742 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
743 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
744 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
745 }
746 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
747 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
748 }
749
750 local_irq_restore(flags);
751 }
752
753
754 /*
755 * This handler is triggered by the local APIC, so the APIC IRQ handling
756 * rules apply:
757 */
758 static int intel_pmu_handle_irq(struct pt_regs *regs, int nmi)
759 {
760 struct cpu_hw_counters *cpuc;
761 struct cpu_hw_counters;
762 int bit, cpu, loops;
763 u64 ack, status;
764
765 cpu = smp_processor_id();
766 cpuc = &per_cpu(cpu_hw_counters, cpu);
767
768 perf_disable();
769 status = intel_pmu_get_status();
770 if (!status) {
771 perf_enable();
772 return 0;
773 }
774
775 loops = 0;
776 again:
777 if (++loops > 100) {
778 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
779 perf_counter_print_debug();
780 intel_pmu_reset();
781 perf_enable();
782 return 1;
783 }
784
785 inc_irq_stat(apic_perf_irqs);
786 ack = status;
787 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
788 struct perf_counter *counter = cpuc->counters[bit];
789
790 clear_bit(bit, (unsigned long *) &status);
791 if (!test_bit(bit, cpuc->active_mask))
792 continue;
793
794 if (!intel_pmu_save_and_restart(counter))
795 continue;
796
797 if (perf_counter_overflow(counter, nmi, regs, 0))
798 intel_pmu_disable_counter(&counter->hw, bit);
799 }
800
801 intel_pmu_ack_status(ack);
802
803 /*
804 * Repeat if there is more work to be done:
805 */
806 status = intel_pmu_get_status();
807 if (status)
808 goto again;
809
810 perf_enable();
811
812 return 1;
813 }
814
815 static int amd_pmu_handle_irq(struct pt_regs *regs, int nmi)
816 {
817 int cpu, idx, handled = 0;
818 struct cpu_hw_counters *cpuc;
819 struct perf_counter *counter;
820 struct hw_perf_counter *hwc;
821 u64 val;
822
823 cpu = smp_processor_id();
824 cpuc = &per_cpu(cpu_hw_counters, cpu);
825
826 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
827 if (!test_bit(idx, cpuc->active_mask))
828 continue;
829
830 counter = cpuc->counters[idx];
831 hwc = &counter->hw;
832
833 val = x86_perf_counter_update(counter, hwc, idx);
834 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
835 continue;
836
837 /* counter overflow */
838 handled = 1;
839 inc_irq_stat(apic_perf_irqs);
840 if (!x86_perf_counter_set_period(counter, hwc, idx))
841 continue;
842
843 if (perf_counter_overflow(counter, nmi, regs, 0))
844 amd_pmu_disable_counter(hwc, idx);
845 }
846
847 return handled;
848 }
849
850 void smp_perf_counter_interrupt(struct pt_regs *regs)
851 {
852 irq_enter();
853 apic_write(APIC_LVTPC, LOCAL_PERF_VECTOR);
854 ack_APIC_irq();
855 x86_pmu.handle_irq(regs, 0);
856 irq_exit();
857 }
858
859 void smp_perf_pending_interrupt(struct pt_regs *regs)
860 {
861 irq_enter();
862 ack_APIC_irq();
863 inc_irq_stat(apic_pending_irqs);
864 perf_counter_do_pending();
865 irq_exit();
866 }
867
868 void set_perf_counter_pending(void)
869 {
870 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
871 }
872
873 void perf_counters_lapic_init(void)
874 {
875 if (!x86_pmu_initialized())
876 return;
877
878 /*
879 * Always use NMI for PMU
880 */
881 apic_write(APIC_LVTPC, APIC_DM_NMI);
882 }
883
884 static int __kprobes
885 perf_counter_nmi_handler(struct notifier_block *self,
886 unsigned long cmd, void *__args)
887 {
888 struct die_args *args = __args;
889 struct pt_regs *regs;
890
891 if (!atomic_read(&active_counters))
892 return NOTIFY_DONE;
893
894 switch (cmd) {
895 case DIE_NMI:
896 case DIE_NMI_IPI:
897 break;
898
899 default:
900 return NOTIFY_DONE;
901 }
902
903 regs = args->regs;
904
905 apic_write(APIC_LVTPC, APIC_DM_NMI);
906 /*
907 * Can't rely on the handled return value to say it was our NMI, two
908 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
909 *
910 * If the first NMI handles both, the latter will be empty and daze
911 * the CPU.
912 */
913 x86_pmu.handle_irq(regs, 1);
914
915 return NOTIFY_STOP;
916 }
917
918 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
919 .notifier_call = perf_counter_nmi_handler,
920 .next = NULL,
921 .priority = 1
922 };
923
924 static struct x86_pmu intel_pmu = {
925 .name = "Intel",
926 .handle_irq = intel_pmu_handle_irq,
927 .disable_all = intel_pmu_disable_all,
928 .enable_all = intel_pmu_enable_all,
929 .enable = intel_pmu_enable_counter,
930 .disable = intel_pmu_disable_counter,
931 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
932 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
933 .event_map = intel_pmu_event_map,
934 .raw_event = intel_pmu_raw_event,
935 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
936 /*
937 * Intel PMCs cannot be accessed sanely above 32 bit width,
938 * so we install an artificial 1<<31 period regardless of
939 * the generic counter period:
940 */
941 .max_period = (1ULL << 31) - 1,
942 };
943
944 static struct x86_pmu amd_pmu = {
945 .name = "AMD",
946 .handle_irq = amd_pmu_handle_irq,
947 .disable_all = amd_pmu_disable_all,
948 .enable_all = amd_pmu_enable_all,
949 .enable = amd_pmu_enable_counter,
950 .disable = amd_pmu_disable_counter,
951 .eventsel = MSR_K7_EVNTSEL0,
952 .perfctr = MSR_K7_PERFCTR0,
953 .event_map = amd_pmu_event_map,
954 .raw_event = amd_pmu_raw_event,
955 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
956 .num_counters = 4,
957 .counter_bits = 48,
958 .counter_mask = (1ULL << 48) - 1,
959 /* use highest bit to detect overflow */
960 .max_period = (1ULL << 47) - 1,
961 };
962
963 static int intel_pmu_init(void)
964 {
965 union cpuid10_edx edx;
966 union cpuid10_eax eax;
967 unsigned int unused;
968 unsigned int ebx;
969 int version;
970
971 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
972 return -ENODEV;
973
974 /*
975 * Check whether the Architectural PerfMon supports
976 * Branch Misses Retired Event or not.
977 */
978 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
979 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
980 return -ENODEV;
981
982 version = eax.split.version_id;
983 if (version < 2)
984 return -ENODEV;
985
986 x86_pmu = intel_pmu;
987 x86_pmu.version = version;
988 x86_pmu.num_counters = eax.split.num_counters;
989
990 /*
991 * Quirk: v2 perfmon does not report fixed-purpose counters, so
992 * assume at least 3 counters:
993 */
994 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
995
996 x86_pmu.counter_bits = eax.split.bit_width;
997 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
998
999 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1000
1001 return 0;
1002 }
1003
1004 static int amd_pmu_init(void)
1005 {
1006 x86_pmu = amd_pmu;
1007 return 0;
1008 }
1009
1010 void __init init_hw_perf_counters(void)
1011 {
1012 int err;
1013
1014 switch (boot_cpu_data.x86_vendor) {
1015 case X86_VENDOR_INTEL:
1016 err = intel_pmu_init();
1017 break;
1018 case X86_VENDOR_AMD:
1019 err = amd_pmu_init();
1020 break;
1021 default:
1022 return;
1023 }
1024 if (err != 0)
1025 return;
1026
1027 pr_info("%s Performance Monitoring support detected.\n", x86_pmu.name);
1028 pr_info("... version: %d\n", x86_pmu.version);
1029 pr_info("... bit width: %d\n", x86_pmu.counter_bits);
1030
1031 pr_info("... num counters: %d\n", x86_pmu.num_counters);
1032 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1033 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1034 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
1035 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1036 }
1037 perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1038 perf_max_counters = x86_pmu.num_counters;
1039
1040 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
1041 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1042
1043 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1044 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1045 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1046 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1047 }
1048 pr_info("... fixed counters: %d\n", x86_pmu.num_counters_fixed);
1049
1050 perf_counter_mask |=
1051 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1052
1053 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
1054
1055 perf_counters_lapic_init();
1056 register_die_notifier(&perf_counter_nmi_notifier);
1057 }
1058
1059 static inline void x86_pmu_read(struct perf_counter *counter)
1060 {
1061 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1062 }
1063
1064 static const struct pmu pmu = {
1065 .enable = x86_pmu_enable,
1066 .disable = x86_pmu_disable,
1067 .read = x86_pmu_read,
1068 .unthrottle = x86_pmu_unthrottle,
1069 };
1070
1071 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1072 {
1073 int err;
1074
1075 err = __hw_perf_counter_init(counter);
1076 if (err)
1077 return ERR_PTR(err);
1078
1079 return &pmu;
1080 }
1081
1082 /*
1083 * callchain support
1084 */
1085
1086 static inline
1087 void callchain_store(struct perf_callchain_entry *entry, unsigned long ip)
1088 {
1089 if (entry->nr < MAX_STACK_DEPTH)
1090 entry->ip[entry->nr++] = ip;
1091 }
1092
1093 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1094 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1095
1096
1097 static void
1098 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1099 {
1100 /* Ignore warnings */
1101 }
1102
1103 static void backtrace_warning(void *data, char *msg)
1104 {
1105 /* Ignore warnings */
1106 }
1107
1108 static int backtrace_stack(void *data, char *name)
1109 {
1110 /* Don't bother with IRQ stacks for now */
1111 return -1;
1112 }
1113
1114 static void backtrace_address(void *data, unsigned long addr, int reliable)
1115 {
1116 struct perf_callchain_entry *entry = data;
1117
1118 if (reliable)
1119 callchain_store(entry, addr);
1120 }
1121
1122 static const struct stacktrace_ops backtrace_ops = {
1123 .warning = backtrace_warning,
1124 .warning_symbol = backtrace_warning_symbol,
1125 .stack = backtrace_stack,
1126 .address = backtrace_address,
1127 };
1128
1129 static void
1130 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1131 {
1132 unsigned long bp;
1133 char *stack;
1134 int nr = entry->nr;
1135
1136 callchain_store(entry, instruction_pointer(regs));
1137
1138 stack = ((char *)regs + sizeof(struct pt_regs));
1139 #ifdef CONFIG_FRAME_POINTER
1140 bp = frame_pointer(regs);
1141 #else
1142 bp = 0;
1143 #endif
1144
1145 dump_trace(NULL, regs, (void *)stack, bp, &backtrace_ops, entry);
1146
1147 entry->kernel = entry->nr - nr;
1148 }
1149
1150
1151 struct stack_frame {
1152 const void __user *next_fp;
1153 unsigned long return_address;
1154 };
1155
1156 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1157 {
1158 int ret;
1159
1160 if (!access_ok(VERIFY_READ, fp, sizeof(*frame)))
1161 return 0;
1162
1163 ret = 1;
1164 pagefault_disable();
1165 if (__copy_from_user_inatomic(frame, fp, sizeof(*frame)))
1166 ret = 0;
1167 pagefault_enable();
1168
1169 return ret;
1170 }
1171
1172 static void
1173 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1174 {
1175 struct stack_frame frame;
1176 const void __user *fp;
1177 int nr = entry->nr;
1178
1179 regs = (struct pt_regs *)current->thread.sp0 - 1;
1180 fp = (void __user *)regs->bp;
1181
1182 callchain_store(entry, regs->ip);
1183
1184 while (entry->nr < MAX_STACK_DEPTH) {
1185 frame.next_fp = NULL;
1186 frame.return_address = 0;
1187
1188 if (!copy_stack_frame(fp, &frame))
1189 break;
1190
1191 if ((unsigned long)fp < user_stack_pointer(regs))
1192 break;
1193
1194 callchain_store(entry, frame.return_address);
1195 fp = frame.next_fp;
1196 }
1197
1198 entry->user = entry->nr - nr;
1199 }
1200
1201 static void
1202 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1203 {
1204 int is_user;
1205
1206 if (!regs)
1207 return;
1208
1209 is_user = user_mode(regs);
1210
1211 if (!current || current->pid == 0)
1212 return;
1213
1214 if (is_user && current->state != TASK_RUNNING)
1215 return;
1216
1217 if (!is_user)
1218 perf_callchain_kernel(regs, entry);
1219
1220 if (current->mm)
1221 perf_callchain_user(regs, entry);
1222 }
1223
1224 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1225 {
1226 struct perf_callchain_entry *entry;
1227
1228 if (in_nmi())
1229 entry = &__get_cpu_var(nmi_entry);
1230 else
1231 entry = &__get_cpu_var(irq_entry);
1232
1233 entry->nr = 0;
1234 entry->hv = 0;
1235 entry->kernel = 0;
1236 entry->user = 0;
1237
1238 perf_do_callchain(regs, entry);
1239
1240 return entry;
1241 }
Linux kernel - Deliverables
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