2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
10 * For licencing details see kernel-base/COPYING
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
22 #include <linux/highmem.h>
25 #include <asm/stacktrace.h>
28 static u64 perf_counter_mask __read_mostly
;
30 struct cpu_hw_counters
{
31 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
32 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
33 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
34 unsigned long interrupts
;
39 * struct x86_pmu - generic x86 pmu
44 int (*handle_irq
)(struct pt_regs
*);
45 void (*disable_all
)(void);
46 void (*enable_all
)(void);
47 void (*enable
)(struct hw_perf_counter
*, int);
48 void (*disable
)(struct hw_perf_counter
*, int);
51 u64 (*event_map
)(int);
52 u64 (*raw_event
)(u64
);
55 int num_counters_fixed
;
62 static struct x86_pmu x86_pmu __read_mostly
;
64 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
69 * Not sure about some of these
71 static const u64 p6_perfmon_event_map
[] =
73 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0079,
74 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
75 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x0000,
76 [PERF_COUNT_HW_CACHE_MISSES
] = 0x0000,
77 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
78 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
79 [PERF_COUNT_HW_BUS_CYCLES
] = 0x0062,
82 static u64
p6_pmu_event_map(int event
)
84 return p6_perfmon_event_map
[event
];
87 static u64
p6_pmu_raw_event(u64 event
)
89 #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
90 #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
91 #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
92 #define P6_EVNTSEL_INV_MASK 0x00800000ULL
93 #define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL
95 #define P6_EVNTSEL_MASK \
96 (P6_EVNTSEL_EVENT_MASK | \
97 P6_EVNTSEL_UNIT_MASK | \
98 P6_EVNTSEL_EDGE_MASK | \
99 P6_EVNTSEL_INV_MASK | \
100 P6_EVNTSEL_COUNTER_MASK)
102 return event
& P6_EVNTSEL_MASK
;
107 * Intel PerfMon v3. Used on Core2 and later.
109 static const u64 intel_perfmon_event_map
[] =
111 [PERF_COUNT_HW_CPU_CYCLES
] = 0x003c,
112 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
113 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x4f2e,
114 [PERF_COUNT_HW_CACHE_MISSES
] = 0x412e,
115 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
116 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
117 [PERF_COUNT_HW_BUS_CYCLES
] = 0x013c,
120 static u64
intel_pmu_event_map(int event
)
122 return intel_perfmon_event_map
[event
];
126 * Generalized hw caching related event table, filled
127 * in on a per model basis. A value of 0 means
128 * 'not supported', -1 means 'event makes no sense on
129 * this CPU', any other value means the raw event
133 #define C(x) PERF_COUNT_HW_CACHE_##x
135 static u64 __read_mostly hw_cache_event_ids
136 [PERF_COUNT_HW_CACHE_MAX
]
137 [PERF_COUNT_HW_CACHE_OP_MAX
]
138 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
140 static const u64 nehalem_hw_cache_event_ids
141 [PERF_COUNT_HW_CACHE_MAX
]
142 [PERF_COUNT_HW_CACHE_OP_MAX
]
143 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
147 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
148 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
151 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
152 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
154 [ C(OP_PREFETCH
) ] = {
155 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
156 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
161 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
162 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
165 [ C(RESULT_ACCESS
) ] = -1,
166 [ C(RESULT_MISS
) ] = -1,
168 [ C(OP_PREFETCH
) ] = {
169 [ C(RESULT_ACCESS
) ] = 0x0,
170 [ C(RESULT_MISS
) ] = 0x0,
175 [ C(RESULT_ACCESS
) ] = 0x0324, /* L2_RQSTS.LOADS */
176 [ C(RESULT_MISS
) ] = 0x0224, /* L2_RQSTS.LD_MISS */
179 [ C(RESULT_ACCESS
) ] = 0x0c24, /* L2_RQSTS.RFOS */
180 [ C(RESULT_MISS
) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
182 [ C(OP_PREFETCH
) ] = {
183 [ C(RESULT_ACCESS
) ] = 0x4f2e, /* LLC Reference */
184 [ C(RESULT_MISS
) ] = 0x412e, /* LLC Misses */
189 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
190 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
193 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
194 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
196 [ C(OP_PREFETCH
) ] = {
197 [ C(RESULT_ACCESS
) ] = 0x0,
198 [ C(RESULT_MISS
) ] = 0x0,
203 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
204 [ C(RESULT_MISS
) ] = 0x20c8, /* ITLB_MISS_RETIRED */
207 [ C(RESULT_ACCESS
) ] = -1,
208 [ C(RESULT_MISS
) ] = -1,
210 [ C(OP_PREFETCH
) ] = {
211 [ C(RESULT_ACCESS
) ] = -1,
212 [ C(RESULT_MISS
) ] = -1,
217 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
218 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
221 [ C(RESULT_ACCESS
) ] = -1,
222 [ C(RESULT_MISS
) ] = -1,
224 [ C(OP_PREFETCH
) ] = {
225 [ C(RESULT_ACCESS
) ] = -1,
226 [ C(RESULT_MISS
) ] = -1,
231 static const u64 core2_hw_cache_event_ids
232 [PERF_COUNT_HW_CACHE_MAX
]
233 [PERF_COUNT_HW_CACHE_OP_MAX
]
234 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
238 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
239 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
242 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
243 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
245 [ C(OP_PREFETCH
) ] = {
246 [ C(RESULT_ACCESS
) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
247 [ C(RESULT_MISS
) ] = 0,
252 [ C(RESULT_ACCESS
) ] = 0x0080, /* L1I.READS */
253 [ C(RESULT_MISS
) ] = 0x0081, /* L1I.MISSES */
256 [ C(RESULT_ACCESS
) ] = -1,
257 [ C(RESULT_MISS
) ] = -1,
259 [ C(OP_PREFETCH
) ] = {
260 [ C(RESULT_ACCESS
) ] = 0,
261 [ C(RESULT_MISS
) ] = 0,
266 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
267 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
270 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
271 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
273 [ C(OP_PREFETCH
) ] = {
274 [ C(RESULT_ACCESS
) ] = 0,
275 [ C(RESULT_MISS
) ] = 0,
280 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
281 [ C(RESULT_MISS
) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
284 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
285 [ C(RESULT_MISS
) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
287 [ C(OP_PREFETCH
) ] = {
288 [ C(RESULT_ACCESS
) ] = 0,
289 [ C(RESULT_MISS
) ] = 0,
294 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
295 [ C(RESULT_MISS
) ] = 0x1282, /* ITLBMISSES */
298 [ C(RESULT_ACCESS
) ] = -1,
299 [ C(RESULT_MISS
) ] = -1,
301 [ C(OP_PREFETCH
) ] = {
302 [ C(RESULT_ACCESS
) ] = -1,
303 [ C(RESULT_MISS
) ] = -1,
308 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
309 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
312 [ C(RESULT_ACCESS
) ] = -1,
313 [ C(RESULT_MISS
) ] = -1,
315 [ C(OP_PREFETCH
) ] = {
316 [ C(RESULT_ACCESS
) ] = -1,
317 [ C(RESULT_MISS
) ] = -1,
322 static const u64 atom_hw_cache_event_ids
323 [PERF_COUNT_HW_CACHE_MAX
]
324 [PERF_COUNT_HW_CACHE_OP_MAX
]
325 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
329 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE.LD */
330 [ C(RESULT_MISS
) ] = 0,
333 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE.ST */
334 [ C(RESULT_MISS
) ] = 0,
336 [ C(OP_PREFETCH
) ] = {
337 [ C(RESULT_ACCESS
) ] = 0x0,
338 [ C(RESULT_MISS
) ] = 0,
343 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
344 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
347 [ C(RESULT_ACCESS
) ] = -1,
348 [ C(RESULT_MISS
) ] = -1,
350 [ C(OP_PREFETCH
) ] = {
351 [ C(RESULT_ACCESS
) ] = 0,
352 [ C(RESULT_MISS
) ] = 0,
357 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
358 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
361 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
362 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
364 [ C(OP_PREFETCH
) ] = {
365 [ C(RESULT_ACCESS
) ] = 0,
366 [ C(RESULT_MISS
) ] = 0,
371 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
372 [ C(RESULT_MISS
) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
375 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
376 [ C(RESULT_MISS
) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
378 [ C(OP_PREFETCH
) ] = {
379 [ C(RESULT_ACCESS
) ] = 0,
380 [ C(RESULT_MISS
) ] = 0,
385 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
386 [ C(RESULT_MISS
) ] = 0x0282, /* ITLB.MISSES */
389 [ C(RESULT_ACCESS
) ] = -1,
390 [ C(RESULT_MISS
) ] = -1,
392 [ C(OP_PREFETCH
) ] = {
393 [ C(RESULT_ACCESS
) ] = -1,
394 [ C(RESULT_MISS
) ] = -1,
399 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
400 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
403 [ C(RESULT_ACCESS
) ] = -1,
404 [ C(RESULT_MISS
) ] = -1,
406 [ C(OP_PREFETCH
) ] = {
407 [ C(RESULT_ACCESS
) ] = -1,
408 [ C(RESULT_MISS
) ] = -1,
413 static u64
intel_pmu_raw_event(u64 event
)
415 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
416 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
417 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
418 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
419 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
421 #define CORE_EVNTSEL_MASK \
422 (CORE_EVNTSEL_EVENT_MASK | \
423 CORE_EVNTSEL_UNIT_MASK | \
424 CORE_EVNTSEL_EDGE_MASK | \
425 CORE_EVNTSEL_INV_MASK | \
426 CORE_EVNTSEL_COUNTER_MASK)
428 return event
& CORE_EVNTSEL_MASK
;
431 static const u64 amd_hw_cache_event_ids
432 [PERF_COUNT_HW_CACHE_MAX
]
433 [PERF_COUNT_HW_CACHE_OP_MAX
]
434 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
438 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
439 [ C(RESULT_MISS
) ] = 0x0041, /* Data Cache Misses */
442 [ C(RESULT_ACCESS
) ] = 0x0142, /* Data Cache Refills :system */
443 [ C(RESULT_MISS
) ] = 0,
445 [ C(OP_PREFETCH
) ] = {
446 [ C(RESULT_ACCESS
) ] = 0x0267, /* Data Prefetcher :attempts */
447 [ C(RESULT_MISS
) ] = 0x0167, /* Data Prefetcher :cancelled */
452 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction cache fetches */
453 [ C(RESULT_MISS
) ] = 0x0081, /* Instruction cache misses */
456 [ C(RESULT_ACCESS
) ] = -1,
457 [ C(RESULT_MISS
) ] = -1,
459 [ C(OP_PREFETCH
) ] = {
460 [ C(RESULT_ACCESS
) ] = 0x014B, /* Prefetch Instructions :Load */
461 [ C(RESULT_MISS
) ] = 0,
466 [ C(RESULT_ACCESS
) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
467 [ C(RESULT_MISS
) ] = 0x037E, /* L2 Cache Misses : IC+DC */
470 [ C(RESULT_ACCESS
) ] = 0x017F, /* L2 Fill/Writeback */
471 [ C(RESULT_MISS
) ] = 0,
473 [ C(OP_PREFETCH
) ] = {
474 [ C(RESULT_ACCESS
) ] = 0,
475 [ C(RESULT_MISS
) ] = 0,
480 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
481 [ C(RESULT_MISS
) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
484 [ C(RESULT_ACCESS
) ] = 0,
485 [ C(RESULT_MISS
) ] = 0,
487 [ C(OP_PREFETCH
) ] = {
488 [ C(RESULT_ACCESS
) ] = 0,
489 [ C(RESULT_MISS
) ] = 0,
494 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction fecthes */
495 [ C(RESULT_MISS
) ] = 0x0085, /* Instr. fetch ITLB misses */
498 [ C(RESULT_ACCESS
) ] = -1,
499 [ C(RESULT_MISS
) ] = -1,
501 [ C(OP_PREFETCH
) ] = {
502 [ C(RESULT_ACCESS
) ] = -1,
503 [ C(RESULT_MISS
) ] = -1,
508 [ C(RESULT_ACCESS
) ] = 0x00c2, /* Retired Branch Instr. */
509 [ C(RESULT_MISS
) ] = 0x00c3, /* Retired Mispredicted BI */
512 [ C(RESULT_ACCESS
) ] = -1,
513 [ C(RESULT_MISS
) ] = -1,
515 [ C(OP_PREFETCH
) ] = {
516 [ C(RESULT_ACCESS
) ] = -1,
517 [ C(RESULT_MISS
) ] = -1,
523 * AMD Performance Monitor K7 and later.
525 static const u64 amd_perfmon_event_map
[] =
527 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0076,
528 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
529 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x0080,
530 [PERF_COUNT_HW_CACHE_MISSES
] = 0x0081,
531 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
532 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
535 static u64
amd_pmu_event_map(int event
)
537 return amd_perfmon_event_map
[event
];
540 static u64
amd_pmu_raw_event(u64 event
)
542 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
543 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
544 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
545 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
546 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
548 #define K7_EVNTSEL_MASK \
549 (K7_EVNTSEL_EVENT_MASK | \
550 K7_EVNTSEL_UNIT_MASK | \
551 K7_EVNTSEL_EDGE_MASK | \
552 K7_EVNTSEL_INV_MASK | \
553 K7_EVNTSEL_COUNTER_MASK)
555 return event
& K7_EVNTSEL_MASK
;
559 * Propagate counter elapsed time into the generic counter.
560 * Can only be executed on the CPU where the counter is active.
561 * Returns the delta events processed.
564 x86_perf_counter_update(struct perf_counter
*counter
,
565 struct hw_perf_counter
*hwc
, int idx
)
567 int shift
= 64 - x86_pmu
.counter_bits
;
568 u64 prev_raw_count
, new_raw_count
;
572 * Careful: an NMI might modify the previous counter value.
574 * Our tactic to handle this is to first atomically read and
575 * exchange a new raw count - then add that new-prev delta
576 * count to the generic counter atomically:
579 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
580 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
582 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
583 new_raw_count
) != prev_raw_count
)
587 * Now we have the new raw value and have updated the prev
588 * timestamp already. We can now calculate the elapsed delta
589 * (counter-)time and add that to the generic counter.
591 * Careful, not all hw sign-extends above the physical width
594 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
597 atomic64_add(delta
, &counter
->count
);
598 atomic64_sub(delta
, &hwc
->period_left
);
600 return new_raw_count
;
603 static atomic_t active_counters
;
604 static DEFINE_MUTEX(pmc_reserve_mutex
);
606 static bool reserve_pmc_hardware(void)
610 if (nmi_watchdog
== NMI_LOCAL_APIC
)
611 disable_lapic_nmi_watchdog();
613 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
614 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
618 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
619 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
626 for (i
--; i
>= 0; i
--)
627 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
629 i
= x86_pmu
.num_counters
;
632 for (i
--; i
>= 0; i
--)
633 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
635 if (nmi_watchdog
== NMI_LOCAL_APIC
)
636 enable_lapic_nmi_watchdog();
641 static void release_pmc_hardware(void)
645 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
646 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
647 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
650 if (nmi_watchdog
== NMI_LOCAL_APIC
)
651 enable_lapic_nmi_watchdog();
654 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
656 if (atomic_dec_and_mutex_lock(&active_counters
, &pmc_reserve_mutex
)) {
657 release_pmc_hardware();
658 mutex_unlock(&pmc_reserve_mutex
);
662 static inline int x86_pmu_initialized(void)
664 return x86_pmu
.handle_irq
!= NULL
;
668 set_ext_hw_attr(struct hw_perf_counter
*hwc
, struct perf_counter_attr
*attr
)
670 unsigned int cache_type
, cache_op
, cache_result
;
673 config
= attr
->config
;
675 cache_type
= (config
>> 0) & 0xff;
676 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
679 cache_op
= (config
>> 8) & 0xff;
680 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
683 cache_result
= (config
>> 16) & 0xff;
684 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
687 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
701 * Setup the hardware configuration for a given attr_type
703 static int __hw_perf_counter_init(struct perf_counter
*counter
)
705 struct perf_counter_attr
*attr
= &counter
->attr
;
706 struct hw_perf_counter
*hwc
= &counter
->hw
;
709 if (!x86_pmu_initialized())
713 if (!atomic_inc_not_zero(&active_counters
)) {
714 mutex_lock(&pmc_reserve_mutex
);
715 if (atomic_read(&active_counters
) == 0 && !reserve_pmc_hardware())
718 atomic_inc(&active_counters
);
719 mutex_unlock(&pmc_reserve_mutex
);
726 * (keep 'enabled' bit clear for now)
728 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
731 * Count user and OS events unless requested not to.
733 if (!attr
->exclude_user
)
734 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
735 if (!attr
->exclude_kernel
)
736 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
738 if (!hwc
->sample_period
) {
739 hwc
->sample_period
= x86_pmu
.max_period
;
740 hwc
->last_period
= hwc
->sample_period
;
741 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
744 counter
->destroy
= hw_perf_counter_destroy
;
747 * Raw event type provide the config in the event structure
749 if (attr
->type
== PERF_TYPE_RAW
) {
750 hwc
->config
|= x86_pmu
.raw_event(attr
->config
);
754 if (attr
->type
== PERF_TYPE_HW_CACHE
)
755 return set_ext_hw_attr(hwc
, attr
);
757 if (attr
->config
>= x86_pmu
.max_events
)
762 hwc
->config
|= x86_pmu
.event_map(attr
->config
);
767 static void p6_pmu_disable_all(void)
769 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
778 /* p6 only has one enable register */
779 rdmsrl(MSR_P6_EVNTSEL0
, val
);
780 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
781 wrmsrl(MSR_P6_EVNTSEL0
, val
);
784 static void intel_pmu_disable_all(void)
786 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
789 static void amd_pmu_disable_all(void)
791 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
799 * ensure we write the disable before we start disabling the
800 * counters proper, so that amd_pmu_enable_counter() does the
805 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
808 if (!test_bit(idx
, cpuc
->active_mask
))
810 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
811 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
813 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
814 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
818 void hw_perf_disable(void)
820 if (!x86_pmu_initialized())
822 return x86_pmu
.disable_all();
825 static void p6_pmu_enable_all(void)
827 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
836 /* p6 only has one enable register */
837 rdmsrl(MSR_P6_EVNTSEL0
, val
);
838 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
839 wrmsrl(MSR_P6_EVNTSEL0
, val
);
842 static void intel_pmu_enable_all(void)
844 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, x86_pmu
.intel_ctrl
);
847 static void amd_pmu_enable_all(void)
849 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
858 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
861 if (!test_bit(idx
, cpuc
->active_mask
))
863 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
864 if (val
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
866 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
867 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
871 void hw_perf_enable(void)
873 if (!x86_pmu_initialized())
875 x86_pmu
.enable_all();
878 static inline u64
intel_pmu_get_status(void)
882 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
887 static inline void intel_pmu_ack_status(u64 ack
)
889 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
892 static inline void x86_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
894 (void)checking_wrmsrl(hwc
->config_base
+ idx
,
895 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
898 static inline void x86_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
900 (void)checking_wrmsrl(hwc
->config_base
+ idx
, hwc
->config
);
904 intel_pmu_disable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
906 int idx
= __idx
- X86_PMC_IDX_FIXED
;
909 mask
= 0xfULL
<< (idx
* 4);
911 rdmsrl(hwc
->config_base
, ctrl_val
);
913 (void)checking_wrmsrl(hwc
->config_base
, ctrl_val
);
917 p6_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
919 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
920 unsigned long val
= ARCH_PERFMON_EVENTSEL0_ENABLE
;
925 (void)checking_wrmsrl(hwc
->config_base
+ idx
, val
);
929 intel_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
931 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
932 intel_pmu_disable_fixed(hwc
, idx
);
936 x86_pmu_disable_counter(hwc
, idx
);
940 amd_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
942 x86_pmu_disable_counter(hwc
, idx
);
945 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
948 * Set the next IRQ period, based on the hwc->period_left value.
949 * To be called with the counter disabled in hw:
952 x86_perf_counter_set_period(struct perf_counter
*counter
,
953 struct hw_perf_counter
*hwc
, int idx
)
955 s64 left
= atomic64_read(&hwc
->period_left
);
956 s64 period
= hwc
->sample_period
;
960 * If we are way outside a reasoable range then just skip forward:
962 if (unlikely(left
<= -period
)) {
964 atomic64_set(&hwc
->period_left
, left
);
965 hwc
->last_period
= period
;
969 if (unlikely(left
<= 0)) {
971 atomic64_set(&hwc
->period_left
, left
);
972 hwc
->last_period
= period
;
976 * Quirk: certain CPUs dont like it if just 1 event is left:
978 if (unlikely(left
< 2))
981 if (left
> x86_pmu
.max_period
)
982 left
= x86_pmu
.max_period
;
984 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
987 * The hw counter starts counting from this counter offset,
988 * mark it to be able to extra future deltas:
990 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
992 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
993 (u64
)(-left
) & x86_pmu
.counter_mask
);
995 perf_counter_update_userpage(counter
);
1001 intel_pmu_enable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
1003 int idx
= __idx
- X86_PMC_IDX_FIXED
;
1004 u64 ctrl_val
, bits
, mask
;
1008 * Enable IRQ generation (0x8),
1009 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1013 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
1015 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
1018 mask
= 0xfULL
<< (idx
* 4);
1020 rdmsrl(hwc
->config_base
, ctrl_val
);
1023 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
1026 static void p6_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1028 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1031 x86_pmu_enable_counter(hwc
, idx
);
1033 x86_pmu_disable_counter(hwc
, idx
);
1037 static void intel_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1039 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
1040 intel_pmu_enable_fixed(hwc
, idx
);
1044 x86_pmu_enable_counter(hwc
, idx
);
1047 static void amd_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1049 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1052 x86_pmu_enable_counter(hwc
, idx
);
1054 x86_pmu_disable_counter(hwc
, idx
);
1058 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
1062 if (!x86_pmu
.num_counters_fixed
)
1065 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
1067 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_INSTRUCTIONS
)))
1068 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
1069 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_CPU_CYCLES
)))
1070 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
1071 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_BUS_CYCLES
)))
1072 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
1078 * Find a PMC slot for the freshly enabled / scheduled in counter:
1080 static int x86_pmu_enable(struct perf_counter
*counter
)
1082 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1083 struct hw_perf_counter
*hwc
= &counter
->hw
;
1086 idx
= fixed_mode_idx(counter
, hwc
);
1089 * Try to get the fixed counter, if that is already taken
1090 * then try to get a generic counter:
1092 if (test_and_set_bit(idx
, cpuc
->used_mask
))
1095 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1097 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1098 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1101 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
1105 /* Try to get the previous generic counter again */
1106 if (test_and_set_bit(idx
, cpuc
->used_mask
)) {
1108 idx
= find_first_zero_bit(cpuc
->used_mask
,
1109 x86_pmu
.num_counters
);
1110 if (idx
== x86_pmu
.num_counters
)
1113 set_bit(idx
, cpuc
->used_mask
);
1116 hwc
->config_base
= x86_pmu
.eventsel
;
1117 hwc
->counter_base
= x86_pmu
.perfctr
;
1120 perf_counters_lapic_init();
1122 x86_pmu
.disable(hwc
, idx
);
1124 cpuc
->counters
[idx
] = counter
;
1125 set_bit(idx
, cpuc
->active_mask
);
1127 x86_perf_counter_set_period(counter
, hwc
, idx
);
1128 x86_pmu
.enable(hwc
, idx
);
1130 perf_counter_update_userpage(counter
);
1135 static void x86_pmu_unthrottle(struct perf_counter
*counter
)
1137 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1138 struct hw_perf_counter
*hwc
= &counter
->hw
;
1140 if (WARN_ON_ONCE(hwc
->idx
>= X86_PMC_IDX_MAX
||
1141 cpuc
->counters
[hwc
->idx
] != counter
))
1144 x86_pmu
.enable(hwc
, hwc
->idx
);
1147 void perf_counter_print_debug(void)
1149 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1150 struct cpu_hw_counters
*cpuc
;
1151 unsigned long flags
;
1154 if (!x86_pmu
.num_counters
)
1157 local_irq_save(flags
);
1159 cpu
= smp_processor_id();
1160 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
1162 if (x86_pmu
.version
>= 2) {
1163 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1164 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1165 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1166 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1169 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1170 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1171 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1172 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1174 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used_mask
);
1176 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1177 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1178 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1180 prev_left
= per_cpu(prev_left
[idx
], cpu
);
1182 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1183 cpu
, idx
, pmc_ctrl
);
1184 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1185 cpu
, idx
, pmc_count
);
1186 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1187 cpu
, idx
, prev_left
);
1189 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1190 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1192 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1193 cpu
, idx
, pmc_count
);
1195 local_irq_restore(flags
);
1198 static void x86_pmu_disable(struct perf_counter
*counter
)
1200 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1201 struct hw_perf_counter
*hwc
= &counter
->hw
;
1205 * Must be done before we disable, otherwise the nmi handler
1206 * could reenable again:
1208 clear_bit(idx
, cpuc
->active_mask
);
1209 x86_pmu
.disable(hwc
, idx
);
1212 * Make sure the cleared pointer becomes visible before we
1213 * (potentially) free the counter:
1218 * Drain the remaining delta count out of a counter
1219 * that we are disabling:
1221 x86_perf_counter_update(counter
, hwc
, idx
);
1222 cpuc
->counters
[idx
] = NULL
;
1223 clear_bit(idx
, cpuc
->used_mask
);
1225 perf_counter_update_userpage(counter
);
1229 * Save and restart an expired counter. Called by NMI contexts,
1230 * so it has to be careful about preempting normal counter ops:
1232 static int intel_pmu_save_and_restart(struct perf_counter
*counter
)
1234 struct hw_perf_counter
*hwc
= &counter
->hw
;
1238 x86_perf_counter_update(counter
, hwc
, idx
);
1239 ret
= x86_perf_counter_set_period(counter
, hwc
, idx
);
1241 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
1242 intel_pmu_enable_counter(hwc
, idx
);
1247 static void intel_pmu_reset(void)
1249 unsigned long flags
;
1252 if (!x86_pmu
.num_counters
)
1255 local_irq_save(flags
);
1257 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1259 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1260 checking_wrmsrl(x86_pmu
.eventsel
+ idx
, 0ull);
1261 checking_wrmsrl(x86_pmu
.perfctr
+ idx
, 0ull);
1263 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1264 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, 0ull);
1267 local_irq_restore(flags
);
1270 static int p6_pmu_handle_irq(struct pt_regs
*regs
)
1272 struct perf_sample_data data
;
1273 struct cpu_hw_counters
*cpuc
;
1274 struct perf_counter
*counter
;
1275 struct hw_perf_counter
*hwc
;
1276 int idx
, handled
= 0;
1282 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1284 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1285 if (!test_bit(idx
, cpuc
->active_mask
))
1288 counter
= cpuc
->counters
[idx
];
1291 val
= x86_perf_counter_update(counter
, hwc
, idx
);
1292 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
1299 data
.period
= counter
->hw
.last_period
;
1301 if (!x86_perf_counter_set_period(counter
, hwc
, idx
))
1304 if (perf_counter_overflow(counter
, 1, &data
))
1305 p6_pmu_disable_counter(hwc
, idx
);
1309 inc_irq_stat(apic_perf_irqs
);
1315 * This handler is triggered by the local APIC, so the APIC IRQ handling
1318 static int intel_pmu_handle_irq(struct pt_regs
*regs
)
1320 struct perf_sample_data data
;
1321 struct cpu_hw_counters
*cpuc
;
1328 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1331 status
= intel_pmu_get_status();
1339 if (++loops
> 100) {
1340 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
1341 perf_counter_print_debug();
1347 inc_irq_stat(apic_perf_irqs
);
1349 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
1350 struct perf_counter
*counter
= cpuc
->counters
[bit
];
1352 clear_bit(bit
, (unsigned long *) &status
);
1353 if (!test_bit(bit
, cpuc
->active_mask
))
1356 if (!intel_pmu_save_and_restart(counter
))
1359 data
.period
= counter
->hw
.last_period
;
1361 if (perf_counter_overflow(counter
, 1, &data
))
1362 intel_pmu_disable_counter(&counter
->hw
, bit
);
1365 intel_pmu_ack_status(ack
);
1368 * Repeat if there is more work to be done:
1370 status
= intel_pmu_get_status();
1379 static int amd_pmu_handle_irq(struct pt_regs
*regs
)
1381 struct perf_sample_data data
;
1382 struct cpu_hw_counters
*cpuc
;
1383 struct perf_counter
*counter
;
1384 struct hw_perf_counter
*hwc
;
1385 int idx
, handled
= 0;
1391 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1393 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1394 if (!test_bit(idx
, cpuc
->active_mask
))
1397 counter
= cpuc
->counters
[idx
];
1400 val
= x86_perf_counter_update(counter
, hwc
, idx
);
1401 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
1408 data
.period
= counter
->hw
.last_period
;
1410 if (!x86_perf_counter_set_period(counter
, hwc
, idx
))
1413 if (perf_counter_overflow(counter
, 1, &data
))
1414 amd_pmu_disable_counter(hwc
, idx
);
1418 inc_irq_stat(apic_perf_irqs
);
1423 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1427 inc_irq_stat(apic_pending_irqs
);
1428 perf_counter_do_pending();
1432 void set_perf_counter_pending(void)
1434 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1437 void perf_counters_lapic_init(void)
1439 if (!x86_pmu_initialized())
1443 * Always use NMI for PMU
1445 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1448 static int __kprobes
1449 perf_counter_nmi_handler(struct notifier_block
*self
,
1450 unsigned long cmd
, void *__args
)
1452 struct die_args
*args
= __args
;
1453 struct pt_regs
*regs
;
1455 if (!atomic_read(&active_counters
))
1469 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1471 * Can't rely on the handled return value to say it was our NMI, two
1472 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1474 * If the first NMI handles both, the latter will be empty and daze
1477 x86_pmu
.handle_irq(regs
);
1482 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
1483 .notifier_call
= perf_counter_nmi_handler
,
1488 static struct x86_pmu p6_pmu
= {
1490 .handle_irq
= p6_pmu_handle_irq
,
1491 .disable_all
= p6_pmu_disable_all
,
1492 .enable_all
= p6_pmu_enable_all
,
1493 .enable
= p6_pmu_enable_counter
,
1494 .disable
= p6_pmu_disable_counter
,
1495 .eventsel
= MSR_P6_EVNTSEL0
,
1496 .perfctr
= MSR_P6_PERFCTR0
,
1497 .event_map
= p6_pmu_event_map
,
1498 .raw_event
= p6_pmu_raw_event
,
1499 .max_events
= ARRAY_SIZE(p6_perfmon_event_map
),
1500 .max_period
= (1ULL << 31) - 1,
1504 * Counters have 40 bits implemented. However they are designed such
1505 * that bits [32-39] are sign extensions of bit 31. As such the
1506 * effective width of a counter for P6-like PMU is 32 bits only.
1508 * See IA-32 Intel Architecture Software developer manual Vol 3B
1511 .counter_mask
= (1ULL << 32) - 1,
1514 static struct x86_pmu intel_pmu
= {
1516 .handle_irq
= intel_pmu_handle_irq
,
1517 .disable_all
= intel_pmu_disable_all
,
1518 .enable_all
= intel_pmu_enable_all
,
1519 .enable
= intel_pmu_enable_counter
,
1520 .disable
= intel_pmu_disable_counter
,
1521 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
1522 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
1523 .event_map
= intel_pmu_event_map
,
1524 .raw_event
= intel_pmu_raw_event
,
1525 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
1527 * Intel PMCs cannot be accessed sanely above 32 bit width,
1528 * so we install an artificial 1<<31 period regardless of
1529 * the generic counter period:
1531 .max_period
= (1ULL << 31) - 1,
1534 static struct x86_pmu amd_pmu
= {
1536 .handle_irq
= amd_pmu_handle_irq
,
1537 .disable_all
= amd_pmu_disable_all
,
1538 .enable_all
= amd_pmu_enable_all
,
1539 .enable
= amd_pmu_enable_counter
,
1540 .disable
= amd_pmu_disable_counter
,
1541 .eventsel
= MSR_K7_EVNTSEL0
,
1542 .perfctr
= MSR_K7_PERFCTR0
,
1543 .event_map
= amd_pmu_event_map
,
1544 .raw_event
= amd_pmu_raw_event
,
1545 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
1548 .counter_mask
= (1ULL << 48) - 1,
1549 /* use highest bit to detect overflow */
1550 .max_period
= (1ULL << 47) - 1,
1553 static int p6_pmu_init(void)
1557 switch (boot_cpu_data
.x86_model
) {
1559 case 3: /* Pentium Pro */
1561 case 6: /* Pentium II */
1564 case 11: /* Pentium III */
1568 /* for Pentium M, we need to check if PMU exist */
1569 rdmsr(MSR_IA32_MISC_ENABLE
, low
, high
);
1570 if (low
& MSR_IA32_MISC_ENABLE_EMON
)
1573 pr_cont("unsupported p6 CPU model %d ",
1574 boot_cpu_data
.x86_model
);
1578 if (!cpu_has_apic
) {
1579 pr_info("no Local APIC, try rebooting with lapic");
1588 static int intel_pmu_init(void)
1590 union cpuid10_edx edx
;
1591 union cpuid10_eax eax
;
1592 unsigned int unused
;
1596 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
)) {
1597 /* check for P6 processor family */
1598 if (boot_cpu_data
.x86
== 6) {
1599 return p6_pmu_init();
1606 * Check whether the Architectural PerfMon supports
1607 * Branch Misses Retired Event or not.
1609 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
1610 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
1613 version
= eax
.split
.version_id
;
1617 x86_pmu
= intel_pmu
;
1618 x86_pmu
.version
= version
;
1619 x86_pmu
.num_counters
= eax
.split
.num_counters
;
1620 x86_pmu
.counter_bits
= eax
.split
.bit_width
;
1621 x86_pmu
.counter_mask
= (1ULL << eax
.split
.bit_width
) - 1;
1624 * Quirk: v2 perfmon does not report fixed-purpose counters, so
1625 * assume at least 3 counters:
1627 x86_pmu
.num_counters_fixed
= max((int)edx
.split
.num_counters_fixed
, 3);
1630 * Install the hw-cache-events table:
1632 switch (boot_cpu_data
.x86_model
) {
1633 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1634 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1635 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1636 case 29: /* six-core 45 nm xeon "Dunnington" */
1637 memcpy(hw_cache_event_ids
, core2_hw_cache_event_ids
,
1638 sizeof(hw_cache_event_ids
));
1640 pr_cont("Core2 events, ");
1644 memcpy(hw_cache_event_ids
, nehalem_hw_cache_event_ids
,
1645 sizeof(hw_cache_event_ids
));
1647 pr_cont("Nehalem/Corei7 events, ");
1650 memcpy(hw_cache_event_ids
, atom_hw_cache_event_ids
,
1651 sizeof(hw_cache_event_ids
));
1653 pr_cont("Atom events, ");
1659 static int amd_pmu_init(void)
1661 /* Performance-monitoring supported from K7 and later: */
1662 if (boot_cpu_data
.x86
< 6)
1667 /* Events are common for all AMDs */
1668 memcpy(hw_cache_event_ids
, amd_hw_cache_event_ids
,
1669 sizeof(hw_cache_event_ids
));
1674 void __init
init_hw_perf_counters(void)
1678 pr_info("Performance Counters: ");
1680 switch (boot_cpu_data
.x86_vendor
) {
1681 case X86_VENDOR_INTEL
:
1682 err
= intel_pmu_init();
1684 case X86_VENDOR_AMD
:
1685 err
= amd_pmu_init();
1691 pr_cont("no PMU driver, software counters only.\n");
1695 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1697 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1698 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
1699 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1700 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1702 perf_counter_mask
= (1 << x86_pmu
.num_counters
) - 1;
1703 perf_max_counters
= x86_pmu
.num_counters
;
1705 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1706 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
1707 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1708 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1711 perf_counter_mask
|=
1712 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1713 x86_pmu
.intel_ctrl
= perf_counter_mask
;
1715 perf_counters_lapic_init();
1716 register_die_notifier(&perf_counter_nmi_notifier
);
1718 pr_info("... version: %d\n", x86_pmu
.version
);
1719 pr_info("... bit width: %d\n", x86_pmu
.counter_bits
);
1720 pr_info("... generic counters: %d\n", x86_pmu
.num_counters
);
1721 pr_info("... value mask: %016Lx\n", x86_pmu
.counter_mask
);
1722 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1723 pr_info("... fixed-purpose counters: %d\n", x86_pmu
.num_counters_fixed
);
1724 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
1727 static inline void x86_pmu_read(struct perf_counter
*counter
)
1729 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1732 static const struct pmu pmu
= {
1733 .enable
= x86_pmu_enable
,
1734 .disable
= x86_pmu_disable
,
1735 .read
= x86_pmu_read
,
1736 .unthrottle
= x86_pmu_unthrottle
,
1739 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1743 err
= __hw_perf_counter_init(counter
);
1745 return ERR_PTR(err
);
1755 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
1757 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
1758 entry
->ip
[entry
->nr
++] = ip
;
1761 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1762 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1763 static DEFINE_PER_CPU(int, in_nmi_frame
);
1767 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1769 /* Ignore warnings */
1772 static void backtrace_warning(void *data
, char *msg
)
1774 /* Ignore warnings */
1777 static int backtrace_stack(void *data
, char *name
)
1779 per_cpu(in_nmi_frame
, smp_processor_id()) =
1780 x86_is_stack_id(NMI_STACK
, name
);
1785 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1787 struct perf_callchain_entry
*entry
= data
;
1789 if (per_cpu(in_nmi_frame
, smp_processor_id()))
1793 callchain_store(entry
, addr
);
1796 static const struct stacktrace_ops backtrace_ops
= {
1797 .warning
= backtrace_warning
,
1798 .warning_symbol
= backtrace_warning_symbol
,
1799 .stack
= backtrace_stack
,
1800 .address
= backtrace_address
,
1803 #include "../dumpstack.h"
1806 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1808 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
1809 callchain_store(entry
, regs
->ip
);
1811 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
1815 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1817 static unsigned long
1818 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
1820 unsigned long offset
, addr
= (unsigned long)from
;
1821 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
1822 unsigned long size
, len
= 0;
1828 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
1832 offset
= addr
& (PAGE_SIZE
- 1);
1833 size
= min(PAGE_SIZE
- offset
, n
- len
);
1835 map
= kmap_atomic(page
, type
);
1836 memcpy(to
, map
+offset
, size
);
1837 kunmap_atomic(map
, type
);
1849 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1851 unsigned long bytes
;
1853 bytes
= copy_from_user_nmi(frame
, fp
, sizeof(*frame
));
1855 return bytes
== sizeof(*frame
);
1859 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1861 struct stack_frame frame
;
1862 const void __user
*fp
;
1864 if (!user_mode(regs
))
1865 regs
= task_pt_regs(current
);
1867 fp
= (void __user
*)regs
->bp
;
1869 callchain_store(entry
, PERF_CONTEXT_USER
);
1870 callchain_store(entry
, regs
->ip
);
1872 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1873 frame
.next_frame
= NULL
;
1874 frame
.return_address
= 0;
1876 if (!copy_stack_frame(fp
, &frame
))
1879 if ((unsigned long)fp
< regs
->sp
)
1882 callchain_store(entry
, frame
.return_address
);
1883 fp
= frame
.next_frame
;
1888 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1895 is_user
= user_mode(regs
);
1897 if (!current
|| current
->pid
== 0)
1900 if (is_user
&& current
->state
!= TASK_RUNNING
)
1904 perf_callchain_kernel(regs
, entry
);
1907 perf_callchain_user(regs
, entry
);
1910 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1912 struct perf_callchain_entry
*entry
;
1915 entry
= &__get_cpu_var(nmi_entry
);
1917 entry
= &__get_cpu_var(irq_entry
);
1921 perf_do_callchain(regs
, entry
);