2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
7 * For licencing details see kernel-base/COPYING
10 #include <linux/perf_counter.h>
11 #include <linux/capability.h>
12 #include <linux/notifier.h>
13 #include <linux/hardirq.h>
14 #include <linux/kprobes.h>
15 #include <linux/module.h>
16 #include <linux/kdebug.h>
17 #include <linux/sched.h>
19 #include <asm/perf_counter.h>
22 static bool perf_counters_initialized __read_mostly
;
25 * Number of (generic) HW counters:
27 static int nr_counters_generic __read_mostly
;
28 static u64 perf_counter_mask __read_mostly
;
29 static u64 counter_value_mask __read_mostly
;
31 static int nr_counters_fixed __read_mostly
;
33 struct cpu_hw_counters
{
34 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
35 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
42 * Intel PerfMon v3. Used on Core2 and later.
44 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
);
46 static const int intel_perfmon_event_map
[] =
48 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
49 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
50 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
51 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
52 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
53 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
54 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
57 static const int max_intel_perfmon_events
= ARRAY_SIZE(intel_perfmon_event_map
);
60 * Propagate counter elapsed time into the generic counter.
61 * Can only be executed on the CPU where the counter is active.
62 * Returns the delta events processed.
65 x86_perf_counter_update(struct perf_counter
*counter
,
66 struct hw_perf_counter
*hwc
, int idx
)
68 u64 prev_raw_count
, new_raw_count
, delta
;
71 * Careful: an NMI might modify the previous counter value.
73 * Our tactic to handle this is to first atomically read and
74 * exchange a new raw count - then add that new-prev delta
75 * count to the generic counter atomically:
78 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
79 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
81 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
82 new_raw_count
) != prev_raw_count
)
86 * Now we have the new raw value and have updated the prev
87 * timestamp already. We can now calculate the elapsed delta
88 * (counter-)time and add that to the generic counter.
90 * Careful, not all hw sign-extends above the physical width
91 * of the count, so we do that by clipping the delta to 32 bits:
93 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
95 atomic64_add(delta
, &counter
->count
);
96 atomic64_sub(delta
, &hwc
->period_left
);
100 * Setup the hardware configuration for a given hw_event_type
102 static int __hw_perf_counter_init(struct perf_counter
*counter
)
104 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
105 struct hw_perf_counter
*hwc
= &counter
->hw
;
107 if (unlikely(!perf_counters_initialized
))
111 * Count user events, and generate PMC IRQs:
112 * (keep 'enabled' bit clear for now)
114 hwc
->config
= ARCH_PERFMON_EVENTSEL_USR
| ARCH_PERFMON_EVENTSEL_INT
;
117 * If privileged enough, count OS events too, and allow
118 * NMI events as well:
121 if (capable(CAP_SYS_ADMIN
)) {
122 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
127 hwc
->irq_period
= hw_event
->irq_period
;
129 * Intel PMCs cannot be accessed sanely above 32 bit width,
130 * so we install an artificial 1<<31 period regardless of
131 * the generic counter period:
133 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
134 hwc
->irq_period
= 0x7FFFFFFF;
136 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
139 * Raw event type provide the config in the event structure
142 hwc
->config
|= hw_event
->type
;
144 if (hw_event
->type
>= max_intel_perfmon_events
)
149 hwc
->config
|= intel_perfmon_event_map
[hw_event
->type
];
151 counter
->wakeup_pending
= 0;
156 u64
hw_perf_save_disable(void)
160 if (unlikely(!perf_counters_initialized
))
163 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
164 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
168 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
170 void hw_perf_restore(u64 ctrl
)
172 if (unlikely(!perf_counters_initialized
))
175 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
177 EXPORT_SYMBOL_GPL(hw_perf_restore
);
180 __pmc_fixed_disable(struct perf_counter
*counter
,
181 struct hw_perf_counter
*hwc
, unsigned int __idx
)
183 int idx
= __idx
- X86_PMC_IDX_FIXED
;
187 mask
= 0xfULL
<< (idx
* 4);
189 rdmsrl(hwc
->config_base
, ctrl_val
);
191 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
195 __pmc_generic_disable(struct perf_counter
*counter
,
196 struct hw_perf_counter
*hwc
, unsigned int idx
)
198 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
199 __pmc_fixed_disable(counter
, hwc
, idx
);
201 wrmsr_safe(hwc
->config_base
+ idx
, hwc
->config
, 0);
204 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
207 * Set the next IRQ period, based on the hwc->period_left value.
208 * To be called with the counter disabled in hw:
211 __hw_perf_counter_set_period(struct perf_counter
*counter
,
212 struct hw_perf_counter
*hwc
, int idx
)
214 s64 left
= atomic64_read(&hwc
->period_left
);
215 s32 period
= hwc
->irq_period
;
219 * If we are way outside a reasoable range then just skip forward:
221 if (unlikely(left
<= -period
)) {
223 atomic64_set(&hwc
->period_left
, left
);
226 if (unlikely(left
<= 0)) {
228 atomic64_set(&hwc
->period_left
, left
);
231 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
234 * The hw counter starts counting from this counter offset,
235 * mark it to be able to extra future deltas:
237 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
239 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
240 (u64
)(-left
) & counter_value_mask
);
244 __pmc_fixed_enable(struct perf_counter
*counter
,
245 struct hw_perf_counter
*hwc
, unsigned int __idx
)
247 int idx
= __idx
- X86_PMC_IDX_FIXED
;
248 u64 ctrl_val
, bits
, mask
;
252 * Enable IRQ generation (0x8) and ring-3 counting (0x2),
253 * and enable ring-0 counting if allowed:
255 bits
= 0x8ULL
| 0x2ULL
;
256 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
259 mask
= 0xfULL
<< (idx
* 4);
261 rdmsrl(hwc
->config_base
, ctrl_val
);
264 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
268 __pmc_generic_enable(struct perf_counter
*counter
,
269 struct hw_perf_counter
*hwc
, int idx
)
271 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
272 __pmc_fixed_enable(counter
, hwc
, idx
);
274 wrmsr(hwc
->config_base
+ idx
,
275 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
, 0);
279 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
283 if (unlikely(hwc
->nmi
))
286 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
288 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_INSTRUCTIONS
]))
289 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
290 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_CPU_CYCLES
]))
291 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
292 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_BUS_CYCLES
]))
293 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
299 * Find a PMC slot for the freshly enabled / scheduled in counter:
301 static int pmc_generic_enable(struct perf_counter
*counter
)
303 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
304 struct hw_perf_counter
*hwc
= &counter
->hw
;
307 idx
= fixed_mode_idx(counter
, hwc
);
310 * Try to get the fixed counter, if that is already taken
311 * then try to get a generic counter:
313 if (test_and_set_bit(idx
, cpuc
->used
))
316 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
318 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
319 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
322 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
326 /* Try to get the previous generic counter again */
327 if (test_and_set_bit(idx
, cpuc
->used
)) {
329 idx
= find_first_zero_bit(cpuc
->used
, nr_counters_generic
);
330 if (idx
== nr_counters_generic
)
333 set_bit(idx
, cpuc
->used
);
336 hwc
->config_base
= MSR_ARCH_PERFMON_EVENTSEL0
;
337 hwc
->counter_base
= MSR_ARCH_PERFMON_PERFCTR0
;
340 perf_counters_lapic_init(hwc
->nmi
);
342 __pmc_generic_disable(counter
, hwc
, idx
);
344 cpuc
->counters
[idx
] = counter
;
346 * Make it visible before enabling the hw:
350 __hw_perf_counter_set_period(counter
, hwc
, idx
);
351 __pmc_generic_enable(counter
, hwc
, idx
);
356 void perf_counter_print_debug(void)
358 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
359 struct cpu_hw_counters
*cpuc
;
362 if (!nr_counters_generic
)
367 cpu
= smp_processor_id();
368 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
370 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
371 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
372 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
373 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
375 printk(KERN_INFO
"\n");
376 printk(KERN_INFO
"CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
377 printk(KERN_INFO
"CPU#%d: status: %016llx\n", cpu
, status
);
378 printk(KERN_INFO
"CPU#%d: overflow: %016llx\n", cpu
, overflow
);
379 printk(KERN_INFO
"CPU#%d: fixed: %016llx\n", cpu
, fixed
);
380 printk(KERN_INFO
"CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used
);
382 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
383 rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, pmc_ctrl
);
384 rdmsrl(MSR_ARCH_PERFMON_PERFCTR0
+ idx
, pmc_count
);
386 prev_left
= per_cpu(prev_left
[idx
], cpu
);
388 printk(KERN_INFO
"CPU#%d: gen-PMC%d ctrl: %016llx\n",
390 printk(KERN_INFO
"CPU#%d: gen-PMC%d count: %016llx\n",
391 cpu
, idx
, pmc_count
);
392 printk(KERN_INFO
"CPU#%d: gen-PMC%d left: %016llx\n",
393 cpu
, idx
, prev_left
);
395 for (idx
= 0; idx
< nr_counters_fixed
; idx
++) {
396 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
398 printk(KERN_INFO
"CPU#%d: fixed-PMC%d count: %016llx\n",
399 cpu
, idx
, pmc_count
);
404 static void pmc_generic_disable(struct perf_counter
*counter
)
406 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
407 struct hw_perf_counter
*hwc
= &counter
->hw
;
408 unsigned int idx
= hwc
->idx
;
410 __pmc_generic_disable(counter
, hwc
, idx
);
412 clear_bit(idx
, cpuc
->used
);
413 cpuc
->counters
[idx
] = NULL
;
415 * Make sure the cleared pointer becomes visible before we
416 * (potentially) free the counter:
421 * Drain the remaining delta count out of a counter
422 * that we are disabling:
424 x86_perf_counter_update(counter
, hwc
, idx
);
427 static void perf_store_irq_data(struct perf_counter
*counter
, u64 data
)
429 struct perf_data
*irqdata
= counter
->irqdata
;
431 if (irqdata
->len
> PERF_DATA_BUFLEN
- sizeof(u64
)) {
434 u64
*p
= (u64
*) &irqdata
->data
[irqdata
->len
];
437 irqdata
->len
+= sizeof(u64
);
442 * Save and restart an expired counter. Called by NMI contexts,
443 * so it has to be careful about preempting normal counter ops:
445 static void perf_save_and_restart(struct perf_counter
*counter
)
447 struct hw_perf_counter
*hwc
= &counter
->hw
;
450 x86_perf_counter_update(counter
, hwc
, idx
);
451 __hw_perf_counter_set_period(counter
, hwc
, idx
);
453 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
454 __pmc_generic_enable(counter
, hwc
, idx
);
458 perf_handle_group(struct perf_counter
*sibling
, u64
*status
, u64
*overflown
)
460 struct perf_counter
*counter
, *group_leader
= sibling
->group_leader
;
463 * Store sibling timestamps (if any):
465 list_for_each_entry(counter
, &group_leader
->sibling_list
, list_entry
) {
467 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
468 perf_store_irq_data(sibling
, counter
->hw_event
.type
);
469 perf_store_irq_data(sibling
, atomic64_read(&counter
->count
));
474 * This handler is triggered by the local APIC, so the APIC IRQ handling
477 static void __smp_perf_counter_interrupt(struct pt_regs
*regs
, int nmi
)
479 int bit
, cpu
= smp_processor_id();
480 u64 ack
, status
, now
;
481 struct cpu_hw_counters
*cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
483 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, cpuc
->global_enable
);
485 /* Disable counters globally */
486 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
490 if (now
- cpuc
->last_interrupt
< PERFMON_MIN_PERIOD_NS
)
492 cpuc
->last_interrupt
= now
;
494 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
500 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
501 struct perf_counter
*counter
= cpuc
->counters
[bit
];
503 clear_bit(bit
, (unsigned long *) &status
);
507 perf_save_and_restart(counter
);
509 switch (counter
->hw_event
.record_type
) {
510 case PERF_RECORD_SIMPLE
:
512 case PERF_RECORD_IRQ
:
513 perf_store_irq_data(counter
, instruction_pointer(regs
));
515 case PERF_RECORD_GROUP
:
516 perf_handle_group(counter
, &status
, &ack
);
520 * From NMI context we cannot call into the scheduler to
521 * do a task wakeup - but we mark these generic as
522 * wakeup_pending and initate a wakeup callback:
525 counter
->wakeup_pending
= 1;
526 set_tsk_thread_flag(current
, TIF_PERF_COUNTERS
);
528 wake_up(&counter
->waitq
);
532 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
535 * Repeat if there is more work to be done:
537 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
542 * Restore - do not reenable when global enable is off or throttled:
544 if (!cpuc
->throttled
)
545 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, cpuc
->global_enable
);
548 void perf_counter_unthrottle(void)
550 struct cpu_hw_counters
*cpuc
;
552 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
555 if (unlikely(!perf_counters_initialized
))
558 cpuc
= &per_cpu(cpu_hw_counters
, smp_processor_id());
559 if (cpuc
->throttled
) {
560 if (printk_ratelimit())
561 printk(KERN_WARNING
"PERFMON: max event frequency exceeded!\n");
562 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, cpuc
->global_enable
);
567 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
570 inc_irq_stat(apic_perf_irqs
);
571 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
572 __smp_perf_counter_interrupt(regs
, 0);
578 * This handler is triggered by NMI contexts:
580 void perf_counter_notify(struct pt_regs
*regs
)
582 struct cpu_hw_counters
*cpuc
;
586 local_irq_save(flags
);
587 cpu
= smp_processor_id();
588 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
590 for_each_bit(bit
, cpuc
->used
, X86_PMC_IDX_MAX
) {
591 struct perf_counter
*counter
= cpuc
->counters
[bit
];
596 if (counter
->wakeup_pending
) {
597 counter
->wakeup_pending
= 0;
598 wake_up(&counter
->waitq
);
602 local_irq_restore(flags
);
605 void __cpuinit
perf_counters_lapic_init(int nmi
)
609 if (!perf_counters_initialized
)
612 * Enable the performance counter vector in the APIC LVT:
614 apic_val
= apic_read(APIC_LVTERR
);
616 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
618 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
620 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
621 apic_write(APIC_LVTERR
, apic_val
);
625 perf_counter_nmi_handler(struct notifier_block
*self
,
626 unsigned long cmd
, void *__args
)
628 struct die_args
*args
= __args
;
629 struct pt_regs
*regs
;
631 if (likely(cmd
!= DIE_NMI_IPI
))
636 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
637 __smp_perf_counter_interrupt(regs
, 1);
642 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
643 .notifier_call
= perf_counter_nmi_handler
646 void __init
init_hw_perf_counters(void)
648 union cpuid10_eax eax
;
651 union cpuid10_edx edx
;
653 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
657 * Check whether the Architectural PerfMon supports
658 * Branch Misses Retired Event or not.
660 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
661 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
664 printk(KERN_INFO
"Intel Performance Monitoring support detected.\n");
666 printk(KERN_INFO
"... version: %d\n", eax
.split
.version_id
);
667 printk(KERN_INFO
"... num counters: %d\n", eax
.split
.num_counters
);
668 nr_counters_generic
= eax
.split
.num_counters
;
669 if (nr_counters_generic
> X86_PMC_MAX_GENERIC
) {
670 nr_counters_generic
= X86_PMC_MAX_GENERIC
;
671 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
672 nr_counters_generic
, X86_PMC_MAX_GENERIC
);
674 perf_counter_mask
= (1 << nr_counters_generic
) - 1;
675 perf_max_counters
= nr_counters_generic
;
677 printk(KERN_INFO
"... bit width: %d\n", eax
.split
.bit_width
);
678 counter_value_mask
= (1ULL << eax
.split
.bit_width
) - 1;
679 printk(KERN_INFO
"... value mask: %016Lx\n", counter_value_mask
);
681 printk(KERN_INFO
"... mask length: %d\n", eax
.split
.mask_length
);
683 nr_counters_fixed
= edx
.split
.num_counters_fixed
;
684 if (nr_counters_fixed
> X86_PMC_MAX_FIXED
) {
685 nr_counters_fixed
= X86_PMC_MAX_FIXED
;
686 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
687 nr_counters_fixed
, X86_PMC_MAX_FIXED
);
689 printk(KERN_INFO
"... fixed counters: %d\n", nr_counters_fixed
);
691 perf_counter_mask
|= ((1LL << nr_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
693 printk(KERN_INFO
"... counter mask: %016Lx\n", perf_counter_mask
);
694 perf_counters_initialized
= true;
696 perf_counters_lapic_init(0);
697 register_die_notifier(&perf_counter_nmi_notifier
);
700 static void pmc_generic_read(struct perf_counter
*counter
)
702 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
705 static const struct hw_perf_counter_ops x86_perf_counter_ops
= {
706 .enable
= pmc_generic_enable
,
707 .disable
= pmc_generic_disable
,
708 .read
= pmc_generic_read
,
711 const struct hw_perf_counter_ops
*
712 hw_perf_counter_init(struct perf_counter
*counter
)
716 err
= __hw_perf_counter_init(counter
);
720 return &x86_perf_counter_ops
;