2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
7 * For licencing details see kernel-base/COPYING
10 #include <linux/perf_counter.h>
11 #include <linux/capability.h>
12 #include <linux/notifier.h>
13 #include <linux/hardirq.h>
14 #include <linux/kprobes.h>
15 #include <linux/module.h>
16 #include <linux/kdebug.h>
17 #include <linux/sched.h>
19 #include <asm/perf_counter.h>
22 static bool perf_counters_initialized __read_mostly
;
25 * Number of (generic) HW counters:
27 static int nr_counters_generic __read_mostly
;
28 static u64 perf_counter_mask __read_mostly
;
29 static u64 counter_value_mask __read_mostly
;
31 static int nr_counters_fixed __read_mostly
;
33 struct cpu_hw_counters
{
34 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
35 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
39 * Intel PerfMon v3. Used on Core2 and later.
41 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
);
43 static const int intel_perfmon_event_map
[] =
45 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
46 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
47 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
48 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
49 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
50 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
51 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
54 static const int max_intel_perfmon_events
= ARRAY_SIZE(intel_perfmon_event_map
);
57 * Propagate counter elapsed time into the generic counter.
58 * Can only be executed on the CPU where the counter is active.
59 * Returns the delta events processed.
62 x86_perf_counter_update(struct perf_counter
*counter
,
63 struct hw_perf_counter
*hwc
, int idx
)
65 u64 prev_raw_count
, new_raw_count
, delta
;
68 * Careful: an NMI might modify the previous counter value.
70 * Our tactic to handle this is to first atomically read and
71 * exchange a new raw count - then add that new-prev delta
72 * count to the generic counter atomically:
75 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
76 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
78 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
79 new_raw_count
) != prev_raw_count
)
83 * Now we have the new raw value and have updated the prev
84 * timestamp already. We can now calculate the elapsed delta
85 * (counter-)time and add that to the generic counter.
87 * Careful, not all hw sign-extends above the physical width
88 * of the count, so we do that by clipping the delta to 32 bits:
90 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
92 atomic64_add(delta
, &counter
->count
);
93 atomic64_sub(delta
, &hwc
->period_left
);
97 * Setup the hardware configuration for a given hw_event_type
99 static int __hw_perf_counter_init(struct perf_counter
*counter
)
101 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
102 struct hw_perf_counter
*hwc
= &counter
->hw
;
104 if (unlikely(!perf_counters_initialized
))
108 * Count user events, and generate PMC IRQs:
109 * (keep 'enabled' bit clear for now)
111 hwc
->config
= ARCH_PERFMON_EVENTSEL_USR
| ARCH_PERFMON_EVENTSEL_INT
;
114 * If privileged enough, count OS events too, and allow
115 * NMI events as well:
118 if (capable(CAP_SYS_ADMIN
)) {
119 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
124 hwc
->irq_period
= hw_event
->irq_period
;
126 * Intel PMCs cannot be accessed sanely above 32 bit width,
127 * so we install an artificial 1<<31 period regardless of
128 * the generic counter period:
130 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
131 hwc
->irq_period
= 0x7FFFFFFF;
133 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
136 * Raw event type provide the config in the event structure
139 hwc
->config
|= hw_event
->type
;
141 if (hw_event
->type
>= max_intel_perfmon_events
)
146 hwc
->config
|= intel_perfmon_event_map
[hw_event
->type
];
148 counter
->wakeup_pending
= 0;
153 void hw_perf_enable_all(void)
155 if (unlikely(!perf_counters_initialized
))
158 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, perf_counter_mask
);
161 u64
hw_perf_save_disable(void)
165 if (unlikely(!perf_counters_initialized
))
168 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
169 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
173 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
175 void hw_perf_restore(u64 ctrl
)
177 if (unlikely(!perf_counters_initialized
))
180 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
182 EXPORT_SYMBOL_GPL(hw_perf_restore
);
185 __pmc_fixed_disable(struct perf_counter
*counter
,
186 struct hw_perf_counter
*hwc
, unsigned int __idx
)
188 int idx
= __idx
- X86_PMC_IDX_FIXED
;
192 mask
= 0xfULL
<< (idx
* 4);
194 rdmsrl(hwc
->config_base
, ctrl_val
);
196 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
200 __pmc_generic_disable(struct perf_counter
*counter
,
201 struct hw_perf_counter
*hwc
, unsigned int idx
)
205 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
206 return __pmc_fixed_disable(counter
, hwc
, idx
);
208 err
= wrmsr_safe(hwc
->config_base
+ idx
, hwc
->config
, 0);
211 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
214 * Set the next IRQ period, based on the hwc->period_left value.
215 * To be called with the counter disabled in hw:
218 __hw_perf_counter_set_period(struct perf_counter
*counter
,
219 struct hw_perf_counter
*hwc
, int idx
)
221 s64 left
= atomic64_read(&hwc
->period_left
);
222 s32 period
= hwc
->irq_period
;
226 * If we are way outside a reasoable range then just skip forward:
228 if (unlikely(left
<= -period
)) {
230 atomic64_set(&hwc
->period_left
, left
);
233 if (unlikely(left
<= 0)) {
235 atomic64_set(&hwc
->period_left
, left
);
238 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
241 * The hw counter starts counting from this counter offset,
242 * mark it to be able to extra future deltas:
244 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
246 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
247 (u64
)(-left
) & counter_value_mask
);
251 __pmc_fixed_enable(struct perf_counter
*counter
,
252 struct hw_perf_counter
*hwc
, unsigned int __idx
)
254 int idx
= __idx
- X86_PMC_IDX_FIXED
;
255 u64 ctrl_val
, bits
, mask
;
259 * Enable IRQ generation (0x8) and ring-3 counting (0x2),
260 * and enable ring-0 counting if allowed:
262 bits
= 0x8ULL
| 0x2ULL
;
263 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
266 mask
= 0xfULL
<< (idx
* 4);
268 rdmsrl(hwc
->config_base
, ctrl_val
);
271 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
275 __pmc_generic_enable(struct perf_counter
*counter
,
276 struct hw_perf_counter
*hwc
, int idx
)
278 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
279 return __pmc_fixed_enable(counter
, hwc
, idx
);
281 wrmsr(hwc
->config_base
+ idx
,
282 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
, 0);
286 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
290 if (unlikely(hwc
->nmi
))
293 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
295 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_INSTRUCTIONS
]))
296 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
297 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_CPU_CYCLES
]))
298 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
299 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_BUS_CYCLES
]))
300 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
306 * Find a PMC slot for the freshly enabled / scheduled in counter:
308 static int pmc_generic_enable(struct perf_counter
*counter
)
310 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
311 struct hw_perf_counter
*hwc
= &counter
->hw
;
314 idx
= fixed_mode_idx(counter
, hwc
);
317 * Try to get the fixed counter, if that is already taken
318 * then try to get a generic counter:
320 if (test_and_set_bit(idx
, cpuc
->used
))
323 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
325 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
326 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
329 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
333 /* Try to get the previous generic counter again */
334 if (test_and_set_bit(idx
, cpuc
->used
)) {
336 idx
= find_first_zero_bit(cpuc
->used
, nr_counters_generic
);
337 if (idx
== nr_counters_generic
)
340 set_bit(idx
, cpuc
->used
);
343 hwc
->config_base
= MSR_ARCH_PERFMON_EVENTSEL0
;
344 hwc
->counter_base
= MSR_ARCH_PERFMON_PERFCTR0
;
347 perf_counters_lapic_init(hwc
->nmi
);
349 __pmc_generic_disable(counter
, hwc
, idx
);
351 cpuc
->counters
[idx
] = counter
;
353 * Make it visible before enabling the hw:
357 __hw_perf_counter_set_period(counter
, hwc
, idx
);
358 __pmc_generic_enable(counter
, hwc
, idx
);
363 void perf_counter_print_debug(void)
365 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
366 struct cpu_hw_counters
*cpuc
;
369 if (!nr_counters_generic
)
374 cpu
= smp_processor_id();
375 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
377 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
378 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
379 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
380 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
382 printk(KERN_INFO
"\n");
383 printk(KERN_INFO
"CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
384 printk(KERN_INFO
"CPU#%d: status: %016llx\n", cpu
, status
);
385 printk(KERN_INFO
"CPU#%d: overflow: %016llx\n", cpu
, overflow
);
386 printk(KERN_INFO
"CPU#%d: fixed: %016llx\n", cpu
, fixed
);
387 printk(KERN_INFO
"CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used
);
389 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
390 rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, pmc_ctrl
);
391 rdmsrl(MSR_ARCH_PERFMON_PERFCTR0
+ idx
, pmc_count
);
393 prev_left
= per_cpu(prev_left
[idx
], cpu
);
395 printk(KERN_INFO
"CPU#%d: gen-PMC%d ctrl: %016llx\n",
397 printk(KERN_INFO
"CPU#%d: gen-PMC%d count: %016llx\n",
398 cpu
, idx
, pmc_count
);
399 printk(KERN_INFO
"CPU#%d: gen-PMC%d left: %016llx\n",
400 cpu
, idx
, prev_left
);
402 for (idx
= 0; idx
< nr_counters_fixed
; idx
++) {
403 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
405 printk(KERN_INFO
"CPU#%d: fixed-PMC%d count: %016llx\n",
406 cpu
, idx
, pmc_count
);
411 static void pmc_generic_disable(struct perf_counter
*counter
)
413 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
414 struct hw_perf_counter
*hwc
= &counter
->hw
;
415 unsigned int idx
= hwc
->idx
;
417 __pmc_generic_disable(counter
, hwc
, idx
);
419 clear_bit(idx
, cpuc
->used
);
420 cpuc
->counters
[idx
] = NULL
;
422 * Make sure the cleared pointer becomes visible before we
423 * (potentially) free the counter:
428 * Drain the remaining delta count out of a counter
429 * that we are disabling:
431 x86_perf_counter_update(counter
, hwc
, idx
);
434 static void perf_store_irq_data(struct perf_counter
*counter
, u64 data
)
436 struct perf_data
*irqdata
= counter
->irqdata
;
438 if (irqdata
->len
> PERF_DATA_BUFLEN
- sizeof(u64
)) {
441 u64
*p
= (u64
*) &irqdata
->data
[irqdata
->len
];
444 irqdata
->len
+= sizeof(u64
);
449 * Save and restart an expired counter. Called by NMI contexts,
450 * so it has to be careful about preempting normal counter ops:
452 static void perf_save_and_restart(struct perf_counter
*counter
)
454 struct hw_perf_counter
*hwc
= &counter
->hw
;
457 x86_perf_counter_update(counter
, hwc
, idx
);
458 __hw_perf_counter_set_period(counter
, hwc
, idx
);
460 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
461 __pmc_generic_enable(counter
, hwc
, idx
);
465 perf_handle_group(struct perf_counter
*sibling
, u64
*status
, u64
*overflown
)
467 struct perf_counter
*counter
, *group_leader
= sibling
->group_leader
;
470 * Store sibling timestamps (if any):
472 list_for_each_entry(counter
, &group_leader
->sibling_list
, list_entry
) {
474 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
475 perf_store_irq_data(sibling
, counter
->hw_event
.type
);
476 perf_store_irq_data(sibling
, atomic64_read(&counter
->count
));
481 * This handler is triggered by the local APIC, so the APIC IRQ handling
484 static void __smp_perf_counter_interrupt(struct pt_regs
*regs
, int nmi
)
486 int bit
, cpu
= smp_processor_id();
487 u64 ack
, status
, saved_global
;
488 struct cpu_hw_counters
*cpuc
;
490 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, saved_global
);
492 /* Disable counters globally */
493 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
496 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
498 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
504 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
505 struct perf_counter
*counter
= cpuc
->counters
[bit
];
507 clear_bit(bit
, (unsigned long *) &status
);
511 perf_save_and_restart(counter
);
513 switch (counter
->hw_event
.record_type
) {
514 case PERF_RECORD_SIMPLE
:
516 case PERF_RECORD_IRQ
:
517 perf_store_irq_data(counter
, instruction_pointer(regs
));
519 case PERF_RECORD_GROUP
:
520 perf_handle_group(counter
, &status
, &ack
);
524 * From NMI context we cannot call into the scheduler to
525 * do a task wakeup - but we mark these generic as
526 * wakeup_pending and initate a wakeup callback:
529 counter
->wakeup_pending
= 1;
530 set_tsk_thread_flag(current
, TIF_PERF_COUNTERS
);
532 wake_up(&counter
->waitq
);
536 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
539 * Repeat if there is more work to be done:
541 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
546 * Restore - do not reenable when global enable is off:
548 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, saved_global
);
551 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
554 inc_irq_stat(apic_perf_irqs
);
555 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
556 __smp_perf_counter_interrupt(regs
, 0);
562 * This handler is triggered by NMI contexts:
564 void perf_counter_notify(struct pt_regs
*regs
)
566 struct cpu_hw_counters
*cpuc
;
570 local_irq_save(flags
);
571 cpu
= smp_processor_id();
572 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
574 for_each_bit(bit
, cpuc
->used
, X86_PMC_IDX_MAX
) {
575 struct perf_counter
*counter
= cpuc
->counters
[bit
];
580 if (counter
->wakeup_pending
) {
581 counter
->wakeup_pending
= 0;
582 wake_up(&counter
->waitq
);
586 local_irq_restore(flags
);
589 void __cpuinit
perf_counters_lapic_init(int nmi
)
593 if (!perf_counters_initialized
)
596 * Enable the performance counter vector in the APIC LVT:
598 apic_val
= apic_read(APIC_LVTERR
);
600 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
602 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
604 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
605 apic_write(APIC_LVTERR
, apic_val
);
609 perf_counter_nmi_handler(struct notifier_block
*self
,
610 unsigned long cmd
, void *__args
)
612 struct die_args
*args
= __args
;
613 struct pt_regs
*regs
;
615 if (likely(cmd
!= DIE_NMI_IPI
))
620 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
621 __smp_perf_counter_interrupt(regs
, 1);
626 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
627 .notifier_call
= perf_counter_nmi_handler
630 void __init
init_hw_perf_counters(void)
632 union cpuid10_eax eax
;
635 union cpuid10_edx edx
;
637 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
641 * Check whether the Architectural PerfMon supports
642 * Branch Misses Retired Event or not.
644 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
645 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
648 printk(KERN_INFO
"Intel Performance Monitoring support detected.\n");
650 printk(KERN_INFO
"... version: %d\n", eax
.split
.version_id
);
651 printk(KERN_INFO
"... num counters: %d\n", eax
.split
.num_counters
);
652 nr_counters_generic
= eax
.split
.num_counters
;
653 if (nr_counters_generic
> X86_PMC_MAX_GENERIC
) {
654 nr_counters_generic
= X86_PMC_MAX_GENERIC
;
655 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
656 nr_counters_generic
, X86_PMC_MAX_GENERIC
);
658 perf_counter_mask
= (1 << nr_counters_generic
) - 1;
659 perf_max_counters
= nr_counters_generic
;
661 printk(KERN_INFO
"... bit width: %d\n", eax
.split
.bit_width
);
662 counter_value_mask
= (1ULL << eax
.split
.bit_width
) - 1;
663 printk(KERN_INFO
"... value mask: %016Lx\n", counter_value_mask
);
665 printk(KERN_INFO
"... mask length: %d\n", eax
.split
.mask_length
);
667 nr_counters_fixed
= edx
.split
.num_counters_fixed
;
668 if (nr_counters_fixed
> X86_PMC_MAX_FIXED
) {
669 nr_counters_fixed
= X86_PMC_MAX_FIXED
;
670 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
671 nr_counters_fixed
, X86_PMC_MAX_FIXED
);
673 printk(KERN_INFO
"... fixed counters: %d\n", nr_counters_fixed
);
675 perf_counter_mask
|= ((1LL << nr_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
677 printk(KERN_INFO
"... counter mask: %016Lx\n", perf_counter_mask
);
678 perf_counters_initialized
= true;
680 perf_counters_lapic_init(0);
681 register_die_notifier(&perf_counter_nmi_notifier
);
684 static void pmc_generic_read(struct perf_counter
*counter
)
686 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
689 static const struct hw_perf_counter_ops x86_perf_counter_ops
= {
690 .enable
= pmc_generic_enable
,
691 .disable
= pmc_generic_disable
,
692 .read
= pmc_generic_read
,
695 const struct hw_perf_counter_ops
*
696 hw_perf_counter_init(struct perf_counter
*counter
)
700 err
= __hw_perf_counter_init(counter
);
704 return &x86_perf_counter_ops
;