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x86, perf_counter, bts: Add BTS support to perfcounters
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_counter.c
1 /*
2 * Performance counter x86 architecture code
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 *
11 * For licencing details see kernel-base/COPYING
12 */
13
14 #include <linux/perf_counter.h>
15 #include <linux/capability.h>
16 #include <linux/notifier.h>
17 #include <linux/hardirq.h>
18 #include <linux/kprobes.h>
19 #include <linux/module.h>
20 #include <linux/kdebug.h>
21 #include <linux/sched.h>
22 #include <linux/uaccess.h>
23 #include <linux/highmem.h>
24 #include <linux/cpu.h>
25
26 #include <asm/apic.h>
27 #include <asm/stacktrace.h>
28 #include <asm/nmi.h>
29
30 static u64 perf_counter_mask __read_mostly;
31
32 /* The maximal number of PEBS counters: */
33 #define MAX_PEBS_COUNTERS 4
34
35 /* The size of a BTS record in bytes: */
36 #define BTS_RECORD_SIZE 24
37
38 /* The size of a per-cpu BTS buffer in bytes: */
39 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 1024)
40
41 /* The BTS overflow threshold in bytes from the end of the buffer: */
42 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 64)
43
44
45 /*
46 * Bits in the debugctlmsr controlling branch tracing.
47 */
48 #define X86_DEBUGCTL_TR (1 << 6)
49 #define X86_DEBUGCTL_BTS (1 << 7)
50 #define X86_DEBUGCTL_BTINT (1 << 8)
51 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
52 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
53
54 /*
55 * A debug store configuration.
56 *
57 * We only support architectures that use 64bit fields.
58 */
59 struct debug_store {
60 u64 bts_buffer_base;
61 u64 bts_index;
62 u64 bts_absolute_maximum;
63 u64 bts_interrupt_threshold;
64 u64 pebs_buffer_base;
65 u64 pebs_index;
66 u64 pebs_absolute_maximum;
67 u64 pebs_interrupt_threshold;
68 u64 pebs_counter_reset[MAX_PEBS_COUNTERS];
69 };
70
71 struct cpu_hw_counters {
72 struct perf_counter *counters[X86_PMC_IDX_MAX];
73 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
74 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
75 unsigned long interrupts;
76 int enabled;
77 struct debug_store *ds;
78 };
79
80 /*
81 * struct x86_pmu - generic x86 pmu
82 */
83 struct x86_pmu {
84 const char *name;
85 int version;
86 int (*handle_irq)(struct pt_regs *);
87 void (*disable_all)(void);
88 void (*enable_all)(void);
89 void (*enable)(struct hw_perf_counter *, int);
90 void (*disable)(struct hw_perf_counter *, int);
91 unsigned eventsel;
92 unsigned perfctr;
93 u64 (*event_map)(int);
94 u64 (*raw_event)(u64);
95 int max_events;
96 int num_counters;
97 int num_counters_fixed;
98 int counter_bits;
99 u64 counter_mask;
100 u64 max_period;
101 u64 intel_ctrl;
102 void (*enable_bts)(u64 config);
103 void (*disable_bts)(void);
104 };
105
106 static struct x86_pmu x86_pmu __read_mostly;
107
108 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
109 .enabled = 1,
110 };
111
112 /*
113 * Not sure about some of these
114 */
115 static const u64 p6_perfmon_event_map[] =
116 {
117 [PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
118 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
119 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0000,
120 [PERF_COUNT_HW_CACHE_MISSES] = 0x0000,
121 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
122 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
123 [PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
124 };
125
126 static u64 p6_pmu_event_map(int event)
127 {
128 return p6_perfmon_event_map[event];
129 }
130
131 /*
132 * Counter setting that is specified not to count anything.
133 * We use this to effectively disable a counter.
134 *
135 * L2_RQSTS with 0 MESI unit mask.
136 */
137 #define P6_NOP_COUNTER 0x0000002EULL
138
139 static u64 p6_pmu_raw_event(u64 event)
140 {
141 #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
142 #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
143 #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
144 #define P6_EVNTSEL_INV_MASK 0x00800000ULL
145 #define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL
146
147 #define P6_EVNTSEL_MASK \
148 (P6_EVNTSEL_EVENT_MASK | \
149 P6_EVNTSEL_UNIT_MASK | \
150 P6_EVNTSEL_EDGE_MASK | \
151 P6_EVNTSEL_INV_MASK | \
152 P6_EVNTSEL_COUNTER_MASK)
153
154 return event & P6_EVNTSEL_MASK;
155 }
156
157
158 /*
159 * Intel PerfMon v3. Used on Core2 and later.
160 */
161 static const u64 intel_perfmon_event_map[] =
162 {
163 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
164 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
165 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
166 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
167 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
168 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
169 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
170 };
171
172 static u64 intel_pmu_event_map(int event)
173 {
174 return intel_perfmon_event_map[event];
175 }
176
177 /*
178 * Generalized hw caching related event table, filled
179 * in on a per model basis. A value of 0 means
180 * 'not supported', -1 means 'event makes no sense on
181 * this CPU', any other value means the raw event
182 * ID.
183 */
184
185 #define C(x) PERF_COUNT_HW_CACHE_##x
186
187 static u64 __read_mostly hw_cache_event_ids
188 [PERF_COUNT_HW_CACHE_MAX]
189 [PERF_COUNT_HW_CACHE_OP_MAX]
190 [PERF_COUNT_HW_CACHE_RESULT_MAX];
191
192 static const u64 nehalem_hw_cache_event_ids
193 [PERF_COUNT_HW_CACHE_MAX]
194 [PERF_COUNT_HW_CACHE_OP_MAX]
195 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
196 {
197 [ C(L1D) ] = {
198 [ C(OP_READ) ] = {
199 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
200 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
201 },
202 [ C(OP_WRITE) ] = {
203 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
204 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
205 },
206 [ C(OP_PREFETCH) ] = {
207 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
208 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
209 },
210 },
211 [ C(L1I ) ] = {
212 [ C(OP_READ) ] = {
213 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
214 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
215 },
216 [ C(OP_WRITE) ] = {
217 [ C(RESULT_ACCESS) ] = -1,
218 [ C(RESULT_MISS) ] = -1,
219 },
220 [ C(OP_PREFETCH) ] = {
221 [ C(RESULT_ACCESS) ] = 0x0,
222 [ C(RESULT_MISS) ] = 0x0,
223 },
224 },
225 [ C(LL ) ] = {
226 [ C(OP_READ) ] = {
227 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */
228 [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */
229 },
230 [ C(OP_WRITE) ] = {
231 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */
232 [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
233 },
234 [ C(OP_PREFETCH) ] = {
235 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */
236 [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */
237 },
238 },
239 [ C(DTLB) ] = {
240 [ C(OP_READ) ] = {
241 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
242 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
243 },
244 [ C(OP_WRITE) ] = {
245 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
246 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
247 },
248 [ C(OP_PREFETCH) ] = {
249 [ C(RESULT_ACCESS) ] = 0x0,
250 [ C(RESULT_MISS) ] = 0x0,
251 },
252 },
253 [ C(ITLB) ] = {
254 [ C(OP_READ) ] = {
255 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
256 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
257 },
258 [ C(OP_WRITE) ] = {
259 [ C(RESULT_ACCESS) ] = -1,
260 [ C(RESULT_MISS) ] = -1,
261 },
262 [ C(OP_PREFETCH) ] = {
263 [ C(RESULT_ACCESS) ] = -1,
264 [ C(RESULT_MISS) ] = -1,
265 },
266 },
267 [ C(BPU ) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
270 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
271 },
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = -1,
274 [ C(RESULT_MISS) ] = -1,
275 },
276 [ C(OP_PREFETCH) ] = {
277 [ C(RESULT_ACCESS) ] = -1,
278 [ C(RESULT_MISS) ] = -1,
279 },
280 },
281 };
282
283 static const u64 core2_hw_cache_event_ids
284 [PERF_COUNT_HW_CACHE_MAX]
285 [PERF_COUNT_HW_CACHE_OP_MAX]
286 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
287 {
288 [ C(L1D) ] = {
289 [ C(OP_READ) ] = {
290 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
291 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
292 },
293 [ C(OP_WRITE) ] = {
294 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
295 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
296 },
297 [ C(OP_PREFETCH) ] = {
298 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
299 [ C(RESULT_MISS) ] = 0,
300 },
301 },
302 [ C(L1I ) ] = {
303 [ C(OP_READ) ] = {
304 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
305 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
306 },
307 [ C(OP_WRITE) ] = {
308 [ C(RESULT_ACCESS) ] = -1,
309 [ C(RESULT_MISS) ] = -1,
310 },
311 [ C(OP_PREFETCH) ] = {
312 [ C(RESULT_ACCESS) ] = 0,
313 [ C(RESULT_MISS) ] = 0,
314 },
315 },
316 [ C(LL ) ] = {
317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
319 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
320 },
321 [ C(OP_WRITE) ] = {
322 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
323 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
324 },
325 [ C(OP_PREFETCH) ] = {
326 [ C(RESULT_ACCESS) ] = 0,
327 [ C(RESULT_MISS) ] = 0,
328 },
329 },
330 [ C(DTLB) ] = {
331 [ C(OP_READ) ] = {
332 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
333 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
334 },
335 [ C(OP_WRITE) ] = {
336 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
337 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
338 },
339 [ C(OP_PREFETCH) ] = {
340 [ C(RESULT_ACCESS) ] = 0,
341 [ C(RESULT_MISS) ] = 0,
342 },
343 },
344 [ C(ITLB) ] = {
345 [ C(OP_READ) ] = {
346 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
347 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
348 },
349 [ C(OP_WRITE) ] = {
350 [ C(RESULT_ACCESS) ] = -1,
351 [ C(RESULT_MISS) ] = -1,
352 },
353 [ C(OP_PREFETCH) ] = {
354 [ C(RESULT_ACCESS) ] = -1,
355 [ C(RESULT_MISS) ] = -1,
356 },
357 },
358 [ C(BPU ) ] = {
359 [ C(OP_READ) ] = {
360 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
361 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
362 },
363 [ C(OP_WRITE) ] = {
364 [ C(RESULT_ACCESS) ] = -1,
365 [ C(RESULT_MISS) ] = -1,
366 },
367 [ C(OP_PREFETCH) ] = {
368 [ C(RESULT_ACCESS) ] = -1,
369 [ C(RESULT_MISS) ] = -1,
370 },
371 },
372 };
373
374 static const u64 atom_hw_cache_event_ids
375 [PERF_COUNT_HW_CACHE_MAX]
376 [PERF_COUNT_HW_CACHE_OP_MAX]
377 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
378 {
379 [ C(L1D) ] = {
380 [ C(OP_READ) ] = {
381 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
382 [ C(RESULT_MISS) ] = 0,
383 },
384 [ C(OP_WRITE) ] = {
385 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
386 [ C(RESULT_MISS) ] = 0,
387 },
388 [ C(OP_PREFETCH) ] = {
389 [ C(RESULT_ACCESS) ] = 0x0,
390 [ C(RESULT_MISS) ] = 0,
391 },
392 },
393 [ C(L1I ) ] = {
394 [ C(OP_READ) ] = {
395 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
396 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
397 },
398 [ C(OP_WRITE) ] = {
399 [ C(RESULT_ACCESS) ] = -1,
400 [ C(RESULT_MISS) ] = -1,
401 },
402 [ C(OP_PREFETCH) ] = {
403 [ C(RESULT_ACCESS) ] = 0,
404 [ C(RESULT_MISS) ] = 0,
405 },
406 },
407 [ C(LL ) ] = {
408 [ C(OP_READ) ] = {
409 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
410 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
411 },
412 [ C(OP_WRITE) ] = {
413 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
414 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
415 },
416 [ C(OP_PREFETCH) ] = {
417 [ C(RESULT_ACCESS) ] = 0,
418 [ C(RESULT_MISS) ] = 0,
419 },
420 },
421 [ C(DTLB) ] = {
422 [ C(OP_READ) ] = {
423 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
424 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
425 },
426 [ C(OP_WRITE) ] = {
427 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
428 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
429 },
430 [ C(OP_PREFETCH) ] = {
431 [ C(RESULT_ACCESS) ] = 0,
432 [ C(RESULT_MISS) ] = 0,
433 },
434 },
435 [ C(ITLB) ] = {
436 [ C(OP_READ) ] = {
437 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
438 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
439 },
440 [ C(OP_WRITE) ] = {
441 [ C(RESULT_ACCESS) ] = -1,
442 [ C(RESULT_MISS) ] = -1,
443 },
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = -1,
446 [ C(RESULT_MISS) ] = -1,
447 },
448 },
449 [ C(BPU ) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
452 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
453 },
454 [ C(OP_WRITE) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 [ C(OP_PREFETCH) ] = {
459 [ C(RESULT_ACCESS) ] = -1,
460 [ C(RESULT_MISS) ] = -1,
461 },
462 },
463 };
464
465 static u64 intel_pmu_raw_event(u64 event)
466 {
467 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
468 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
469 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
470 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
471 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
472
473 #define CORE_EVNTSEL_MASK \
474 (CORE_EVNTSEL_EVENT_MASK | \
475 CORE_EVNTSEL_UNIT_MASK | \
476 CORE_EVNTSEL_EDGE_MASK | \
477 CORE_EVNTSEL_INV_MASK | \
478 CORE_EVNTSEL_COUNTER_MASK)
479
480 return event & CORE_EVNTSEL_MASK;
481 }
482
483 static const u64 amd_hw_cache_event_ids
484 [PERF_COUNT_HW_CACHE_MAX]
485 [PERF_COUNT_HW_CACHE_OP_MAX]
486 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
487 {
488 [ C(L1D) ] = {
489 [ C(OP_READ) ] = {
490 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
491 [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */
492 },
493 [ C(OP_WRITE) ] = {
494 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
495 [ C(RESULT_MISS) ] = 0,
496 },
497 [ C(OP_PREFETCH) ] = {
498 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
499 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
500 },
501 },
502 [ C(L1I ) ] = {
503 [ C(OP_READ) ] = {
504 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
505 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
506 },
507 [ C(OP_WRITE) ] = {
508 [ C(RESULT_ACCESS) ] = -1,
509 [ C(RESULT_MISS) ] = -1,
510 },
511 [ C(OP_PREFETCH) ] = {
512 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
513 [ C(RESULT_MISS) ] = 0,
514 },
515 },
516 [ C(LL ) ] = {
517 [ C(OP_READ) ] = {
518 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
519 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
520 },
521 [ C(OP_WRITE) ] = {
522 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
523 [ C(RESULT_MISS) ] = 0,
524 },
525 [ C(OP_PREFETCH) ] = {
526 [ C(RESULT_ACCESS) ] = 0,
527 [ C(RESULT_MISS) ] = 0,
528 },
529 },
530 [ C(DTLB) ] = {
531 [ C(OP_READ) ] = {
532 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
533 [ C(RESULT_MISS) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
534 },
535 [ C(OP_WRITE) ] = {
536 [ C(RESULT_ACCESS) ] = 0,
537 [ C(RESULT_MISS) ] = 0,
538 },
539 [ C(OP_PREFETCH) ] = {
540 [ C(RESULT_ACCESS) ] = 0,
541 [ C(RESULT_MISS) ] = 0,
542 },
543 },
544 [ C(ITLB) ] = {
545 [ C(OP_READ) ] = {
546 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
547 [ C(RESULT_MISS) ] = 0x0085, /* Instr. fetch ITLB misses */
548 },
549 [ C(OP_WRITE) ] = {
550 [ C(RESULT_ACCESS) ] = -1,
551 [ C(RESULT_MISS) ] = -1,
552 },
553 [ C(OP_PREFETCH) ] = {
554 [ C(RESULT_ACCESS) ] = -1,
555 [ C(RESULT_MISS) ] = -1,
556 },
557 },
558 [ C(BPU ) ] = {
559 [ C(OP_READ) ] = {
560 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
561 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
562 },
563 [ C(OP_WRITE) ] = {
564 [ C(RESULT_ACCESS) ] = -1,
565 [ C(RESULT_MISS) ] = -1,
566 },
567 [ C(OP_PREFETCH) ] = {
568 [ C(RESULT_ACCESS) ] = -1,
569 [ C(RESULT_MISS) ] = -1,
570 },
571 },
572 };
573
574 /*
575 * AMD Performance Monitor K7 and later.
576 */
577 static const u64 amd_perfmon_event_map[] =
578 {
579 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076,
580 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
581 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0080,
582 [PERF_COUNT_HW_CACHE_MISSES] = 0x0081,
583 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
584 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
585 };
586
587 static u64 amd_pmu_event_map(int event)
588 {
589 return amd_perfmon_event_map[event];
590 }
591
592 static u64 amd_pmu_raw_event(u64 event)
593 {
594 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
595 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
596 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
597 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
598 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
599
600 #define K7_EVNTSEL_MASK \
601 (K7_EVNTSEL_EVENT_MASK | \
602 K7_EVNTSEL_UNIT_MASK | \
603 K7_EVNTSEL_EDGE_MASK | \
604 K7_EVNTSEL_INV_MASK | \
605 K7_EVNTSEL_COUNTER_MASK)
606
607 return event & K7_EVNTSEL_MASK;
608 }
609
610 /*
611 * Propagate counter elapsed time into the generic counter.
612 * Can only be executed on the CPU where the counter is active.
613 * Returns the delta events processed.
614 */
615 static u64
616 x86_perf_counter_update(struct perf_counter *counter,
617 struct hw_perf_counter *hwc, int idx)
618 {
619 int shift = 64 - x86_pmu.counter_bits;
620 u64 prev_raw_count, new_raw_count;
621 s64 delta;
622
623 if (idx == X86_PMC_IDX_FIXED_BTS)
624 return 0;
625
626 /*
627 * Careful: an NMI might modify the previous counter value.
628 *
629 * Our tactic to handle this is to first atomically read and
630 * exchange a new raw count - then add that new-prev delta
631 * count to the generic counter atomically:
632 */
633 again:
634 prev_raw_count = atomic64_read(&hwc->prev_count);
635 rdmsrl(hwc->counter_base + idx, new_raw_count);
636
637 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
638 new_raw_count) != prev_raw_count)
639 goto again;
640
641 /*
642 * Now we have the new raw value and have updated the prev
643 * timestamp already. We can now calculate the elapsed delta
644 * (counter-)time and add that to the generic counter.
645 *
646 * Careful, not all hw sign-extends above the physical width
647 * of the count.
648 */
649 delta = (new_raw_count << shift) - (prev_raw_count << shift);
650 delta >>= shift;
651
652 atomic64_add(delta, &counter->count);
653 atomic64_sub(delta, &hwc->period_left);
654
655 return new_raw_count;
656 }
657
658 static atomic_t active_counters;
659 static DEFINE_MUTEX(pmc_reserve_mutex);
660
661 static bool reserve_pmc_hardware(void)
662 {
663 int i;
664
665 if (nmi_watchdog == NMI_LOCAL_APIC)
666 disable_lapic_nmi_watchdog();
667
668 for (i = 0; i < x86_pmu.num_counters; i++) {
669 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
670 goto perfctr_fail;
671 }
672
673 for (i = 0; i < x86_pmu.num_counters; i++) {
674 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
675 goto eventsel_fail;
676 }
677
678 return true;
679
680 eventsel_fail:
681 for (i--; i >= 0; i--)
682 release_evntsel_nmi(x86_pmu.eventsel + i);
683
684 i = x86_pmu.num_counters;
685
686 perfctr_fail:
687 for (i--; i >= 0; i--)
688 release_perfctr_nmi(x86_pmu.perfctr + i);
689
690 if (nmi_watchdog == NMI_LOCAL_APIC)
691 enable_lapic_nmi_watchdog();
692
693 return false;
694 }
695
696 static void release_pmc_hardware(void)
697 {
698 int i;
699
700 for (i = 0; i < x86_pmu.num_counters; i++) {
701 release_perfctr_nmi(x86_pmu.perfctr + i);
702 release_evntsel_nmi(x86_pmu.eventsel + i);
703 }
704
705 if (nmi_watchdog == NMI_LOCAL_APIC)
706 enable_lapic_nmi_watchdog();
707 }
708
709 static inline bool bts_available(void)
710 {
711 return x86_pmu.enable_bts != NULL;
712 }
713
714 static inline void init_debug_store_on_cpu(int cpu)
715 {
716 struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds;
717
718 if (!ds)
719 return;
720
721 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
722 (u32)((u64)(long)ds), (u32)((u64)(long)ds >> 32));
723 }
724
725 static inline void fini_debug_store_on_cpu(int cpu)
726 {
727 if (!per_cpu(cpu_hw_counters, cpu).ds)
728 return;
729
730 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
731 }
732
733 static void release_bts_hardware(void)
734 {
735 int cpu;
736
737 if (!bts_available())
738 return;
739
740 get_online_cpus();
741
742 for_each_online_cpu(cpu)
743 fini_debug_store_on_cpu(cpu);
744
745 for_each_possible_cpu(cpu) {
746 struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds;
747
748 if (!ds)
749 continue;
750
751 per_cpu(cpu_hw_counters, cpu).ds = NULL;
752
753 kfree((void *)(long)ds->bts_buffer_base);
754 kfree(ds);
755 }
756
757 put_online_cpus();
758 }
759
760 static int reserve_bts_hardware(void)
761 {
762 int cpu, err = 0;
763
764 if (!bts_available())
765 return -EOPNOTSUPP;
766
767 get_online_cpus();
768
769 for_each_possible_cpu(cpu) {
770 struct debug_store *ds;
771 void *buffer;
772
773 err = -ENOMEM;
774 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
775 if (unlikely(!buffer))
776 break;
777
778 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
779 if (unlikely(!ds)) {
780 kfree(buffer);
781 break;
782 }
783
784 ds->bts_buffer_base = (u64)(long)buffer;
785 ds->bts_index = ds->bts_buffer_base;
786 ds->bts_absolute_maximum =
787 ds->bts_buffer_base + BTS_BUFFER_SIZE;
788 ds->bts_interrupt_threshold =
789 ds->bts_absolute_maximum - BTS_OVFL_TH;
790
791 per_cpu(cpu_hw_counters, cpu).ds = ds;
792 err = 0;
793 }
794
795 if (err)
796 release_bts_hardware();
797 else {
798 for_each_online_cpu(cpu)
799 init_debug_store_on_cpu(cpu);
800 }
801
802 put_online_cpus();
803
804 return err;
805 }
806
807 static void hw_perf_counter_destroy(struct perf_counter *counter)
808 {
809 if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
810 release_pmc_hardware();
811 release_bts_hardware();
812 mutex_unlock(&pmc_reserve_mutex);
813 }
814 }
815
816 static inline int x86_pmu_initialized(void)
817 {
818 return x86_pmu.handle_irq != NULL;
819 }
820
821 static inline int
822 set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr)
823 {
824 unsigned int cache_type, cache_op, cache_result;
825 u64 config, val;
826
827 config = attr->config;
828
829 cache_type = (config >> 0) & 0xff;
830 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
831 return -EINVAL;
832
833 cache_op = (config >> 8) & 0xff;
834 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
835 return -EINVAL;
836
837 cache_result = (config >> 16) & 0xff;
838 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
839 return -EINVAL;
840
841 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
842
843 if (val == 0)
844 return -ENOENT;
845
846 if (val == -1)
847 return -EINVAL;
848
849 hwc->config |= val;
850
851 return 0;
852 }
853
854 static void intel_pmu_enable_bts(u64 config)
855 {
856 unsigned long debugctlmsr;
857
858 debugctlmsr = get_debugctlmsr();
859
860 debugctlmsr |= X86_DEBUGCTL_TR;
861 debugctlmsr |= X86_DEBUGCTL_BTS;
862 debugctlmsr |= X86_DEBUGCTL_BTINT;
863
864 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
865 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
866
867 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
868 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
869
870 update_debugctlmsr(debugctlmsr);
871 }
872
873 static void intel_pmu_disable_bts(void)
874 {
875 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
876 unsigned long debugctlmsr;
877
878 if (!cpuc->ds)
879 return;
880
881 debugctlmsr = get_debugctlmsr();
882
883 debugctlmsr &=
884 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
885 X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
886
887 update_debugctlmsr(debugctlmsr);
888 }
889
890 /*
891 * Setup the hardware configuration for a given attr_type
892 */
893 static int __hw_perf_counter_init(struct perf_counter *counter)
894 {
895 struct perf_counter_attr *attr = &counter->attr;
896 struct hw_perf_counter *hwc = &counter->hw;
897 u64 config;
898 int err;
899
900 if (!x86_pmu_initialized())
901 return -ENODEV;
902
903 err = 0;
904 if (!atomic_inc_not_zero(&active_counters)) {
905 mutex_lock(&pmc_reserve_mutex);
906 if (atomic_read(&active_counters) == 0) {
907 if (!reserve_pmc_hardware())
908 err = -EBUSY;
909 else
910 reserve_bts_hardware();
911 }
912 if (!err)
913 atomic_inc(&active_counters);
914 mutex_unlock(&pmc_reserve_mutex);
915 }
916 if (err)
917 return err;
918
919 /*
920 * Generate PMC IRQs:
921 * (keep 'enabled' bit clear for now)
922 */
923 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
924
925 /*
926 * Count user and OS events unless requested not to.
927 */
928 if (!attr->exclude_user)
929 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
930 if (!attr->exclude_kernel)
931 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
932
933 if (!hwc->sample_period) {
934 hwc->sample_period = x86_pmu.max_period;
935 hwc->last_period = hwc->sample_period;
936 atomic64_set(&hwc->period_left, hwc->sample_period);
937 }
938
939 counter->destroy = hw_perf_counter_destroy;
940
941 /*
942 * Raw event type provide the config in the event structure
943 */
944 if (attr->type == PERF_TYPE_RAW) {
945 hwc->config |= x86_pmu.raw_event(attr->config);
946 return 0;
947 }
948
949 if (attr->type == PERF_TYPE_HW_CACHE)
950 return set_ext_hw_attr(hwc, attr);
951
952 if (attr->config >= x86_pmu.max_events)
953 return -EINVAL;
954
955 /*
956 * The generic map:
957 */
958 config = x86_pmu.event_map(attr->config);
959
960 if (config == 0)
961 return -ENOENT;
962
963 if (config == -1LL)
964 return -EINVAL;
965
966 hwc->config |= config;
967
968 return 0;
969 }
970
971 static void p6_pmu_disable_all(void)
972 {
973 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
974 u64 val;
975
976 if (!cpuc->enabled)
977 return;
978
979 cpuc->enabled = 0;
980 barrier();
981
982 /* p6 only has one enable register */
983 rdmsrl(MSR_P6_EVNTSEL0, val);
984 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
985 wrmsrl(MSR_P6_EVNTSEL0, val);
986 }
987
988 static void intel_pmu_disable_all(void)
989 {
990 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
991
992 if (!cpuc->enabled)
993 return;
994
995 cpuc->enabled = 0;
996 barrier();
997
998 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
999
1000 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1001 intel_pmu_disable_bts();
1002 }
1003
1004 static void amd_pmu_disable_all(void)
1005 {
1006 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1007 int idx;
1008
1009 if (!cpuc->enabled)
1010 return;
1011
1012 cpuc->enabled = 0;
1013 /*
1014 * ensure we write the disable before we start disabling the
1015 * counters proper, so that amd_pmu_enable_counter() does the
1016 * right thing.
1017 */
1018 barrier();
1019
1020 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1021 u64 val;
1022
1023 if (!test_bit(idx, cpuc->active_mask))
1024 continue;
1025 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
1026 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
1027 continue;
1028 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1029 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1030 }
1031 }
1032
1033 void hw_perf_disable(void)
1034 {
1035 if (!x86_pmu_initialized())
1036 return;
1037 return x86_pmu.disable_all();
1038 }
1039
1040 static void p6_pmu_enable_all(void)
1041 {
1042 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1043 unsigned long val;
1044
1045 if (cpuc->enabled)
1046 return;
1047
1048 cpuc->enabled = 1;
1049 barrier();
1050
1051 /* p6 only has one enable register */
1052 rdmsrl(MSR_P6_EVNTSEL0, val);
1053 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1054 wrmsrl(MSR_P6_EVNTSEL0, val);
1055 }
1056
1057 static void intel_pmu_enable_all(void)
1058 {
1059 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1060
1061 if (cpuc->enabled)
1062 return;
1063
1064 cpuc->enabled = 1;
1065 barrier();
1066
1067 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1068
1069 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1070 struct perf_counter *counter =
1071 cpuc->counters[X86_PMC_IDX_FIXED_BTS];
1072
1073 if (WARN_ON_ONCE(!counter))
1074 return;
1075
1076 intel_pmu_enable_bts(counter->hw.config);
1077 }
1078 }
1079
1080 static void amd_pmu_enable_all(void)
1081 {
1082 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1083 int idx;
1084
1085 if (cpuc->enabled)
1086 return;
1087
1088 cpuc->enabled = 1;
1089 barrier();
1090
1091 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1092 struct perf_counter *counter = cpuc->counters[idx];
1093 u64 val;
1094
1095 if (!test_bit(idx, cpuc->active_mask))
1096 continue;
1097
1098 val = counter->hw.config;
1099 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1100 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1101 }
1102 }
1103
1104 void hw_perf_enable(void)
1105 {
1106 if (!x86_pmu_initialized())
1107 return;
1108 x86_pmu.enable_all();
1109 }
1110
1111 static inline u64 intel_pmu_get_status(void)
1112 {
1113 u64 status;
1114
1115 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1116
1117 return status;
1118 }
1119
1120 static inline void intel_pmu_ack_status(u64 ack)
1121 {
1122 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1123 }
1124
1125 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
1126 {
1127 (void)checking_wrmsrl(hwc->config_base + idx,
1128 hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
1129 }
1130
1131 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
1132 {
1133 (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
1134 }
1135
1136 static inline void
1137 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
1138 {
1139 int idx = __idx - X86_PMC_IDX_FIXED;
1140 u64 ctrl_val, mask;
1141
1142 mask = 0xfULL << (idx * 4);
1143
1144 rdmsrl(hwc->config_base, ctrl_val);
1145 ctrl_val &= ~mask;
1146 (void)checking_wrmsrl(hwc->config_base, ctrl_val);
1147 }
1148
1149 static inline void
1150 p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
1151 {
1152 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1153 u64 val = P6_NOP_COUNTER;
1154
1155 if (cpuc->enabled)
1156 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1157
1158 (void)checking_wrmsrl(hwc->config_base + idx, val);
1159 }
1160
1161 static inline void
1162 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
1163 {
1164 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1165 intel_pmu_disable_bts();
1166 return;
1167 }
1168
1169 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1170 intel_pmu_disable_fixed(hwc, idx);
1171 return;
1172 }
1173
1174 x86_pmu_disable_counter(hwc, idx);
1175 }
1176
1177 static inline void
1178 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
1179 {
1180 x86_pmu_disable_counter(hwc, idx);
1181 }
1182
1183 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
1184
1185 /*
1186 * Set the next IRQ period, based on the hwc->period_left value.
1187 * To be called with the counter disabled in hw:
1188 */
1189 static int
1190 x86_perf_counter_set_period(struct perf_counter *counter,
1191 struct hw_perf_counter *hwc, int idx)
1192 {
1193 s64 left = atomic64_read(&hwc->period_left);
1194 s64 period = hwc->sample_period;
1195 int err, ret = 0;
1196
1197 if (idx == X86_PMC_IDX_FIXED_BTS)
1198 return 0;
1199
1200 /*
1201 * If we are way outside a reasoable range then just skip forward:
1202 */
1203 if (unlikely(left <= -period)) {
1204 left = period;
1205 atomic64_set(&hwc->period_left, left);
1206 hwc->last_period = period;
1207 ret = 1;
1208 }
1209
1210 if (unlikely(left <= 0)) {
1211 left += period;
1212 atomic64_set(&hwc->period_left, left);
1213 hwc->last_period = period;
1214 ret = 1;
1215 }
1216 /*
1217 * Quirk: certain CPUs dont like it if just 1 event is left:
1218 */
1219 if (unlikely(left < 2))
1220 left = 2;
1221
1222 if (left > x86_pmu.max_period)
1223 left = x86_pmu.max_period;
1224
1225 per_cpu(prev_left[idx], smp_processor_id()) = left;
1226
1227 /*
1228 * The hw counter starts counting from this counter offset,
1229 * mark it to be able to extra future deltas:
1230 */
1231 atomic64_set(&hwc->prev_count, (u64)-left);
1232
1233 err = checking_wrmsrl(hwc->counter_base + idx,
1234 (u64)(-left) & x86_pmu.counter_mask);
1235
1236 perf_counter_update_userpage(counter);
1237
1238 return ret;
1239 }
1240
1241 static inline void
1242 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
1243 {
1244 int idx = __idx - X86_PMC_IDX_FIXED;
1245 u64 ctrl_val, bits, mask;
1246 int err;
1247
1248 /*
1249 * Enable IRQ generation (0x8),
1250 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1251 * if requested:
1252 */
1253 bits = 0x8ULL;
1254 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1255 bits |= 0x2;
1256 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1257 bits |= 0x1;
1258 bits <<= (idx * 4);
1259 mask = 0xfULL << (idx * 4);
1260
1261 rdmsrl(hwc->config_base, ctrl_val);
1262 ctrl_val &= ~mask;
1263 ctrl_val |= bits;
1264 err = checking_wrmsrl(hwc->config_base, ctrl_val);
1265 }
1266
1267 static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
1268 {
1269 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1270 u64 val;
1271
1272 val = hwc->config;
1273 if (cpuc->enabled)
1274 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1275
1276 (void)checking_wrmsrl(hwc->config_base + idx, val);
1277 }
1278
1279
1280 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
1281 {
1282 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1283 if (!__get_cpu_var(cpu_hw_counters).enabled)
1284 return;
1285
1286 intel_pmu_enable_bts(hwc->config);
1287 return;
1288 }
1289
1290 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1291 intel_pmu_enable_fixed(hwc, idx);
1292 return;
1293 }
1294
1295 x86_pmu_enable_counter(hwc, idx);
1296 }
1297
1298 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
1299 {
1300 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1301
1302 if (cpuc->enabled)
1303 x86_pmu_enable_counter(hwc, idx);
1304 }
1305
1306 static int
1307 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
1308 {
1309 unsigned int event;
1310
1311 event = hwc->config & ARCH_PERFMON_EVENT_MASK;
1312
1313 if (unlikely((event ==
1314 x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
1315 (hwc->sample_period == 1)))
1316 return X86_PMC_IDX_FIXED_BTS;
1317
1318 if (!x86_pmu.num_counters_fixed)
1319 return -1;
1320
1321 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
1322 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
1323 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
1324 return X86_PMC_IDX_FIXED_CPU_CYCLES;
1325 if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES)))
1326 return X86_PMC_IDX_FIXED_BUS_CYCLES;
1327
1328 return -1;
1329 }
1330
1331 /*
1332 * Find a PMC slot for the freshly enabled / scheduled in counter:
1333 */
1334 static int x86_pmu_enable(struct perf_counter *counter)
1335 {
1336 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1337 struct hw_perf_counter *hwc = &counter->hw;
1338 int idx;
1339
1340 idx = fixed_mode_idx(counter, hwc);
1341 if (idx == X86_PMC_IDX_FIXED_BTS) {
1342 /*
1343 * Try to use BTS for branch tracing. If that is not
1344 * available, try to get a generic counter.
1345 */
1346 if (unlikely(!cpuc->ds))
1347 goto try_generic;
1348
1349 /*
1350 * Try to get the fixed counter, if that is already taken
1351 * then try to get a generic counter:
1352 */
1353 if (test_and_set_bit(idx, cpuc->used_mask))
1354 goto try_generic;
1355
1356 hwc->config_base = 0;
1357 hwc->counter_base = 0;
1358 hwc->idx = idx;
1359 } else if (idx >= 0) {
1360 /*
1361 * Try to get the fixed counter, if that is already taken
1362 * then try to get a generic counter:
1363 */
1364 if (test_and_set_bit(idx, cpuc->used_mask))
1365 goto try_generic;
1366
1367 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1368 /*
1369 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1370 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1371 */
1372 hwc->counter_base =
1373 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1374 hwc->idx = idx;
1375 } else {
1376 idx = hwc->idx;
1377 /* Try to get the previous generic counter again */
1378 if (test_and_set_bit(idx, cpuc->used_mask)) {
1379 try_generic:
1380 idx = find_first_zero_bit(cpuc->used_mask,
1381 x86_pmu.num_counters);
1382 if (idx == x86_pmu.num_counters)
1383 return -EAGAIN;
1384
1385 set_bit(idx, cpuc->used_mask);
1386 hwc->idx = idx;
1387 }
1388 hwc->config_base = x86_pmu.eventsel;
1389 hwc->counter_base = x86_pmu.perfctr;
1390 }
1391
1392 perf_counters_lapic_init();
1393
1394 x86_pmu.disable(hwc, idx);
1395
1396 cpuc->counters[idx] = counter;
1397 set_bit(idx, cpuc->active_mask);
1398
1399 x86_perf_counter_set_period(counter, hwc, idx);
1400 x86_pmu.enable(hwc, idx);
1401
1402 perf_counter_update_userpage(counter);
1403
1404 return 0;
1405 }
1406
1407 static void x86_pmu_unthrottle(struct perf_counter *counter)
1408 {
1409 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1410 struct hw_perf_counter *hwc = &counter->hw;
1411
1412 if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1413 cpuc->counters[hwc->idx] != counter))
1414 return;
1415
1416 x86_pmu.enable(hwc, hwc->idx);
1417 }
1418
1419 void perf_counter_print_debug(void)
1420 {
1421 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1422 struct cpu_hw_counters *cpuc;
1423 unsigned long flags;
1424 int cpu, idx;
1425
1426 if (!x86_pmu.num_counters)
1427 return;
1428
1429 local_irq_save(flags);
1430
1431 cpu = smp_processor_id();
1432 cpuc = &per_cpu(cpu_hw_counters, cpu);
1433
1434 if (x86_pmu.version >= 2) {
1435 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1436 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1437 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1438 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1439
1440 pr_info("\n");
1441 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1442 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1443 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1444 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1445 }
1446 pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used_mask);
1447
1448 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1449 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1450 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1451
1452 prev_left = per_cpu(prev_left[idx], cpu);
1453
1454 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1455 cpu, idx, pmc_ctrl);
1456 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1457 cpu, idx, pmc_count);
1458 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1459 cpu, idx, prev_left);
1460 }
1461 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1462 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1463
1464 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1465 cpu, idx, pmc_count);
1466 }
1467 local_irq_restore(flags);
1468 }
1469
1470 static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc,
1471 struct perf_sample_data *data)
1472 {
1473 struct debug_store *ds = cpuc->ds;
1474 struct bts_record {
1475 u64 from;
1476 u64 to;
1477 u64 flags;
1478 };
1479 struct perf_counter *counter = cpuc->counters[X86_PMC_IDX_FIXED_BTS];
1480 unsigned long orig_ip = data->regs->ip;
1481 u64 at;
1482
1483 if (!counter)
1484 return;
1485
1486 if (!ds)
1487 return;
1488
1489 for (at = ds->bts_buffer_base;
1490 at < ds->bts_index;
1491 at += sizeof(struct bts_record)) {
1492 struct bts_record *rec = (struct bts_record *)(long)at;
1493
1494 data->regs->ip = rec->from;
1495 data->addr = rec->to;
1496
1497 perf_counter_output(counter, 1, data);
1498 }
1499
1500 ds->bts_index = ds->bts_buffer_base;
1501
1502 data->regs->ip = orig_ip;
1503 data->addr = 0;
1504
1505 /* There's new data available. */
1506 counter->pending_kill = POLL_IN;
1507 }
1508
1509 static void x86_pmu_disable(struct perf_counter *counter)
1510 {
1511 struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1512 struct hw_perf_counter *hwc = &counter->hw;
1513 int idx = hwc->idx;
1514
1515 /*
1516 * Must be done before we disable, otherwise the nmi handler
1517 * could reenable again:
1518 */
1519 clear_bit(idx, cpuc->active_mask);
1520 x86_pmu.disable(hwc, idx);
1521
1522 /*
1523 * Make sure the cleared pointer becomes visible before we
1524 * (potentially) free the counter:
1525 */
1526 barrier();
1527
1528 /*
1529 * Drain the remaining delta count out of a counter
1530 * that we are disabling:
1531 */
1532 x86_perf_counter_update(counter, hwc, idx);
1533
1534 /* Drain the remaining BTS records. */
1535 if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1536 struct perf_sample_data data;
1537 struct pt_regs regs;
1538
1539 data.regs = &regs;
1540 intel_pmu_drain_bts_buffer(cpuc, &data);
1541 }
1542 cpuc->counters[idx] = NULL;
1543 clear_bit(idx, cpuc->used_mask);
1544
1545 perf_counter_update_userpage(counter);
1546 }
1547
1548 /*
1549 * Save and restart an expired counter. Called by NMI contexts,
1550 * so it has to be careful about preempting normal counter ops:
1551 */
1552 static int intel_pmu_save_and_restart(struct perf_counter *counter)
1553 {
1554 struct hw_perf_counter *hwc = &counter->hw;
1555 int idx = hwc->idx;
1556 int ret;
1557
1558 x86_perf_counter_update(counter, hwc, idx);
1559 ret = x86_perf_counter_set_period(counter, hwc, idx);
1560
1561 if (counter->state == PERF_COUNTER_STATE_ACTIVE)
1562 intel_pmu_enable_counter(hwc, idx);
1563
1564 return ret;
1565 }
1566
1567 static void intel_pmu_reset(void)
1568 {
1569 struct debug_store *ds = __get_cpu_var(cpu_hw_counters).ds;
1570 unsigned long flags;
1571 int idx;
1572
1573 if (!x86_pmu.num_counters)
1574 return;
1575
1576 local_irq_save(flags);
1577
1578 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1579
1580 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1581 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1582 checking_wrmsrl(x86_pmu.perfctr + idx, 0ull);
1583 }
1584 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1585 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1586 }
1587 if (ds)
1588 ds->bts_index = ds->bts_buffer_base;
1589
1590 local_irq_restore(flags);
1591 }
1592
1593 static int p6_pmu_handle_irq(struct pt_regs *regs)
1594 {
1595 struct perf_sample_data data;
1596 struct cpu_hw_counters *cpuc;
1597 struct perf_counter *counter;
1598 struct hw_perf_counter *hwc;
1599 int idx, handled = 0;
1600 u64 val;
1601
1602 data.regs = regs;
1603 data.addr = 0;
1604
1605 cpuc = &__get_cpu_var(cpu_hw_counters);
1606
1607 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1608 if (!test_bit(idx, cpuc->active_mask))
1609 continue;
1610
1611 counter = cpuc->counters[idx];
1612 hwc = &counter->hw;
1613
1614 val = x86_perf_counter_update(counter, hwc, idx);
1615 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
1616 continue;
1617
1618 /*
1619 * counter overflow
1620 */
1621 handled = 1;
1622 data.period = counter->hw.last_period;
1623
1624 if (!x86_perf_counter_set_period(counter, hwc, idx))
1625 continue;
1626
1627 if (perf_counter_overflow(counter, 1, &data))
1628 p6_pmu_disable_counter(hwc, idx);
1629 }
1630
1631 if (handled)
1632 inc_irq_stat(apic_perf_irqs);
1633
1634 return handled;
1635 }
1636
1637 /*
1638 * This handler is triggered by the local APIC, so the APIC IRQ handling
1639 * rules apply:
1640 */
1641 static int intel_pmu_handle_irq(struct pt_regs *regs)
1642 {
1643 struct perf_sample_data data;
1644 struct cpu_hw_counters *cpuc;
1645 int bit, loops;
1646 u64 ack, status;
1647
1648 data.regs = regs;
1649 data.addr = 0;
1650
1651 cpuc = &__get_cpu_var(cpu_hw_counters);
1652
1653 perf_disable();
1654 intel_pmu_drain_bts_buffer(cpuc, &data);
1655 status = intel_pmu_get_status();
1656 if (!status) {
1657 perf_enable();
1658 return 0;
1659 }
1660
1661 loops = 0;
1662 again:
1663 if (++loops > 100) {
1664 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
1665 perf_counter_print_debug();
1666 intel_pmu_reset();
1667 perf_enable();
1668 return 1;
1669 }
1670
1671 inc_irq_stat(apic_perf_irqs);
1672 ack = status;
1673 for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1674 struct perf_counter *counter = cpuc->counters[bit];
1675
1676 clear_bit(bit, (unsigned long *) &status);
1677 if (!test_bit(bit, cpuc->active_mask))
1678 continue;
1679
1680 if (!intel_pmu_save_and_restart(counter))
1681 continue;
1682
1683 data.period = counter->hw.last_period;
1684
1685 if (perf_counter_overflow(counter, 1, &data))
1686 intel_pmu_disable_counter(&counter->hw, bit);
1687 }
1688
1689 intel_pmu_ack_status(ack);
1690
1691 /*
1692 * Repeat if there is more work to be done:
1693 */
1694 status = intel_pmu_get_status();
1695 if (status)
1696 goto again;
1697
1698 perf_enable();
1699
1700 return 1;
1701 }
1702
1703 static int amd_pmu_handle_irq(struct pt_regs *regs)
1704 {
1705 struct perf_sample_data data;
1706 struct cpu_hw_counters *cpuc;
1707 struct perf_counter *counter;
1708 struct hw_perf_counter *hwc;
1709 int idx, handled = 0;
1710 u64 val;
1711
1712 data.regs = regs;
1713 data.addr = 0;
1714
1715 cpuc = &__get_cpu_var(cpu_hw_counters);
1716
1717 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1718 if (!test_bit(idx, cpuc->active_mask))
1719 continue;
1720
1721 counter = cpuc->counters[idx];
1722 hwc = &counter->hw;
1723
1724 val = x86_perf_counter_update(counter, hwc, idx);
1725 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
1726 continue;
1727
1728 /*
1729 * counter overflow
1730 */
1731 handled = 1;
1732 data.period = counter->hw.last_period;
1733
1734 if (!x86_perf_counter_set_period(counter, hwc, idx))
1735 continue;
1736
1737 if (perf_counter_overflow(counter, 1, &data))
1738 amd_pmu_disable_counter(hwc, idx);
1739 }
1740
1741 if (handled)
1742 inc_irq_stat(apic_perf_irqs);
1743
1744 return handled;
1745 }
1746
1747 void smp_perf_pending_interrupt(struct pt_regs *regs)
1748 {
1749 irq_enter();
1750 ack_APIC_irq();
1751 inc_irq_stat(apic_pending_irqs);
1752 perf_counter_do_pending();
1753 irq_exit();
1754 }
1755
1756 void set_perf_counter_pending(void)
1757 {
1758 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1759 }
1760
1761 void perf_counters_lapic_init(void)
1762 {
1763 if (!x86_pmu_initialized())
1764 return;
1765
1766 /*
1767 * Always use NMI for PMU
1768 */
1769 apic_write(APIC_LVTPC, APIC_DM_NMI);
1770 }
1771
1772 static int __kprobes
1773 perf_counter_nmi_handler(struct notifier_block *self,
1774 unsigned long cmd, void *__args)
1775 {
1776 struct die_args *args = __args;
1777 struct pt_regs *regs;
1778
1779 if (!atomic_read(&active_counters))
1780 return NOTIFY_DONE;
1781
1782 switch (cmd) {
1783 case DIE_NMI:
1784 case DIE_NMI_IPI:
1785 break;
1786
1787 default:
1788 return NOTIFY_DONE;
1789 }
1790
1791 regs = args->regs;
1792
1793 apic_write(APIC_LVTPC, APIC_DM_NMI);
1794 /*
1795 * Can't rely on the handled return value to say it was our NMI, two
1796 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1797 *
1798 * If the first NMI handles both, the latter will be empty and daze
1799 * the CPU.
1800 */
1801 x86_pmu.handle_irq(regs);
1802
1803 return NOTIFY_STOP;
1804 }
1805
1806 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
1807 .notifier_call = perf_counter_nmi_handler,
1808 .next = NULL,
1809 .priority = 1
1810 };
1811
1812 static struct x86_pmu p6_pmu = {
1813 .name = "p6",
1814 .handle_irq = p6_pmu_handle_irq,
1815 .disable_all = p6_pmu_disable_all,
1816 .enable_all = p6_pmu_enable_all,
1817 .enable = p6_pmu_enable_counter,
1818 .disable = p6_pmu_disable_counter,
1819 .eventsel = MSR_P6_EVNTSEL0,
1820 .perfctr = MSR_P6_PERFCTR0,
1821 .event_map = p6_pmu_event_map,
1822 .raw_event = p6_pmu_raw_event,
1823 .max_events = ARRAY_SIZE(p6_perfmon_event_map),
1824 .max_period = (1ULL << 31) - 1,
1825 .version = 0,
1826 .num_counters = 2,
1827 /*
1828 * Counters have 40 bits implemented. However they are designed such
1829 * that bits [32-39] are sign extensions of bit 31. As such the
1830 * effective width of a counter for P6-like PMU is 32 bits only.
1831 *
1832 * See IA-32 Intel Architecture Software developer manual Vol 3B
1833 */
1834 .counter_bits = 32,
1835 .counter_mask = (1ULL << 32) - 1,
1836 };
1837
1838 static struct x86_pmu intel_pmu = {
1839 .name = "Intel",
1840 .handle_irq = intel_pmu_handle_irq,
1841 .disable_all = intel_pmu_disable_all,
1842 .enable_all = intel_pmu_enable_all,
1843 .enable = intel_pmu_enable_counter,
1844 .disable = intel_pmu_disable_counter,
1845 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1846 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1847 .event_map = intel_pmu_event_map,
1848 .raw_event = intel_pmu_raw_event,
1849 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1850 /*
1851 * Intel PMCs cannot be accessed sanely above 32 bit width,
1852 * so we install an artificial 1<<31 period regardless of
1853 * the generic counter period:
1854 */
1855 .max_period = (1ULL << 31) - 1,
1856 .enable_bts = intel_pmu_enable_bts,
1857 .disable_bts = intel_pmu_disable_bts,
1858 };
1859
1860 static struct x86_pmu amd_pmu = {
1861 .name = "AMD",
1862 .handle_irq = amd_pmu_handle_irq,
1863 .disable_all = amd_pmu_disable_all,
1864 .enable_all = amd_pmu_enable_all,
1865 .enable = amd_pmu_enable_counter,
1866 .disable = amd_pmu_disable_counter,
1867 .eventsel = MSR_K7_EVNTSEL0,
1868 .perfctr = MSR_K7_PERFCTR0,
1869 .event_map = amd_pmu_event_map,
1870 .raw_event = amd_pmu_raw_event,
1871 .max_events = ARRAY_SIZE(amd_perfmon_event_map),
1872 .num_counters = 4,
1873 .counter_bits = 48,
1874 .counter_mask = (1ULL << 48) - 1,
1875 /* use highest bit to detect overflow */
1876 .max_period = (1ULL << 47) - 1,
1877 };
1878
1879 static int p6_pmu_init(void)
1880 {
1881 switch (boot_cpu_data.x86_model) {
1882 case 1:
1883 case 3: /* Pentium Pro */
1884 case 5:
1885 case 6: /* Pentium II */
1886 case 7:
1887 case 8:
1888 case 11: /* Pentium III */
1889 break;
1890 case 9:
1891 case 13:
1892 /* Pentium M */
1893 break;
1894 default:
1895 pr_cont("unsupported p6 CPU model %d ",
1896 boot_cpu_data.x86_model);
1897 return -ENODEV;
1898 }
1899
1900 if (!cpu_has_apic) {
1901 pr_info("no Local APIC, try rebooting with lapic");
1902 return -ENODEV;
1903 }
1904
1905 x86_pmu = p6_pmu;
1906
1907 return 0;
1908 }
1909
1910 static int intel_pmu_init(void)
1911 {
1912 union cpuid10_edx edx;
1913 union cpuid10_eax eax;
1914 unsigned int unused;
1915 unsigned int ebx;
1916 int version;
1917
1918 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
1919 /* check for P6 processor family */
1920 if (boot_cpu_data.x86 == 6) {
1921 return p6_pmu_init();
1922 } else {
1923 return -ENODEV;
1924 }
1925 }
1926
1927 /*
1928 * Check whether the Architectural PerfMon supports
1929 * Branch Misses Retired Event or not.
1930 */
1931 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1932 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1933 return -ENODEV;
1934
1935 version = eax.split.version_id;
1936 if (version < 2)
1937 return -ENODEV;
1938
1939 x86_pmu = intel_pmu;
1940 x86_pmu.version = version;
1941 x86_pmu.num_counters = eax.split.num_counters;
1942 x86_pmu.counter_bits = eax.split.bit_width;
1943 x86_pmu.counter_mask = (1ULL << eax.split.bit_width) - 1;
1944
1945 /*
1946 * Quirk: v2 perfmon does not report fixed-purpose counters, so
1947 * assume at least 3 counters:
1948 */
1949 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
1950
1951 /*
1952 * Install the hw-cache-events table:
1953 */
1954 switch (boot_cpu_data.x86_model) {
1955 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1956 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1957 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1958 case 29: /* six-core 45 nm xeon "Dunnington" */
1959 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1960 sizeof(hw_cache_event_ids));
1961
1962 pr_cont("Core2 events, ");
1963 break;
1964 default:
1965 case 26:
1966 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1967 sizeof(hw_cache_event_ids));
1968
1969 pr_cont("Nehalem/Corei7 events, ");
1970 break;
1971 case 28:
1972 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1973 sizeof(hw_cache_event_ids));
1974
1975 pr_cont("Atom events, ");
1976 break;
1977 }
1978 return 0;
1979 }
1980
1981 static int amd_pmu_init(void)
1982 {
1983 /* Performance-monitoring supported from K7 and later: */
1984 if (boot_cpu_data.x86 < 6)
1985 return -ENODEV;
1986
1987 x86_pmu = amd_pmu;
1988
1989 /* Events are common for all AMDs */
1990 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
1991 sizeof(hw_cache_event_ids));
1992
1993 return 0;
1994 }
1995
1996 void __init init_hw_perf_counters(void)
1997 {
1998 int err;
1999
2000 pr_info("Performance Counters: ");
2001
2002 switch (boot_cpu_data.x86_vendor) {
2003 case X86_VENDOR_INTEL:
2004 err = intel_pmu_init();
2005 break;
2006 case X86_VENDOR_AMD:
2007 err = amd_pmu_init();
2008 break;
2009 default:
2010 return;
2011 }
2012 if (err != 0) {
2013 pr_cont("no PMU driver, software counters only.\n");
2014 return;
2015 }
2016
2017 pr_cont("%s PMU driver.\n", x86_pmu.name);
2018
2019 if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
2020 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
2021 x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
2022 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
2023 }
2024 perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
2025 perf_max_counters = x86_pmu.num_counters;
2026
2027 if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
2028 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
2029 x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
2030 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
2031 }
2032
2033 perf_counter_mask |=
2034 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
2035 x86_pmu.intel_ctrl = perf_counter_mask;
2036
2037 perf_counters_lapic_init();
2038 register_die_notifier(&perf_counter_nmi_notifier);
2039
2040 pr_info("... version: %d\n", x86_pmu.version);
2041 pr_info("... bit width: %d\n", x86_pmu.counter_bits);
2042 pr_info("... generic counters: %d\n", x86_pmu.num_counters);
2043 pr_info("... value mask: %016Lx\n", x86_pmu.counter_mask);
2044 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2045 pr_info("... fixed-purpose counters: %d\n", x86_pmu.num_counters_fixed);
2046 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
2047 }
2048
2049 static inline void x86_pmu_read(struct perf_counter *counter)
2050 {
2051 x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
2052 }
2053
2054 static const struct pmu pmu = {
2055 .enable = x86_pmu_enable,
2056 .disable = x86_pmu_disable,
2057 .read = x86_pmu_read,
2058 .unthrottle = x86_pmu_unthrottle,
2059 };
2060
2061 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
2062 {
2063 int err;
2064
2065 err = __hw_perf_counter_init(counter);
2066 if (err)
2067 return ERR_PTR(err);
2068
2069 return &pmu;
2070 }
2071
2072 /*
2073 * callchain support
2074 */
2075
2076 static inline
2077 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
2078 {
2079 if (entry->nr < PERF_MAX_STACK_DEPTH)
2080 entry->ip[entry->nr++] = ip;
2081 }
2082
2083 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
2084 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
2085 static DEFINE_PER_CPU(int, in_nmi_frame);
2086
2087
2088 static void
2089 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
2090 {
2091 /* Ignore warnings */
2092 }
2093
2094 static void backtrace_warning(void *data, char *msg)
2095 {
2096 /* Ignore warnings */
2097 }
2098
2099 static int backtrace_stack(void *data, char *name)
2100 {
2101 per_cpu(in_nmi_frame, smp_processor_id()) =
2102 x86_is_stack_id(NMI_STACK, name);
2103
2104 return 0;
2105 }
2106
2107 static void backtrace_address(void *data, unsigned long addr, int reliable)
2108 {
2109 struct perf_callchain_entry *entry = data;
2110
2111 if (per_cpu(in_nmi_frame, smp_processor_id()))
2112 return;
2113
2114 if (reliable)
2115 callchain_store(entry, addr);
2116 }
2117
2118 static const struct stacktrace_ops backtrace_ops = {
2119 .warning = backtrace_warning,
2120 .warning_symbol = backtrace_warning_symbol,
2121 .stack = backtrace_stack,
2122 .address = backtrace_address,
2123 };
2124
2125 #include "../dumpstack.h"
2126
2127 static void
2128 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
2129 {
2130 callchain_store(entry, PERF_CONTEXT_KERNEL);
2131 callchain_store(entry, regs->ip);
2132
2133 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
2134 }
2135
2136 /*
2137 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
2138 */
2139 static unsigned long
2140 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
2141 {
2142 unsigned long offset, addr = (unsigned long)from;
2143 int type = in_nmi() ? KM_NMI : KM_IRQ0;
2144 unsigned long size, len = 0;
2145 struct page *page;
2146 void *map;
2147 int ret;
2148
2149 do {
2150 ret = __get_user_pages_fast(addr, 1, 0, &page);
2151 if (!ret)
2152 break;
2153
2154 offset = addr & (PAGE_SIZE - 1);
2155 size = min(PAGE_SIZE - offset, n - len);
2156
2157 map = kmap_atomic(page, type);
2158 memcpy(to, map+offset, size);
2159 kunmap_atomic(map, type);
2160 put_page(page);
2161
2162 len += size;
2163 to += size;
2164 addr += size;
2165
2166 } while (len < n);
2167
2168 return len;
2169 }
2170
2171 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
2172 {
2173 unsigned long bytes;
2174
2175 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
2176
2177 return bytes == sizeof(*frame);
2178 }
2179
2180 static void
2181 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
2182 {
2183 struct stack_frame frame;
2184 const void __user *fp;
2185
2186 if (!user_mode(regs))
2187 regs = task_pt_regs(current);
2188
2189 fp = (void __user *)regs->bp;
2190
2191 callchain_store(entry, PERF_CONTEXT_USER);
2192 callchain_store(entry, regs->ip);
2193
2194 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2195 frame.next_frame = NULL;
2196 frame.return_address = 0;
2197
2198 if (!copy_stack_frame(fp, &frame))
2199 break;
2200
2201 if ((unsigned long)fp < regs->sp)
2202 break;
2203
2204 callchain_store(entry, frame.return_address);
2205 fp = frame.next_frame;
2206 }
2207 }
2208
2209 static void
2210 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
2211 {
2212 int is_user;
2213
2214 if (!regs)
2215 return;
2216
2217 is_user = user_mode(regs);
2218
2219 if (!current || current->pid == 0)
2220 return;
2221
2222 if (is_user && current->state != TASK_RUNNING)
2223 return;
2224
2225 if (!is_user)
2226 perf_callchain_kernel(regs, entry);
2227
2228 if (current->mm)
2229 perf_callchain_user(regs, entry);
2230 }
2231
2232 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2233 {
2234 struct perf_callchain_entry *entry;
2235
2236 if (in_nmi())
2237 entry = &__get_cpu_var(nmi_entry);
2238 else
2239 entry = &__get_cpu_var(irq_entry);
2240
2241 entry->nr = 0;
2242
2243 perf_do_callchain(regs, entry);
2244
2245 return entry;
2246 }
2247
2248 void hw_perf_counter_setup_online(int cpu)
2249 {
2250 init_debug_store_on_cpu(cpu);
2251 }
Linux kernel - Deliverables
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