2 * Performance counter x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
11 * For licencing details see kernel-base/COPYING
14 #include <linux/perf_counter.h>
15 #include <linux/capability.h>
16 #include <linux/notifier.h>
17 #include <linux/hardirq.h>
18 #include <linux/kprobes.h>
19 #include <linux/module.h>
20 #include <linux/kdebug.h>
21 #include <linux/sched.h>
22 #include <linux/uaccess.h>
23 #include <linux/highmem.h>
24 #include <linux/cpu.h>
27 #include <asm/stacktrace.h>
30 static u64 perf_counter_mask __read_mostly
;
32 /* The maximal number of PEBS counters: */
33 #define MAX_PEBS_COUNTERS 4
35 /* The size of a BTS record in bytes: */
36 #define BTS_RECORD_SIZE 24
38 /* The size of a per-cpu BTS buffer in bytes: */
39 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 1024)
41 /* The BTS overflow threshold in bytes from the end of the buffer: */
42 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 64)
46 * Bits in the debugctlmsr controlling branch tracing.
48 #define X86_DEBUGCTL_TR (1 << 6)
49 #define X86_DEBUGCTL_BTS (1 << 7)
50 #define X86_DEBUGCTL_BTINT (1 << 8)
51 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
52 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
55 * A debug store configuration.
57 * We only support architectures that use 64bit fields.
62 u64 bts_absolute_maximum
;
63 u64 bts_interrupt_threshold
;
66 u64 pebs_absolute_maximum
;
67 u64 pebs_interrupt_threshold
;
68 u64 pebs_counter_reset
[MAX_PEBS_COUNTERS
];
71 struct cpu_hw_counters
{
72 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
73 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
74 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
75 unsigned long interrupts
;
77 struct debug_store
*ds
;
81 * struct x86_pmu - generic x86 pmu
86 int (*handle_irq
)(struct pt_regs
*);
87 void (*disable_all
)(void);
88 void (*enable_all
)(void);
89 void (*enable
)(struct hw_perf_counter
*, int);
90 void (*disable
)(struct hw_perf_counter
*, int);
93 u64 (*event_map
)(int);
94 u64 (*raw_event
)(u64
);
97 int num_counters_fixed
;
103 void (*enable_bts
)(u64 config
);
104 void (*disable_bts
)(void);
107 static struct x86_pmu x86_pmu __read_mostly
;
109 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
114 * Not sure about some of these
116 static const u64 p6_perfmon_event_map
[] =
118 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0079,
119 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
120 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x0f2e,
121 [PERF_COUNT_HW_CACHE_MISSES
] = 0x012e,
122 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
123 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
124 [PERF_COUNT_HW_BUS_CYCLES
] = 0x0062,
127 static u64
p6_pmu_event_map(int event
)
129 return p6_perfmon_event_map
[event
];
133 * Counter setting that is specified not to count anything.
134 * We use this to effectively disable a counter.
136 * L2_RQSTS with 0 MESI unit mask.
138 #define P6_NOP_COUNTER 0x0000002EULL
140 static u64
p6_pmu_raw_event(u64 event
)
142 #define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
143 #define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
144 #define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
145 #define P6_EVNTSEL_INV_MASK 0x00800000ULL
146 #define P6_EVNTSEL_COUNTER_MASK 0xFF000000ULL
148 #define P6_EVNTSEL_MASK \
149 (P6_EVNTSEL_EVENT_MASK | \
150 P6_EVNTSEL_UNIT_MASK | \
151 P6_EVNTSEL_EDGE_MASK | \
152 P6_EVNTSEL_INV_MASK | \
153 P6_EVNTSEL_COUNTER_MASK)
155 return event
& P6_EVNTSEL_MASK
;
160 * Intel PerfMon v3. Used on Core2 and later.
162 static const u64 intel_perfmon_event_map
[] =
164 [PERF_COUNT_HW_CPU_CYCLES
] = 0x003c,
165 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
166 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x4f2e,
167 [PERF_COUNT_HW_CACHE_MISSES
] = 0x412e,
168 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
169 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
170 [PERF_COUNT_HW_BUS_CYCLES
] = 0x013c,
173 static u64
intel_pmu_event_map(int event
)
175 return intel_perfmon_event_map
[event
];
179 * Generalized hw caching related event table, filled
180 * in on a per model basis. A value of 0 means
181 * 'not supported', -1 means 'event makes no sense on
182 * this CPU', any other value means the raw event
186 #define C(x) PERF_COUNT_HW_CACHE_##x
188 static u64 __read_mostly hw_cache_event_ids
189 [PERF_COUNT_HW_CACHE_MAX
]
190 [PERF_COUNT_HW_CACHE_OP_MAX
]
191 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
193 static const u64 nehalem_hw_cache_event_ids
194 [PERF_COUNT_HW_CACHE_MAX
]
195 [PERF_COUNT_HW_CACHE_OP_MAX
]
196 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
200 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
201 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
204 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
205 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
207 [ C(OP_PREFETCH
) ] = {
208 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
209 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
214 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
215 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
218 [ C(RESULT_ACCESS
) ] = -1,
219 [ C(RESULT_MISS
) ] = -1,
221 [ C(OP_PREFETCH
) ] = {
222 [ C(RESULT_ACCESS
) ] = 0x0,
223 [ C(RESULT_MISS
) ] = 0x0,
228 [ C(RESULT_ACCESS
) ] = 0x0324, /* L2_RQSTS.LOADS */
229 [ C(RESULT_MISS
) ] = 0x0224, /* L2_RQSTS.LD_MISS */
232 [ C(RESULT_ACCESS
) ] = 0x0c24, /* L2_RQSTS.RFOS */
233 [ C(RESULT_MISS
) ] = 0x0824, /* L2_RQSTS.RFO_MISS */
235 [ C(OP_PREFETCH
) ] = {
236 [ C(RESULT_ACCESS
) ] = 0x4f2e, /* LLC Reference */
237 [ C(RESULT_MISS
) ] = 0x412e, /* LLC Misses */
242 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
243 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
246 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
247 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
249 [ C(OP_PREFETCH
) ] = {
250 [ C(RESULT_ACCESS
) ] = 0x0,
251 [ C(RESULT_MISS
) ] = 0x0,
256 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
257 [ C(RESULT_MISS
) ] = 0x20c8, /* ITLB_MISS_RETIRED */
260 [ C(RESULT_ACCESS
) ] = -1,
261 [ C(RESULT_MISS
) ] = -1,
263 [ C(OP_PREFETCH
) ] = {
264 [ C(RESULT_ACCESS
) ] = -1,
265 [ C(RESULT_MISS
) ] = -1,
270 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
271 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
274 [ C(RESULT_ACCESS
) ] = -1,
275 [ C(RESULT_MISS
) ] = -1,
277 [ C(OP_PREFETCH
) ] = {
278 [ C(RESULT_ACCESS
) ] = -1,
279 [ C(RESULT_MISS
) ] = -1,
284 static const u64 core2_hw_cache_event_ids
285 [PERF_COUNT_HW_CACHE_MAX
]
286 [PERF_COUNT_HW_CACHE_OP_MAX
]
287 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
291 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
292 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
295 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
296 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
298 [ C(OP_PREFETCH
) ] = {
299 [ C(RESULT_ACCESS
) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
300 [ C(RESULT_MISS
) ] = 0,
305 [ C(RESULT_ACCESS
) ] = 0x0080, /* L1I.READS */
306 [ C(RESULT_MISS
) ] = 0x0081, /* L1I.MISSES */
309 [ C(RESULT_ACCESS
) ] = -1,
310 [ C(RESULT_MISS
) ] = -1,
312 [ C(OP_PREFETCH
) ] = {
313 [ C(RESULT_ACCESS
) ] = 0,
314 [ C(RESULT_MISS
) ] = 0,
319 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
320 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
323 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
324 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
326 [ C(OP_PREFETCH
) ] = {
327 [ C(RESULT_ACCESS
) ] = 0,
328 [ C(RESULT_MISS
) ] = 0,
333 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
334 [ C(RESULT_MISS
) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
337 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
338 [ C(RESULT_MISS
) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
340 [ C(OP_PREFETCH
) ] = {
341 [ C(RESULT_ACCESS
) ] = 0,
342 [ C(RESULT_MISS
) ] = 0,
347 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
348 [ C(RESULT_MISS
) ] = 0x1282, /* ITLBMISSES */
351 [ C(RESULT_ACCESS
) ] = -1,
352 [ C(RESULT_MISS
) ] = -1,
354 [ C(OP_PREFETCH
) ] = {
355 [ C(RESULT_ACCESS
) ] = -1,
356 [ C(RESULT_MISS
) ] = -1,
361 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
362 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
365 [ C(RESULT_ACCESS
) ] = -1,
366 [ C(RESULT_MISS
) ] = -1,
368 [ C(OP_PREFETCH
) ] = {
369 [ C(RESULT_ACCESS
) ] = -1,
370 [ C(RESULT_MISS
) ] = -1,
375 static const u64 atom_hw_cache_event_ids
376 [PERF_COUNT_HW_CACHE_MAX
]
377 [PERF_COUNT_HW_CACHE_OP_MAX
]
378 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
382 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE.LD */
383 [ C(RESULT_MISS
) ] = 0,
386 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE.ST */
387 [ C(RESULT_MISS
) ] = 0,
389 [ C(OP_PREFETCH
) ] = {
390 [ C(RESULT_ACCESS
) ] = 0x0,
391 [ C(RESULT_MISS
) ] = 0,
396 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
397 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
400 [ C(RESULT_ACCESS
) ] = -1,
401 [ C(RESULT_MISS
) ] = -1,
403 [ C(OP_PREFETCH
) ] = {
404 [ C(RESULT_ACCESS
) ] = 0,
405 [ C(RESULT_MISS
) ] = 0,
410 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
411 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
414 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
415 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
417 [ C(OP_PREFETCH
) ] = {
418 [ C(RESULT_ACCESS
) ] = 0,
419 [ C(RESULT_MISS
) ] = 0,
424 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
425 [ C(RESULT_MISS
) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
428 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
429 [ C(RESULT_MISS
) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
431 [ C(OP_PREFETCH
) ] = {
432 [ C(RESULT_ACCESS
) ] = 0,
433 [ C(RESULT_MISS
) ] = 0,
438 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
439 [ C(RESULT_MISS
) ] = 0x0282, /* ITLB.MISSES */
442 [ C(RESULT_ACCESS
) ] = -1,
443 [ C(RESULT_MISS
) ] = -1,
445 [ C(OP_PREFETCH
) ] = {
446 [ C(RESULT_ACCESS
) ] = -1,
447 [ C(RESULT_MISS
) ] = -1,
452 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
453 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
456 [ C(RESULT_ACCESS
) ] = -1,
457 [ C(RESULT_MISS
) ] = -1,
459 [ C(OP_PREFETCH
) ] = {
460 [ C(RESULT_ACCESS
) ] = -1,
461 [ C(RESULT_MISS
) ] = -1,
466 static u64
intel_pmu_raw_event(u64 event
)
468 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
469 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
470 #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
471 #define CORE_EVNTSEL_INV_MASK 0x00800000ULL
472 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
474 #define CORE_EVNTSEL_MASK \
475 (CORE_EVNTSEL_EVENT_MASK | \
476 CORE_EVNTSEL_UNIT_MASK | \
477 CORE_EVNTSEL_EDGE_MASK | \
478 CORE_EVNTSEL_INV_MASK | \
479 CORE_EVNTSEL_COUNTER_MASK)
481 return event
& CORE_EVNTSEL_MASK
;
484 static const u64 amd_hw_cache_event_ids
485 [PERF_COUNT_HW_CACHE_MAX
]
486 [PERF_COUNT_HW_CACHE_OP_MAX
]
487 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
491 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
492 [ C(RESULT_MISS
) ] = 0x0041, /* Data Cache Misses */
495 [ C(RESULT_ACCESS
) ] = 0x0142, /* Data Cache Refills :system */
496 [ C(RESULT_MISS
) ] = 0,
498 [ C(OP_PREFETCH
) ] = {
499 [ C(RESULT_ACCESS
) ] = 0x0267, /* Data Prefetcher :attempts */
500 [ C(RESULT_MISS
) ] = 0x0167, /* Data Prefetcher :cancelled */
505 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction cache fetches */
506 [ C(RESULT_MISS
) ] = 0x0081, /* Instruction cache misses */
509 [ C(RESULT_ACCESS
) ] = -1,
510 [ C(RESULT_MISS
) ] = -1,
512 [ C(OP_PREFETCH
) ] = {
513 [ C(RESULT_ACCESS
) ] = 0x014B, /* Prefetch Instructions :Load */
514 [ C(RESULT_MISS
) ] = 0,
519 [ C(RESULT_ACCESS
) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
520 [ C(RESULT_MISS
) ] = 0x037E, /* L2 Cache Misses : IC+DC */
523 [ C(RESULT_ACCESS
) ] = 0x017F, /* L2 Fill/Writeback */
524 [ C(RESULT_MISS
) ] = 0,
526 [ C(OP_PREFETCH
) ] = {
527 [ C(RESULT_ACCESS
) ] = 0,
528 [ C(RESULT_MISS
) ] = 0,
533 [ C(RESULT_ACCESS
) ] = 0x0040, /* Data Cache Accesses */
534 [ C(RESULT_MISS
) ] = 0x0046, /* L1 DTLB and L2 DLTB Miss */
537 [ C(RESULT_ACCESS
) ] = 0,
538 [ C(RESULT_MISS
) ] = 0,
540 [ C(OP_PREFETCH
) ] = {
541 [ C(RESULT_ACCESS
) ] = 0,
542 [ C(RESULT_MISS
) ] = 0,
547 [ C(RESULT_ACCESS
) ] = 0x0080, /* Instruction fecthes */
548 [ C(RESULT_MISS
) ] = 0x0085, /* Instr. fetch ITLB misses */
551 [ C(RESULT_ACCESS
) ] = -1,
552 [ C(RESULT_MISS
) ] = -1,
554 [ C(OP_PREFETCH
) ] = {
555 [ C(RESULT_ACCESS
) ] = -1,
556 [ C(RESULT_MISS
) ] = -1,
561 [ C(RESULT_ACCESS
) ] = 0x00c2, /* Retired Branch Instr. */
562 [ C(RESULT_MISS
) ] = 0x00c3, /* Retired Mispredicted BI */
565 [ C(RESULT_ACCESS
) ] = -1,
566 [ C(RESULT_MISS
) ] = -1,
568 [ C(OP_PREFETCH
) ] = {
569 [ C(RESULT_ACCESS
) ] = -1,
570 [ C(RESULT_MISS
) ] = -1,
576 * AMD Performance Monitor K7 and later.
578 static const u64 amd_perfmon_event_map
[] =
580 [PERF_COUNT_HW_CPU_CYCLES
] = 0x0076,
581 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
582 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x0080,
583 [PERF_COUNT_HW_CACHE_MISSES
] = 0x0081,
584 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
585 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
588 static u64
amd_pmu_event_map(int event
)
590 return amd_perfmon_event_map
[event
];
593 static u64
amd_pmu_raw_event(u64 event
)
595 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
596 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
597 #define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
598 #define K7_EVNTSEL_INV_MASK 0x000800000ULL
599 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
601 #define K7_EVNTSEL_MASK \
602 (K7_EVNTSEL_EVENT_MASK | \
603 K7_EVNTSEL_UNIT_MASK | \
604 K7_EVNTSEL_EDGE_MASK | \
605 K7_EVNTSEL_INV_MASK | \
606 K7_EVNTSEL_COUNTER_MASK)
608 return event
& K7_EVNTSEL_MASK
;
612 * Propagate counter elapsed time into the generic counter.
613 * Can only be executed on the CPU where the counter is active.
614 * Returns the delta events processed.
617 x86_perf_counter_update(struct perf_counter
*counter
,
618 struct hw_perf_counter
*hwc
, int idx
)
620 int shift
= 64 - x86_pmu
.counter_bits
;
621 u64 prev_raw_count
, new_raw_count
;
624 if (idx
== X86_PMC_IDX_FIXED_BTS
)
628 * Careful: an NMI might modify the previous counter value.
630 * Our tactic to handle this is to first atomically read and
631 * exchange a new raw count - then add that new-prev delta
632 * count to the generic counter atomically:
635 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
636 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
638 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
639 new_raw_count
) != prev_raw_count
)
643 * Now we have the new raw value and have updated the prev
644 * timestamp already. We can now calculate the elapsed delta
645 * (counter-)time and add that to the generic counter.
647 * Careful, not all hw sign-extends above the physical width
650 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
653 atomic64_add(delta
, &counter
->count
);
654 atomic64_sub(delta
, &hwc
->period_left
);
656 return new_raw_count
;
659 static atomic_t active_counters
;
660 static DEFINE_MUTEX(pmc_reserve_mutex
);
662 static bool reserve_pmc_hardware(void)
664 #ifdef CONFIG_X86_LOCAL_APIC
667 if (nmi_watchdog
== NMI_LOCAL_APIC
)
668 disable_lapic_nmi_watchdog();
670 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
671 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
675 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
676 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
683 #ifdef CONFIG_X86_LOCAL_APIC
685 for (i
--; i
>= 0; i
--)
686 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
688 i
= x86_pmu
.num_counters
;
691 for (i
--; i
>= 0; i
--)
692 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
694 if (nmi_watchdog
== NMI_LOCAL_APIC
)
695 enable_lapic_nmi_watchdog();
701 static void release_pmc_hardware(void)
703 #ifdef CONFIG_X86_LOCAL_APIC
706 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
707 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
708 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
711 if (nmi_watchdog
== NMI_LOCAL_APIC
)
712 enable_lapic_nmi_watchdog();
716 static inline bool bts_available(void)
718 return x86_pmu
.enable_bts
!= NULL
;
721 static inline void init_debug_store_on_cpu(int cpu
)
723 struct debug_store
*ds
= per_cpu(cpu_hw_counters
, cpu
).ds
;
728 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
,
729 (u32
)((u64
)(long)ds
), (u32
)((u64
)(long)ds
>> 32));
732 static inline void fini_debug_store_on_cpu(int cpu
)
734 if (!per_cpu(cpu_hw_counters
, cpu
).ds
)
737 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
, 0, 0);
740 static void release_bts_hardware(void)
744 if (!bts_available())
749 for_each_online_cpu(cpu
)
750 fini_debug_store_on_cpu(cpu
);
752 for_each_possible_cpu(cpu
) {
753 struct debug_store
*ds
= per_cpu(cpu_hw_counters
, cpu
).ds
;
758 per_cpu(cpu_hw_counters
, cpu
).ds
= NULL
;
760 kfree((void *)(long)ds
->bts_buffer_base
);
767 static int reserve_bts_hardware(void)
771 if (!bts_available())
776 for_each_possible_cpu(cpu
) {
777 struct debug_store
*ds
;
781 buffer
= kzalloc(BTS_BUFFER_SIZE
, GFP_KERNEL
);
782 if (unlikely(!buffer
))
785 ds
= kzalloc(sizeof(*ds
), GFP_KERNEL
);
791 ds
->bts_buffer_base
= (u64
)(long)buffer
;
792 ds
->bts_index
= ds
->bts_buffer_base
;
793 ds
->bts_absolute_maximum
=
794 ds
->bts_buffer_base
+ BTS_BUFFER_SIZE
;
795 ds
->bts_interrupt_threshold
=
796 ds
->bts_absolute_maximum
- BTS_OVFL_TH
;
798 per_cpu(cpu_hw_counters
, cpu
).ds
= ds
;
803 release_bts_hardware();
805 for_each_online_cpu(cpu
)
806 init_debug_store_on_cpu(cpu
);
814 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
816 if (atomic_dec_and_mutex_lock(&active_counters
, &pmc_reserve_mutex
)) {
817 release_pmc_hardware();
818 release_bts_hardware();
819 mutex_unlock(&pmc_reserve_mutex
);
823 static inline int x86_pmu_initialized(void)
825 return x86_pmu
.handle_irq
!= NULL
;
829 set_ext_hw_attr(struct hw_perf_counter
*hwc
, struct perf_counter_attr
*attr
)
831 unsigned int cache_type
, cache_op
, cache_result
;
834 config
= attr
->config
;
836 cache_type
= (config
>> 0) & 0xff;
837 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
840 cache_op
= (config
>> 8) & 0xff;
841 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
844 cache_result
= (config
>> 16) & 0xff;
845 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
848 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
861 static void intel_pmu_enable_bts(u64 config
)
863 unsigned long debugctlmsr
;
865 debugctlmsr
= get_debugctlmsr();
867 debugctlmsr
|= X86_DEBUGCTL_TR
;
868 debugctlmsr
|= X86_DEBUGCTL_BTS
;
869 debugctlmsr
|= X86_DEBUGCTL_BTINT
;
871 if (!(config
& ARCH_PERFMON_EVENTSEL_OS
))
872 debugctlmsr
|= X86_DEBUGCTL_BTS_OFF_OS
;
874 if (!(config
& ARCH_PERFMON_EVENTSEL_USR
))
875 debugctlmsr
|= X86_DEBUGCTL_BTS_OFF_USR
;
877 update_debugctlmsr(debugctlmsr
);
880 static void intel_pmu_disable_bts(void)
882 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
883 unsigned long debugctlmsr
;
888 debugctlmsr
= get_debugctlmsr();
891 ~(X86_DEBUGCTL_TR
| X86_DEBUGCTL_BTS
| X86_DEBUGCTL_BTINT
|
892 X86_DEBUGCTL_BTS_OFF_OS
| X86_DEBUGCTL_BTS_OFF_USR
);
894 update_debugctlmsr(debugctlmsr
);
898 * Setup the hardware configuration for a given attr_type
900 static int __hw_perf_counter_init(struct perf_counter
*counter
)
902 struct perf_counter_attr
*attr
= &counter
->attr
;
903 struct hw_perf_counter
*hwc
= &counter
->hw
;
907 if (!x86_pmu_initialized())
911 if (!atomic_inc_not_zero(&active_counters
)) {
912 mutex_lock(&pmc_reserve_mutex
);
913 if (atomic_read(&active_counters
) == 0) {
914 if (!reserve_pmc_hardware())
917 err
= reserve_bts_hardware();
920 atomic_inc(&active_counters
);
921 mutex_unlock(&pmc_reserve_mutex
);
928 * (keep 'enabled' bit clear for now)
930 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
933 * Count user and OS events unless requested not to.
935 if (!attr
->exclude_user
)
936 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
937 if (!attr
->exclude_kernel
)
938 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
940 if (!hwc
->sample_period
) {
941 hwc
->sample_period
= x86_pmu
.max_period
;
942 hwc
->last_period
= hwc
->sample_period
;
943 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
946 * If we have a PMU initialized but no APIC
947 * interrupts, we cannot sample hardware
948 * counters (user-space has to fall back and
949 * sample via a hrtimer based software counter):
955 counter
->destroy
= hw_perf_counter_destroy
;
958 * Raw event type provide the config in the event structure
960 if (attr
->type
== PERF_TYPE_RAW
) {
961 hwc
->config
|= x86_pmu
.raw_event(attr
->config
);
965 if (attr
->type
== PERF_TYPE_HW_CACHE
)
966 return set_ext_hw_attr(hwc
, attr
);
968 if (attr
->config
>= x86_pmu
.max_events
)
974 config
= x86_pmu
.event_map(attr
->config
);
985 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
986 (hwc
->sample_period
== 1) && !bts_available())
989 hwc
->config
|= config
;
994 static void p6_pmu_disable_all(void)
996 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1005 /* p6 only has one enable register */
1006 rdmsrl(MSR_P6_EVNTSEL0
, val
);
1007 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
1008 wrmsrl(MSR_P6_EVNTSEL0
, val
);
1011 static void intel_pmu_disable_all(void)
1013 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1021 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1023 if (test_bit(X86_PMC_IDX_FIXED_BTS
, cpuc
->active_mask
))
1024 intel_pmu_disable_bts();
1027 static void amd_pmu_disable_all(void)
1029 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1037 * ensure we write the disable before we start disabling the
1038 * counters proper, so that amd_pmu_enable_counter() does the
1043 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1046 if (!test_bit(idx
, cpuc
->active_mask
))
1048 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
1049 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
1051 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
1052 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
1056 void hw_perf_disable(void)
1058 if (!x86_pmu_initialized())
1060 return x86_pmu
.disable_all();
1063 static void p6_pmu_enable_all(void)
1065 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1074 /* p6 only has one enable register */
1075 rdmsrl(MSR_P6_EVNTSEL0
, val
);
1076 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
1077 wrmsrl(MSR_P6_EVNTSEL0
, val
);
1080 static void intel_pmu_enable_all(void)
1082 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1090 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, x86_pmu
.intel_ctrl
);
1092 if (test_bit(X86_PMC_IDX_FIXED_BTS
, cpuc
->active_mask
)) {
1093 struct perf_counter
*counter
=
1094 cpuc
->counters
[X86_PMC_IDX_FIXED_BTS
];
1096 if (WARN_ON_ONCE(!counter
))
1099 intel_pmu_enable_bts(counter
->hw
.config
);
1103 static void amd_pmu_enable_all(void)
1105 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1114 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1115 struct perf_counter
*counter
= cpuc
->counters
[idx
];
1118 if (!test_bit(idx
, cpuc
->active_mask
))
1121 val
= counter
->hw
.config
;
1122 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
1123 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
1127 void hw_perf_enable(void)
1129 if (!x86_pmu_initialized())
1131 x86_pmu
.enable_all();
1134 static inline u64
intel_pmu_get_status(void)
1138 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1143 static inline void intel_pmu_ack_status(u64 ack
)
1145 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
1148 static inline void x86_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1150 (void)checking_wrmsrl(hwc
->config_base
+ idx
,
1151 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
1154 static inline void x86_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
1156 (void)checking_wrmsrl(hwc
->config_base
+ idx
, hwc
->config
);
1160 intel_pmu_disable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
1162 int idx
= __idx
- X86_PMC_IDX_FIXED
;
1165 mask
= 0xfULL
<< (idx
* 4);
1167 rdmsrl(hwc
->config_base
, ctrl_val
);
1169 (void)checking_wrmsrl(hwc
->config_base
, ctrl_val
);
1173 p6_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
1175 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1176 u64 val
= P6_NOP_COUNTER
;
1179 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
1181 (void)checking_wrmsrl(hwc
->config_base
+ idx
, val
);
1185 intel_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
1187 if (unlikely(idx
== X86_PMC_IDX_FIXED_BTS
)) {
1188 intel_pmu_disable_bts();
1192 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
1193 intel_pmu_disable_fixed(hwc
, idx
);
1197 x86_pmu_disable_counter(hwc
, idx
);
1201 amd_pmu_disable_counter(struct hw_perf_counter
*hwc
, int idx
)
1203 x86_pmu_disable_counter(hwc
, idx
);
1206 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
1209 * Set the next IRQ period, based on the hwc->period_left value.
1210 * To be called with the counter disabled in hw:
1213 x86_perf_counter_set_period(struct perf_counter
*counter
,
1214 struct hw_perf_counter
*hwc
, int idx
)
1216 s64 left
= atomic64_read(&hwc
->period_left
);
1217 s64 period
= hwc
->sample_period
;
1220 if (idx
== X86_PMC_IDX_FIXED_BTS
)
1224 * If we are way outside a reasoable range then just skip forward:
1226 if (unlikely(left
<= -period
)) {
1228 atomic64_set(&hwc
->period_left
, left
);
1229 hwc
->last_period
= period
;
1233 if (unlikely(left
<= 0)) {
1235 atomic64_set(&hwc
->period_left
, left
);
1236 hwc
->last_period
= period
;
1240 * Quirk: certain CPUs dont like it if just 1 event is left:
1242 if (unlikely(left
< 2))
1245 if (left
> x86_pmu
.max_period
)
1246 left
= x86_pmu
.max_period
;
1248 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
1251 * The hw counter starts counting from this counter offset,
1252 * mark it to be able to extra future deltas:
1254 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
1256 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
1257 (u64
)(-left
) & x86_pmu
.counter_mask
);
1259 perf_counter_update_userpage(counter
);
1265 intel_pmu_enable_fixed(struct hw_perf_counter
*hwc
, int __idx
)
1267 int idx
= __idx
- X86_PMC_IDX_FIXED
;
1268 u64 ctrl_val
, bits
, mask
;
1272 * Enable IRQ generation (0x8),
1273 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1277 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
1279 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
1282 mask
= 0xfULL
<< (idx
* 4);
1284 rdmsrl(hwc
->config_base
, ctrl_val
);
1287 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
1290 static void p6_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1292 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1297 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
1299 (void)checking_wrmsrl(hwc
->config_base
+ idx
, val
);
1303 static void intel_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1305 if (unlikely(idx
== X86_PMC_IDX_FIXED_BTS
)) {
1306 if (!__get_cpu_var(cpu_hw_counters
).enabled
)
1309 intel_pmu_enable_bts(hwc
->config
);
1313 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
1314 intel_pmu_enable_fixed(hwc
, idx
);
1318 x86_pmu_enable_counter(hwc
, idx
);
1321 static void amd_pmu_enable_counter(struct hw_perf_counter
*hwc
, int idx
)
1323 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1326 x86_pmu_enable_counter(hwc
, idx
);
1330 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
1334 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
1336 if (unlikely((event
==
1337 x86_pmu
.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS
)) &&
1338 (hwc
->sample_period
== 1)))
1339 return X86_PMC_IDX_FIXED_BTS
;
1341 if (!x86_pmu
.num_counters_fixed
)
1344 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_INSTRUCTIONS
)))
1345 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
1346 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_CPU_CYCLES
)))
1347 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
1348 if (unlikely(event
== x86_pmu
.event_map(PERF_COUNT_HW_BUS_CYCLES
)))
1349 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
1355 * Find a PMC slot for the freshly enabled / scheduled in counter:
1357 static int x86_pmu_enable(struct perf_counter
*counter
)
1359 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1360 struct hw_perf_counter
*hwc
= &counter
->hw
;
1363 idx
= fixed_mode_idx(counter
, hwc
);
1364 if (idx
== X86_PMC_IDX_FIXED_BTS
) {
1365 /* BTS is already occupied. */
1366 if (test_and_set_bit(idx
, cpuc
->used_mask
))
1369 hwc
->config_base
= 0;
1370 hwc
->counter_base
= 0;
1372 } else if (idx
>= 0) {
1374 * Try to get the fixed counter, if that is already taken
1375 * then try to get a generic counter:
1377 if (test_and_set_bit(idx
, cpuc
->used_mask
))
1380 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1382 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1383 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1386 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
1390 /* Try to get the previous generic counter again */
1391 if (test_and_set_bit(idx
, cpuc
->used_mask
)) {
1393 idx
= find_first_zero_bit(cpuc
->used_mask
,
1394 x86_pmu
.num_counters
);
1395 if (idx
== x86_pmu
.num_counters
)
1398 set_bit(idx
, cpuc
->used_mask
);
1401 hwc
->config_base
= x86_pmu
.eventsel
;
1402 hwc
->counter_base
= x86_pmu
.perfctr
;
1405 perf_counters_lapic_init();
1407 x86_pmu
.disable(hwc
, idx
);
1409 cpuc
->counters
[idx
] = counter
;
1410 set_bit(idx
, cpuc
->active_mask
);
1412 x86_perf_counter_set_period(counter
, hwc
, idx
);
1413 x86_pmu
.enable(hwc
, idx
);
1415 perf_counter_update_userpage(counter
);
1420 static void x86_pmu_unthrottle(struct perf_counter
*counter
)
1422 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1423 struct hw_perf_counter
*hwc
= &counter
->hw
;
1425 if (WARN_ON_ONCE(hwc
->idx
>= X86_PMC_IDX_MAX
||
1426 cpuc
->counters
[hwc
->idx
] != counter
))
1429 x86_pmu
.enable(hwc
, hwc
->idx
);
1432 void perf_counter_print_debug(void)
1434 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1435 struct cpu_hw_counters
*cpuc
;
1436 unsigned long flags
;
1439 if (!x86_pmu
.num_counters
)
1442 local_irq_save(flags
);
1444 cpu
= smp_processor_id();
1445 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
1447 if (x86_pmu
.version
>= 2) {
1448 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1449 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1450 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1451 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1454 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1455 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1456 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1457 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1459 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used_mask
);
1461 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1462 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1463 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1465 prev_left
= per_cpu(prev_left
[idx
], cpu
);
1467 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1468 cpu
, idx
, pmc_ctrl
);
1469 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1470 cpu
, idx
, pmc_count
);
1471 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1472 cpu
, idx
, prev_left
);
1474 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1475 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1477 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1478 cpu
, idx
, pmc_count
);
1480 local_irq_restore(flags
);
1483 static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters
*cpuc
,
1484 struct perf_sample_data
*data
)
1486 struct debug_store
*ds
= cpuc
->ds
;
1492 struct perf_counter
*counter
= cpuc
->counters
[X86_PMC_IDX_FIXED_BTS
];
1493 unsigned long orig_ip
= data
->regs
->ip
;
1502 for (at
= ds
->bts_buffer_base
;
1504 at
+= sizeof(struct bts_record
)) {
1505 struct bts_record
*rec
= (struct bts_record
*)(long)at
;
1507 data
->regs
->ip
= rec
->from
;
1508 data
->addr
= rec
->to
;
1510 perf_counter_output(counter
, 1, data
);
1513 ds
->bts_index
= ds
->bts_buffer_base
;
1515 data
->regs
->ip
= orig_ip
;
1518 /* There's new data available. */
1519 counter
->pending_kill
= POLL_IN
;
1522 static void x86_pmu_disable(struct perf_counter
*counter
)
1524 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
1525 struct hw_perf_counter
*hwc
= &counter
->hw
;
1529 * Must be done before we disable, otherwise the nmi handler
1530 * could reenable again:
1532 clear_bit(idx
, cpuc
->active_mask
);
1533 x86_pmu
.disable(hwc
, idx
);
1536 * Make sure the cleared pointer becomes visible before we
1537 * (potentially) free the counter:
1542 * Drain the remaining delta count out of a counter
1543 * that we are disabling:
1545 x86_perf_counter_update(counter
, hwc
, idx
);
1547 /* Drain the remaining BTS records. */
1548 if (unlikely(idx
== X86_PMC_IDX_FIXED_BTS
)) {
1549 struct perf_sample_data data
;
1550 struct pt_regs regs
;
1553 intel_pmu_drain_bts_buffer(cpuc
, &data
);
1555 cpuc
->counters
[idx
] = NULL
;
1556 clear_bit(idx
, cpuc
->used_mask
);
1558 perf_counter_update_userpage(counter
);
1562 * Save and restart an expired counter. Called by NMI contexts,
1563 * so it has to be careful about preempting normal counter ops:
1565 static int intel_pmu_save_and_restart(struct perf_counter
*counter
)
1567 struct hw_perf_counter
*hwc
= &counter
->hw
;
1571 x86_perf_counter_update(counter
, hwc
, idx
);
1572 ret
= x86_perf_counter_set_period(counter
, hwc
, idx
);
1574 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
1575 intel_pmu_enable_counter(hwc
, idx
);
1580 static void intel_pmu_reset(void)
1582 struct debug_store
*ds
= __get_cpu_var(cpu_hw_counters
).ds
;
1583 unsigned long flags
;
1586 if (!x86_pmu
.num_counters
)
1589 local_irq_save(flags
);
1591 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1593 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1594 checking_wrmsrl(x86_pmu
.eventsel
+ idx
, 0ull);
1595 checking_wrmsrl(x86_pmu
.perfctr
+ idx
, 0ull);
1597 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1598 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, 0ull);
1601 ds
->bts_index
= ds
->bts_buffer_base
;
1603 local_irq_restore(flags
);
1606 static int p6_pmu_handle_irq(struct pt_regs
*regs
)
1608 struct perf_sample_data data
;
1609 struct cpu_hw_counters
*cpuc
;
1610 struct perf_counter
*counter
;
1611 struct hw_perf_counter
*hwc
;
1612 int idx
, handled
= 0;
1618 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1620 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1621 if (!test_bit(idx
, cpuc
->active_mask
))
1624 counter
= cpuc
->counters
[idx
];
1627 val
= x86_perf_counter_update(counter
, hwc
, idx
);
1628 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
1635 data
.period
= counter
->hw
.last_period
;
1637 if (!x86_perf_counter_set_period(counter
, hwc
, idx
))
1640 if (perf_counter_overflow(counter
, 1, &data
))
1641 p6_pmu_disable_counter(hwc
, idx
);
1645 inc_irq_stat(apic_perf_irqs
);
1651 * This handler is triggered by the local APIC, so the APIC IRQ handling
1654 static int intel_pmu_handle_irq(struct pt_regs
*regs
)
1656 struct perf_sample_data data
;
1657 struct cpu_hw_counters
*cpuc
;
1664 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1667 intel_pmu_drain_bts_buffer(cpuc
, &data
);
1668 status
= intel_pmu_get_status();
1676 if (++loops
> 100) {
1677 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
1678 perf_counter_print_debug();
1684 inc_irq_stat(apic_perf_irqs
);
1686 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
1687 struct perf_counter
*counter
= cpuc
->counters
[bit
];
1689 clear_bit(bit
, (unsigned long *) &status
);
1690 if (!test_bit(bit
, cpuc
->active_mask
))
1693 if (!intel_pmu_save_and_restart(counter
))
1696 data
.period
= counter
->hw
.last_period
;
1698 if (perf_counter_overflow(counter
, 1, &data
))
1699 intel_pmu_disable_counter(&counter
->hw
, bit
);
1702 intel_pmu_ack_status(ack
);
1705 * Repeat if there is more work to be done:
1707 status
= intel_pmu_get_status();
1716 static int amd_pmu_handle_irq(struct pt_regs
*regs
)
1718 struct perf_sample_data data
;
1719 struct cpu_hw_counters
*cpuc
;
1720 struct perf_counter
*counter
;
1721 struct hw_perf_counter
*hwc
;
1722 int idx
, handled
= 0;
1728 cpuc
= &__get_cpu_var(cpu_hw_counters
);
1730 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1731 if (!test_bit(idx
, cpuc
->active_mask
))
1734 counter
= cpuc
->counters
[idx
];
1737 val
= x86_perf_counter_update(counter
, hwc
, idx
);
1738 if (val
& (1ULL << (x86_pmu
.counter_bits
- 1)))
1745 data
.period
= counter
->hw
.last_period
;
1747 if (!x86_perf_counter_set_period(counter
, hwc
, idx
))
1750 if (perf_counter_overflow(counter
, 1, &data
))
1751 amd_pmu_disable_counter(hwc
, idx
);
1755 inc_irq_stat(apic_perf_irqs
);
1760 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1764 inc_irq_stat(apic_pending_irqs
);
1765 perf_counter_do_pending();
1769 void set_perf_counter_pending(void)
1771 #ifdef CONFIG_X86_LOCAL_APIC
1772 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1776 void perf_counters_lapic_init(void)
1778 #ifdef CONFIG_X86_LOCAL_APIC
1779 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1783 * Always use NMI for PMU
1785 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1789 static int __kprobes
1790 perf_counter_nmi_handler(struct notifier_block
*self
,
1791 unsigned long cmd
, void *__args
)
1793 struct die_args
*args
= __args
;
1794 struct pt_regs
*regs
;
1796 if (!atomic_read(&active_counters
))
1810 #ifdef CONFIG_X86_LOCAL_APIC
1811 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1814 * Can't rely on the handled return value to say it was our NMI, two
1815 * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1817 * If the first NMI handles both, the latter will be empty and daze
1820 x86_pmu
.handle_irq(regs
);
1825 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
1826 .notifier_call
= perf_counter_nmi_handler
,
1831 static struct x86_pmu p6_pmu
= {
1833 .handle_irq
= p6_pmu_handle_irq
,
1834 .disable_all
= p6_pmu_disable_all
,
1835 .enable_all
= p6_pmu_enable_all
,
1836 .enable
= p6_pmu_enable_counter
,
1837 .disable
= p6_pmu_disable_counter
,
1838 .eventsel
= MSR_P6_EVNTSEL0
,
1839 .perfctr
= MSR_P6_PERFCTR0
,
1840 .event_map
= p6_pmu_event_map
,
1841 .raw_event
= p6_pmu_raw_event
,
1842 .max_events
= ARRAY_SIZE(p6_perfmon_event_map
),
1844 .max_period
= (1ULL << 31) - 1,
1848 * Counters have 40 bits implemented. However they are designed such
1849 * that bits [32-39] are sign extensions of bit 31. As such the
1850 * effective width of a counter for P6-like PMU is 32 bits only.
1852 * See IA-32 Intel Architecture Software developer manual Vol 3B
1855 .counter_mask
= (1ULL << 32) - 1,
1858 static struct x86_pmu intel_pmu
= {
1860 .handle_irq
= intel_pmu_handle_irq
,
1861 .disable_all
= intel_pmu_disable_all
,
1862 .enable_all
= intel_pmu_enable_all
,
1863 .enable
= intel_pmu_enable_counter
,
1864 .disable
= intel_pmu_disable_counter
,
1865 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
1866 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
1867 .event_map
= intel_pmu_event_map
,
1868 .raw_event
= intel_pmu_raw_event
,
1869 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
1872 * Intel PMCs cannot be accessed sanely above 32 bit width,
1873 * so we install an artificial 1<<31 period regardless of
1874 * the generic counter period:
1876 .max_period
= (1ULL << 31) - 1,
1877 .enable_bts
= intel_pmu_enable_bts
,
1878 .disable_bts
= intel_pmu_disable_bts
,
1881 static struct x86_pmu amd_pmu
= {
1883 .handle_irq
= amd_pmu_handle_irq
,
1884 .disable_all
= amd_pmu_disable_all
,
1885 .enable_all
= amd_pmu_enable_all
,
1886 .enable
= amd_pmu_enable_counter
,
1887 .disable
= amd_pmu_disable_counter
,
1888 .eventsel
= MSR_K7_EVNTSEL0
,
1889 .perfctr
= MSR_K7_PERFCTR0
,
1890 .event_map
= amd_pmu_event_map
,
1891 .raw_event
= amd_pmu_raw_event
,
1892 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
1895 .counter_mask
= (1ULL << 48) - 1,
1897 /* use highest bit to detect overflow */
1898 .max_period
= (1ULL << 47) - 1,
1901 static int p6_pmu_init(void)
1903 switch (boot_cpu_data
.x86_model
) {
1905 case 3: /* Pentium Pro */
1907 case 6: /* Pentium II */
1910 case 11: /* Pentium III */
1917 pr_cont("unsupported p6 CPU model %d ",
1918 boot_cpu_data
.x86_model
);
1924 if (!cpu_has_apic
) {
1925 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1926 pr_info("no hardware sampling interrupt available.\n");
1933 static int intel_pmu_init(void)
1935 union cpuid10_edx edx
;
1936 union cpuid10_eax eax
;
1937 unsigned int unused
;
1941 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
)) {
1942 /* check for P6 processor family */
1943 if (boot_cpu_data
.x86
== 6) {
1944 return p6_pmu_init();
1951 * Check whether the Architectural PerfMon supports
1952 * Branch Misses Retired Event or not.
1954 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
1955 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
1958 version
= eax
.split
.version_id
;
1962 x86_pmu
= intel_pmu
;
1963 x86_pmu
.version
= version
;
1964 x86_pmu
.num_counters
= eax
.split
.num_counters
;
1965 x86_pmu
.counter_bits
= eax
.split
.bit_width
;
1966 x86_pmu
.counter_mask
= (1ULL << eax
.split
.bit_width
) - 1;
1969 * Quirk: v2 perfmon does not report fixed-purpose counters, so
1970 * assume at least 3 counters:
1972 x86_pmu
.num_counters_fixed
= max((int)edx
.split
.num_counters_fixed
, 3);
1975 * Install the hw-cache-events table:
1977 switch (boot_cpu_data
.x86_model
) {
1978 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1979 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1980 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1981 case 29: /* six-core 45 nm xeon "Dunnington" */
1982 memcpy(hw_cache_event_ids
, core2_hw_cache_event_ids
,
1983 sizeof(hw_cache_event_ids
));
1985 pr_cont("Core2 events, ");
1989 memcpy(hw_cache_event_ids
, nehalem_hw_cache_event_ids
,
1990 sizeof(hw_cache_event_ids
));
1992 pr_cont("Nehalem/Corei7 events, ");
1995 memcpy(hw_cache_event_ids
, atom_hw_cache_event_ids
,
1996 sizeof(hw_cache_event_ids
));
1998 pr_cont("Atom events, ");
2004 static int amd_pmu_init(void)
2006 /* Performance-monitoring supported from K7 and later: */
2007 if (boot_cpu_data
.x86
< 6)
2012 /* Events are common for all AMDs */
2013 memcpy(hw_cache_event_ids
, amd_hw_cache_event_ids
,
2014 sizeof(hw_cache_event_ids
));
2019 void __init
init_hw_perf_counters(void)
2023 pr_info("Performance Counters: ");
2025 switch (boot_cpu_data
.x86_vendor
) {
2026 case X86_VENDOR_INTEL
:
2027 err
= intel_pmu_init();
2029 case X86_VENDOR_AMD
:
2030 err
= amd_pmu_init();
2036 pr_cont("no PMU driver, software counters only.\n");
2040 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
2042 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
2043 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
2044 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
2045 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
2047 perf_counter_mask
= (1 << x86_pmu
.num_counters
) - 1;
2048 perf_max_counters
= x86_pmu
.num_counters
;
2050 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
2051 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
2052 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
2053 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
2056 perf_counter_mask
|=
2057 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
2058 x86_pmu
.intel_ctrl
= perf_counter_mask
;
2060 perf_counters_lapic_init();
2061 register_die_notifier(&perf_counter_nmi_notifier
);
2063 pr_info("... version: %d\n", x86_pmu
.version
);
2064 pr_info("... bit width: %d\n", x86_pmu
.counter_bits
);
2065 pr_info("... generic counters: %d\n", x86_pmu
.num_counters
);
2066 pr_info("... value mask: %016Lx\n", x86_pmu
.counter_mask
);
2067 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
2068 pr_info("... fixed-purpose counters: %d\n", x86_pmu
.num_counters_fixed
);
2069 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
2072 static inline void x86_pmu_read(struct perf_counter
*counter
)
2074 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
2077 static const struct pmu pmu
= {
2078 .enable
= x86_pmu_enable
,
2079 .disable
= x86_pmu_disable
,
2080 .read
= x86_pmu_read
,
2081 .unthrottle
= x86_pmu_unthrottle
,
2084 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
2088 err
= __hw_perf_counter_init(counter
);
2090 return ERR_PTR(err
);
2100 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
2102 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
2103 entry
->ip
[entry
->nr
++] = ip
;
2106 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
2107 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
2108 static DEFINE_PER_CPU(int, in_nmi_frame
);
2112 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
2114 /* Ignore warnings */
2117 static void backtrace_warning(void *data
, char *msg
)
2119 /* Ignore warnings */
2122 static int backtrace_stack(void *data
, char *name
)
2124 per_cpu(in_nmi_frame
, smp_processor_id()) =
2125 x86_is_stack_id(NMI_STACK
, name
);
2130 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
2132 struct perf_callchain_entry
*entry
= data
;
2134 if (per_cpu(in_nmi_frame
, smp_processor_id()))
2138 callchain_store(entry
, addr
);
2141 static const struct stacktrace_ops backtrace_ops
= {
2142 .warning
= backtrace_warning
,
2143 .warning_symbol
= backtrace_warning_symbol
,
2144 .stack
= backtrace_stack
,
2145 .address
= backtrace_address
,
2148 #include "../dumpstack.h"
2151 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2153 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
2154 callchain_store(entry
, regs
->ip
);
2156 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
2160 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
2162 static unsigned long
2163 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
2165 unsigned long offset
, addr
= (unsigned long)from
;
2166 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
2167 unsigned long size
, len
= 0;
2173 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
2177 offset
= addr
& (PAGE_SIZE
- 1);
2178 size
= min(PAGE_SIZE
- offset
, n
- len
);
2180 map
= kmap_atomic(page
, type
);
2181 memcpy(to
, map
+offset
, size
);
2182 kunmap_atomic(map
, type
);
2194 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
2196 unsigned long bytes
;
2198 bytes
= copy_from_user_nmi(frame
, fp
, sizeof(*frame
));
2200 return bytes
== sizeof(*frame
);
2204 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2206 struct stack_frame frame
;
2207 const void __user
*fp
;
2209 if (!user_mode(regs
))
2210 regs
= task_pt_regs(current
);
2212 fp
= (void __user
*)regs
->bp
;
2214 callchain_store(entry
, PERF_CONTEXT_USER
);
2215 callchain_store(entry
, regs
->ip
);
2217 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2218 frame
.next_frame
= NULL
;
2219 frame
.return_address
= 0;
2221 if (!copy_stack_frame(fp
, &frame
))
2224 if ((unsigned long)fp
< regs
->sp
)
2227 callchain_store(entry
, frame
.return_address
);
2228 fp
= frame
.next_frame
;
2233 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2240 is_user
= user_mode(regs
);
2242 if (!current
|| current
->pid
== 0)
2245 if (is_user
&& current
->state
!= TASK_RUNNING
)
2249 perf_callchain_kernel(regs
, entry
);
2252 perf_callchain_user(regs
, entry
);
2255 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
2257 struct perf_callchain_entry
*entry
;
2260 entry
= &__get_cpu_var(nmi_entry
);
2262 entry
= &__get_cpu_var(irq_entry
);
2266 perf_do_callchain(regs
, entry
);
2271 void hw_perf_counter_setup_online(int cpu
)
2273 init_debug_store_on_cpu(cpu
);