2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
7 * For licencing details see kernel-base/COPYING
10 #include <linux/perf_counter.h>
11 #include <linux/capability.h>
12 #include <linux/notifier.h>
13 #include <linux/hardirq.h>
14 #include <linux/kprobes.h>
15 #include <linux/module.h>
16 #include <linux/kdebug.h>
17 #include <linux/sched.h>
19 #include <asm/intel_arch_perfmon.h>
22 static bool perf_counters_initialized __read_mostly
;
25 * Number of (generic) HW counters:
27 static int nr_hw_counters __read_mostly
;
28 static u32 perf_counter_mask __read_mostly
;
30 /* No support for fixed function counters yet */
32 #define MAX_HW_COUNTERS 8
34 struct cpu_hw_counters
{
35 struct perf_counter
*counters
[MAX_HW_COUNTERS
];
36 unsigned long used
[BITS_TO_LONGS(MAX_HW_COUNTERS
)];
40 * Intel PerfMon v3. Used on Core2 and later.
42 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
);
44 static const int intel_perfmon_event_map
[] =
46 [PERF_COUNT_CYCLES
] = 0x003c,
47 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
48 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
49 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
50 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
51 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
54 static const int max_intel_perfmon_events
= ARRAY_SIZE(intel_perfmon_event_map
);
57 * Propagate counter elapsed time into the generic counter.
58 * Can only be executed on the CPU where the counter is active.
59 * Returns the delta events processed.
62 x86_perf_counter_update(struct perf_counter
*counter
,
63 struct hw_perf_counter
*hwc
, int idx
)
65 u64 prev_raw_count
, new_raw_count
, delta
;
68 * Careful: an NMI might modify the previous counter value.
70 * Our tactic to handle this is to first atomically read and
71 * exchange a new raw count - then add that new-prev delta
72 * count to the generic counter atomically:
75 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
76 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
78 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
79 new_raw_count
) != prev_raw_count
)
83 * Now we have the new raw value and have updated the prev
84 * timestamp already. We can now calculate the elapsed delta
85 * (counter-)time and add that to the generic counter.
87 * Careful, not all hw sign-extends above the physical width
88 * of the count, so we do that by clipping the delta to 32 bits:
90 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
92 atomic64_add(delta
, &counter
->count
);
93 atomic64_sub(delta
, &hwc
->period_left
);
97 * Setup the hardware configuration for a given hw_event_type
99 static int __hw_perf_counter_init(struct perf_counter
*counter
)
101 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
102 struct hw_perf_counter
*hwc
= &counter
->hw
;
104 if (unlikely(!perf_counters_initialized
))
108 * Count user events, and generate PMC IRQs:
109 * (keep 'enabled' bit clear for now)
111 hwc
->config
= ARCH_PERFMON_EVENTSEL_USR
| ARCH_PERFMON_EVENTSEL_INT
;
114 * If privileged enough, count OS events too, and allow
115 * NMI events as well:
118 if (capable(CAP_SYS_ADMIN
)) {
119 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
124 hwc
->config_base
= MSR_ARCH_PERFMON_EVENTSEL0
;
125 hwc
->counter_base
= MSR_ARCH_PERFMON_PERFCTR0
;
127 hwc
->irq_period
= hw_event
->irq_period
;
129 * Intel PMCs cannot be accessed sanely above 32 bit width,
130 * so we install an artificial 1<<31 period regardless of
131 * the generic counter period:
133 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
134 hwc
->irq_period
= 0x7FFFFFFF;
136 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
139 * Raw event type provide the config in the event structure
142 hwc
->config
|= hw_event
->type
;
144 if (hw_event
->type
>= max_intel_perfmon_events
)
149 hwc
->config
|= intel_perfmon_event_map
[hw_event
->type
];
151 counter
->wakeup_pending
= 0;
156 void hw_perf_enable_all(void)
158 if (unlikely(!perf_counters_initialized
))
161 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL
, perf_counter_mask
, 0);
164 u64
hw_perf_save_disable(void)
168 if (unlikely(!perf_counters_initialized
))
171 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
172 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL
, 0, 0);
176 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
178 void hw_perf_restore(u64 ctrl
)
180 if (unlikely(!perf_counters_initialized
))
183 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
, 0);
185 EXPORT_SYMBOL_GPL(hw_perf_restore
);
188 __x86_perf_counter_disable(struct perf_counter
*counter
,
189 struct hw_perf_counter
*hwc
, unsigned int idx
)
193 err
= wrmsr_safe(hwc
->config_base
+ idx
, hwc
->config
, 0);
196 static DEFINE_PER_CPU(u64
, prev_left
[MAX_HW_COUNTERS
]);
199 * Set the next IRQ period, based on the hwc->period_left value.
200 * To be called with the counter disabled in hw:
203 __hw_perf_counter_set_period(struct perf_counter
*counter
,
204 struct hw_perf_counter
*hwc
, int idx
)
206 s32 left
= atomic64_read(&hwc
->period_left
);
207 s32 period
= hwc
->irq_period
;
210 * If we are way outside a reasoable range then just skip forward:
212 if (unlikely(left
<= -period
)) {
214 atomic64_set(&hwc
->period_left
, left
);
217 if (unlikely(left
<= 0)) {
219 atomic64_set(&hwc
->period_left
, left
);
222 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
225 * The hw counter starts counting from this counter offset,
226 * mark it to be able to extra future deltas:
228 atomic64_set(&hwc
->prev_count
, (u64
)(s64
)-left
);
230 wrmsr(hwc
->counter_base
+ idx
, -left
, 0);
234 __x86_perf_counter_enable(struct perf_counter
*counter
,
235 struct hw_perf_counter
*hwc
, int idx
)
237 wrmsr(hwc
->config_base
+ idx
,
238 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
, 0);
242 * Find a PMC slot for the freshly enabled / scheduled in counter:
244 static void x86_perf_counter_enable(struct perf_counter
*counter
)
246 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
247 struct hw_perf_counter
*hwc
= &counter
->hw
;
250 /* Try to get the previous counter again */
251 if (test_and_set_bit(idx
, cpuc
->used
)) {
252 idx
= find_first_zero_bit(cpuc
->used
, nr_hw_counters
);
253 set_bit(idx
, cpuc
->used
);
257 perf_counters_lapic_init(hwc
->nmi
);
259 __x86_perf_counter_disable(counter
, hwc
, idx
);
261 cpuc
->counters
[idx
] = counter
;
263 __hw_perf_counter_set_period(counter
, hwc
, idx
);
264 __x86_perf_counter_enable(counter
, hwc
, idx
);
267 void perf_counter_print_debug(void)
269 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
;
277 cpu
= smp_processor_id();
279 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
280 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
281 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
283 printk(KERN_INFO
"\n");
284 printk(KERN_INFO
"CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
285 printk(KERN_INFO
"CPU#%d: status: %016llx\n", cpu
, status
);
286 printk(KERN_INFO
"CPU#%d: overflow: %016llx\n", cpu
, overflow
);
288 for (idx
= 0; idx
< nr_hw_counters
; idx
++) {
289 rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, pmc_ctrl
);
290 rdmsrl(MSR_ARCH_PERFMON_PERFCTR0
+ idx
, pmc_count
);
292 prev_left
= per_cpu(prev_left
[idx
], cpu
);
294 printk(KERN_INFO
"CPU#%d: PMC%d ctrl: %016llx\n",
296 printk(KERN_INFO
"CPU#%d: PMC%d count: %016llx\n",
297 cpu
, idx
, pmc_count
);
298 printk(KERN_INFO
"CPU#%d: PMC%d left: %016llx\n",
299 cpu
, idx
, prev_left
);
304 static void x86_perf_counter_disable(struct perf_counter
*counter
)
306 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
307 struct hw_perf_counter
*hwc
= &counter
->hw
;
308 unsigned int idx
= hwc
->idx
;
310 __x86_perf_counter_disable(counter
, hwc
, idx
);
312 clear_bit(idx
, cpuc
->used
);
313 cpuc
->counters
[idx
] = NULL
;
316 * Drain the remaining delta count out of a counter
317 * that we are disabling:
319 x86_perf_counter_update(counter
, hwc
, idx
);
322 static void perf_store_irq_data(struct perf_counter
*counter
, u64 data
)
324 struct perf_data
*irqdata
= counter
->irqdata
;
326 if (irqdata
->len
> PERF_DATA_BUFLEN
- sizeof(u64
)) {
329 u64
*p
= (u64
*) &irqdata
->data
[irqdata
->len
];
332 irqdata
->len
+= sizeof(u64
);
337 * Save and restart an expired counter. Called by NMI contexts,
338 * so it has to be careful about preempting normal counter ops:
340 static void perf_save_and_restart(struct perf_counter
*counter
)
342 struct hw_perf_counter
*hwc
= &counter
->hw
;
346 rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, pmc_ctrl
);
348 x86_perf_counter_update(counter
, hwc
, idx
);
349 __hw_perf_counter_set_period(counter
, hwc
, idx
);
351 if (pmc_ctrl
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
352 __x86_perf_counter_enable(counter
, hwc
, idx
);
356 perf_handle_group(struct perf_counter
*sibling
, u64
*status
, u64
*overflown
)
358 struct perf_counter
*counter
, *group_leader
= sibling
->group_leader
;
361 * Store sibling timestamps (if any):
363 list_for_each_entry(counter
, &group_leader
->sibling_list
, list_entry
) {
364 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
365 perf_store_irq_data(sibling
, counter
->hw_event
.type
);
366 perf_store_irq_data(sibling
, atomic64_read(&counter
->count
));
371 * This handler is triggered by the local APIC, so the APIC IRQ handling
374 static void __smp_perf_counter_interrupt(struct pt_regs
*regs
, int nmi
)
376 int bit
, cpu
= smp_processor_id();
377 u64 ack
, status
, saved_global
;
378 struct cpu_hw_counters
*cpuc
;
380 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, saved_global
);
382 /* Disable counters globally */
383 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL
, 0, 0);
386 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
388 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
394 for_each_bit(bit
, (unsigned long *) &status
, nr_hw_counters
) {
395 struct perf_counter
*counter
= cpuc
->counters
[bit
];
397 clear_bit(bit
, (unsigned long *) &status
);
401 perf_save_and_restart(counter
);
403 switch (counter
->hw_event
.record_type
) {
404 case PERF_RECORD_SIMPLE
:
406 case PERF_RECORD_IRQ
:
407 perf_store_irq_data(counter
, instruction_pointer(regs
));
409 case PERF_RECORD_GROUP
:
410 perf_handle_group(counter
, &status
, &ack
);
414 * From NMI context we cannot call into the scheduler to
415 * do a task wakeup - but we mark these counters as
416 * wakeup_pending and initate a wakeup callback:
419 counter
->wakeup_pending
= 1;
420 set_tsk_thread_flag(current
, TIF_PERF_COUNTERS
);
422 wake_up(&counter
->waitq
);
426 wrmsr(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
, 0);
429 * Repeat if there is more work to be done:
431 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
436 * Restore - do not reenable when global enable is off:
438 wrmsr(MSR_CORE_PERF_GLOBAL_CTRL
, saved_global
, 0);
441 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
444 inc_irq_stat(apic_perf_irqs
);
445 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
446 __smp_perf_counter_interrupt(regs
, 0);
452 * This handler is triggered by NMI contexts:
454 void perf_counter_notify(struct pt_regs
*regs
)
456 struct cpu_hw_counters
*cpuc
;
460 local_irq_save(flags
);
461 cpu
= smp_processor_id();
462 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
464 for_each_bit(bit
, cpuc
->used
, nr_hw_counters
) {
465 struct perf_counter
*counter
= cpuc
->counters
[bit
];
470 if (counter
->wakeup_pending
) {
471 counter
->wakeup_pending
= 0;
472 wake_up(&counter
->waitq
);
476 local_irq_restore(flags
);
479 void __cpuinit
perf_counters_lapic_init(int nmi
)
483 if (!perf_counters_initialized
)
486 * Enable the performance counter vector in the APIC LVT:
488 apic_val
= apic_read(APIC_LVTERR
);
490 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
492 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
494 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
495 apic_write(APIC_LVTERR
, apic_val
);
499 perf_counter_nmi_handler(struct notifier_block
*self
,
500 unsigned long cmd
, void *__args
)
502 struct die_args
*args
= __args
;
503 struct pt_regs
*regs
;
505 if (likely(cmd
!= DIE_NMI_IPI
))
510 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
511 __smp_perf_counter_interrupt(regs
, 1);
516 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
517 .notifier_call
= perf_counter_nmi_handler
520 void __init
init_hw_perf_counters(void)
522 union cpuid10_eax eax
;
526 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
530 * Check whether the Architectural PerfMon supports
531 * Branch Misses Retired Event or not.
533 cpuid(10, &(eax
.full
), &ebx
, &unused
, &unused
);
534 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
537 printk(KERN_INFO
"Intel Performance Monitoring support detected.\n");
539 printk(KERN_INFO
"... version: %d\n", eax
.split
.version_id
);
540 printk(KERN_INFO
"... num_counters: %d\n", eax
.split
.num_counters
);
541 nr_hw_counters
= eax
.split
.num_counters
;
542 if (nr_hw_counters
> MAX_HW_COUNTERS
) {
543 nr_hw_counters
= MAX_HW_COUNTERS
;
544 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
545 nr_hw_counters
, MAX_HW_COUNTERS
);
547 perf_counter_mask
= (1 << nr_hw_counters
) - 1;
548 perf_max_counters
= nr_hw_counters
;
550 printk(KERN_INFO
"... bit_width: %d\n", eax
.split
.bit_width
);
551 printk(KERN_INFO
"... mask_length: %d\n", eax
.split
.mask_length
);
553 perf_counters_initialized
= true;
555 perf_counters_lapic_init(0);
556 register_die_notifier(&perf_counter_nmi_notifier
);
559 static void x86_perf_counter_read(struct perf_counter
*counter
)
561 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
564 static const struct hw_perf_counter_ops x86_perf_counter_ops
= {
565 .hw_perf_counter_enable
= x86_perf_counter_enable
,
566 .hw_perf_counter_disable
= x86_perf_counter_disable
,
567 .hw_perf_counter_read
= x86_perf_counter_read
,
570 const struct hw_perf_counter_ops
*
571 hw_perf_counter_init(struct perf_counter
*counter
)
575 err
= __hw_perf_counter_init(counter
);
579 return &x86_perf_counter_ops
;