2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
7 * For licencing details see kernel-base/COPYING
10 #include <linux/perf_counter.h>
11 #include <linux/capability.h>
12 #include <linux/notifier.h>
13 #include <linux/hardirq.h>
14 #include <linux/kprobes.h>
15 #include <linux/module.h>
16 #include <linux/kdebug.h>
17 #include <linux/sched.h>
19 #include <asm/perf_counter.h>
22 static bool perf_counters_initialized __read_mostly
;
25 * Number of (generic) HW counters:
27 static int nr_counters_generic __read_mostly
;
28 static u64 perf_counter_mask __read_mostly
;
29 static u64 counter_value_mask __read_mostly
;
31 static int nr_counters_fixed __read_mostly
;
33 struct cpu_hw_counters
{
34 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
35 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
39 * Intel PerfMon v3. Used on Core2 and later.
41 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
);
43 static const int intel_perfmon_event_map
[] =
45 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
46 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
47 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
48 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
49 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
50 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
51 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
54 static const int max_intel_perfmon_events
= ARRAY_SIZE(intel_perfmon_event_map
);
57 * Propagate counter elapsed time into the generic counter.
58 * Can only be executed on the CPU where the counter is active.
59 * Returns the delta events processed.
62 x86_perf_counter_update(struct perf_counter
*counter
,
63 struct hw_perf_counter
*hwc
, int idx
)
65 u64 prev_raw_count
, new_raw_count
, delta
;
68 * Careful: an NMI might modify the previous counter value.
70 * Our tactic to handle this is to first atomically read and
71 * exchange a new raw count - then add that new-prev delta
72 * count to the generic counter atomically:
75 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
76 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
78 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
79 new_raw_count
) != prev_raw_count
)
83 * Now we have the new raw value and have updated the prev
84 * timestamp already. We can now calculate the elapsed delta
85 * (counter-)time and add that to the generic counter.
87 * Careful, not all hw sign-extends above the physical width
88 * of the count, so we do that by clipping the delta to 32 bits:
90 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
92 atomic64_add(delta
, &counter
->count
);
93 atomic64_sub(delta
, &hwc
->period_left
);
97 * Setup the hardware configuration for a given hw_event_type
99 static int __hw_perf_counter_init(struct perf_counter
*counter
)
101 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
102 struct hw_perf_counter
*hwc
= &counter
->hw
;
104 if (unlikely(!perf_counters_initialized
))
108 * Count user events, and generate PMC IRQs:
109 * (keep 'enabled' bit clear for now)
111 hwc
->config
= ARCH_PERFMON_EVENTSEL_USR
| ARCH_PERFMON_EVENTSEL_INT
;
114 * If privileged enough, count OS events too, and allow
115 * NMI events as well:
118 if (capable(CAP_SYS_ADMIN
)) {
119 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
124 hwc
->irq_period
= hw_event
->irq_period
;
126 * Intel PMCs cannot be accessed sanely above 32 bit width,
127 * so we install an artificial 1<<31 period regardless of
128 * the generic counter period:
130 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
131 hwc
->irq_period
= 0x7FFFFFFF;
133 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
136 * Raw event type provide the config in the event structure
139 hwc
->config
|= hw_event
->type
;
141 if (hw_event
->type
>= max_intel_perfmon_events
)
146 hwc
->config
|= intel_perfmon_event_map
[hw_event
->type
];
148 counter
->wakeup_pending
= 0;
153 u64
hw_perf_save_disable(void)
157 if (unlikely(!perf_counters_initialized
))
160 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
161 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
165 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
167 void hw_perf_restore(u64 ctrl
)
169 if (unlikely(!perf_counters_initialized
))
172 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
174 EXPORT_SYMBOL_GPL(hw_perf_restore
);
177 __pmc_fixed_disable(struct perf_counter
*counter
,
178 struct hw_perf_counter
*hwc
, unsigned int __idx
)
180 int idx
= __idx
- X86_PMC_IDX_FIXED
;
184 mask
= 0xfULL
<< (idx
* 4);
186 rdmsrl(hwc
->config_base
, ctrl_val
);
188 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
192 __pmc_generic_disable(struct perf_counter
*counter
,
193 struct hw_perf_counter
*hwc
, unsigned int idx
)
195 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
196 __pmc_fixed_disable(counter
, hwc
, idx
);
198 wrmsr_safe(hwc
->config_base
+ idx
, hwc
->config
, 0);
201 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
204 * Set the next IRQ period, based on the hwc->period_left value.
205 * To be called with the counter disabled in hw:
208 __hw_perf_counter_set_period(struct perf_counter
*counter
,
209 struct hw_perf_counter
*hwc
, int idx
)
211 s64 left
= atomic64_read(&hwc
->period_left
);
212 s32 period
= hwc
->irq_period
;
216 * If we are way outside a reasoable range then just skip forward:
218 if (unlikely(left
<= -period
)) {
220 atomic64_set(&hwc
->period_left
, left
);
223 if (unlikely(left
<= 0)) {
225 atomic64_set(&hwc
->period_left
, left
);
228 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
231 * The hw counter starts counting from this counter offset,
232 * mark it to be able to extra future deltas:
234 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
236 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
237 (u64
)(-left
) & counter_value_mask
);
241 __pmc_fixed_enable(struct perf_counter
*counter
,
242 struct hw_perf_counter
*hwc
, unsigned int __idx
)
244 int idx
= __idx
- X86_PMC_IDX_FIXED
;
245 u64 ctrl_val
, bits
, mask
;
249 * Enable IRQ generation (0x8) and ring-3 counting (0x2),
250 * and enable ring-0 counting if allowed:
252 bits
= 0x8ULL
| 0x2ULL
;
253 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
256 mask
= 0xfULL
<< (idx
* 4);
258 rdmsrl(hwc
->config_base
, ctrl_val
);
261 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
265 __pmc_generic_enable(struct perf_counter
*counter
,
266 struct hw_perf_counter
*hwc
, int idx
)
268 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
269 __pmc_fixed_enable(counter
, hwc
, idx
);
271 wrmsr(hwc
->config_base
+ idx
,
272 hwc
->config
| ARCH_PERFMON_EVENTSEL0_ENABLE
, 0);
276 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
280 if (unlikely(hwc
->nmi
))
283 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
285 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_INSTRUCTIONS
]))
286 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
287 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_CPU_CYCLES
]))
288 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
289 if (unlikely(event
== intel_perfmon_event_map
[PERF_COUNT_BUS_CYCLES
]))
290 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
296 * Find a PMC slot for the freshly enabled / scheduled in counter:
298 static int pmc_generic_enable(struct perf_counter
*counter
)
300 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
301 struct hw_perf_counter
*hwc
= &counter
->hw
;
304 idx
= fixed_mode_idx(counter
, hwc
);
307 * Try to get the fixed counter, if that is already taken
308 * then try to get a generic counter:
310 if (test_and_set_bit(idx
, cpuc
->used
))
313 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
315 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
316 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
319 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
323 /* Try to get the previous generic counter again */
324 if (test_and_set_bit(idx
, cpuc
->used
)) {
326 idx
= find_first_zero_bit(cpuc
->used
, nr_counters_generic
);
327 if (idx
== nr_counters_generic
)
330 set_bit(idx
, cpuc
->used
);
333 hwc
->config_base
= MSR_ARCH_PERFMON_EVENTSEL0
;
334 hwc
->counter_base
= MSR_ARCH_PERFMON_PERFCTR0
;
337 perf_counters_lapic_init(hwc
->nmi
);
339 __pmc_generic_disable(counter
, hwc
, idx
);
341 cpuc
->counters
[idx
] = counter
;
343 * Make it visible before enabling the hw:
347 __hw_perf_counter_set_period(counter
, hwc
, idx
);
348 __pmc_generic_enable(counter
, hwc
, idx
);
353 void perf_counter_print_debug(void)
355 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
356 struct cpu_hw_counters
*cpuc
;
359 if (!nr_counters_generic
)
364 cpu
= smp_processor_id();
365 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
367 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
368 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
369 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
370 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
372 printk(KERN_INFO
"\n");
373 printk(KERN_INFO
"CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
374 printk(KERN_INFO
"CPU#%d: status: %016llx\n", cpu
, status
);
375 printk(KERN_INFO
"CPU#%d: overflow: %016llx\n", cpu
, overflow
);
376 printk(KERN_INFO
"CPU#%d: fixed: %016llx\n", cpu
, fixed
);
377 printk(KERN_INFO
"CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used
);
379 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
380 rdmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, pmc_ctrl
);
381 rdmsrl(MSR_ARCH_PERFMON_PERFCTR0
+ idx
, pmc_count
);
383 prev_left
= per_cpu(prev_left
[idx
], cpu
);
385 printk(KERN_INFO
"CPU#%d: gen-PMC%d ctrl: %016llx\n",
387 printk(KERN_INFO
"CPU#%d: gen-PMC%d count: %016llx\n",
388 cpu
, idx
, pmc_count
);
389 printk(KERN_INFO
"CPU#%d: gen-PMC%d left: %016llx\n",
390 cpu
, idx
, prev_left
);
392 for (idx
= 0; idx
< nr_counters_fixed
; idx
++) {
393 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
395 printk(KERN_INFO
"CPU#%d: fixed-PMC%d count: %016llx\n",
396 cpu
, idx
, pmc_count
);
401 static void pmc_generic_disable(struct perf_counter
*counter
)
403 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
404 struct hw_perf_counter
*hwc
= &counter
->hw
;
405 unsigned int idx
= hwc
->idx
;
407 __pmc_generic_disable(counter
, hwc
, idx
);
409 clear_bit(idx
, cpuc
->used
);
410 cpuc
->counters
[idx
] = NULL
;
412 * Make sure the cleared pointer becomes visible before we
413 * (potentially) free the counter:
418 * Drain the remaining delta count out of a counter
419 * that we are disabling:
421 x86_perf_counter_update(counter
, hwc
, idx
);
424 static void perf_store_irq_data(struct perf_counter
*counter
, u64 data
)
426 struct perf_data
*irqdata
= counter
->irqdata
;
428 if (irqdata
->len
> PERF_DATA_BUFLEN
- sizeof(u64
)) {
431 u64
*p
= (u64
*) &irqdata
->data
[irqdata
->len
];
434 irqdata
->len
+= sizeof(u64
);
439 * Save and restart an expired counter. Called by NMI contexts,
440 * so it has to be careful about preempting normal counter ops:
442 static void perf_save_and_restart(struct perf_counter
*counter
)
444 struct hw_perf_counter
*hwc
= &counter
->hw
;
447 x86_perf_counter_update(counter
, hwc
, idx
);
448 __hw_perf_counter_set_period(counter
, hwc
, idx
);
450 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
451 __pmc_generic_enable(counter
, hwc
, idx
);
455 perf_handle_group(struct perf_counter
*sibling
, u64
*status
, u64
*overflown
)
457 struct perf_counter
*counter
, *group_leader
= sibling
->group_leader
;
460 * Store sibling timestamps (if any):
462 list_for_each_entry(counter
, &group_leader
->sibling_list
, list_entry
) {
464 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
465 perf_store_irq_data(sibling
, counter
->hw_event
.type
);
466 perf_store_irq_data(sibling
, atomic64_read(&counter
->count
));
471 * This handler is triggered by the local APIC, so the APIC IRQ handling
474 static void __smp_perf_counter_interrupt(struct pt_regs
*regs
, int nmi
)
476 int bit
, cpu
= smp_processor_id();
477 u64 ack
, status
, saved_global
;
478 struct cpu_hw_counters
*cpuc
;
480 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, saved_global
);
482 /* Disable counters globally */
483 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
486 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
488 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
494 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
495 struct perf_counter
*counter
= cpuc
->counters
[bit
];
497 clear_bit(bit
, (unsigned long *) &status
);
501 perf_save_and_restart(counter
);
503 switch (counter
->hw_event
.record_type
) {
504 case PERF_RECORD_SIMPLE
:
506 case PERF_RECORD_IRQ
:
507 perf_store_irq_data(counter
, instruction_pointer(regs
));
509 case PERF_RECORD_GROUP
:
510 perf_handle_group(counter
, &status
, &ack
);
514 * From NMI context we cannot call into the scheduler to
515 * do a task wakeup - but we mark these generic as
516 * wakeup_pending and initate a wakeup callback:
519 counter
->wakeup_pending
= 1;
520 set_tsk_thread_flag(current
, TIF_PERF_COUNTERS
);
522 wake_up(&counter
->waitq
);
526 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
529 * Repeat if there is more work to be done:
531 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
536 * Restore - do not reenable when global enable is off:
538 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, saved_global
);
541 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
544 inc_irq_stat(apic_perf_irqs
);
545 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
546 __smp_perf_counter_interrupt(regs
, 0);
552 * This handler is triggered by NMI contexts:
554 void perf_counter_notify(struct pt_regs
*regs
)
556 struct cpu_hw_counters
*cpuc
;
560 local_irq_save(flags
);
561 cpu
= smp_processor_id();
562 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
564 for_each_bit(bit
, cpuc
->used
, X86_PMC_IDX_MAX
) {
565 struct perf_counter
*counter
= cpuc
->counters
[bit
];
570 if (counter
->wakeup_pending
) {
571 counter
->wakeup_pending
= 0;
572 wake_up(&counter
->waitq
);
576 local_irq_restore(flags
);
579 void __cpuinit
perf_counters_lapic_init(int nmi
)
583 if (!perf_counters_initialized
)
586 * Enable the performance counter vector in the APIC LVT:
588 apic_val
= apic_read(APIC_LVTERR
);
590 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
592 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
594 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
595 apic_write(APIC_LVTERR
, apic_val
);
599 perf_counter_nmi_handler(struct notifier_block
*self
,
600 unsigned long cmd
, void *__args
)
602 struct die_args
*args
= __args
;
603 struct pt_regs
*regs
;
605 if (likely(cmd
!= DIE_NMI_IPI
))
610 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
611 __smp_perf_counter_interrupt(regs
, 1);
616 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
617 .notifier_call
= perf_counter_nmi_handler
620 void __init
init_hw_perf_counters(void)
622 union cpuid10_eax eax
;
625 union cpuid10_edx edx
;
627 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
631 * Check whether the Architectural PerfMon supports
632 * Branch Misses Retired Event or not.
634 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
635 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
638 printk(KERN_INFO
"Intel Performance Monitoring support detected.\n");
640 printk(KERN_INFO
"... version: %d\n", eax
.split
.version_id
);
641 printk(KERN_INFO
"... num counters: %d\n", eax
.split
.num_counters
);
642 nr_counters_generic
= eax
.split
.num_counters
;
643 if (nr_counters_generic
> X86_PMC_MAX_GENERIC
) {
644 nr_counters_generic
= X86_PMC_MAX_GENERIC
;
645 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
646 nr_counters_generic
, X86_PMC_MAX_GENERIC
);
648 perf_counter_mask
= (1 << nr_counters_generic
) - 1;
649 perf_max_counters
= nr_counters_generic
;
651 printk(KERN_INFO
"... bit width: %d\n", eax
.split
.bit_width
);
652 counter_value_mask
= (1ULL << eax
.split
.bit_width
) - 1;
653 printk(KERN_INFO
"... value mask: %016Lx\n", counter_value_mask
);
655 printk(KERN_INFO
"... mask length: %d\n", eax
.split
.mask_length
);
657 nr_counters_fixed
= edx
.split
.num_counters_fixed
;
658 if (nr_counters_fixed
> X86_PMC_MAX_FIXED
) {
659 nr_counters_fixed
= X86_PMC_MAX_FIXED
;
660 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
661 nr_counters_fixed
, X86_PMC_MAX_FIXED
);
663 printk(KERN_INFO
"... fixed counters: %d\n", nr_counters_fixed
);
665 perf_counter_mask
|= ((1LL << nr_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
667 printk(KERN_INFO
"... counter mask: %016Lx\n", perf_counter_mask
);
668 perf_counters_initialized
= true;
670 perf_counters_lapic_init(0);
671 register_die_notifier(&perf_counter_nmi_notifier
);
674 static void pmc_generic_read(struct perf_counter
*counter
)
676 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
679 static const struct hw_perf_counter_ops x86_perf_counter_ops
= {
680 .enable
= pmc_generic_enable
,
681 .disable
= pmc_generic_disable
,
682 .read
= pmc_generic_read
,
685 const struct hw_perf_counter_ops
*
686 hw_perf_counter_init(struct perf_counter
*counter
)
690 err
= __hw_perf_counter_init(counter
);
694 return &x86_perf_counter_ops
;