2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/timer.h>
36 #include "perf_event.h"
38 struct x86_pmu x86_pmu __read_mostly
;
40 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
44 u64 __read_mostly hw_cache_event_ids
45 [PERF_COUNT_HW_CACHE_MAX
]
46 [PERF_COUNT_HW_CACHE_OP_MAX
]
47 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
48 u64 __read_mostly hw_cache_extra_regs
49 [PERF_COUNT_HW_CACHE_MAX
]
50 [PERF_COUNT_HW_CACHE_OP_MAX
]
51 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
54 * Propagate event elapsed time into the generic event.
55 * Can only be executed on the CPU where the event is active.
56 * Returns the delta events processed.
58 u64
x86_perf_event_update(struct perf_event
*event
)
60 struct hw_perf_event
*hwc
= &event
->hw
;
61 int shift
= 64 - x86_pmu
.cntval_bits
;
62 u64 prev_raw_count
, new_raw_count
;
66 if (idx
== X86_PMC_IDX_FIXED_BTS
)
70 * Careful: an NMI might modify the previous event value.
72 * Our tactic to handle this is to first atomically read and
73 * exchange a new raw count - then add that new-prev delta
74 * count to the generic event atomically:
77 prev_raw_count
= local64_read(&hwc
->prev_count
);
78 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
80 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
81 new_raw_count
) != prev_raw_count
)
85 * Now we have the new raw value and have updated the prev
86 * timestamp already. We can now calculate the elapsed delta
87 * (event-)time and add that to the generic event.
89 * Careful, not all hw sign-extends above the physical width
92 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
95 local64_add(delta
, &event
->count
);
96 local64_sub(delta
, &hwc
->period_left
);
102 * Find and validate any extra registers to set up.
104 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
106 struct hw_perf_event_extra
*reg
;
107 struct extra_reg
*er
;
109 reg
= &event
->hw
.extra_reg
;
111 if (!x86_pmu
.extra_regs
)
114 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
115 if (er
->event
!= (config
& er
->config_mask
))
117 if (event
->attr
.config1
& ~er
->valid_mask
)
121 reg
->config
= event
->attr
.config1
;
128 static atomic_t active_events
;
129 static DEFINE_MUTEX(pmc_reserve_mutex
);
131 #ifdef CONFIG_X86_LOCAL_APIC
133 static bool reserve_pmc_hardware(void)
137 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
138 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
142 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
143 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
150 for (i
--; i
>= 0; i
--)
151 release_evntsel_nmi(x86_pmu_config_addr(i
));
153 i
= x86_pmu
.num_counters
;
156 for (i
--; i
>= 0; i
--)
157 release_perfctr_nmi(x86_pmu_event_addr(i
));
162 static void release_pmc_hardware(void)
166 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
167 release_perfctr_nmi(x86_pmu_event_addr(i
));
168 release_evntsel_nmi(x86_pmu_config_addr(i
));
174 static bool reserve_pmc_hardware(void) { return true; }
175 static void release_pmc_hardware(void) {}
179 static bool check_hw_exists(void)
181 u64 val
, val_new
= 0;
185 * Check to see if the BIOS enabled any of the counters, if so
188 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
189 reg
= x86_pmu_config_addr(i
);
190 ret
= rdmsrl_safe(reg
, &val
);
193 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
)
197 if (x86_pmu
.num_counters_fixed
) {
198 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
199 ret
= rdmsrl_safe(reg
, &val
);
202 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
203 if (val
& (0x03 << i
*4))
209 * Now write a value and read it back to see if it matches,
210 * this is needed to detect certain hardware emulators (qemu/kvm)
211 * that don't trap on the MSR access and always return 0s.
214 ret
= checking_wrmsrl(x86_pmu_event_addr(0), val
);
215 ret
|= rdmsrl_safe(x86_pmu_event_addr(0), &val_new
);
216 if (ret
|| val
!= val_new
)
223 * We still allow the PMU driver to operate:
225 printk(KERN_CONT
"Broken BIOS detected, complain to your hardware vendor.\n");
226 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg
, val
);
231 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
236 static void hw_perf_event_destroy(struct perf_event
*event
)
238 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
239 release_pmc_hardware();
240 release_ds_buffers();
241 mutex_unlock(&pmc_reserve_mutex
);
245 static inline int x86_pmu_initialized(void)
247 return x86_pmu
.handle_irq
!= NULL
;
251 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
253 struct perf_event_attr
*attr
= &event
->attr
;
254 unsigned int cache_type
, cache_op
, cache_result
;
257 config
= attr
->config
;
259 cache_type
= (config
>> 0) & 0xff;
260 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
263 cache_op
= (config
>> 8) & 0xff;
264 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
267 cache_result
= (config
>> 16) & 0xff;
268 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
271 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
280 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
281 return x86_pmu_extra_regs(val
, event
);
284 int x86_setup_perfctr(struct perf_event
*event
)
286 struct perf_event_attr
*attr
= &event
->attr
;
287 struct hw_perf_event
*hwc
= &event
->hw
;
290 if (!is_sampling_event(event
)) {
291 hwc
->sample_period
= x86_pmu
.max_period
;
292 hwc
->last_period
= hwc
->sample_period
;
293 local64_set(&hwc
->period_left
, hwc
->sample_period
);
296 * If we have a PMU initialized but no APIC
297 * interrupts, we cannot sample hardware
298 * events (user-space has to fall back and
299 * sample via a hrtimer based software event):
305 if (attr
->type
== PERF_TYPE_RAW
)
306 return x86_pmu_extra_regs(event
->attr
.config
, event
);
308 if (attr
->type
== PERF_TYPE_HW_CACHE
)
309 return set_ext_hw_attr(hwc
, event
);
311 if (attr
->config
>= x86_pmu
.max_events
)
317 config
= x86_pmu
.event_map(attr
->config
);
328 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
329 !attr
->freq
&& hwc
->sample_period
== 1) {
330 /* BTS is not supported by this architecture. */
331 if (!x86_pmu
.bts_active
)
334 /* BTS is currently only allowed for user-mode. */
335 if (!attr
->exclude_kernel
)
339 hwc
->config
|= config
;
345 * check that branch_sample_type is compatible with
346 * settings needed for precise_ip > 1 which implies
347 * using the LBR to capture ALL taken branches at the
348 * priv levels of the measurement
350 static inline int precise_br_compat(struct perf_event
*event
)
352 u64 m
= event
->attr
.branch_sample_type
;
355 /* must capture all branches */
356 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
359 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
361 if (!event
->attr
.exclude_user
)
362 b
|= PERF_SAMPLE_BRANCH_USER
;
364 if (!event
->attr
.exclude_kernel
)
365 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
368 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
374 int x86_pmu_hw_config(struct perf_event
*event
)
376 if (event
->attr
.precise_ip
) {
379 /* Support for constant skid */
380 if (x86_pmu
.pebs_active
) {
383 /* Support for IP fixup */
388 if (event
->attr
.precise_ip
> precise
)
391 * check that PEBS LBR correction does not conflict with
392 * whatever the user is asking with attr->branch_sample_type
394 if (event
->attr
.precise_ip
> 1) {
395 u64
*br_type
= &event
->attr
.branch_sample_type
;
397 if (has_branch_stack(event
)) {
398 if (!precise_br_compat(event
))
401 /* branch_sample_type is compatible */
405 * user did not specify branch_sample_type
407 * For PEBS fixups, we capture all
408 * the branches at the priv level of the
411 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
413 if (!event
->attr
.exclude_user
)
414 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
416 if (!event
->attr
.exclude_kernel
)
417 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
424 * (keep 'enabled' bit clear for now)
426 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
429 * Count user and OS events unless requested not to
431 if (!event
->attr
.exclude_user
)
432 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
433 if (!event
->attr
.exclude_kernel
)
434 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
436 if (event
->attr
.type
== PERF_TYPE_RAW
)
437 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
439 return x86_setup_perfctr(event
);
443 * Setup the hardware configuration for a given attr_type
445 static int __x86_pmu_event_init(struct perf_event
*event
)
449 if (!x86_pmu_initialized())
453 if (!atomic_inc_not_zero(&active_events
)) {
454 mutex_lock(&pmc_reserve_mutex
);
455 if (atomic_read(&active_events
) == 0) {
456 if (!reserve_pmc_hardware())
459 reserve_ds_buffers();
462 atomic_inc(&active_events
);
463 mutex_unlock(&pmc_reserve_mutex
);
468 event
->destroy
= hw_perf_event_destroy
;
471 event
->hw
.last_cpu
= -1;
472 event
->hw
.last_tag
= ~0ULL;
475 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
476 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
478 return x86_pmu
.hw_config(event
);
481 void x86_pmu_disable_all(void)
483 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
486 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
489 if (!test_bit(idx
, cpuc
->active_mask
))
491 rdmsrl(x86_pmu_config_addr(idx
), val
);
492 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
494 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
495 wrmsrl(x86_pmu_config_addr(idx
), val
);
499 static void x86_pmu_disable(struct pmu
*pmu
)
501 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
503 if (!x86_pmu_initialized())
513 x86_pmu
.disable_all();
516 void x86_pmu_enable_all(int added
)
518 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
521 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
522 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
524 if (!test_bit(idx
, cpuc
->active_mask
))
527 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
531 static struct pmu pmu
;
533 static inline int is_x86_event(struct perf_event
*event
)
535 return event
->pmu
== &pmu
;
539 * Event scheduler state:
541 * Assign events iterating over all events and counters, beginning
542 * with events with least weights first. Keep the current iterator
543 * state in struct sched_state.
547 int event
; /* event index */
548 int counter
; /* counter index */
549 int unassigned
; /* number of events to be assigned left */
550 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
553 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
554 #define SCHED_STATES_MAX 2
559 struct event_constraint
**constraints
;
560 struct sched_state state
;
562 struct sched_state saved
[SCHED_STATES_MAX
];
566 * Initialize interator that runs through all events and counters.
568 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**c
,
569 int num
, int wmin
, int wmax
)
573 memset(sched
, 0, sizeof(*sched
));
574 sched
->max_events
= num
;
575 sched
->max_weight
= wmax
;
576 sched
->constraints
= c
;
578 for (idx
= 0; idx
< num
; idx
++) {
579 if (c
[idx
]->weight
== wmin
)
583 sched
->state
.event
= idx
; /* start with min weight */
584 sched
->state
.weight
= wmin
;
585 sched
->state
.unassigned
= num
;
588 static void perf_sched_save_state(struct perf_sched
*sched
)
590 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
593 sched
->saved
[sched
->saved_states
] = sched
->state
;
594 sched
->saved_states
++;
597 static bool perf_sched_restore_state(struct perf_sched
*sched
)
599 if (!sched
->saved_states
)
602 sched
->saved_states
--;
603 sched
->state
= sched
->saved
[sched
->saved_states
];
605 /* continue with next counter: */
606 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
612 * Select a counter for the current event to schedule. Return true on
615 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
617 struct event_constraint
*c
;
620 if (!sched
->state
.unassigned
)
623 if (sched
->state
.event
>= sched
->max_events
)
626 c
= sched
->constraints
[sched
->state
.event
];
628 /* Prefer fixed purpose counters */
629 if (x86_pmu
.num_counters_fixed
) {
630 idx
= X86_PMC_IDX_FIXED
;
631 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
632 if (!__test_and_set_bit(idx
, sched
->state
.used
))
636 /* Grab the first unused counter starting with idx */
637 idx
= sched
->state
.counter
;
638 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_FIXED
) {
639 if (!__test_and_set_bit(idx
, sched
->state
.used
))
646 sched
->state
.counter
= idx
;
649 perf_sched_save_state(sched
);
654 static bool perf_sched_find_counter(struct perf_sched
*sched
)
656 while (!__perf_sched_find_counter(sched
)) {
657 if (!perf_sched_restore_state(sched
))
665 * Go through all unassigned events and find the next one to schedule.
666 * Take events with the least weight first. Return true on success.
668 static bool perf_sched_next_event(struct perf_sched
*sched
)
670 struct event_constraint
*c
;
672 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
677 sched
->state
.event
++;
678 if (sched
->state
.event
>= sched
->max_events
) {
680 sched
->state
.event
= 0;
681 sched
->state
.weight
++;
682 if (sched
->state
.weight
> sched
->max_weight
)
685 c
= sched
->constraints
[sched
->state
.event
];
686 } while (c
->weight
!= sched
->state
.weight
);
688 sched
->state
.counter
= 0; /* start with first counter */
694 * Assign a counter for each event.
696 static int perf_assign_events(struct event_constraint
**constraints
, int n
,
697 int wmin
, int wmax
, int *assign
)
699 struct perf_sched sched
;
701 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
);
704 if (!perf_sched_find_counter(&sched
))
707 assign
[sched
.state
.event
] = sched
.state
.counter
;
708 } while (perf_sched_next_event(&sched
));
710 return sched
.state
.unassigned
;
713 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
715 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
716 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
717 int i
, wmin
, wmax
, num
= 0;
718 struct hw_perf_event
*hwc
;
720 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
722 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
723 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
725 wmin
= min(wmin
, c
->weight
);
726 wmax
= max(wmax
, c
->weight
);
730 * fastpath, try to reuse previous register
732 for (i
= 0; i
< n
; i
++) {
733 hwc
= &cpuc
->event_list
[i
]->hw
;
740 /* constraint still honored */
741 if (!test_bit(hwc
->idx
, c
->idxmsk
))
744 /* not already used */
745 if (test_bit(hwc
->idx
, used_mask
))
748 __set_bit(hwc
->idx
, used_mask
);
750 assign
[i
] = hwc
->idx
;
755 num
= perf_assign_events(constraints
, n
, wmin
, wmax
, assign
);
758 * scheduling failed or is just a simulation,
759 * free resources if necessary
761 if (!assign
|| num
) {
762 for (i
= 0; i
< n
; i
++) {
763 if (x86_pmu
.put_event_constraints
)
764 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
767 return num
? -EINVAL
: 0;
771 * dogrp: true if must collect siblings events (group)
772 * returns total number of events and error code
774 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
776 struct perf_event
*event
;
779 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
781 /* current number of events already accepted */
784 if (is_x86_event(leader
)) {
787 cpuc
->event_list
[n
] = leader
;
793 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
794 if (!is_x86_event(event
) ||
795 event
->state
<= PERF_EVENT_STATE_OFF
)
801 cpuc
->event_list
[n
] = event
;
807 static inline void x86_assign_hw_event(struct perf_event
*event
,
808 struct cpu_hw_events
*cpuc
, int i
)
810 struct hw_perf_event
*hwc
= &event
->hw
;
812 hwc
->idx
= cpuc
->assign
[i
];
813 hwc
->last_cpu
= smp_processor_id();
814 hwc
->last_tag
= ++cpuc
->tags
[i
];
816 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
817 hwc
->config_base
= 0;
819 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
820 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
821 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- X86_PMC_IDX_FIXED
);
822 hwc
->event_base_rdpmc
= (hwc
->idx
- X86_PMC_IDX_FIXED
) | 1<<30;
824 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
825 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
826 hwc
->event_base_rdpmc
= x86_pmu_addr_offset(hwc
->idx
);
830 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
831 struct cpu_hw_events
*cpuc
,
834 return hwc
->idx
== cpuc
->assign
[i
] &&
835 hwc
->last_cpu
== smp_processor_id() &&
836 hwc
->last_tag
== cpuc
->tags
[i
];
839 static void x86_pmu_start(struct perf_event
*event
, int flags
);
841 static void x86_pmu_enable(struct pmu
*pmu
)
843 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
844 struct perf_event
*event
;
845 struct hw_perf_event
*hwc
;
846 int i
, added
= cpuc
->n_added
;
848 if (!x86_pmu_initialized())
855 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
857 * apply assignment obtained either from
858 * hw_perf_group_sched_in() or x86_pmu_enable()
860 * step1: save events moving to new counters
861 * step2: reprogram moved events into new counters
863 for (i
= 0; i
< n_running
; i
++) {
864 event
= cpuc
->event_list
[i
];
868 * we can avoid reprogramming counter if:
869 * - assigned same counter as last time
870 * - running on same CPU as last time
871 * - no other event has used the counter since
873 if (hwc
->idx
== -1 ||
874 match_prev_assignment(hwc
, cpuc
, i
))
878 * Ensure we don't accidentally enable a stopped
879 * counter simply because we rescheduled.
881 if (hwc
->state
& PERF_HES_STOPPED
)
882 hwc
->state
|= PERF_HES_ARCH
;
884 x86_pmu_stop(event
, PERF_EF_UPDATE
);
887 for (i
= 0; i
< cpuc
->n_events
; i
++) {
888 event
= cpuc
->event_list
[i
];
891 if (!match_prev_assignment(hwc
, cpuc
, i
))
892 x86_assign_hw_event(event
, cpuc
, i
);
893 else if (i
< n_running
)
896 if (hwc
->state
& PERF_HES_ARCH
)
899 x86_pmu_start(event
, PERF_EF_RELOAD
);
902 perf_events_lapic_init();
908 x86_pmu
.enable_all(added
);
911 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
914 * Set the next IRQ period, based on the hwc->period_left value.
915 * To be called with the event disabled in hw:
917 int x86_perf_event_set_period(struct perf_event
*event
)
919 struct hw_perf_event
*hwc
= &event
->hw
;
920 s64 left
= local64_read(&hwc
->period_left
);
921 s64 period
= hwc
->sample_period
;
922 int ret
= 0, idx
= hwc
->idx
;
924 if (idx
== X86_PMC_IDX_FIXED_BTS
)
928 * If we are way outside a reasonable range then just skip forward:
930 if (unlikely(left
<= -period
)) {
932 local64_set(&hwc
->period_left
, left
);
933 hwc
->last_period
= period
;
937 if (unlikely(left
<= 0)) {
939 local64_set(&hwc
->period_left
, left
);
940 hwc
->last_period
= period
;
944 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
946 if (unlikely(left
< 2))
949 if (left
> x86_pmu
.max_period
)
950 left
= x86_pmu
.max_period
;
952 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
955 * The hw event starts counting from this event offset,
956 * mark it to be able to extra future deltas:
958 local64_set(&hwc
->prev_count
, (u64
)-left
);
960 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
963 * Due to erratum on certan cpu we need
964 * a second write to be sure the register
965 * is updated properly
967 if (x86_pmu
.perfctr_second_write
) {
968 wrmsrl(hwc
->event_base
,
969 (u64
)(-left
) & x86_pmu
.cntval_mask
);
972 perf_event_update_userpage(event
);
977 void x86_pmu_enable_event(struct perf_event
*event
)
979 if (__this_cpu_read(cpu_hw_events
.enabled
))
980 __x86_pmu_enable_event(&event
->hw
,
981 ARCH_PERFMON_EVENTSEL_ENABLE
);
985 * Add a single event to the PMU.
987 * The event is added to the group of enabled events
988 * but only if it can be scehduled with existing events.
990 static int x86_pmu_add(struct perf_event
*event
, int flags
)
992 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
993 struct hw_perf_event
*hwc
;
994 int assign
[X86_PMC_IDX_MAX
];
999 perf_pmu_disable(event
->pmu
);
1000 n0
= cpuc
->n_events
;
1001 ret
= n
= collect_events(cpuc
, event
, false);
1005 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1006 if (!(flags
& PERF_EF_START
))
1007 hwc
->state
|= PERF_HES_ARCH
;
1010 * If group events scheduling transaction was started,
1011 * skip the schedulability test here, it will be performed
1012 * at commit time (->commit_txn) as a whole
1014 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1017 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1021 * copy new assignment, now we know it is possible
1022 * will be used by hw_perf_enable()
1024 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1028 cpuc
->n_added
+= n
- n0
;
1029 cpuc
->n_txn
+= n
- n0
;
1033 perf_pmu_enable(event
->pmu
);
1037 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1039 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1040 int idx
= event
->hw
.idx
;
1042 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1045 if (WARN_ON_ONCE(idx
== -1))
1048 if (flags
& PERF_EF_RELOAD
) {
1049 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1050 x86_perf_event_set_period(event
);
1053 event
->hw
.state
= 0;
1055 cpuc
->events
[idx
] = event
;
1056 __set_bit(idx
, cpuc
->active_mask
);
1057 __set_bit(idx
, cpuc
->running
);
1058 x86_pmu
.enable(event
);
1059 perf_event_update_userpage(event
);
1062 void perf_event_print_debug(void)
1064 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1066 struct cpu_hw_events
*cpuc
;
1067 unsigned long flags
;
1070 if (!x86_pmu
.num_counters
)
1073 local_irq_save(flags
);
1075 cpu
= smp_processor_id();
1076 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1078 if (x86_pmu
.version
>= 2) {
1079 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1080 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1081 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1082 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1083 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1086 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1087 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1088 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1089 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1090 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1092 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1094 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1095 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1096 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1098 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1100 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1101 cpu
, idx
, pmc_ctrl
);
1102 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1103 cpu
, idx
, pmc_count
);
1104 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1105 cpu
, idx
, prev_left
);
1107 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1108 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1110 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1111 cpu
, idx
, pmc_count
);
1113 local_irq_restore(flags
);
1116 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1118 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1119 struct hw_perf_event
*hwc
= &event
->hw
;
1121 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1122 x86_pmu
.disable(event
);
1123 cpuc
->events
[hwc
->idx
] = NULL
;
1124 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1125 hwc
->state
|= PERF_HES_STOPPED
;
1128 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1130 * Drain the remaining delta count out of a event
1131 * that we are disabling:
1133 x86_perf_event_update(event
);
1134 hwc
->state
|= PERF_HES_UPTODATE
;
1138 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1140 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1144 * If we're called during a txn, we don't need to do anything.
1145 * The events never got scheduled and ->cancel_txn will truncate
1148 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1151 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1153 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1154 if (event
== cpuc
->event_list
[i
]) {
1156 if (x86_pmu
.put_event_constraints
)
1157 x86_pmu
.put_event_constraints(cpuc
, event
);
1159 while (++i
< cpuc
->n_events
)
1160 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1166 perf_event_update_userpage(event
);
1169 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1171 struct perf_sample_data data
;
1172 struct cpu_hw_events
*cpuc
;
1173 struct perf_event
*event
;
1174 int idx
, handled
= 0;
1177 cpuc
= &__get_cpu_var(cpu_hw_events
);
1180 * Some chipsets need to unmask the LVTPC in a particular spot
1181 * inside the nmi handler. As a result, the unmasking was pushed
1182 * into all the nmi handlers.
1184 * This generic handler doesn't seem to have any issues where the
1185 * unmasking occurs so it was left at the top.
1187 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1189 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1190 if (!test_bit(idx
, cpuc
->active_mask
)) {
1192 * Though we deactivated the counter some cpus
1193 * might still deliver spurious interrupts still
1194 * in flight. Catch them:
1196 if (__test_and_clear_bit(idx
, cpuc
->running
))
1201 event
= cpuc
->events
[idx
];
1203 val
= x86_perf_event_update(event
);
1204 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1211 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1213 if (!x86_perf_event_set_period(event
))
1216 if (perf_event_overflow(event
, &data
, regs
))
1217 x86_pmu_stop(event
, 0);
1221 inc_irq_stat(apic_perf_irqs
);
1226 void perf_events_lapic_init(void)
1228 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1232 * Always use NMI for PMU
1234 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1237 static int __kprobes
1238 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1240 if (!atomic_read(&active_events
))
1243 return x86_pmu
.handle_irq(regs
);
1246 struct event_constraint emptyconstraint
;
1247 struct event_constraint unconstrained
;
1249 static int __cpuinit
1250 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1252 unsigned int cpu
= (long)hcpu
;
1253 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1254 int ret
= NOTIFY_OK
;
1256 switch (action
& ~CPU_TASKS_FROZEN
) {
1257 case CPU_UP_PREPARE
:
1258 cpuc
->kfree_on_online
= NULL
;
1259 if (x86_pmu
.cpu_prepare
)
1260 ret
= x86_pmu
.cpu_prepare(cpu
);
1264 if (x86_pmu
.attr_rdpmc
)
1265 set_in_cr4(X86_CR4_PCE
);
1266 if (x86_pmu
.cpu_starting
)
1267 x86_pmu
.cpu_starting(cpu
);
1271 kfree(cpuc
->kfree_on_online
);
1275 if (x86_pmu
.cpu_dying
)
1276 x86_pmu
.cpu_dying(cpu
);
1279 case CPU_UP_CANCELED
:
1281 if (x86_pmu
.cpu_dead
)
1282 x86_pmu
.cpu_dead(cpu
);
1292 static void __init
pmu_check_apic(void)
1298 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1299 pr_info("no hardware sampling interrupt available.\n");
1302 static struct attribute_group x86_pmu_format_group
= {
1307 static int __init
init_hw_perf_events(void)
1309 struct x86_pmu_quirk
*quirk
;
1310 struct event_constraint
*c
;
1313 pr_info("Performance Events: ");
1315 switch (boot_cpu_data
.x86_vendor
) {
1316 case X86_VENDOR_INTEL
:
1317 err
= intel_pmu_init();
1319 case X86_VENDOR_AMD
:
1320 err
= amd_pmu_init();
1326 pr_cont("no PMU driver, software events only.\n");
1332 /* sanity check that the hardware exists or is emulated */
1333 if (!check_hw_exists())
1336 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1338 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1341 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1342 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1343 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1344 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1346 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1348 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1349 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1350 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1351 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1354 x86_pmu
.intel_ctrl
|=
1355 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1357 perf_events_lapic_init();
1358 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1360 unconstrained
= (struct event_constraint
)
1361 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1362 0, x86_pmu
.num_counters
, 0);
1364 if (x86_pmu
.event_constraints
) {
1366 * event on fixed counter2 (REF_CYCLES) only works on this
1367 * counter, so do not extend mask to generic counters
1369 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1370 if (c
->cmask
!= X86_RAW_EVENT_MASK
1371 || c
->idxmsk64
== X86_PMC_MSK_FIXED_REF_CYCLES
) {
1375 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
1376 c
->weight
+= x86_pmu
.num_counters
;
1380 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1381 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1383 pr_info("... version: %d\n", x86_pmu
.version
);
1384 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1385 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1386 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1387 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1388 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1389 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1391 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1392 perf_cpu_notifier(x86_pmu_notifier
);
1396 early_initcall(init_hw_perf_events
);
1398 static inline void x86_pmu_read(struct perf_event
*event
)
1400 x86_perf_event_update(event
);
1404 * Start group events scheduling transaction
1405 * Set the flag to make pmu::enable() not perform the
1406 * schedulability test, it will be performed at commit time
1408 static void x86_pmu_start_txn(struct pmu
*pmu
)
1410 perf_pmu_disable(pmu
);
1411 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1412 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1416 * Stop group events scheduling transaction
1417 * Clear the flag and pmu::enable() will perform the
1418 * schedulability test.
1420 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1422 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1424 * Truncate the collected events.
1426 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1427 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1428 perf_pmu_enable(pmu
);
1432 * Commit group events scheduling transaction
1433 * Perform the group schedulability test as a whole
1434 * Return 0 if success
1436 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1438 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1439 int assign
[X86_PMC_IDX_MAX
];
1444 if (!x86_pmu_initialized())
1447 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1452 * copy new assignment, now we know it is possible
1453 * will be used by hw_perf_enable()
1455 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1457 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1458 perf_pmu_enable(pmu
);
1462 * a fake_cpuc is used to validate event groups. Due to
1463 * the extra reg logic, we need to also allocate a fake
1464 * per_core and per_cpu structure. Otherwise, group events
1465 * using extra reg may conflict without the kernel being
1466 * able to catch this when the last event gets added to
1469 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1471 kfree(cpuc
->shared_regs
);
1475 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1477 struct cpu_hw_events
*cpuc
;
1478 int cpu
= raw_smp_processor_id();
1480 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1482 return ERR_PTR(-ENOMEM
);
1484 /* only needed, if we have extra_regs */
1485 if (x86_pmu
.extra_regs
) {
1486 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1487 if (!cpuc
->shared_regs
)
1493 free_fake_cpuc(cpuc
);
1494 return ERR_PTR(-ENOMEM
);
1498 * validate that we can schedule this event
1500 static int validate_event(struct perf_event
*event
)
1502 struct cpu_hw_events
*fake_cpuc
;
1503 struct event_constraint
*c
;
1506 fake_cpuc
= allocate_fake_cpuc();
1507 if (IS_ERR(fake_cpuc
))
1508 return PTR_ERR(fake_cpuc
);
1510 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1512 if (!c
|| !c
->weight
)
1515 if (x86_pmu
.put_event_constraints
)
1516 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1518 free_fake_cpuc(fake_cpuc
);
1524 * validate a single event group
1526 * validation include:
1527 * - check events are compatible which each other
1528 * - events do not compete for the same counter
1529 * - number of events <= number of counters
1531 * validation ensures the group can be loaded onto the
1532 * PMU if it was the only group available.
1534 static int validate_group(struct perf_event
*event
)
1536 struct perf_event
*leader
= event
->group_leader
;
1537 struct cpu_hw_events
*fake_cpuc
;
1538 int ret
= -EINVAL
, n
;
1540 fake_cpuc
= allocate_fake_cpuc();
1541 if (IS_ERR(fake_cpuc
))
1542 return PTR_ERR(fake_cpuc
);
1544 * the event is not yet connected with its
1545 * siblings therefore we must first collect
1546 * existing siblings, then add the new event
1547 * before we can simulate the scheduling
1549 n
= collect_events(fake_cpuc
, leader
, true);
1553 fake_cpuc
->n_events
= n
;
1554 n
= collect_events(fake_cpuc
, event
, false);
1558 fake_cpuc
->n_events
= n
;
1560 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1563 free_fake_cpuc(fake_cpuc
);
1567 static int x86_pmu_event_init(struct perf_event
*event
)
1572 switch (event
->attr
.type
) {
1574 case PERF_TYPE_HARDWARE
:
1575 case PERF_TYPE_HW_CACHE
:
1582 err
= __x86_pmu_event_init(event
);
1585 * we temporarily connect event to its pmu
1586 * such that validate_group() can classify
1587 * it as an x86 event using is_x86_event()
1592 if (event
->group_leader
!= event
)
1593 err
= validate_group(event
);
1595 err
= validate_event(event
);
1601 event
->destroy(event
);
1607 static int x86_pmu_event_idx(struct perf_event
*event
)
1609 int idx
= event
->hw
.idx
;
1611 if (!x86_pmu
.attr_rdpmc
)
1614 if (x86_pmu
.num_counters_fixed
&& idx
>= X86_PMC_IDX_FIXED
) {
1615 idx
-= X86_PMC_IDX_FIXED
;
1622 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
1623 struct device_attribute
*attr
,
1626 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
1629 static void change_rdpmc(void *info
)
1631 bool enable
= !!(unsigned long)info
;
1634 set_in_cr4(X86_CR4_PCE
);
1636 clear_in_cr4(X86_CR4_PCE
);
1639 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
1640 struct device_attribute
*attr
,
1641 const char *buf
, size_t count
)
1643 unsigned long val
= simple_strtoul(buf
, NULL
, 0);
1645 if (!!val
!= !!x86_pmu
.attr_rdpmc
) {
1646 x86_pmu
.attr_rdpmc
= !!val
;
1647 smp_call_function(change_rdpmc
, (void *)val
, 1);
1653 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
1655 static struct attribute
*x86_pmu_attrs
[] = {
1656 &dev_attr_rdpmc
.attr
,
1660 static struct attribute_group x86_pmu_attr_group
= {
1661 .attrs
= x86_pmu_attrs
,
1664 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
1665 &x86_pmu_attr_group
,
1666 &x86_pmu_format_group
,
1670 static void x86_pmu_flush_branch_stack(void)
1672 if (x86_pmu
.flush_branch_stack
)
1673 x86_pmu
.flush_branch_stack();
1676 static struct pmu pmu
= {
1677 .pmu_enable
= x86_pmu_enable
,
1678 .pmu_disable
= x86_pmu_disable
,
1680 .attr_groups
= x86_pmu_attr_groups
,
1682 .event_init
= x86_pmu_event_init
,
1686 .start
= x86_pmu_start
,
1687 .stop
= x86_pmu_stop
,
1688 .read
= x86_pmu_read
,
1690 .start_txn
= x86_pmu_start_txn
,
1691 .cancel_txn
= x86_pmu_cancel_txn
,
1692 .commit_txn
= x86_pmu_commit_txn
,
1694 .event_idx
= x86_pmu_event_idx
,
1695 .flush_branch_stack
= x86_pmu_flush_branch_stack
,
1698 void arch_perf_update_userpage(struct perf_event_mmap_page
*userpg
, u64 now
)
1700 userpg
->cap_usr_time
= 0;
1701 userpg
->cap_usr_rdpmc
= x86_pmu
.attr_rdpmc
;
1702 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
1704 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
1707 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
1710 userpg
->cap_usr_time
= 1;
1711 userpg
->time_mult
= this_cpu_read(cyc2ns
);
1712 userpg
->time_shift
= CYC2NS_SCALE_FACTOR
;
1713 userpg
->time_offset
= this_cpu_read(cyc2ns_offset
) - now
;
1720 static int backtrace_stack(void *data
, char *name
)
1725 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1727 struct perf_callchain_entry
*entry
= data
;
1729 perf_callchain_store(entry
, addr
);
1732 static const struct stacktrace_ops backtrace_ops
= {
1733 .stack
= backtrace_stack
,
1734 .address
= backtrace_address
,
1735 .walk_stack
= print_context_stack_bp
,
1739 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1741 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1742 /* TODO: We don't support guest os callchain now */
1746 perf_callchain_store(entry
, regs
->ip
);
1748 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
1752 valid_user_frame(const void __user
*fp
, unsigned long size
)
1754 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
1757 #ifdef CONFIG_COMPAT
1759 #include <asm/compat.h>
1762 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1764 /* 32-bit process in 64-bit kernel. */
1765 struct stack_frame_ia32 frame
;
1766 const void __user
*fp
;
1768 if (!test_thread_flag(TIF_IA32
))
1771 fp
= compat_ptr(regs
->bp
);
1772 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1773 unsigned long bytes
;
1774 frame
.next_frame
= 0;
1775 frame
.return_address
= 0;
1777 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1778 if (bytes
!= sizeof(frame
))
1781 if (!valid_user_frame(fp
, sizeof(frame
)))
1784 perf_callchain_store(entry
, frame
.return_address
);
1785 fp
= compat_ptr(frame
.next_frame
);
1791 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1798 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1800 struct stack_frame frame
;
1801 const void __user
*fp
;
1803 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1804 /* TODO: We don't support guest os callchain now */
1808 fp
= (void __user
*)regs
->bp
;
1810 perf_callchain_store(entry
, regs
->ip
);
1815 if (perf_callchain_user32(regs
, entry
))
1818 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1819 unsigned long bytes
;
1820 frame
.next_frame
= NULL
;
1821 frame
.return_address
= 0;
1823 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1824 if (bytes
!= sizeof(frame
))
1827 if (!valid_user_frame(fp
, sizeof(frame
)))
1830 perf_callchain_store(entry
, frame
.return_address
);
1831 fp
= frame
.next_frame
;
1835 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1839 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1840 ip
= perf_guest_cbs
->get_guest_ip();
1842 ip
= instruction_pointer(regs
);
1847 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1851 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1852 if (perf_guest_cbs
->is_user_mode())
1853 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1855 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1857 if (user_mode(regs
))
1858 misc
|= PERF_RECORD_MISC_USER
;
1860 misc
|= PERF_RECORD_MISC_KERNEL
;
1863 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1864 misc
|= PERF_RECORD_MISC_EXACT_IP
;
1869 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
1871 cap
->version
= x86_pmu
.version
;
1872 cap
->num_counters_gp
= x86_pmu
.num_counters
;
1873 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
1874 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
1875 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
1876 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
1877 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
1879 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);