2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/timer.h>
40 #include "perf_event.h"
42 struct x86_pmu x86_pmu __read_mostly
;
44 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
48 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
50 u64 __read_mostly hw_cache_event_ids
51 [PERF_COUNT_HW_CACHE_MAX
]
52 [PERF_COUNT_HW_CACHE_OP_MAX
]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
54 u64 __read_mostly hw_cache_extra_regs
55 [PERF_COUNT_HW_CACHE_MAX
]
56 [PERF_COUNT_HW_CACHE_OP_MAX
]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
60 * Propagate event elapsed time into the generic event.
61 * Can only be executed on the CPU where the event is active.
62 * Returns the delta events processed.
64 u64
x86_perf_event_update(struct perf_event
*event
)
66 struct hw_perf_event
*hwc
= &event
->hw
;
67 int shift
= 64 - x86_pmu
.cntval_bits
;
68 u64 prev_raw_count
, new_raw_count
;
72 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
76 * Careful: an NMI might modify the previous event value.
78 * Our tactic to handle this is to first atomically read and
79 * exchange a new raw count - then add that new-prev delta
80 * count to the generic event atomically:
83 prev_raw_count
= local64_read(&hwc
->prev_count
);
84 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
86 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
87 new_raw_count
) != prev_raw_count
)
91 * Now we have the new raw value and have updated the prev
92 * timestamp already. We can now calculate the elapsed delta
93 * (event-)time and add that to the generic event.
95 * Careful, not all hw sign-extends above the physical width
98 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
101 local64_add(delta
, &event
->count
);
102 local64_sub(delta
, &hwc
->period_left
);
104 return new_raw_count
;
108 * Find and validate any extra registers to set up.
110 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
112 struct hw_perf_event_extra
*reg
;
113 struct extra_reg
*er
;
115 reg
= &event
->hw
.extra_reg
;
117 if (!x86_pmu
.extra_regs
)
120 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
121 if (er
->event
!= (config
& er
->config_mask
))
123 if (event
->attr
.config1
& ~er
->valid_mask
)
125 /* Check if the extra msrs can be safely accessed*/
126 if (!er
->extra_msr_access
)
130 reg
->config
= event
->attr
.config1
;
137 static atomic_t active_events
;
138 static DEFINE_MUTEX(pmc_reserve_mutex
);
140 #ifdef CONFIG_X86_LOCAL_APIC
142 static bool reserve_pmc_hardware(void)
146 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
147 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
151 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
152 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
159 for (i
--; i
>= 0; i
--)
160 release_evntsel_nmi(x86_pmu_config_addr(i
));
162 i
= x86_pmu
.num_counters
;
165 for (i
--; i
>= 0; i
--)
166 release_perfctr_nmi(x86_pmu_event_addr(i
));
171 static void release_pmc_hardware(void)
175 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
176 release_perfctr_nmi(x86_pmu_event_addr(i
));
177 release_evntsel_nmi(x86_pmu_config_addr(i
));
183 static bool reserve_pmc_hardware(void) { return true; }
184 static void release_pmc_hardware(void) {}
188 static bool check_hw_exists(void)
190 u64 val
, val_fail
, val_new
= ~0;
191 int i
, reg
, reg_fail
, ret
= 0;
195 * Check to see if the BIOS enabled any of the counters, if so
198 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
199 reg
= x86_pmu_config_addr(i
);
200 ret
= rdmsrl_safe(reg
, &val
);
203 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
210 if (x86_pmu
.num_counters_fixed
) {
211 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
212 ret
= rdmsrl_safe(reg
, &val
);
215 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
216 if (val
& (0x03 << i
*4)) {
225 * Read the current value, change it and read it back to see if it
226 * matches, this is needed to detect certain hardware emulators
227 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
229 reg
= x86_pmu_event_addr(0);
230 if (rdmsrl_safe(reg
, &val
))
233 ret
= wrmsrl_safe(reg
, val
);
234 ret
|= rdmsrl_safe(reg
, &val_new
);
235 if (ret
|| val
!= val_new
)
239 * We still allow the PMU driver to operate:
242 printk(KERN_CONT
"Broken BIOS detected, complain to your hardware vendor.\n");
243 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail
, val_fail
);
249 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
250 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
251 boot_cpu_has(X86_FEATURE_HYPERVISOR
) ? KERN_INFO
: KERN_ERR
,
257 static void hw_perf_event_destroy(struct perf_event
*event
)
259 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
260 release_pmc_hardware();
261 release_ds_buffers();
262 mutex_unlock(&pmc_reserve_mutex
);
266 static inline int x86_pmu_initialized(void)
268 return x86_pmu
.handle_irq
!= NULL
;
272 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
274 struct perf_event_attr
*attr
= &event
->attr
;
275 unsigned int cache_type
, cache_op
, cache_result
;
278 config
= attr
->config
;
280 cache_type
= (config
>> 0) & 0xff;
281 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
284 cache_op
= (config
>> 8) & 0xff;
285 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
288 cache_result
= (config
>> 16) & 0xff;
289 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
292 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
301 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
302 return x86_pmu_extra_regs(val
, event
);
305 int x86_setup_perfctr(struct perf_event
*event
)
307 struct perf_event_attr
*attr
= &event
->attr
;
308 struct hw_perf_event
*hwc
= &event
->hw
;
311 if (!is_sampling_event(event
)) {
312 hwc
->sample_period
= x86_pmu
.max_period
;
313 hwc
->last_period
= hwc
->sample_period
;
314 local64_set(&hwc
->period_left
, hwc
->sample_period
);
317 if (attr
->type
== PERF_TYPE_RAW
)
318 return x86_pmu_extra_regs(event
->attr
.config
, event
);
320 if (attr
->type
== PERF_TYPE_HW_CACHE
)
321 return set_ext_hw_attr(hwc
, event
);
323 if (attr
->config
>= x86_pmu
.max_events
)
329 config
= x86_pmu
.event_map(attr
->config
);
340 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
341 !attr
->freq
&& hwc
->sample_period
== 1) {
342 /* BTS is not supported by this architecture. */
343 if (!x86_pmu
.bts_active
)
346 /* BTS is currently only allowed for user-mode. */
347 if (!attr
->exclude_kernel
)
351 hwc
->config
|= config
;
357 * check that branch_sample_type is compatible with
358 * settings needed for precise_ip > 1 which implies
359 * using the LBR to capture ALL taken branches at the
360 * priv levels of the measurement
362 static inline int precise_br_compat(struct perf_event
*event
)
364 u64 m
= event
->attr
.branch_sample_type
;
367 /* must capture all branches */
368 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
371 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
373 if (!event
->attr
.exclude_user
)
374 b
|= PERF_SAMPLE_BRANCH_USER
;
376 if (!event
->attr
.exclude_kernel
)
377 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
380 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
386 int x86_pmu_hw_config(struct perf_event
*event
)
388 if (event
->attr
.precise_ip
) {
391 /* Support for constant skid */
392 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
395 /* Support for IP fixup */
396 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
400 if (event
->attr
.precise_ip
> precise
)
404 * check that PEBS LBR correction does not conflict with
405 * whatever the user is asking with attr->branch_sample_type
407 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
408 u64
*br_type
= &event
->attr
.branch_sample_type
;
410 if (has_branch_stack(event
)) {
411 if (!precise_br_compat(event
))
414 /* branch_sample_type is compatible */
418 * user did not specify branch_sample_type
420 * For PEBS fixups, we capture all
421 * the branches at the priv level of the
424 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
426 if (!event
->attr
.exclude_user
)
427 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
429 if (!event
->attr
.exclude_kernel
)
430 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
434 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
435 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
439 * (keep 'enabled' bit clear for now)
441 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
444 * Count user and OS events unless requested not to
446 if (!event
->attr
.exclude_user
)
447 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
448 if (!event
->attr
.exclude_kernel
)
449 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
451 if (event
->attr
.type
== PERF_TYPE_RAW
)
452 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
454 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
455 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
456 event
->attr
.sample_period
)
460 return x86_setup_perfctr(event
);
464 * Setup the hardware configuration for a given attr_type
466 static int __x86_pmu_event_init(struct perf_event
*event
)
470 if (!x86_pmu_initialized())
474 if (!atomic_inc_not_zero(&active_events
)) {
475 mutex_lock(&pmc_reserve_mutex
);
476 if (atomic_read(&active_events
) == 0) {
477 if (!reserve_pmc_hardware())
480 reserve_ds_buffers();
483 atomic_inc(&active_events
);
484 mutex_unlock(&pmc_reserve_mutex
);
489 event
->destroy
= hw_perf_event_destroy
;
492 event
->hw
.last_cpu
= -1;
493 event
->hw
.last_tag
= ~0ULL;
496 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
497 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
499 return x86_pmu
.hw_config(event
);
502 void x86_pmu_disable_all(void)
504 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
507 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
510 if (!test_bit(idx
, cpuc
->active_mask
))
512 rdmsrl(x86_pmu_config_addr(idx
), val
);
513 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
515 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
516 wrmsrl(x86_pmu_config_addr(idx
), val
);
520 static void x86_pmu_disable(struct pmu
*pmu
)
522 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
524 if (!x86_pmu_initialized())
534 x86_pmu
.disable_all();
537 void x86_pmu_enable_all(int added
)
539 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
542 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
543 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
545 if (!test_bit(idx
, cpuc
->active_mask
))
548 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
552 static struct pmu pmu
;
554 static inline int is_x86_event(struct perf_event
*event
)
556 return event
->pmu
== &pmu
;
560 * Event scheduler state:
562 * Assign events iterating over all events and counters, beginning
563 * with events with least weights first. Keep the current iterator
564 * state in struct sched_state.
568 int event
; /* event index */
569 int counter
; /* counter index */
570 int unassigned
; /* number of events to be assigned left */
571 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
574 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
575 #define SCHED_STATES_MAX 2
580 struct perf_event
**events
;
581 struct sched_state state
;
583 struct sched_state saved
[SCHED_STATES_MAX
];
587 * Initialize interator that runs through all events and counters.
589 static void perf_sched_init(struct perf_sched
*sched
, struct perf_event
**events
,
590 int num
, int wmin
, int wmax
)
594 memset(sched
, 0, sizeof(*sched
));
595 sched
->max_events
= num
;
596 sched
->max_weight
= wmax
;
597 sched
->events
= events
;
599 for (idx
= 0; idx
< num
; idx
++) {
600 if (events
[idx
]->hw
.constraint
->weight
== wmin
)
604 sched
->state
.event
= idx
; /* start with min weight */
605 sched
->state
.weight
= wmin
;
606 sched
->state
.unassigned
= num
;
609 static void perf_sched_save_state(struct perf_sched
*sched
)
611 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
614 sched
->saved
[sched
->saved_states
] = sched
->state
;
615 sched
->saved_states
++;
618 static bool perf_sched_restore_state(struct perf_sched
*sched
)
620 if (!sched
->saved_states
)
623 sched
->saved_states
--;
624 sched
->state
= sched
->saved
[sched
->saved_states
];
626 /* continue with next counter: */
627 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
633 * Select a counter for the current event to schedule. Return true on
636 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
638 struct event_constraint
*c
;
641 if (!sched
->state
.unassigned
)
644 if (sched
->state
.event
>= sched
->max_events
)
647 c
= sched
->events
[sched
->state
.event
]->hw
.constraint
;
648 /* Prefer fixed purpose counters */
649 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
650 idx
= INTEL_PMC_IDX_FIXED
;
651 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
652 if (!__test_and_set_bit(idx
, sched
->state
.used
))
656 /* Grab the first unused counter starting with idx */
657 idx
= sched
->state
.counter
;
658 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
659 if (!__test_and_set_bit(idx
, sched
->state
.used
))
666 sched
->state
.counter
= idx
;
669 perf_sched_save_state(sched
);
674 static bool perf_sched_find_counter(struct perf_sched
*sched
)
676 while (!__perf_sched_find_counter(sched
)) {
677 if (!perf_sched_restore_state(sched
))
685 * Go through all unassigned events and find the next one to schedule.
686 * Take events with the least weight first. Return true on success.
688 static bool perf_sched_next_event(struct perf_sched
*sched
)
690 struct event_constraint
*c
;
692 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
697 sched
->state
.event
++;
698 if (sched
->state
.event
>= sched
->max_events
) {
700 sched
->state
.event
= 0;
701 sched
->state
.weight
++;
702 if (sched
->state
.weight
> sched
->max_weight
)
705 c
= sched
->events
[sched
->state
.event
]->hw
.constraint
;
706 } while (c
->weight
!= sched
->state
.weight
);
708 sched
->state
.counter
= 0; /* start with first counter */
714 * Assign a counter for each event.
716 int perf_assign_events(struct perf_event
**events
, int n
,
717 int wmin
, int wmax
, int *assign
)
719 struct perf_sched sched
;
721 perf_sched_init(&sched
, events
, n
, wmin
, wmax
);
724 if (!perf_sched_find_counter(&sched
))
727 assign
[sched
.state
.event
] = sched
.state
.counter
;
728 } while (perf_sched_next_event(&sched
));
730 return sched
.state
.unassigned
;
732 EXPORT_SYMBOL_GPL(perf_assign_events
);
734 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
736 struct event_constraint
*c
;
737 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
738 struct perf_event
*e
;
739 int i
, wmin
, wmax
, num
= 0;
740 struct hw_perf_event
*hwc
;
742 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
744 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
745 hwc
= &cpuc
->event_list
[i
]->hw
;
746 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
749 wmin
= min(wmin
, c
->weight
);
750 wmax
= max(wmax
, c
->weight
);
754 * fastpath, try to reuse previous register
756 for (i
= 0; i
< n
; i
++) {
757 hwc
= &cpuc
->event_list
[i
]->hw
;
764 /* constraint still honored */
765 if (!test_bit(hwc
->idx
, c
->idxmsk
))
768 /* not already used */
769 if (test_bit(hwc
->idx
, used_mask
))
772 __set_bit(hwc
->idx
, used_mask
);
774 assign
[i
] = hwc
->idx
;
779 num
= perf_assign_events(cpuc
->event_list
, n
, wmin
,
783 * Mark the event as committed, so we do not put_constraint()
784 * in case new events are added and fail scheduling.
786 if (!num
&& assign
) {
787 for (i
= 0; i
< n
; i
++) {
788 e
= cpuc
->event_list
[i
];
789 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
793 * scheduling failed or is just a simulation,
794 * free resources if necessary
796 if (!assign
|| num
) {
797 for (i
= 0; i
< n
; i
++) {
798 e
= cpuc
->event_list
[i
];
800 * do not put_constraint() on comitted events,
801 * because they are good to go
803 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
806 if (x86_pmu
.put_event_constraints
)
807 x86_pmu
.put_event_constraints(cpuc
, e
);
810 return num
? -EINVAL
: 0;
814 * dogrp: true if must collect siblings events (group)
815 * returns total number of events and error code
817 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
819 struct perf_event
*event
;
822 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
824 /* current number of events already accepted */
827 if (is_x86_event(leader
)) {
830 cpuc
->event_list
[n
] = leader
;
836 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
837 if (!is_x86_event(event
) ||
838 event
->state
<= PERF_EVENT_STATE_OFF
)
844 cpuc
->event_list
[n
] = event
;
850 static inline void x86_assign_hw_event(struct perf_event
*event
,
851 struct cpu_hw_events
*cpuc
, int i
)
853 struct hw_perf_event
*hwc
= &event
->hw
;
855 hwc
->idx
= cpuc
->assign
[i
];
856 hwc
->last_cpu
= smp_processor_id();
857 hwc
->last_tag
= ++cpuc
->tags
[i
];
859 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
860 hwc
->config_base
= 0;
862 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
863 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
864 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
865 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
867 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
868 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
869 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
873 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
874 struct cpu_hw_events
*cpuc
,
877 return hwc
->idx
== cpuc
->assign
[i
] &&
878 hwc
->last_cpu
== smp_processor_id() &&
879 hwc
->last_tag
== cpuc
->tags
[i
];
882 static void x86_pmu_start(struct perf_event
*event
, int flags
);
884 static void x86_pmu_enable(struct pmu
*pmu
)
886 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
887 struct perf_event
*event
;
888 struct hw_perf_event
*hwc
;
889 int i
, added
= cpuc
->n_added
;
891 if (!x86_pmu_initialized())
898 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
900 * apply assignment obtained either from
901 * hw_perf_group_sched_in() or x86_pmu_enable()
903 * step1: save events moving to new counters
905 for (i
= 0; i
< n_running
; i
++) {
906 event
= cpuc
->event_list
[i
];
910 * we can avoid reprogramming counter if:
911 * - assigned same counter as last time
912 * - running on same CPU as last time
913 * - no other event has used the counter since
915 if (hwc
->idx
== -1 ||
916 match_prev_assignment(hwc
, cpuc
, i
))
920 * Ensure we don't accidentally enable a stopped
921 * counter simply because we rescheduled.
923 if (hwc
->state
& PERF_HES_STOPPED
)
924 hwc
->state
|= PERF_HES_ARCH
;
926 x86_pmu_stop(event
, PERF_EF_UPDATE
);
930 * step2: reprogram moved events into new counters
932 for (i
= 0; i
< cpuc
->n_events
; i
++) {
933 event
= cpuc
->event_list
[i
];
936 if (!match_prev_assignment(hwc
, cpuc
, i
))
937 x86_assign_hw_event(event
, cpuc
, i
);
938 else if (i
< n_running
)
941 if (hwc
->state
& PERF_HES_ARCH
)
944 x86_pmu_start(event
, PERF_EF_RELOAD
);
947 perf_events_lapic_init();
953 x86_pmu
.enable_all(added
);
956 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
959 * Set the next IRQ period, based on the hwc->period_left value.
960 * To be called with the event disabled in hw:
962 int x86_perf_event_set_period(struct perf_event
*event
)
964 struct hw_perf_event
*hwc
= &event
->hw
;
965 s64 left
= local64_read(&hwc
->period_left
);
966 s64 period
= hwc
->sample_period
;
967 int ret
= 0, idx
= hwc
->idx
;
969 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
973 * If we are way outside a reasonable range then just skip forward:
975 if (unlikely(left
<= -period
)) {
977 local64_set(&hwc
->period_left
, left
);
978 hwc
->last_period
= period
;
982 if (unlikely(left
<= 0)) {
984 local64_set(&hwc
->period_left
, left
);
985 hwc
->last_period
= period
;
989 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
991 if (unlikely(left
< 2))
994 if (left
> x86_pmu
.max_period
)
995 left
= x86_pmu
.max_period
;
997 if (x86_pmu
.limit_period
)
998 left
= x86_pmu
.limit_period(event
, left
);
1000 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1003 * The hw event starts counting from this event offset,
1004 * mark it to be able to extra future deltas:
1006 local64_set(&hwc
->prev_count
, (u64
)-left
);
1008 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1011 * Due to erratum on certan cpu we need
1012 * a second write to be sure the register
1013 * is updated properly
1015 if (x86_pmu
.perfctr_second_write
) {
1016 wrmsrl(hwc
->event_base
,
1017 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1020 perf_event_update_userpage(event
);
1025 void x86_pmu_enable_event(struct perf_event
*event
)
1027 if (__this_cpu_read(cpu_hw_events
.enabled
))
1028 __x86_pmu_enable_event(&event
->hw
,
1029 ARCH_PERFMON_EVENTSEL_ENABLE
);
1033 * Add a single event to the PMU.
1035 * The event is added to the group of enabled events
1036 * but only if it can be scehduled with existing events.
1038 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1040 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1041 struct hw_perf_event
*hwc
;
1042 int assign
[X86_PMC_IDX_MAX
];
1047 n0
= cpuc
->n_events
;
1048 ret
= n
= collect_events(cpuc
, event
, false);
1052 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1053 if (!(flags
& PERF_EF_START
))
1054 hwc
->state
|= PERF_HES_ARCH
;
1057 * If group events scheduling transaction was started,
1058 * skip the schedulability test here, it will be performed
1059 * at commit time (->commit_txn) as a whole.
1061 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1064 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1068 * copy new assignment, now we know it is possible
1069 * will be used by hw_perf_enable()
1071 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1075 * Commit the collect_events() state. See x86_pmu_del() and
1079 cpuc
->n_added
+= n
- n0
;
1080 cpuc
->n_txn
+= n
- n0
;
1087 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1089 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1090 int idx
= event
->hw
.idx
;
1092 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1095 if (WARN_ON_ONCE(idx
== -1))
1098 if (flags
& PERF_EF_RELOAD
) {
1099 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1100 x86_perf_event_set_period(event
);
1103 event
->hw
.state
= 0;
1105 cpuc
->events
[idx
] = event
;
1106 __set_bit(idx
, cpuc
->active_mask
);
1107 __set_bit(idx
, cpuc
->running
);
1108 x86_pmu
.enable(event
);
1109 perf_event_update_userpage(event
);
1112 void perf_event_print_debug(void)
1114 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1116 struct cpu_hw_events
*cpuc
;
1117 unsigned long flags
;
1120 if (!x86_pmu
.num_counters
)
1123 local_irq_save(flags
);
1125 cpu
= smp_processor_id();
1126 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1128 if (x86_pmu
.version
>= 2) {
1129 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1130 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1131 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1132 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1133 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1136 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1137 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1138 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1139 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1140 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1142 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1144 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1145 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1146 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1148 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1150 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1151 cpu
, idx
, pmc_ctrl
);
1152 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1153 cpu
, idx
, pmc_count
);
1154 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1155 cpu
, idx
, prev_left
);
1157 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1158 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1160 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1161 cpu
, idx
, pmc_count
);
1163 local_irq_restore(flags
);
1166 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1168 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1169 struct hw_perf_event
*hwc
= &event
->hw
;
1171 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1172 x86_pmu
.disable(event
);
1173 cpuc
->events
[hwc
->idx
] = NULL
;
1174 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1175 hwc
->state
|= PERF_HES_STOPPED
;
1178 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1180 * Drain the remaining delta count out of a event
1181 * that we are disabling:
1183 x86_perf_event_update(event
);
1184 hwc
->state
|= PERF_HES_UPTODATE
;
1188 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1190 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1194 * event is descheduled
1196 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1199 * If we're called during a txn, we don't need to do anything.
1200 * The events never got scheduled and ->cancel_txn will truncate
1203 * XXX assumes any ->del() called during a TXN will only be on
1204 * an event added during that same TXN.
1206 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1210 * Not a TXN, therefore cleanup properly.
1212 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1214 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1215 if (event
== cpuc
->event_list
[i
])
1219 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1222 /* If we have a newly added event; make sure to decrease n_added. */
1223 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1226 if (x86_pmu
.put_event_constraints
)
1227 x86_pmu
.put_event_constraints(cpuc
, event
);
1229 /* Delete the array entry. */
1230 while (++i
< cpuc
->n_events
)
1231 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1234 perf_event_update_userpage(event
);
1237 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1239 struct perf_sample_data data
;
1240 struct cpu_hw_events
*cpuc
;
1241 struct perf_event
*event
;
1242 int idx
, handled
= 0;
1245 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1248 * Some chipsets need to unmask the LVTPC in a particular spot
1249 * inside the nmi handler. As a result, the unmasking was pushed
1250 * into all the nmi handlers.
1252 * This generic handler doesn't seem to have any issues where the
1253 * unmasking occurs so it was left at the top.
1255 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1257 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1258 if (!test_bit(idx
, cpuc
->active_mask
)) {
1260 * Though we deactivated the counter some cpus
1261 * might still deliver spurious interrupts still
1262 * in flight. Catch them:
1264 if (__test_and_clear_bit(idx
, cpuc
->running
))
1269 event
= cpuc
->events
[idx
];
1271 val
= x86_perf_event_update(event
);
1272 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1279 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1281 if (!x86_perf_event_set_period(event
))
1284 if (perf_event_overflow(event
, &data
, regs
))
1285 x86_pmu_stop(event
, 0);
1289 inc_irq_stat(apic_perf_irqs
);
1294 void perf_events_lapic_init(void)
1296 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1300 * Always use NMI for PMU
1302 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1306 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1312 if (!atomic_read(&active_events
))
1315 start_clock
= sched_clock();
1316 ret
= x86_pmu
.handle_irq(regs
);
1317 finish_clock
= sched_clock();
1319 perf_sample_event_took(finish_clock
- start_clock
);
1323 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1325 struct event_constraint emptyconstraint
;
1326 struct event_constraint unconstrained
;
1329 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1331 unsigned int cpu
= (long)hcpu
;
1332 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1333 int ret
= NOTIFY_OK
;
1335 switch (action
& ~CPU_TASKS_FROZEN
) {
1336 case CPU_UP_PREPARE
:
1337 cpuc
->kfree_on_online
= NULL
;
1338 if (x86_pmu
.cpu_prepare
)
1339 ret
= x86_pmu
.cpu_prepare(cpu
);
1343 if (x86_pmu
.cpu_starting
)
1344 x86_pmu
.cpu_starting(cpu
);
1348 kfree(cpuc
->kfree_on_online
);
1352 if (x86_pmu
.cpu_dying
)
1353 x86_pmu
.cpu_dying(cpu
);
1356 case CPU_UP_CANCELED
:
1358 if (x86_pmu
.cpu_dead
)
1359 x86_pmu
.cpu_dead(cpu
);
1369 static void __init
pmu_check_apic(void)
1375 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1376 pr_info("no hardware sampling interrupt available.\n");
1379 * If we have a PMU initialized but no APIC
1380 * interrupts, we cannot sample hardware
1381 * events (user-space has to fall back and
1382 * sample via a hrtimer based software event):
1384 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1388 static struct attribute_group x86_pmu_format_group
= {
1394 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1395 * out of events_attr attributes.
1397 static void __init
filter_events(struct attribute
**attrs
)
1399 struct device_attribute
*d
;
1400 struct perf_pmu_events_attr
*pmu_attr
;
1403 for (i
= 0; attrs
[i
]; i
++) {
1404 d
= (struct device_attribute
*)attrs
[i
];
1405 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1407 if (pmu_attr
->event_str
)
1409 if (x86_pmu
.event_map(i
))
1412 for (j
= i
; attrs
[j
]; j
++)
1413 attrs
[j
] = attrs
[j
+ 1];
1415 /* Check the shifted attr. */
1420 /* Merge two pointer arrays */
1421 static __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1423 struct attribute
**new;
1426 for (j
= 0; a
[j
]; j
++)
1428 for (i
= 0; b
[i
]; i
++)
1432 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1437 for (i
= 0; a
[i
]; i
++)
1439 for (i
= 0; b
[i
]; i
++)
1446 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1449 struct perf_pmu_events_attr
*pmu_attr
= \
1450 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1451 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1453 /* string trumps id */
1454 if (pmu_attr
->event_str
)
1455 return sprintf(page
, "%s", pmu_attr
->event_str
);
1457 return x86_pmu
.events_sysfs_show(page
, config
);
1460 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1461 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1462 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1463 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1464 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1465 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1466 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1467 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1468 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1469 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1471 static struct attribute
*empty_attrs
;
1473 static struct attribute
*events_attr
[] = {
1474 EVENT_PTR(CPU_CYCLES
),
1475 EVENT_PTR(INSTRUCTIONS
),
1476 EVENT_PTR(CACHE_REFERENCES
),
1477 EVENT_PTR(CACHE_MISSES
),
1478 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1479 EVENT_PTR(BRANCH_MISSES
),
1480 EVENT_PTR(BUS_CYCLES
),
1481 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1482 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1483 EVENT_PTR(REF_CPU_CYCLES
),
1487 static struct attribute_group x86_pmu_events_group
= {
1489 .attrs
= events_attr
,
1492 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1494 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1495 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1496 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1497 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1498 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1499 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1503 * We have whole page size to spend and just little data
1504 * to write, so we can safely use sprintf.
1506 ret
= sprintf(page
, "event=0x%02llx", event
);
1509 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1512 ret
+= sprintf(page
+ ret
, ",edge");
1515 ret
+= sprintf(page
+ ret
, ",pc");
1518 ret
+= sprintf(page
+ ret
, ",any");
1521 ret
+= sprintf(page
+ ret
, ",inv");
1524 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1526 ret
+= sprintf(page
+ ret
, "\n");
1531 static int __init
init_hw_perf_events(void)
1533 struct x86_pmu_quirk
*quirk
;
1536 pr_info("Performance Events: ");
1538 switch (boot_cpu_data
.x86_vendor
) {
1539 case X86_VENDOR_INTEL
:
1540 err
= intel_pmu_init();
1542 case X86_VENDOR_AMD
:
1543 err
= amd_pmu_init();
1549 pr_cont("no PMU driver, software events only.\n");
1555 /* sanity check that the hardware exists or is emulated */
1556 if (!check_hw_exists())
1559 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1561 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1563 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1566 if (!x86_pmu
.intel_ctrl
)
1567 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1569 perf_events_lapic_init();
1570 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1572 unconstrained
= (struct event_constraint
)
1573 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1574 0, x86_pmu
.num_counters
, 0, 0);
1576 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1578 if (x86_pmu
.event_attrs
)
1579 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1581 if (!x86_pmu
.events_sysfs_show
)
1582 x86_pmu_events_group
.attrs
= &empty_attrs
;
1584 filter_events(x86_pmu_events_group
.attrs
);
1586 if (x86_pmu
.cpu_events
) {
1587 struct attribute
**tmp
;
1589 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1591 x86_pmu_events_group
.attrs
= tmp
;
1594 pr_info("... version: %d\n", x86_pmu
.version
);
1595 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1596 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1597 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1598 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1599 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1600 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1602 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1603 perf_cpu_notifier(x86_pmu_notifier
);
1607 early_initcall(init_hw_perf_events
);
1609 static inline void x86_pmu_read(struct perf_event
*event
)
1611 x86_perf_event_update(event
);
1615 * Start group events scheduling transaction
1616 * Set the flag to make pmu::enable() not perform the
1617 * schedulability test, it will be performed at commit time
1619 static void x86_pmu_start_txn(struct pmu
*pmu
)
1621 perf_pmu_disable(pmu
);
1622 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1623 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1627 * Stop group events scheduling transaction
1628 * Clear the flag and pmu::enable() will perform the
1629 * schedulability test.
1631 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1633 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1635 * Truncate collected array by the number of events added in this
1636 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1638 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1639 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1640 perf_pmu_enable(pmu
);
1644 * Commit group events scheduling transaction
1645 * Perform the group schedulability test as a whole
1646 * Return 0 if success
1648 * Does not cancel the transaction on failure; expects the caller to do this.
1650 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1652 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1653 int assign
[X86_PMC_IDX_MAX
];
1658 if (!x86_pmu_initialized())
1661 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1666 * copy new assignment, now we know it is possible
1667 * will be used by hw_perf_enable()
1669 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1671 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1672 perf_pmu_enable(pmu
);
1676 * a fake_cpuc is used to validate event groups. Due to
1677 * the extra reg logic, we need to also allocate a fake
1678 * per_core and per_cpu structure. Otherwise, group events
1679 * using extra reg may conflict without the kernel being
1680 * able to catch this when the last event gets added to
1683 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1685 kfree(cpuc
->shared_regs
);
1689 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1691 struct cpu_hw_events
*cpuc
;
1692 int cpu
= raw_smp_processor_id();
1694 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1696 return ERR_PTR(-ENOMEM
);
1698 /* only needed, if we have extra_regs */
1699 if (x86_pmu
.extra_regs
) {
1700 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1701 if (!cpuc
->shared_regs
)
1707 free_fake_cpuc(cpuc
);
1708 return ERR_PTR(-ENOMEM
);
1712 * validate that we can schedule this event
1714 static int validate_event(struct perf_event
*event
)
1716 struct cpu_hw_events
*fake_cpuc
;
1717 struct event_constraint
*c
;
1720 fake_cpuc
= allocate_fake_cpuc();
1721 if (IS_ERR(fake_cpuc
))
1722 return PTR_ERR(fake_cpuc
);
1724 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1726 if (!c
|| !c
->weight
)
1729 if (x86_pmu
.put_event_constraints
)
1730 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1732 free_fake_cpuc(fake_cpuc
);
1738 * validate a single event group
1740 * validation include:
1741 * - check events are compatible which each other
1742 * - events do not compete for the same counter
1743 * - number of events <= number of counters
1745 * validation ensures the group can be loaded onto the
1746 * PMU if it was the only group available.
1748 static int validate_group(struct perf_event
*event
)
1750 struct perf_event
*leader
= event
->group_leader
;
1751 struct cpu_hw_events
*fake_cpuc
;
1752 int ret
= -EINVAL
, n
;
1754 fake_cpuc
= allocate_fake_cpuc();
1755 if (IS_ERR(fake_cpuc
))
1756 return PTR_ERR(fake_cpuc
);
1758 * the event is not yet connected with its
1759 * siblings therefore we must first collect
1760 * existing siblings, then add the new event
1761 * before we can simulate the scheduling
1763 n
= collect_events(fake_cpuc
, leader
, true);
1767 fake_cpuc
->n_events
= n
;
1768 n
= collect_events(fake_cpuc
, event
, false);
1772 fake_cpuc
->n_events
= n
;
1774 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1777 free_fake_cpuc(fake_cpuc
);
1781 static int x86_pmu_event_init(struct perf_event
*event
)
1786 switch (event
->attr
.type
) {
1788 case PERF_TYPE_HARDWARE
:
1789 case PERF_TYPE_HW_CACHE
:
1796 err
= __x86_pmu_event_init(event
);
1799 * we temporarily connect event to its pmu
1800 * such that validate_group() can classify
1801 * it as an x86 event using is_x86_event()
1806 if (event
->group_leader
!= event
)
1807 err
= validate_group(event
);
1809 err
= validate_event(event
);
1815 event
->destroy(event
);
1818 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
1819 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
1824 static void refresh_pce(void *ignored
)
1827 load_mm_cr4(current
->mm
);
1830 static void x86_pmu_event_mapped(struct perf_event
*event
)
1832 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1835 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
1836 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
1839 static void x86_pmu_event_unmapped(struct perf_event
*event
)
1844 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1847 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
1848 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
1851 static int x86_pmu_event_idx(struct perf_event
*event
)
1853 int idx
= event
->hw
.idx
;
1855 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1858 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
1859 idx
-= INTEL_PMC_IDX_FIXED
;
1866 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
1867 struct device_attribute
*attr
,
1870 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
1873 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
1874 struct device_attribute
*attr
,
1875 const char *buf
, size_t count
)
1880 ret
= kstrtoul(buf
, 0, &val
);
1887 if (x86_pmu
.attr_rdpmc_broken
)
1890 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
1892 * Changing into or out of always available, aka
1893 * perf-event-bypassing mode. This path is extremely slow,
1894 * but only root can trigger it, so it's okay.
1897 static_key_slow_inc(&rdpmc_always_available
);
1899 static_key_slow_dec(&rdpmc_always_available
);
1900 on_each_cpu(refresh_pce
, NULL
, 1);
1903 x86_pmu
.attr_rdpmc
= val
;
1908 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
1910 static struct attribute
*x86_pmu_attrs
[] = {
1911 &dev_attr_rdpmc
.attr
,
1915 static struct attribute_group x86_pmu_attr_group
= {
1916 .attrs
= x86_pmu_attrs
,
1919 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
1920 &x86_pmu_attr_group
,
1921 &x86_pmu_format_group
,
1922 &x86_pmu_events_group
,
1926 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
1928 if (x86_pmu
.sched_task
)
1929 x86_pmu
.sched_task(ctx
, sched_in
);
1932 void perf_check_microcode(void)
1934 if (x86_pmu
.check_microcode
)
1935 x86_pmu
.check_microcode();
1937 EXPORT_SYMBOL_GPL(perf_check_microcode
);
1939 static struct pmu pmu
= {
1940 .pmu_enable
= x86_pmu_enable
,
1941 .pmu_disable
= x86_pmu_disable
,
1943 .attr_groups
= x86_pmu_attr_groups
,
1945 .event_init
= x86_pmu_event_init
,
1947 .event_mapped
= x86_pmu_event_mapped
,
1948 .event_unmapped
= x86_pmu_event_unmapped
,
1952 .start
= x86_pmu_start
,
1953 .stop
= x86_pmu_stop
,
1954 .read
= x86_pmu_read
,
1956 .start_txn
= x86_pmu_start_txn
,
1957 .cancel_txn
= x86_pmu_cancel_txn
,
1958 .commit_txn
= x86_pmu_commit_txn
,
1960 .event_idx
= x86_pmu_event_idx
,
1961 .sched_task
= x86_pmu_sched_task
,
1962 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
1965 void arch_perf_update_userpage(struct perf_event
*event
,
1966 struct perf_event_mmap_page
*userpg
, u64 now
)
1968 struct cyc2ns_data
*data
;
1970 userpg
->cap_user_time
= 0;
1971 userpg
->cap_user_time_zero
= 0;
1972 userpg
->cap_user_rdpmc
=
1973 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
1974 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
1976 if (!sched_clock_stable())
1979 data
= cyc2ns_read_begin();
1982 * Internal timekeeping for enabled/running/stopped times
1983 * is always in the local_clock domain.
1985 userpg
->cap_user_time
= 1;
1986 userpg
->time_mult
= data
->cyc2ns_mul
;
1987 userpg
->time_shift
= data
->cyc2ns_shift
;
1988 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
1991 * cap_user_time_zero doesn't make sense when we're using a different
1992 * time base for the records.
1994 if (event
->clock
== &local_clock
) {
1995 userpg
->cap_user_time_zero
= 1;
1996 userpg
->time_zero
= data
->cyc2ns_offset
;
1999 cyc2ns_read_end(data
);
2006 static int backtrace_stack(void *data
, char *name
)
2011 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
2013 struct perf_callchain_entry
*entry
= data
;
2015 perf_callchain_store(entry
, addr
);
2018 static const struct stacktrace_ops backtrace_ops
= {
2019 .stack
= backtrace_stack
,
2020 .address
= backtrace_address
,
2021 .walk_stack
= print_context_stack_bp
,
2025 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2027 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2028 /* TODO: We don't support guest os callchain now */
2032 perf_callchain_store(entry
, regs
->ip
);
2034 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
2038 valid_user_frame(const void __user
*fp
, unsigned long size
)
2040 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2043 static unsigned long get_segment_base(unsigned int segment
)
2045 struct desc_struct
*desc
;
2046 int idx
= segment
>> 3;
2048 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2049 if (idx
> LDT_ENTRIES
)
2052 if (idx
> current
->active_mm
->context
.size
)
2055 desc
= current
->active_mm
->context
.ldt
;
2057 if (idx
> GDT_ENTRIES
)
2060 desc
= raw_cpu_ptr(gdt_page
.gdt
);
2063 return get_desc_base(desc
+ idx
);
2066 #ifdef CONFIG_COMPAT
2068 #include <asm/compat.h>
2071 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2073 /* 32-bit process in 64-bit kernel. */
2074 unsigned long ss_base
, cs_base
;
2075 struct stack_frame_ia32 frame
;
2076 const void __user
*fp
;
2078 if (!test_thread_flag(TIF_IA32
))
2081 cs_base
= get_segment_base(regs
->cs
);
2082 ss_base
= get_segment_base(regs
->ss
);
2084 fp
= compat_ptr(ss_base
+ regs
->bp
);
2085 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2086 unsigned long bytes
;
2087 frame
.next_frame
= 0;
2088 frame
.return_address
= 0;
2090 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2094 if (!valid_user_frame(fp
, sizeof(frame
)))
2097 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2098 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2104 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2111 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2113 struct stack_frame frame
;
2114 const void __user
*fp
;
2116 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2117 /* TODO: We don't support guest os callchain now */
2122 * We don't know what to do with VM86 stacks.. ignore them for now.
2124 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2127 fp
= (void __user
*)regs
->bp
;
2129 perf_callchain_store(entry
, regs
->ip
);
2134 if (perf_callchain_user32(regs
, entry
))
2137 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2138 unsigned long bytes
;
2139 frame
.next_frame
= NULL
;
2140 frame
.return_address
= 0;
2142 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2146 if (!valid_user_frame(fp
, sizeof(frame
)))
2149 perf_callchain_store(entry
, frame
.return_address
);
2150 fp
= frame
.next_frame
;
2155 * Deal with code segment offsets for the various execution modes:
2157 * VM86 - the good olde 16 bit days, where the linear address is
2158 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2160 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2161 * to figure out what the 32bit base address is.
2163 * X32 - has TIF_X32 set, but is running in x86_64
2165 * X86_64 - CS,DS,SS,ES are all zero based.
2167 static unsigned long code_segment_base(struct pt_regs
*regs
)
2170 * If we are in VM86 mode, add the segment offset to convert to a
2173 if (regs
->flags
& X86_VM_MASK
)
2174 return 0x10 * regs
->cs
;
2177 * For IA32 we look at the GDT/LDT segment base to convert the
2178 * effective IP to a linear address.
2180 #ifdef CONFIG_X86_32
2181 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2182 return get_segment_base(regs
->cs
);
2184 if (test_thread_flag(TIF_IA32
)) {
2185 if (user_mode(regs
) && regs
->cs
!= __USER32_CS
)
2186 return get_segment_base(regs
->cs
);
2192 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2194 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2195 return perf_guest_cbs
->get_guest_ip();
2197 return regs
->ip
+ code_segment_base(regs
);
2200 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2204 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2205 if (perf_guest_cbs
->is_user_mode())
2206 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2208 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2210 if (user_mode(regs
))
2211 misc
|= PERF_RECORD_MISC_USER
;
2213 misc
|= PERF_RECORD_MISC_KERNEL
;
2216 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2217 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2222 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2224 cap
->version
= x86_pmu
.version
;
2225 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2226 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2227 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2228 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2229 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2230 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2232 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);