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[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event.c
1 /*
2 * Performance events x86 architecture code
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27
28 #include <asm/apic.h>
29 #include <asm/stacktrace.h>
30 #include <asm/nmi.h>
31
32 static u64 perf_event_mask __read_mostly;
33
34 /* The maximal number of PEBS events: */
35 #define MAX_PEBS_EVENTS 4
36
37 /* The size of a BTS record in bytes: */
38 #define BTS_RECORD_SIZE 24
39
40 /* The size of a per-cpu BTS buffer in bytes: */
41 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
42
43 /* The BTS overflow threshold in bytes from the end of the buffer: */
44 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
45
46
47 /*
48 * Bits in the debugctlmsr controlling branch tracing.
49 */
50 #define X86_DEBUGCTL_TR (1 << 6)
51 #define X86_DEBUGCTL_BTS (1 << 7)
52 #define X86_DEBUGCTL_BTINT (1 << 8)
53 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
54 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
55
56 /*
57 * A debug store configuration.
58 *
59 * We only support architectures that use 64bit fields.
60 */
61 struct debug_store {
62 u64 bts_buffer_base;
63 u64 bts_index;
64 u64 bts_absolute_maximum;
65 u64 bts_interrupt_threshold;
66 u64 pebs_buffer_base;
67 u64 pebs_index;
68 u64 pebs_absolute_maximum;
69 u64 pebs_interrupt_threshold;
70 u64 pebs_event_reset[MAX_PEBS_EVENTS];
71 };
72
73 struct event_constraint {
74 union {
75 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
76 u64 idxmsk64;
77 };
78 u64 code;
79 u64 cmask;
80 int weight;
81 };
82
83 struct amd_nb {
84 int nb_id; /* NorthBridge id */
85 int refcnt; /* reference count */
86 struct perf_event *owners[X86_PMC_IDX_MAX];
87 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
88 };
89
90 struct cpu_hw_events {
91 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
92 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
93 unsigned long interrupts;
94 int enabled;
95 struct debug_store *ds;
96
97 int n_events;
98 int n_added;
99 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
100 u64 tags[X86_PMC_IDX_MAX];
101 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
102 struct amd_nb *amd_nb;
103 };
104
105 #define __EVENT_CONSTRAINT(c, n, m, w) {\
106 { .idxmsk64 = (n) }, \
107 .code = (c), \
108 .cmask = (m), \
109 .weight = (w), \
110 }
111
112 #define EVENT_CONSTRAINT(c, n, m) \
113 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
114
115 #define INTEL_EVENT_CONSTRAINT(c, n) \
116 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
117
118 #define FIXED_EVENT_CONSTRAINT(c, n) \
119 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
120
121 #define EVENT_CONSTRAINT_END \
122 EVENT_CONSTRAINT(0, 0, 0)
123
124 #define for_each_event_constraint(e, c) \
125 for ((e) = (c); (e)->cmask; (e)++)
126
127 /*
128 * struct x86_pmu - generic x86 pmu
129 */
130 struct x86_pmu {
131 const char *name;
132 int version;
133 int (*handle_irq)(struct pt_regs *);
134 void (*disable_all)(void);
135 void (*enable_all)(void);
136 void (*enable)(struct perf_event *);
137 void (*disable)(struct perf_event *);
138 unsigned eventsel;
139 unsigned perfctr;
140 u64 (*event_map)(int);
141 u64 (*raw_event)(u64);
142 int max_events;
143 int num_events;
144 int num_events_fixed;
145 int event_bits;
146 u64 event_mask;
147 int apic;
148 u64 max_period;
149 u64 intel_ctrl;
150 void (*enable_bts)(u64 config);
151 void (*disable_bts)(void);
152
153 struct event_constraint *
154 (*get_event_constraints)(struct cpu_hw_events *cpuc,
155 struct perf_event *event);
156
157 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
158 struct perf_event *event);
159 struct event_constraint *event_constraints;
160
161 void (*cpu_prepare)(int cpu);
162 void (*cpu_starting)(int cpu);
163 void (*cpu_dying)(int cpu);
164 void (*cpu_dead)(int cpu);
165 };
166
167 static struct x86_pmu x86_pmu __read_mostly;
168
169 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
170 .enabled = 1,
171 };
172
173 static int x86_perf_event_set_period(struct perf_event *event);
174
175 /*
176 * Generalized hw caching related hw_event table, filled
177 * in on a per model basis. A value of 0 means
178 * 'not supported', -1 means 'hw_event makes no sense on
179 * this CPU', any other value means the raw hw_event
180 * ID.
181 */
182
183 #define C(x) PERF_COUNT_HW_CACHE_##x
184
185 static u64 __read_mostly hw_cache_event_ids
186 [PERF_COUNT_HW_CACHE_MAX]
187 [PERF_COUNT_HW_CACHE_OP_MAX]
188 [PERF_COUNT_HW_CACHE_RESULT_MAX];
189
190 /*
191 * Propagate event elapsed time into the generic event.
192 * Can only be executed on the CPU where the event is active.
193 * Returns the delta events processed.
194 */
195 static u64
196 x86_perf_event_update(struct perf_event *event)
197 {
198 struct hw_perf_event *hwc = &event->hw;
199 int shift = 64 - x86_pmu.event_bits;
200 u64 prev_raw_count, new_raw_count;
201 int idx = hwc->idx;
202 s64 delta;
203
204 if (idx == X86_PMC_IDX_FIXED_BTS)
205 return 0;
206
207 /*
208 * Careful: an NMI might modify the previous event value.
209 *
210 * Our tactic to handle this is to first atomically read and
211 * exchange a new raw count - then add that new-prev delta
212 * count to the generic event atomically:
213 */
214 again:
215 prev_raw_count = atomic64_read(&hwc->prev_count);
216 rdmsrl(hwc->event_base + idx, new_raw_count);
217
218 if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
219 new_raw_count) != prev_raw_count)
220 goto again;
221
222 /*
223 * Now we have the new raw value and have updated the prev
224 * timestamp already. We can now calculate the elapsed delta
225 * (event-)time and add that to the generic event.
226 *
227 * Careful, not all hw sign-extends above the physical width
228 * of the count.
229 */
230 delta = (new_raw_count << shift) - (prev_raw_count << shift);
231 delta >>= shift;
232
233 atomic64_add(delta, &event->count);
234 atomic64_sub(delta, &hwc->period_left);
235
236 return new_raw_count;
237 }
238
239 static atomic_t active_events;
240 static DEFINE_MUTEX(pmc_reserve_mutex);
241
242 static bool reserve_pmc_hardware(void)
243 {
244 #ifdef CONFIG_X86_LOCAL_APIC
245 int i;
246
247 if (nmi_watchdog == NMI_LOCAL_APIC)
248 disable_lapic_nmi_watchdog();
249
250 for (i = 0; i < x86_pmu.num_events; i++) {
251 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
252 goto perfctr_fail;
253 }
254
255 for (i = 0; i < x86_pmu.num_events; i++) {
256 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
257 goto eventsel_fail;
258 }
259 #endif
260
261 return true;
262
263 #ifdef CONFIG_X86_LOCAL_APIC
264 eventsel_fail:
265 for (i--; i >= 0; i--)
266 release_evntsel_nmi(x86_pmu.eventsel + i);
267
268 i = x86_pmu.num_events;
269
270 perfctr_fail:
271 for (i--; i >= 0; i--)
272 release_perfctr_nmi(x86_pmu.perfctr + i);
273
274 if (nmi_watchdog == NMI_LOCAL_APIC)
275 enable_lapic_nmi_watchdog();
276
277 return false;
278 #endif
279 }
280
281 static void release_pmc_hardware(void)
282 {
283 #ifdef CONFIG_X86_LOCAL_APIC
284 int i;
285
286 for (i = 0; i < x86_pmu.num_events; i++) {
287 release_perfctr_nmi(x86_pmu.perfctr + i);
288 release_evntsel_nmi(x86_pmu.eventsel + i);
289 }
290
291 if (nmi_watchdog == NMI_LOCAL_APIC)
292 enable_lapic_nmi_watchdog();
293 #endif
294 }
295
296 static inline bool bts_available(void)
297 {
298 return x86_pmu.enable_bts != NULL;
299 }
300
301 static void init_debug_store_on_cpu(int cpu)
302 {
303 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
304
305 if (!ds)
306 return;
307
308 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
309 (u32)((u64)(unsigned long)ds),
310 (u32)((u64)(unsigned long)ds >> 32));
311 }
312
313 static void fini_debug_store_on_cpu(int cpu)
314 {
315 if (!per_cpu(cpu_hw_events, cpu).ds)
316 return;
317
318 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
319 }
320
321 static void release_bts_hardware(void)
322 {
323 int cpu;
324
325 if (!bts_available())
326 return;
327
328 get_online_cpus();
329
330 for_each_online_cpu(cpu)
331 fini_debug_store_on_cpu(cpu);
332
333 for_each_possible_cpu(cpu) {
334 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
335
336 if (!ds)
337 continue;
338
339 per_cpu(cpu_hw_events, cpu).ds = NULL;
340
341 kfree((void *)(unsigned long)ds->bts_buffer_base);
342 kfree(ds);
343 }
344
345 put_online_cpus();
346 }
347
348 static int reserve_bts_hardware(void)
349 {
350 int cpu, err = 0;
351
352 if (!bts_available())
353 return 0;
354
355 get_online_cpus();
356
357 for_each_possible_cpu(cpu) {
358 struct debug_store *ds;
359 void *buffer;
360
361 err = -ENOMEM;
362 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
363 if (unlikely(!buffer))
364 break;
365
366 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
367 if (unlikely(!ds)) {
368 kfree(buffer);
369 break;
370 }
371
372 ds->bts_buffer_base = (u64)(unsigned long)buffer;
373 ds->bts_index = ds->bts_buffer_base;
374 ds->bts_absolute_maximum =
375 ds->bts_buffer_base + BTS_BUFFER_SIZE;
376 ds->bts_interrupt_threshold =
377 ds->bts_absolute_maximum - BTS_OVFL_TH;
378
379 per_cpu(cpu_hw_events, cpu).ds = ds;
380 err = 0;
381 }
382
383 if (err)
384 release_bts_hardware();
385 else {
386 for_each_online_cpu(cpu)
387 init_debug_store_on_cpu(cpu);
388 }
389
390 put_online_cpus();
391
392 return err;
393 }
394
395 static void hw_perf_event_destroy(struct perf_event *event)
396 {
397 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
398 release_pmc_hardware();
399 release_bts_hardware();
400 mutex_unlock(&pmc_reserve_mutex);
401 }
402 }
403
404 static inline int x86_pmu_initialized(void)
405 {
406 return x86_pmu.handle_irq != NULL;
407 }
408
409 static inline int
410 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
411 {
412 unsigned int cache_type, cache_op, cache_result;
413 u64 config, val;
414
415 config = attr->config;
416
417 cache_type = (config >> 0) & 0xff;
418 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
419 return -EINVAL;
420
421 cache_op = (config >> 8) & 0xff;
422 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
423 return -EINVAL;
424
425 cache_result = (config >> 16) & 0xff;
426 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
427 return -EINVAL;
428
429 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
430
431 if (val == 0)
432 return -ENOENT;
433
434 if (val == -1)
435 return -EINVAL;
436
437 hwc->config |= val;
438
439 return 0;
440 }
441
442 /*
443 * Setup the hardware configuration for a given attr_type
444 */
445 static int __hw_perf_event_init(struct perf_event *event)
446 {
447 struct perf_event_attr *attr = &event->attr;
448 struct hw_perf_event *hwc = &event->hw;
449 u64 config;
450 int err;
451
452 if (!x86_pmu_initialized())
453 return -ENODEV;
454
455 err = 0;
456 if (!atomic_inc_not_zero(&active_events)) {
457 mutex_lock(&pmc_reserve_mutex);
458 if (atomic_read(&active_events) == 0) {
459 if (!reserve_pmc_hardware())
460 err = -EBUSY;
461 else
462 err = reserve_bts_hardware();
463 }
464 if (!err)
465 atomic_inc(&active_events);
466 mutex_unlock(&pmc_reserve_mutex);
467 }
468 if (err)
469 return err;
470
471 event->destroy = hw_perf_event_destroy;
472
473 /*
474 * Generate PMC IRQs:
475 * (keep 'enabled' bit clear for now)
476 */
477 hwc->config = ARCH_PERFMON_EVENTSEL_INT;
478
479 hwc->idx = -1;
480 hwc->last_cpu = -1;
481 hwc->last_tag = ~0ULL;
482
483 /*
484 * Count user and OS events unless requested not to.
485 */
486 if (!attr->exclude_user)
487 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
488 if (!attr->exclude_kernel)
489 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
490
491 if (!hwc->sample_period) {
492 hwc->sample_period = x86_pmu.max_period;
493 hwc->last_period = hwc->sample_period;
494 atomic64_set(&hwc->period_left, hwc->sample_period);
495 } else {
496 /*
497 * If we have a PMU initialized but no APIC
498 * interrupts, we cannot sample hardware
499 * events (user-space has to fall back and
500 * sample via a hrtimer based software event):
501 */
502 if (!x86_pmu.apic)
503 return -EOPNOTSUPP;
504 }
505
506 /*
507 * Raw hw_event type provide the config in the hw_event structure
508 */
509 if (attr->type == PERF_TYPE_RAW) {
510 hwc->config |= x86_pmu.raw_event(attr->config);
511 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
512 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
513 return -EACCES;
514 return 0;
515 }
516
517 if (attr->type == PERF_TYPE_HW_CACHE)
518 return set_ext_hw_attr(hwc, attr);
519
520 if (attr->config >= x86_pmu.max_events)
521 return -EINVAL;
522
523 /*
524 * The generic map:
525 */
526 config = x86_pmu.event_map(attr->config);
527
528 if (config == 0)
529 return -ENOENT;
530
531 if (config == -1LL)
532 return -EINVAL;
533
534 /*
535 * Branch tracing:
536 */
537 if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
538 (hwc->sample_period == 1)) {
539 /* BTS is not supported by this architecture. */
540 if (!bts_available())
541 return -EOPNOTSUPP;
542
543 /* BTS is currently only allowed for user-mode. */
544 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
545 return -EOPNOTSUPP;
546 }
547
548 hwc->config |= config;
549
550 return 0;
551 }
552
553 static void x86_pmu_disable_all(void)
554 {
555 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
556 int idx;
557
558 for (idx = 0; idx < x86_pmu.num_events; idx++) {
559 u64 val;
560
561 if (!test_bit(idx, cpuc->active_mask))
562 continue;
563 rdmsrl(x86_pmu.eventsel + idx, val);
564 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
565 continue;
566 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
567 wrmsrl(x86_pmu.eventsel + idx, val);
568 }
569 }
570
571 void hw_perf_disable(void)
572 {
573 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
574
575 if (!x86_pmu_initialized())
576 return;
577
578 if (!cpuc->enabled)
579 return;
580
581 cpuc->n_added = 0;
582 cpuc->enabled = 0;
583 barrier();
584
585 x86_pmu.disable_all();
586 }
587
588 static void x86_pmu_enable_all(void)
589 {
590 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
591 int idx;
592
593 for (idx = 0; idx < x86_pmu.num_events; idx++) {
594 struct perf_event *event = cpuc->events[idx];
595 u64 val;
596
597 if (!test_bit(idx, cpuc->active_mask))
598 continue;
599
600 val = event->hw.config;
601 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
602 wrmsrl(x86_pmu.eventsel + idx, val);
603 }
604 }
605
606 static const struct pmu pmu;
607
608 static inline int is_x86_event(struct perf_event *event)
609 {
610 return event->pmu == &pmu;
611 }
612
613 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
614 {
615 struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
616 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
617 int i, j, w, wmax, num = 0;
618 struct hw_perf_event *hwc;
619
620 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
621
622 for (i = 0; i < n; i++) {
623 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
624 constraints[i] = c;
625 }
626
627 /*
628 * fastpath, try to reuse previous register
629 */
630 for (i = 0; i < n; i++) {
631 hwc = &cpuc->event_list[i]->hw;
632 c = constraints[i];
633
634 /* never assigned */
635 if (hwc->idx == -1)
636 break;
637
638 /* constraint still honored */
639 if (!test_bit(hwc->idx, c->idxmsk))
640 break;
641
642 /* not already used */
643 if (test_bit(hwc->idx, used_mask))
644 break;
645
646 __set_bit(hwc->idx, used_mask);
647 if (assign)
648 assign[i] = hwc->idx;
649 }
650 if (i == n)
651 goto done;
652
653 /*
654 * begin slow path
655 */
656
657 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
658
659 /*
660 * weight = number of possible counters
661 *
662 * 1 = most constrained, only works on one counter
663 * wmax = least constrained, works on any counter
664 *
665 * assign events to counters starting with most
666 * constrained events.
667 */
668 wmax = x86_pmu.num_events;
669
670 /*
671 * when fixed event counters are present,
672 * wmax is incremented by 1 to account
673 * for one more choice
674 */
675 if (x86_pmu.num_events_fixed)
676 wmax++;
677
678 for (w = 1, num = n; num && w <= wmax; w++) {
679 /* for each event */
680 for (i = 0; num && i < n; i++) {
681 c = constraints[i];
682 hwc = &cpuc->event_list[i]->hw;
683
684 if (c->weight != w)
685 continue;
686
687 for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
688 if (!test_bit(j, used_mask))
689 break;
690 }
691
692 if (j == X86_PMC_IDX_MAX)
693 break;
694
695 __set_bit(j, used_mask);
696
697 if (assign)
698 assign[i] = j;
699 num--;
700 }
701 }
702 done:
703 /*
704 * scheduling failed or is just a simulation,
705 * free resources if necessary
706 */
707 if (!assign || num) {
708 for (i = 0; i < n; i++) {
709 if (x86_pmu.put_event_constraints)
710 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
711 }
712 }
713 return num ? -ENOSPC : 0;
714 }
715
716 /*
717 * dogrp: true if must collect siblings events (group)
718 * returns total number of events and error code
719 */
720 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
721 {
722 struct perf_event *event;
723 int n, max_count;
724
725 max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
726
727 /* current number of events already accepted */
728 n = cpuc->n_events;
729
730 if (is_x86_event(leader)) {
731 if (n >= max_count)
732 return -ENOSPC;
733 cpuc->event_list[n] = leader;
734 n++;
735 }
736 if (!dogrp)
737 return n;
738
739 list_for_each_entry(event, &leader->sibling_list, group_entry) {
740 if (!is_x86_event(event) ||
741 event->state <= PERF_EVENT_STATE_OFF)
742 continue;
743
744 if (n >= max_count)
745 return -ENOSPC;
746
747 cpuc->event_list[n] = event;
748 n++;
749 }
750 return n;
751 }
752
753 static inline void x86_assign_hw_event(struct perf_event *event,
754 struct cpu_hw_events *cpuc, int i)
755 {
756 struct hw_perf_event *hwc = &event->hw;
757
758 hwc->idx = cpuc->assign[i];
759 hwc->last_cpu = smp_processor_id();
760 hwc->last_tag = ++cpuc->tags[i];
761
762 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
763 hwc->config_base = 0;
764 hwc->event_base = 0;
765 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
766 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
767 /*
768 * We set it so that event_base + idx in wrmsr/rdmsr maps to
769 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
770 */
771 hwc->event_base =
772 MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
773 } else {
774 hwc->config_base = x86_pmu.eventsel;
775 hwc->event_base = x86_pmu.perfctr;
776 }
777 }
778
779 static inline int match_prev_assignment(struct hw_perf_event *hwc,
780 struct cpu_hw_events *cpuc,
781 int i)
782 {
783 return hwc->idx == cpuc->assign[i] &&
784 hwc->last_cpu == smp_processor_id() &&
785 hwc->last_tag == cpuc->tags[i];
786 }
787
788 static int x86_pmu_start(struct perf_event *event);
789 static void x86_pmu_stop(struct perf_event *event);
790
791 void hw_perf_enable(void)
792 {
793 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
794 struct perf_event *event;
795 struct hw_perf_event *hwc;
796 int i;
797
798 if (!x86_pmu_initialized())
799 return;
800
801 if (cpuc->enabled)
802 return;
803
804 if (cpuc->n_added) {
805 int n_running = cpuc->n_events - cpuc->n_added;
806 /*
807 * apply assignment obtained either from
808 * hw_perf_group_sched_in() or x86_pmu_enable()
809 *
810 * step1: save events moving to new counters
811 * step2: reprogram moved events into new counters
812 */
813 for (i = 0; i < n_running; i++) {
814
815 event = cpuc->event_list[i];
816 hwc = &event->hw;
817
818 /*
819 * we can avoid reprogramming counter if:
820 * - assigned same counter as last time
821 * - running on same CPU as last time
822 * - no other event has used the counter since
823 */
824 if (hwc->idx == -1 ||
825 match_prev_assignment(hwc, cpuc, i))
826 continue;
827
828 x86_pmu_stop(event);
829
830 hwc->idx = -1;
831 }
832
833 for (i = 0; i < cpuc->n_events; i++) {
834
835 event = cpuc->event_list[i];
836 hwc = &event->hw;
837
838 if (hwc->idx == -1)
839 x86_assign_hw_event(event, cpuc, i);
840
841 x86_pmu_start(event);
842 }
843 cpuc->n_added = 0;
844 perf_events_lapic_init();
845 }
846
847 cpuc->enabled = 1;
848 barrier();
849
850 x86_pmu.enable_all();
851 }
852
853 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
854 {
855 (void)checking_wrmsrl(hwc->config_base + hwc->idx,
856 hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
857 }
858
859 static inline void x86_pmu_disable_event(struct perf_event *event)
860 {
861 struct hw_perf_event *hwc = &event->hw;
862 (void)checking_wrmsrl(hwc->config_base + hwc->idx, hwc->config);
863 }
864
865 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
866
867 /*
868 * Set the next IRQ period, based on the hwc->period_left value.
869 * To be called with the event disabled in hw:
870 */
871 static int
872 x86_perf_event_set_period(struct perf_event *event)
873 {
874 struct hw_perf_event *hwc = &event->hw;
875 s64 left = atomic64_read(&hwc->period_left);
876 s64 period = hwc->sample_period;
877 int err, ret = 0, idx = hwc->idx;
878
879 if (idx == X86_PMC_IDX_FIXED_BTS)
880 return 0;
881
882 /*
883 * If we are way outside a reasonable range then just skip forward:
884 */
885 if (unlikely(left <= -period)) {
886 left = period;
887 atomic64_set(&hwc->period_left, left);
888 hwc->last_period = period;
889 ret = 1;
890 }
891
892 if (unlikely(left <= 0)) {
893 left += period;
894 atomic64_set(&hwc->period_left, left);
895 hwc->last_period = period;
896 ret = 1;
897 }
898 /*
899 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
900 */
901 if (unlikely(left < 2))
902 left = 2;
903
904 if (left > x86_pmu.max_period)
905 left = x86_pmu.max_period;
906
907 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
908
909 /*
910 * The hw event starts counting from this event offset,
911 * mark it to be able to extra future deltas:
912 */
913 atomic64_set(&hwc->prev_count, (u64)-left);
914
915 err = checking_wrmsrl(hwc->event_base + idx,
916 (u64)(-left) & x86_pmu.event_mask);
917
918 perf_event_update_userpage(event);
919
920 return ret;
921 }
922
923 static void x86_pmu_enable_event(struct perf_event *event)
924 {
925 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
926 if (cpuc->enabled)
927 __x86_pmu_enable_event(&event->hw);
928 }
929
930 /*
931 * activate a single event
932 *
933 * The event is added to the group of enabled events
934 * but only if it can be scehduled with existing events.
935 *
936 * Called with PMU disabled. If successful and return value 1,
937 * then guaranteed to call perf_enable() and hw_perf_enable()
938 */
939 static int x86_pmu_enable(struct perf_event *event)
940 {
941 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
942 struct hw_perf_event *hwc;
943 int assign[X86_PMC_IDX_MAX];
944 int n, n0, ret;
945
946 hwc = &event->hw;
947
948 n0 = cpuc->n_events;
949 n = collect_events(cpuc, event, false);
950 if (n < 0)
951 return n;
952
953 ret = x86_schedule_events(cpuc, n, assign);
954 if (ret)
955 return ret;
956 /*
957 * copy new assignment, now we know it is possible
958 * will be used by hw_perf_enable()
959 */
960 memcpy(cpuc->assign, assign, n*sizeof(int));
961
962 cpuc->n_events = n;
963 cpuc->n_added += n - n0;
964
965 return 0;
966 }
967
968 static int x86_pmu_start(struct perf_event *event)
969 {
970 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
971 int idx = event->hw.idx;
972
973 if (idx == -1)
974 return -EAGAIN;
975
976 x86_perf_event_set_period(event);
977 cpuc->events[idx] = event;
978 __set_bit(idx, cpuc->active_mask);
979 x86_pmu.enable(event);
980 perf_event_update_userpage(event);
981
982 return 0;
983 }
984
985 static void x86_pmu_unthrottle(struct perf_event *event)
986 {
987 int ret = x86_pmu_start(event);
988 WARN_ON_ONCE(ret);
989 }
990
991 void perf_event_print_debug(void)
992 {
993 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
994 struct cpu_hw_events *cpuc;
995 unsigned long flags;
996 int cpu, idx;
997
998 if (!x86_pmu.num_events)
999 return;
1000
1001 local_irq_save(flags);
1002
1003 cpu = smp_processor_id();
1004 cpuc = &per_cpu(cpu_hw_events, cpu);
1005
1006 if (x86_pmu.version >= 2) {
1007 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1008 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1009 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1010 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1011
1012 pr_info("\n");
1013 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1014 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1015 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1016 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1017 }
1018 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1019
1020 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1021 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1022 rdmsrl(x86_pmu.perfctr + idx, pmc_count);
1023
1024 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1025
1026 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1027 cpu, idx, pmc_ctrl);
1028 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1029 cpu, idx, pmc_count);
1030 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1031 cpu, idx, prev_left);
1032 }
1033 for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1034 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1035
1036 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1037 cpu, idx, pmc_count);
1038 }
1039 local_irq_restore(flags);
1040 }
1041
1042 static void x86_pmu_stop(struct perf_event *event)
1043 {
1044 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1045 struct hw_perf_event *hwc = &event->hw;
1046 int idx = hwc->idx;
1047
1048 if (!__test_and_clear_bit(idx, cpuc->active_mask))
1049 return;
1050
1051 x86_pmu.disable(event);
1052
1053 /*
1054 * Drain the remaining delta count out of a event
1055 * that we are disabling:
1056 */
1057 x86_perf_event_update(event);
1058
1059 cpuc->events[idx] = NULL;
1060 }
1061
1062 static void x86_pmu_disable(struct perf_event *event)
1063 {
1064 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1065 int i;
1066
1067 x86_pmu_stop(event);
1068
1069 for (i = 0; i < cpuc->n_events; i++) {
1070 if (event == cpuc->event_list[i]) {
1071
1072 if (x86_pmu.put_event_constraints)
1073 x86_pmu.put_event_constraints(cpuc, event);
1074
1075 while (++i < cpuc->n_events)
1076 cpuc->event_list[i-1] = cpuc->event_list[i];
1077
1078 --cpuc->n_events;
1079 break;
1080 }
1081 }
1082 perf_event_update_userpage(event);
1083 }
1084
1085 static int x86_pmu_handle_irq(struct pt_regs *regs)
1086 {
1087 struct perf_sample_data data;
1088 struct cpu_hw_events *cpuc;
1089 struct perf_event *event;
1090 struct hw_perf_event *hwc;
1091 int idx, handled = 0;
1092 u64 val;
1093
1094 perf_sample_data_init(&data, 0);
1095
1096 cpuc = &__get_cpu_var(cpu_hw_events);
1097
1098 for (idx = 0; idx < x86_pmu.num_events; idx++) {
1099 if (!test_bit(idx, cpuc->active_mask))
1100 continue;
1101
1102 event = cpuc->events[idx];
1103 hwc = &event->hw;
1104
1105 val = x86_perf_event_update(event);
1106 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1107 continue;
1108
1109 /*
1110 * event overflow
1111 */
1112 handled = 1;
1113 data.period = event->hw.last_period;
1114
1115 if (!x86_perf_event_set_period(event))
1116 continue;
1117
1118 if (perf_event_overflow(event, 1, &data, regs))
1119 x86_pmu_stop(event);
1120 }
1121
1122 if (handled)
1123 inc_irq_stat(apic_perf_irqs);
1124
1125 return handled;
1126 }
1127
1128 void smp_perf_pending_interrupt(struct pt_regs *regs)
1129 {
1130 irq_enter();
1131 ack_APIC_irq();
1132 inc_irq_stat(apic_pending_irqs);
1133 perf_event_do_pending();
1134 irq_exit();
1135 }
1136
1137 void set_perf_event_pending(void)
1138 {
1139 #ifdef CONFIG_X86_LOCAL_APIC
1140 if (!x86_pmu.apic || !x86_pmu_initialized())
1141 return;
1142
1143 apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1144 #endif
1145 }
1146
1147 void perf_events_lapic_init(void)
1148 {
1149 #ifdef CONFIG_X86_LOCAL_APIC
1150 if (!x86_pmu.apic || !x86_pmu_initialized())
1151 return;
1152
1153 /*
1154 * Always use NMI for PMU
1155 */
1156 apic_write(APIC_LVTPC, APIC_DM_NMI);
1157 #endif
1158 }
1159
1160 static int __kprobes
1161 perf_event_nmi_handler(struct notifier_block *self,
1162 unsigned long cmd, void *__args)
1163 {
1164 struct die_args *args = __args;
1165 struct pt_regs *regs;
1166
1167 if (!atomic_read(&active_events))
1168 return NOTIFY_DONE;
1169
1170 switch (cmd) {
1171 case DIE_NMI:
1172 case DIE_NMI_IPI:
1173 break;
1174
1175 default:
1176 return NOTIFY_DONE;
1177 }
1178
1179 regs = args->regs;
1180
1181 #ifdef CONFIG_X86_LOCAL_APIC
1182 apic_write(APIC_LVTPC, APIC_DM_NMI);
1183 #endif
1184 /*
1185 * Can't rely on the handled return value to say it was our NMI, two
1186 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1187 *
1188 * If the first NMI handles both, the latter will be empty and daze
1189 * the CPU.
1190 */
1191 x86_pmu.handle_irq(regs);
1192
1193 return NOTIFY_STOP;
1194 }
1195
1196 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1197 .notifier_call = perf_event_nmi_handler,
1198 .next = NULL,
1199 .priority = 1
1200 };
1201
1202 static struct event_constraint unconstrained;
1203 static struct event_constraint emptyconstraint;
1204
1205 static struct event_constraint *
1206 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1207 {
1208 struct event_constraint *c;
1209
1210 if (x86_pmu.event_constraints) {
1211 for_each_event_constraint(c, x86_pmu.event_constraints) {
1212 if ((event->hw.config & c->cmask) == c->code)
1213 return c;
1214 }
1215 }
1216
1217 return &unconstrained;
1218 }
1219
1220 static int x86_event_sched_in(struct perf_event *event,
1221 struct perf_cpu_context *cpuctx)
1222 {
1223 int ret = 0;
1224
1225 event->state = PERF_EVENT_STATE_ACTIVE;
1226 event->oncpu = smp_processor_id();
1227 event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1228
1229 if (!is_x86_event(event))
1230 ret = event->pmu->enable(event);
1231
1232 if (!ret && !is_software_event(event))
1233 cpuctx->active_oncpu++;
1234
1235 if (!ret && event->attr.exclusive)
1236 cpuctx->exclusive = 1;
1237
1238 return ret;
1239 }
1240
1241 static void x86_event_sched_out(struct perf_event *event,
1242 struct perf_cpu_context *cpuctx)
1243 {
1244 event->state = PERF_EVENT_STATE_INACTIVE;
1245 event->oncpu = -1;
1246
1247 if (!is_x86_event(event))
1248 event->pmu->disable(event);
1249
1250 event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1251
1252 if (!is_software_event(event))
1253 cpuctx->active_oncpu--;
1254
1255 if (event->attr.exclusive || !cpuctx->active_oncpu)
1256 cpuctx->exclusive = 0;
1257 }
1258
1259 /*
1260 * Called to enable a whole group of events.
1261 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1262 * Assumes the caller has disabled interrupts and has
1263 * frozen the PMU with hw_perf_save_disable.
1264 *
1265 * called with PMU disabled. If successful and return value 1,
1266 * then guaranteed to call perf_enable() and hw_perf_enable()
1267 */
1268 int hw_perf_group_sched_in(struct perf_event *leader,
1269 struct perf_cpu_context *cpuctx,
1270 struct perf_event_context *ctx)
1271 {
1272 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1273 struct perf_event *sub;
1274 int assign[X86_PMC_IDX_MAX];
1275 int n0, n1, ret;
1276
1277 /* n0 = total number of events */
1278 n0 = collect_events(cpuc, leader, true);
1279 if (n0 < 0)
1280 return n0;
1281
1282 ret = x86_schedule_events(cpuc, n0, assign);
1283 if (ret)
1284 return ret;
1285
1286 ret = x86_event_sched_in(leader, cpuctx);
1287 if (ret)
1288 return ret;
1289
1290 n1 = 1;
1291 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1292 if (sub->state > PERF_EVENT_STATE_OFF) {
1293 ret = x86_event_sched_in(sub, cpuctx);
1294 if (ret)
1295 goto undo;
1296 ++n1;
1297 }
1298 }
1299 /*
1300 * copy new assignment, now we know it is possible
1301 * will be used by hw_perf_enable()
1302 */
1303 memcpy(cpuc->assign, assign, n0*sizeof(int));
1304
1305 cpuc->n_events = n0;
1306 cpuc->n_added += n1;
1307 ctx->nr_active += n1;
1308
1309 /*
1310 * 1 means successful and events are active
1311 * This is not quite true because we defer
1312 * actual activation until hw_perf_enable() but
1313 * this way we* ensure caller won't try to enable
1314 * individual events
1315 */
1316 return 1;
1317 undo:
1318 x86_event_sched_out(leader, cpuctx);
1319 n0 = 1;
1320 list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1321 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1322 x86_event_sched_out(sub, cpuctx);
1323 if (++n0 == n1)
1324 break;
1325 }
1326 }
1327 return ret;
1328 }
1329
1330 #include "perf_event_amd.c"
1331 #include "perf_event_p6.c"
1332 #include "perf_event_intel.c"
1333
1334 static int __cpuinit
1335 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1336 {
1337 unsigned int cpu = (long)hcpu;
1338
1339 switch (action & ~CPU_TASKS_FROZEN) {
1340 case CPU_UP_PREPARE:
1341 if (x86_pmu.cpu_prepare)
1342 x86_pmu.cpu_prepare(cpu);
1343 break;
1344
1345 case CPU_STARTING:
1346 if (x86_pmu.cpu_starting)
1347 x86_pmu.cpu_starting(cpu);
1348 break;
1349
1350 case CPU_DYING:
1351 if (x86_pmu.cpu_dying)
1352 x86_pmu.cpu_dying(cpu);
1353 break;
1354
1355 case CPU_DEAD:
1356 if (x86_pmu.cpu_dead)
1357 x86_pmu.cpu_dead(cpu);
1358 break;
1359
1360 default:
1361 break;
1362 }
1363
1364 return NOTIFY_OK;
1365 }
1366
1367 static void __init pmu_check_apic(void)
1368 {
1369 if (cpu_has_apic)
1370 return;
1371
1372 x86_pmu.apic = 0;
1373 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1374 pr_info("no hardware sampling interrupt available.\n");
1375 }
1376
1377 void __init init_hw_perf_events(void)
1378 {
1379 struct event_constraint *c;
1380 int err;
1381
1382 pr_info("Performance Events: ");
1383
1384 switch (boot_cpu_data.x86_vendor) {
1385 case X86_VENDOR_INTEL:
1386 err = intel_pmu_init();
1387 break;
1388 case X86_VENDOR_AMD:
1389 err = amd_pmu_init();
1390 break;
1391 default:
1392 return;
1393 }
1394 if (err != 0) {
1395 pr_cont("no PMU driver, software events only.\n");
1396 return;
1397 }
1398
1399 pmu_check_apic();
1400
1401 pr_cont("%s PMU driver.\n", x86_pmu.name);
1402
1403 if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1404 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1405 x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1406 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1407 }
1408 perf_event_mask = (1 << x86_pmu.num_events) - 1;
1409 perf_max_events = x86_pmu.num_events;
1410
1411 if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1412 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1413 x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1414 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1415 }
1416
1417 perf_event_mask |=
1418 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1419 x86_pmu.intel_ctrl = perf_event_mask;
1420
1421 perf_events_lapic_init();
1422 register_die_notifier(&perf_event_nmi_notifier);
1423
1424 unconstrained = (struct event_constraint)
1425 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1426 0, x86_pmu.num_events);
1427
1428 if (x86_pmu.event_constraints) {
1429 for_each_event_constraint(c, x86_pmu.event_constraints) {
1430 if (c->cmask != INTEL_ARCH_FIXED_MASK)
1431 continue;
1432
1433 c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1434 c->weight += x86_pmu.num_events;
1435 }
1436 }
1437
1438 pr_info("... version: %d\n", x86_pmu.version);
1439 pr_info("... bit width: %d\n", x86_pmu.event_bits);
1440 pr_info("... generic registers: %d\n", x86_pmu.num_events);
1441 pr_info("... value mask: %016Lx\n", x86_pmu.event_mask);
1442 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1443 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_events_fixed);
1444 pr_info("... event mask: %016Lx\n", perf_event_mask);
1445
1446 perf_cpu_notifier(x86_pmu_notifier);
1447 }
1448
1449 static inline void x86_pmu_read(struct perf_event *event)
1450 {
1451 x86_perf_event_update(event);
1452 }
1453
1454 static const struct pmu pmu = {
1455 .enable = x86_pmu_enable,
1456 .disable = x86_pmu_disable,
1457 .start = x86_pmu_start,
1458 .stop = x86_pmu_stop,
1459 .read = x86_pmu_read,
1460 .unthrottle = x86_pmu_unthrottle,
1461 };
1462
1463 /*
1464 * validate a single event group
1465 *
1466 * validation include:
1467 * - check events are compatible which each other
1468 * - events do not compete for the same counter
1469 * - number of events <= number of counters
1470 *
1471 * validation ensures the group can be loaded onto the
1472 * PMU if it was the only group available.
1473 */
1474 static int validate_group(struct perf_event *event)
1475 {
1476 struct perf_event *leader = event->group_leader;
1477 struct cpu_hw_events *fake_cpuc;
1478 int ret, n;
1479
1480 ret = -ENOMEM;
1481 fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1482 if (!fake_cpuc)
1483 goto out;
1484
1485 /*
1486 * the event is not yet connected with its
1487 * siblings therefore we must first collect
1488 * existing siblings, then add the new event
1489 * before we can simulate the scheduling
1490 */
1491 ret = -ENOSPC;
1492 n = collect_events(fake_cpuc, leader, true);
1493 if (n < 0)
1494 goto out_free;
1495
1496 fake_cpuc->n_events = n;
1497 n = collect_events(fake_cpuc, event, false);
1498 if (n < 0)
1499 goto out_free;
1500
1501 fake_cpuc->n_events = n;
1502
1503 ret = x86_schedule_events(fake_cpuc, n, NULL);
1504
1505 out_free:
1506 kfree(fake_cpuc);
1507 out:
1508 return ret;
1509 }
1510
1511 const struct pmu *hw_perf_event_init(struct perf_event *event)
1512 {
1513 const struct pmu *tmp;
1514 int err;
1515
1516 err = __hw_perf_event_init(event);
1517 if (!err) {
1518 /*
1519 * we temporarily connect event to its pmu
1520 * such that validate_group() can classify
1521 * it as an x86 event using is_x86_event()
1522 */
1523 tmp = event->pmu;
1524 event->pmu = &pmu;
1525
1526 if (event->group_leader != event)
1527 err = validate_group(event);
1528
1529 event->pmu = tmp;
1530 }
1531 if (err) {
1532 if (event->destroy)
1533 event->destroy(event);
1534 return ERR_PTR(err);
1535 }
1536
1537 return &pmu;
1538 }
1539
1540 /*
1541 * callchain support
1542 */
1543
1544 static inline
1545 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1546 {
1547 if (entry->nr < PERF_MAX_STACK_DEPTH)
1548 entry->ip[entry->nr++] = ip;
1549 }
1550
1551 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1552 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1553
1554
1555 static void
1556 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1557 {
1558 /* Ignore warnings */
1559 }
1560
1561 static void backtrace_warning(void *data, char *msg)
1562 {
1563 /* Ignore warnings */
1564 }
1565
1566 static int backtrace_stack(void *data, char *name)
1567 {
1568 return 0;
1569 }
1570
1571 static void backtrace_address(void *data, unsigned long addr, int reliable)
1572 {
1573 struct perf_callchain_entry *entry = data;
1574
1575 if (reliable)
1576 callchain_store(entry, addr);
1577 }
1578
1579 static const struct stacktrace_ops backtrace_ops = {
1580 .warning = backtrace_warning,
1581 .warning_symbol = backtrace_warning_symbol,
1582 .stack = backtrace_stack,
1583 .address = backtrace_address,
1584 .walk_stack = print_context_stack_bp,
1585 };
1586
1587 #include "../dumpstack.h"
1588
1589 static void
1590 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1591 {
1592 callchain_store(entry, PERF_CONTEXT_KERNEL);
1593 callchain_store(entry, regs->ip);
1594
1595 dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1596 }
1597
1598 /*
1599 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1600 */
1601 static unsigned long
1602 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1603 {
1604 unsigned long offset, addr = (unsigned long)from;
1605 int type = in_nmi() ? KM_NMI : KM_IRQ0;
1606 unsigned long size, len = 0;
1607 struct page *page;
1608 void *map;
1609 int ret;
1610
1611 do {
1612 ret = __get_user_pages_fast(addr, 1, 0, &page);
1613 if (!ret)
1614 break;
1615
1616 offset = addr & (PAGE_SIZE - 1);
1617 size = min(PAGE_SIZE - offset, n - len);
1618
1619 map = kmap_atomic(page, type);
1620 memcpy(to, map+offset, size);
1621 kunmap_atomic(map, type);
1622 put_page(page);
1623
1624 len += size;
1625 to += size;
1626 addr += size;
1627
1628 } while (len < n);
1629
1630 return len;
1631 }
1632
1633 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1634 {
1635 unsigned long bytes;
1636
1637 bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1638
1639 return bytes == sizeof(*frame);
1640 }
1641
1642 static void
1643 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1644 {
1645 struct stack_frame frame;
1646 const void __user *fp;
1647
1648 if (!user_mode(regs))
1649 regs = task_pt_regs(current);
1650
1651 fp = (void __user *)regs->bp;
1652
1653 callchain_store(entry, PERF_CONTEXT_USER);
1654 callchain_store(entry, regs->ip);
1655
1656 while (entry->nr < PERF_MAX_STACK_DEPTH) {
1657 frame.next_frame = NULL;
1658 frame.return_address = 0;
1659
1660 if (!copy_stack_frame(fp, &frame))
1661 break;
1662
1663 if ((unsigned long)fp < regs->sp)
1664 break;
1665
1666 callchain_store(entry, frame.return_address);
1667 fp = frame.next_frame;
1668 }
1669 }
1670
1671 static void
1672 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1673 {
1674 int is_user;
1675
1676 if (!regs)
1677 return;
1678
1679 is_user = user_mode(regs);
1680
1681 if (is_user && current->state != TASK_RUNNING)
1682 return;
1683
1684 if (!is_user)
1685 perf_callchain_kernel(regs, entry);
1686
1687 if (current->mm)
1688 perf_callchain_user(regs, entry);
1689 }
1690
1691 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1692 {
1693 struct perf_callchain_entry *entry;
1694
1695 if (in_nmi())
1696 entry = &__get_cpu_var(pmc_nmi_entry);
1697 else
1698 entry = &__get_cpu_var(pmc_irq_entry);
1699
1700 entry->nr = 0;
1701
1702 perf_do_callchain(regs, entry);
1703
1704 return entry;
1705 }
Linux kernel - Deliverables
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