2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
29 #include <asm/stacktrace.h>
32 static u64 perf_event_mask __read_mostly
;
34 /* The maximal number of PEBS events: */
35 #define MAX_PEBS_EVENTS 4
37 /* The size of a BTS record in bytes: */
38 #define BTS_RECORD_SIZE 24
40 /* The size of a per-cpu BTS buffer in bytes: */
41 #define BTS_BUFFER_SIZE (BTS_RECORD_SIZE * 2048)
43 /* The BTS overflow threshold in bytes from the end of the buffer: */
44 #define BTS_OVFL_TH (BTS_RECORD_SIZE * 128)
48 * Bits in the debugctlmsr controlling branch tracing.
50 #define X86_DEBUGCTL_TR (1 << 6)
51 #define X86_DEBUGCTL_BTS (1 << 7)
52 #define X86_DEBUGCTL_BTINT (1 << 8)
53 #define X86_DEBUGCTL_BTS_OFF_OS (1 << 9)
54 #define X86_DEBUGCTL_BTS_OFF_USR (1 << 10)
57 * A debug store configuration.
59 * We only support architectures that use 64bit fields.
64 u64 bts_absolute_maximum
;
65 u64 bts_interrupt_threshold
;
68 u64 pebs_absolute_maximum
;
69 u64 pebs_interrupt_threshold
;
70 u64 pebs_event_reset
[MAX_PEBS_EVENTS
];
73 struct event_constraint
{
75 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
84 int nb_id
; /* NorthBridge id */
85 int refcnt
; /* reference count */
86 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
87 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
90 struct cpu_hw_events
{
91 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
92 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
93 unsigned long interrupts
;
95 struct debug_store
*ds
;
99 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
100 u64 tags
[X86_PMC_IDX_MAX
];
101 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
102 struct amd_nb
*amd_nb
;
105 #define __EVENT_CONSTRAINT(c, n, m, w) {\
106 { .idxmsk64 = (n) }, \
112 #define EVENT_CONSTRAINT(c, n, m) \
113 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
115 #define INTEL_EVENT_CONSTRAINT(c, n) \
116 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
118 #define FIXED_EVENT_CONSTRAINT(c, n) \
119 EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
121 #define EVENT_CONSTRAINT_END \
122 EVENT_CONSTRAINT(0, 0, 0)
124 #define for_each_event_constraint(e, c) \
125 for ((e) = (c); (e)->cmask; (e)++)
128 * struct x86_pmu - generic x86 pmu
133 int (*handle_irq
)(struct pt_regs
*);
134 void (*disable_all
)(void);
135 void (*enable_all
)(void);
136 void (*enable
)(struct hw_perf_event
*, int);
137 void (*disable
)(struct hw_perf_event
*, int);
140 u64 (*event_map
)(int);
141 u64 (*raw_event
)(u64
);
144 int num_events_fixed
;
150 void (*enable_bts
)(u64 config
);
151 void (*disable_bts
)(void);
153 struct event_constraint
*
154 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
155 struct perf_event
*event
);
157 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
158 struct perf_event
*event
);
159 struct event_constraint
*event_constraints
;
162 static struct x86_pmu x86_pmu __read_mostly
;
164 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
168 static int x86_perf_event_set_period(struct perf_event
*event
,
169 struct hw_perf_event
*hwc
, int idx
);
172 * Generalized hw caching related hw_event table, filled
173 * in on a per model basis. A value of 0 means
174 * 'not supported', -1 means 'hw_event makes no sense on
175 * this CPU', any other value means the raw hw_event
179 #define C(x) PERF_COUNT_HW_CACHE_##x
181 static u64 __read_mostly hw_cache_event_ids
182 [PERF_COUNT_HW_CACHE_MAX
]
183 [PERF_COUNT_HW_CACHE_OP_MAX
]
184 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
187 * Propagate event elapsed time into the generic event.
188 * Can only be executed on the CPU where the event is active.
189 * Returns the delta events processed.
192 x86_perf_event_update(struct perf_event
*event
,
193 struct hw_perf_event
*hwc
, int idx
)
195 int shift
= 64 - x86_pmu
.event_bits
;
196 u64 prev_raw_count
, new_raw_count
;
199 if (idx
== X86_PMC_IDX_FIXED_BTS
)
203 * Careful: an NMI might modify the previous event value.
205 * Our tactic to handle this is to first atomically read and
206 * exchange a new raw count - then add that new-prev delta
207 * count to the generic event atomically:
210 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
211 rdmsrl(hwc
->event_base
+ idx
, new_raw_count
);
213 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
214 new_raw_count
) != prev_raw_count
)
218 * Now we have the new raw value and have updated the prev
219 * timestamp already. We can now calculate the elapsed delta
220 * (event-)time and add that to the generic event.
222 * Careful, not all hw sign-extends above the physical width
225 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
228 atomic64_add(delta
, &event
->count
);
229 atomic64_sub(delta
, &hwc
->period_left
);
231 return new_raw_count
;
234 static atomic_t active_events
;
235 static DEFINE_MUTEX(pmc_reserve_mutex
);
237 static bool reserve_pmc_hardware(void)
239 #ifdef CONFIG_X86_LOCAL_APIC
242 if (nmi_watchdog
== NMI_LOCAL_APIC
)
243 disable_lapic_nmi_watchdog();
245 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
246 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
250 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
251 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
258 #ifdef CONFIG_X86_LOCAL_APIC
260 for (i
--; i
>= 0; i
--)
261 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
263 i
= x86_pmu
.num_events
;
266 for (i
--; i
>= 0; i
--)
267 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
269 if (nmi_watchdog
== NMI_LOCAL_APIC
)
270 enable_lapic_nmi_watchdog();
276 static void release_pmc_hardware(void)
278 #ifdef CONFIG_X86_LOCAL_APIC
281 for (i
= 0; i
< x86_pmu
.num_events
; i
++) {
282 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
283 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
286 if (nmi_watchdog
== NMI_LOCAL_APIC
)
287 enable_lapic_nmi_watchdog();
291 static inline bool bts_available(void)
293 return x86_pmu
.enable_bts
!= NULL
;
296 static inline void init_debug_store_on_cpu(int cpu
)
298 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
303 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
,
304 (u32
)((u64
)(unsigned long)ds
),
305 (u32
)((u64
)(unsigned long)ds
>> 32));
308 static inline void fini_debug_store_on_cpu(int cpu
)
310 if (!per_cpu(cpu_hw_events
, cpu
).ds
)
313 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
, 0, 0);
316 static void release_bts_hardware(void)
320 if (!bts_available())
325 for_each_online_cpu(cpu
)
326 fini_debug_store_on_cpu(cpu
);
328 for_each_possible_cpu(cpu
) {
329 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
334 per_cpu(cpu_hw_events
, cpu
).ds
= NULL
;
336 kfree((void *)(unsigned long)ds
->bts_buffer_base
);
343 static int reserve_bts_hardware(void)
347 if (!bts_available())
352 for_each_possible_cpu(cpu
) {
353 struct debug_store
*ds
;
357 buffer
= kzalloc(BTS_BUFFER_SIZE
, GFP_KERNEL
);
358 if (unlikely(!buffer
))
361 ds
= kzalloc(sizeof(*ds
), GFP_KERNEL
);
367 ds
->bts_buffer_base
= (u64
)(unsigned long)buffer
;
368 ds
->bts_index
= ds
->bts_buffer_base
;
369 ds
->bts_absolute_maximum
=
370 ds
->bts_buffer_base
+ BTS_BUFFER_SIZE
;
371 ds
->bts_interrupt_threshold
=
372 ds
->bts_absolute_maximum
- BTS_OVFL_TH
;
374 per_cpu(cpu_hw_events
, cpu
).ds
= ds
;
379 release_bts_hardware();
381 for_each_online_cpu(cpu
)
382 init_debug_store_on_cpu(cpu
);
390 static void hw_perf_event_destroy(struct perf_event
*event
)
392 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
393 release_pmc_hardware();
394 release_bts_hardware();
395 mutex_unlock(&pmc_reserve_mutex
);
399 static inline int x86_pmu_initialized(void)
401 return x86_pmu
.handle_irq
!= NULL
;
405 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event_attr
*attr
)
407 unsigned int cache_type
, cache_op
, cache_result
;
410 config
= attr
->config
;
412 cache_type
= (config
>> 0) & 0xff;
413 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
416 cache_op
= (config
>> 8) & 0xff;
417 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
420 cache_result
= (config
>> 16) & 0xff;
421 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
424 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
438 * Setup the hardware configuration for a given attr_type
440 static int __hw_perf_event_init(struct perf_event
*event
)
442 struct perf_event_attr
*attr
= &event
->attr
;
443 struct hw_perf_event
*hwc
= &event
->hw
;
447 if (!x86_pmu_initialized())
451 if (!atomic_inc_not_zero(&active_events
)) {
452 mutex_lock(&pmc_reserve_mutex
);
453 if (atomic_read(&active_events
) == 0) {
454 if (!reserve_pmc_hardware())
457 err
= reserve_bts_hardware();
460 atomic_inc(&active_events
);
461 mutex_unlock(&pmc_reserve_mutex
);
466 event
->destroy
= hw_perf_event_destroy
;
470 * (keep 'enabled' bit clear for now)
472 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
476 hwc
->last_tag
= ~0ULL;
479 * Count user and OS events unless requested not to.
481 if (!attr
->exclude_user
)
482 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
483 if (!attr
->exclude_kernel
)
484 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
486 if (!hwc
->sample_period
) {
487 hwc
->sample_period
= x86_pmu
.max_period
;
488 hwc
->last_period
= hwc
->sample_period
;
489 atomic64_set(&hwc
->period_left
, hwc
->sample_period
);
492 * If we have a PMU initialized but no APIC
493 * interrupts, we cannot sample hardware
494 * events (user-space has to fall back and
495 * sample via a hrtimer based software event):
502 * Raw hw_event type provide the config in the hw_event structure
504 if (attr
->type
== PERF_TYPE_RAW
) {
505 hwc
->config
|= x86_pmu
.raw_event(attr
->config
);
506 if ((hwc
->config
& ARCH_PERFMON_EVENTSEL_ANY
) &&
507 perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN
))
512 if (attr
->type
== PERF_TYPE_HW_CACHE
)
513 return set_ext_hw_attr(hwc
, attr
);
515 if (attr
->config
>= x86_pmu
.max_events
)
521 config
= x86_pmu
.event_map(attr
->config
);
532 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
533 (hwc
->sample_period
== 1)) {
534 /* BTS is not supported by this architecture. */
535 if (!bts_available())
538 /* BTS is currently only allowed for user-mode. */
539 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
543 hwc
->config
|= config
;
548 static void x86_pmu_disable_all(void)
550 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
553 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
556 if (!test_bit(idx
, cpuc
->active_mask
))
558 rdmsrl(x86_pmu
.eventsel
+ idx
, val
);
559 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
561 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
562 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
566 void hw_perf_disable(void)
568 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
570 if (!x86_pmu_initialized())
580 x86_pmu
.disable_all();
583 static void x86_pmu_enable_all(void)
585 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
588 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
589 struct perf_event
*event
= cpuc
->events
[idx
];
592 if (!test_bit(idx
, cpuc
->active_mask
))
595 val
= event
->hw
.config
;
596 val
|= ARCH_PERFMON_EVENTSEL_ENABLE
;
597 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
601 static const struct pmu pmu
;
603 static inline int is_x86_event(struct perf_event
*event
)
605 return event
->pmu
== &pmu
;
608 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
610 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
611 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
612 int i
, j
, w
, wmax
, num
= 0;
613 struct hw_perf_event
*hwc
;
615 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
617 for (i
= 0; i
< n
; i
++) {
618 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
623 * fastpath, try to reuse previous register
625 for (i
= 0; i
< n
; i
++) {
626 hwc
= &cpuc
->event_list
[i
]->hw
;
633 /* constraint still honored */
634 if (!test_bit(hwc
->idx
, c
->idxmsk
))
637 /* not already used */
638 if (test_bit(hwc
->idx
, used_mask
))
641 set_bit(hwc
->idx
, used_mask
);
643 assign
[i
] = hwc
->idx
;
652 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
655 * weight = number of possible counters
657 * 1 = most constrained, only works on one counter
658 * wmax = least constrained, works on any counter
660 * assign events to counters starting with most
661 * constrained events.
663 wmax
= x86_pmu
.num_events
;
666 * when fixed event counters are present,
667 * wmax is incremented by 1 to account
668 * for one more choice
670 if (x86_pmu
.num_events_fixed
)
673 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
675 for (i
= 0; num
&& i
< n
; i
++) {
677 hwc
= &cpuc
->event_list
[i
]->hw
;
682 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
683 if (!test_bit(j
, used_mask
))
687 if (j
== X86_PMC_IDX_MAX
)
690 set_bit(j
, used_mask
);
699 * scheduling failed or is just a simulation,
700 * free resources if necessary
702 if (!assign
|| num
) {
703 for (i
= 0; i
< n
; i
++) {
704 if (x86_pmu
.put_event_constraints
)
705 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
708 return num
? -ENOSPC
: 0;
712 * dogrp: true if must collect siblings events (group)
713 * returns total number of events and error code
715 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
717 struct perf_event
*event
;
720 max_count
= x86_pmu
.num_events
+ x86_pmu
.num_events_fixed
;
722 /* current number of events already accepted */
725 if (is_x86_event(leader
)) {
728 cpuc
->event_list
[n
] = leader
;
734 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
735 if (!is_x86_event(event
) ||
736 event
->state
<= PERF_EVENT_STATE_OFF
)
742 cpuc
->event_list
[n
] = event
;
748 static inline void x86_assign_hw_event(struct perf_event
*event
,
749 struct cpu_hw_events
*cpuc
, int i
)
751 struct hw_perf_event
*hwc
= &event
->hw
;
753 hwc
->idx
= cpuc
->assign
[i
];
754 hwc
->last_cpu
= smp_processor_id();
755 hwc
->last_tag
= ++cpuc
->tags
[i
];
757 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
758 hwc
->config_base
= 0;
760 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
761 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
763 * We set it so that event_base + idx in wrmsr/rdmsr maps to
764 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
767 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
769 hwc
->config_base
= x86_pmu
.eventsel
;
770 hwc
->event_base
= x86_pmu
.perfctr
;
774 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
775 struct cpu_hw_events
*cpuc
,
778 return hwc
->idx
== cpuc
->assign
[i
] &&
779 hwc
->last_cpu
== smp_processor_id() &&
780 hwc
->last_tag
== cpuc
->tags
[i
];
783 static void x86_pmu_stop(struct perf_event
*event
);
785 void hw_perf_enable(void)
787 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
788 struct perf_event
*event
;
789 struct hw_perf_event
*hwc
;
792 if (!x86_pmu_initialized())
800 * apply assignment obtained either from
801 * hw_perf_group_sched_in() or x86_pmu_enable()
803 * step1: save events moving to new counters
804 * step2: reprogram moved events into new counters
806 for (i
= 0; i
< cpuc
->n_events
; i
++) {
808 event
= cpuc
->event_list
[i
];
812 * we can avoid reprogramming counter if:
813 * - assigned same counter as last time
814 * - running on same CPU as last time
815 * - no other event has used the counter since
817 if (hwc
->idx
== -1 ||
818 match_prev_assignment(hwc
, cpuc
, i
))
826 for (i
= 0; i
< cpuc
->n_events
; i
++) {
828 event
= cpuc
->event_list
[i
];
831 if (hwc
->idx
== -1) {
832 x86_assign_hw_event(event
, cpuc
, i
);
833 x86_perf_event_set_period(event
, hwc
, hwc
->idx
);
836 * need to mark as active because x86_pmu_disable()
837 * clear active_mask and events[] yet it preserves
840 set_bit(hwc
->idx
, cpuc
->active_mask
);
841 cpuc
->events
[hwc
->idx
] = event
;
843 x86_pmu
.enable(hwc
, hwc
->idx
);
844 perf_event_update_userpage(event
);
847 perf_events_lapic_init();
853 x86_pmu
.enable_all();
856 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
, int idx
)
858 (void)checking_wrmsrl(hwc
->config_base
+ idx
,
859 hwc
->config
| ARCH_PERFMON_EVENTSEL_ENABLE
);
862 static inline void x86_pmu_disable_event(struct hw_perf_event
*hwc
, int idx
)
864 (void)checking_wrmsrl(hwc
->config_base
+ idx
, hwc
->config
);
867 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
870 * Set the next IRQ period, based on the hwc->period_left value.
871 * To be called with the event disabled in hw:
874 x86_perf_event_set_period(struct perf_event
*event
,
875 struct hw_perf_event
*hwc
, int idx
)
877 s64 left
= atomic64_read(&hwc
->period_left
);
878 s64 period
= hwc
->sample_period
;
881 if (idx
== X86_PMC_IDX_FIXED_BTS
)
885 * If we are way outside a reasonable range then just skip forward:
887 if (unlikely(left
<= -period
)) {
889 atomic64_set(&hwc
->period_left
, left
);
890 hwc
->last_period
= period
;
894 if (unlikely(left
<= 0)) {
896 atomic64_set(&hwc
->period_left
, left
);
897 hwc
->last_period
= period
;
901 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
903 if (unlikely(left
< 2))
906 if (left
> x86_pmu
.max_period
)
907 left
= x86_pmu
.max_period
;
909 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
912 * The hw event starts counting from this event offset,
913 * mark it to be able to extra future deltas:
915 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
917 err
= checking_wrmsrl(hwc
->event_base
+ idx
,
918 (u64
)(-left
) & x86_pmu
.event_mask
);
920 perf_event_update_userpage(event
);
925 static void x86_pmu_enable_event(struct hw_perf_event
*hwc
, int idx
)
927 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
929 __x86_pmu_enable_event(hwc
, idx
);
933 * activate a single event
935 * The event is added to the group of enabled events
936 * but only if it can be scehduled with existing events.
938 * Called with PMU disabled. If successful and return value 1,
939 * then guaranteed to call perf_enable() and hw_perf_enable()
941 static int x86_pmu_enable(struct perf_event
*event
)
943 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
944 struct hw_perf_event
*hwc
;
945 int assign
[X86_PMC_IDX_MAX
];
951 n
= collect_events(cpuc
, event
, false);
955 ret
= x86_schedule_events(cpuc
, n
, assign
);
959 * copy new assignment, now we know it is possible
960 * will be used by hw_perf_enable()
962 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
965 cpuc
->n_added
= n
- n0
;
970 static int x86_pmu_start(struct perf_event
*event
)
972 struct hw_perf_event
*hwc
= &event
->hw
;
977 x86_perf_event_set_period(event
, hwc
, hwc
->idx
);
978 x86_pmu
.enable(hwc
, hwc
->idx
);
983 static void x86_pmu_unthrottle(struct perf_event
*event
)
985 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
986 struct hw_perf_event
*hwc
= &event
->hw
;
988 if (WARN_ON_ONCE(hwc
->idx
>= X86_PMC_IDX_MAX
||
989 cpuc
->events
[hwc
->idx
] != event
))
992 x86_pmu
.enable(hwc
, hwc
->idx
);
995 void perf_event_print_debug(void)
997 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
998 struct cpu_hw_events
*cpuc
;
1002 if (!x86_pmu
.num_events
)
1005 local_irq_save(flags
);
1007 cpu
= smp_processor_id();
1008 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1010 if (x86_pmu
.version
>= 2) {
1011 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1012 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1013 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1014 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1017 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1018 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1019 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1020 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1022 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1024 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
1025 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1026 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1028 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1030 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1031 cpu
, idx
, pmc_ctrl
);
1032 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1033 cpu
, idx
, pmc_count
);
1034 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1035 cpu
, idx
, prev_left
);
1037 for (idx
= 0; idx
< x86_pmu
.num_events_fixed
; idx
++) {
1038 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1040 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1041 cpu
, idx
, pmc_count
);
1043 local_irq_restore(flags
);
1046 static void x86_pmu_stop(struct perf_event
*event
)
1048 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1049 struct hw_perf_event
*hwc
= &event
->hw
;
1053 * Must be done before we disable, otherwise the nmi handler
1054 * could reenable again:
1056 clear_bit(idx
, cpuc
->active_mask
);
1057 x86_pmu
.disable(hwc
, idx
);
1060 * Drain the remaining delta count out of a event
1061 * that we are disabling:
1063 x86_perf_event_update(event
, hwc
, idx
);
1065 cpuc
->events
[idx
] = NULL
;
1068 static void x86_pmu_disable(struct perf_event
*event
)
1070 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1073 x86_pmu_stop(event
);
1075 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1076 if (event
== cpuc
->event_list
[i
]) {
1078 if (x86_pmu
.put_event_constraints
)
1079 x86_pmu
.put_event_constraints(cpuc
, event
);
1081 while (++i
< cpuc
->n_events
)
1082 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1088 perf_event_update_userpage(event
);
1091 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1093 struct perf_sample_data data
;
1094 struct cpu_hw_events
*cpuc
;
1095 struct perf_event
*event
;
1096 struct hw_perf_event
*hwc
;
1097 int idx
, handled
= 0;
1103 cpuc
= &__get_cpu_var(cpu_hw_events
);
1105 for (idx
= 0; idx
< x86_pmu
.num_events
; idx
++) {
1106 if (!test_bit(idx
, cpuc
->active_mask
))
1109 event
= cpuc
->events
[idx
];
1112 val
= x86_perf_event_update(event
, hwc
, idx
);
1113 if (val
& (1ULL << (x86_pmu
.event_bits
- 1)))
1120 data
.period
= event
->hw
.last_period
;
1122 if (!x86_perf_event_set_period(event
, hwc
, idx
))
1125 if (perf_event_overflow(event
, 1, &data
, regs
))
1126 x86_pmu
.disable(hwc
, idx
);
1130 inc_irq_stat(apic_perf_irqs
);
1135 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
1139 inc_irq_stat(apic_pending_irqs
);
1140 perf_event_do_pending();
1144 void set_perf_event_pending(void)
1146 #ifdef CONFIG_X86_LOCAL_APIC
1147 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1150 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
1154 void perf_events_lapic_init(void)
1156 #ifdef CONFIG_X86_LOCAL_APIC
1157 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1161 * Always use NMI for PMU
1163 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1167 static int __kprobes
1168 perf_event_nmi_handler(struct notifier_block
*self
,
1169 unsigned long cmd
, void *__args
)
1171 struct die_args
*args
= __args
;
1172 struct pt_regs
*regs
;
1174 if (!atomic_read(&active_events
))
1188 #ifdef CONFIG_X86_LOCAL_APIC
1189 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1192 * Can't rely on the handled return value to say it was our NMI, two
1193 * events could trigger 'simultaneously' raising two back-to-back NMIs.
1195 * If the first NMI handles both, the latter will be empty and daze
1198 x86_pmu
.handle_irq(regs
);
1203 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1204 .notifier_call
= perf_event_nmi_handler
,
1209 static struct event_constraint unconstrained
;
1210 static struct event_constraint emptyconstraint
;
1212 static struct event_constraint
*
1213 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1215 struct event_constraint
*c
;
1217 if (x86_pmu
.event_constraints
) {
1218 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1219 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1224 return &unconstrained
;
1227 static int x86_event_sched_in(struct perf_event
*event
,
1228 struct perf_cpu_context
*cpuctx
)
1232 event
->state
= PERF_EVENT_STATE_ACTIVE
;
1233 event
->oncpu
= smp_processor_id();
1234 event
->tstamp_running
+= event
->ctx
->time
- event
->tstamp_stopped
;
1236 if (!is_x86_event(event
))
1237 ret
= event
->pmu
->enable(event
);
1239 if (!ret
&& !is_software_event(event
))
1240 cpuctx
->active_oncpu
++;
1242 if (!ret
&& event
->attr
.exclusive
)
1243 cpuctx
->exclusive
= 1;
1248 static void x86_event_sched_out(struct perf_event
*event
,
1249 struct perf_cpu_context
*cpuctx
)
1251 event
->state
= PERF_EVENT_STATE_INACTIVE
;
1254 if (!is_x86_event(event
))
1255 event
->pmu
->disable(event
);
1257 event
->tstamp_running
-= event
->ctx
->time
- event
->tstamp_stopped
;
1259 if (!is_software_event(event
))
1260 cpuctx
->active_oncpu
--;
1262 if (event
->attr
.exclusive
|| !cpuctx
->active_oncpu
)
1263 cpuctx
->exclusive
= 0;
1267 * Called to enable a whole group of events.
1268 * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1269 * Assumes the caller has disabled interrupts and has
1270 * frozen the PMU with hw_perf_save_disable.
1272 * called with PMU disabled. If successful and return value 1,
1273 * then guaranteed to call perf_enable() and hw_perf_enable()
1275 int hw_perf_group_sched_in(struct perf_event
*leader
,
1276 struct perf_cpu_context
*cpuctx
,
1277 struct perf_event_context
*ctx
)
1279 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1280 struct perf_event
*sub
;
1281 int assign
[X86_PMC_IDX_MAX
];
1284 /* n0 = total number of events */
1285 n0
= collect_events(cpuc
, leader
, true);
1289 ret
= x86_schedule_events(cpuc
, n0
, assign
);
1293 ret
= x86_event_sched_in(leader
, cpuctx
);
1298 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1299 if (sub
->state
> PERF_EVENT_STATE_OFF
) {
1300 ret
= x86_event_sched_in(sub
, cpuctx
);
1307 * copy new assignment, now we know it is possible
1308 * will be used by hw_perf_enable()
1310 memcpy(cpuc
->assign
, assign
, n0
*sizeof(int));
1312 cpuc
->n_events
= n0
;
1314 ctx
->nr_active
+= n1
;
1317 * 1 means successful and events are active
1318 * This is not quite true because we defer
1319 * actual activation until hw_perf_enable() but
1320 * this way we* ensure caller won't try to enable
1325 x86_event_sched_out(leader
, cpuctx
);
1327 list_for_each_entry(sub
, &leader
->sibling_list
, group_entry
) {
1328 if (sub
->state
== PERF_EVENT_STATE_ACTIVE
) {
1329 x86_event_sched_out(sub
, cpuctx
);
1337 #include "perf_event_amd.c"
1338 #include "perf_event_p6.c"
1339 #include "perf_event_intel.c"
1341 static void __init
pmu_check_apic(void)
1347 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1348 pr_info("no hardware sampling interrupt available.\n");
1351 void __init
init_hw_perf_events(void)
1353 struct event_constraint
*c
;
1356 pr_info("Performance Events: ");
1358 switch (boot_cpu_data
.x86_vendor
) {
1359 case X86_VENDOR_INTEL
:
1360 err
= intel_pmu_init();
1362 case X86_VENDOR_AMD
:
1363 err
= amd_pmu_init();
1369 pr_cont("no PMU driver, software events only.\n");
1375 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1377 if (x86_pmu
.num_events
> X86_PMC_MAX_GENERIC
) {
1378 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1379 x86_pmu
.num_events
, X86_PMC_MAX_GENERIC
);
1380 x86_pmu
.num_events
= X86_PMC_MAX_GENERIC
;
1382 perf_event_mask
= (1 << x86_pmu
.num_events
) - 1;
1383 perf_max_events
= x86_pmu
.num_events
;
1385 if (x86_pmu
.num_events_fixed
> X86_PMC_MAX_FIXED
) {
1386 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1387 x86_pmu
.num_events_fixed
, X86_PMC_MAX_FIXED
);
1388 x86_pmu
.num_events_fixed
= X86_PMC_MAX_FIXED
;
1392 ((1LL << x86_pmu
.num_events_fixed
)-1) << X86_PMC_IDX_FIXED
;
1393 x86_pmu
.intel_ctrl
= perf_event_mask
;
1395 perf_events_lapic_init();
1396 register_die_notifier(&perf_event_nmi_notifier
);
1398 unconstrained
= (struct event_constraint
)
1399 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_events
) - 1,
1400 0, x86_pmu
.num_events
);
1402 if (x86_pmu
.event_constraints
) {
1403 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1404 if (c
->cmask
!= INTEL_ARCH_FIXED_MASK
)
1407 c
->idxmsk64
|= (1ULL << x86_pmu
.num_events
) - 1;
1408 c
->weight
+= x86_pmu
.num_events
;
1412 pr_info("... version: %d\n", x86_pmu
.version
);
1413 pr_info("... bit width: %d\n", x86_pmu
.event_bits
);
1414 pr_info("... generic registers: %d\n", x86_pmu
.num_events
);
1415 pr_info("... value mask: %016Lx\n", x86_pmu
.event_mask
);
1416 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1417 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_events_fixed
);
1418 pr_info("... event mask: %016Lx\n", perf_event_mask
);
1421 static inline void x86_pmu_read(struct perf_event
*event
)
1423 x86_perf_event_update(event
, &event
->hw
, event
->hw
.idx
);
1426 static const struct pmu pmu
= {
1427 .enable
= x86_pmu_enable
,
1428 .disable
= x86_pmu_disable
,
1429 .start
= x86_pmu_start
,
1430 .stop
= x86_pmu_stop
,
1431 .read
= x86_pmu_read
,
1432 .unthrottle
= x86_pmu_unthrottle
,
1436 * validate a single event group
1438 * validation include:
1439 * - check events are compatible which each other
1440 * - events do not compete for the same counter
1441 * - number of events <= number of counters
1443 * validation ensures the group can be loaded onto the
1444 * PMU if it was the only group available.
1446 static int validate_group(struct perf_event
*event
)
1448 struct perf_event
*leader
= event
->group_leader
;
1449 struct cpu_hw_events
*fake_cpuc
;
1453 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1458 * the event is not yet connected with its
1459 * siblings therefore we must first collect
1460 * existing siblings, then add the new event
1461 * before we can simulate the scheduling
1464 n
= collect_events(fake_cpuc
, leader
, true);
1468 fake_cpuc
->n_events
= n
;
1469 n
= collect_events(fake_cpuc
, event
, false);
1473 fake_cpuc
->n_events
= n
;
1475 ret
= x86_schedule_events(fake_cpuc
, n
, NULL
);
1483 const struct pmu
*hw_perf_event_init(struct perf_event
*event
)
1485 const struct pmu
*tmp
;
1488 err
= __hw_perf_event_init(event
);
1491 * we temporarily connect event to its pmu
1492 * such that validate_group() can classify
1493 * it as an x86 event using is_x86_event()
1498 if (event
->group_leader
!= event
)
1499 err
= validate_group(event
);
1505 event
->destroy(event
);
1506 return ERR_PTR(err
);
1517 void callchain_store(struct perf_callchain_entry
*entry
, u64 ip
)
1519 if (entry
->nr
< PERF_MAX_STACK_DEPTH
)
1520 entry
->ip
[entry
->nr
++] = ip
;
1523 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_irq_entry
);
1524 static DEFINE_PER_CPU(struct perf_callchain_entry
, pmc_nmi_entry
);
1528 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1530 /* Ignore warnings */
1533 static void backtrace_warning(void *data
, char *msg
)
1535 /* Ignore warnings */
1538 static int backtrace_stack(void *data
, char *name
)
1543 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1545 struct perf_callchain_entry
*entry
= data
;
1548 callchain_store(entry
, addr
);
1551 static const struct stacktrace_ops backtrace_ops
= {
1552 .warning
= backtrace_warning
,
1553 .warning_symbol
= backtrace_warning_symbol
,
1554 .stack
= backtrace_stack
,
1555 .address
= backtrace_address
,
1556 .walk_stack
= print_context_stack_bp
,
1559 #include "../dumpstack.h"
1562 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1564 callchain_store(entry
, PERF_CONTEXT_KERNEL
);
1565 callchain_store(entry
, regs
->ip
);
1567 dump_trace(NULL
, regs
, NULL
, regs
->bp
, &backtrace_ops
, entry
);
1571 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1573 static unsigned long
1574 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
1576 unsigned long offset
, addr
= (unsigned long)from
;
1577 int type
= in_nmi() ? KM_NMI
: KM_IRQ0
;
1578 unsigned long size
, len
= 0;
1584 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
1588 offset
= addr
& (PAGE_SIZE
- 1);
1589 size
= min(PAGE_SIZE
- offset
, n
- len
);
1591 map
= kmap_atomic(page
, type
);
1592 memcpy(to
, map
+offset
, size
);
1593 kunmap_atomic(map
, type
);
1605 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1607 unsigned long bytes
;
1609 bytes
= copy_from_user_nmi(frame
, fp
, sizeof(*frame
));
1611 return bytes
== sizeof(*frame
);
1615 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1617 struct stack_frame frame
;
1618 const void __user
*fp
;
1620 if (!user_mode(regs
))
1621 regs
= task_pt_regs(current
);
1623 fp
= (void __user
*)regs
->bp
;
1625 callchain_store(entry
, PERF_CONTEXT_USER
);
1626 callchain_store(entry
, regs
->ip
);
1628 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1629 frame
.next_frame
= NULL
;
1630 frame
.return_address
= 0;
1632 if (!copy_stack_frame(fp
, &frame
))
1635 if ((unsigned long)fp
< regs
->sp
)
1638 callchain_store(entry
, frame
.return_address
);
1639 fp
= frame
.next_frame
;
1644 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1651 is_user
= user_mode(regs
);
1653 if (is_user
&& current
->state
!= TASK_RUNNING
)
1657 perf_callchain_kernel(regs
, entry
);
1660 perf_callchain_user(regs
, entry
);
1663 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1665 struct perf_callchain_entry
*entry
;
1668 entry
= &__get_cpu_var(pmc_nmi_entry
);
1670 entry
= &__get_cpu_var(pmc_irq_entry
);
1674 perf_do_callchain(regs
, entry
);
1679 void hw_perf_event_setup_online(int cpu
)
1681 init_debug_store_on_cpu(cpu
);
1683 switch (boot_cpu_data
.x86_vendor
) {
1684 case X86_VENDOR_AMD
:
1685 amd_pmu_cpu_online(cpu
);
1692 void hw_perf_event_setup_offline(int cpu
)
1694 init_debug_store_on_cpu(cpu
);
1696 switch (boot_cpu_data
.x86_vendor
) {
1697 case X86_VENDOR_AMD
:
1698 amd_pmu_cpu_offline(cpu
);