2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/timer.h>
40 #include "perf_event.h"
42 struct x86_pmu x86_pmu __read_mostly
;
44 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
48 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
50 u64 __read_mostly hw_cache_event_ids
51 [PERF_COUNT_HW_CACHE_MAX
]
52 [PERF_COUNT_HW_CACHE_OP_MAX
]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
54 u64 __read_mostly hw_cache_extra_regs
55 [PERF_COUNT_HW_CACHE_MAX
]
56 [PERF_COUNT_HW_CACHE_OP_MAX
]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
60 * Propagate event elapsed time into the generic event.
61 * Can only be executed on the CPU where the event is active.
62 * Returns the delta events processed.
64 u64
x86_perf_event_update(struct perf_event
*event
)
66 struct hw_perf_event
*hwc
= &event
->hw
;
67 int shift
= 64 - x86_pmu
.cntval_bits
;
68 u64 prev_raw_count
, new_raw_count
;
72 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
76 * Careful: an NMI might modify the previous event value.
78 * Our tactic to handle this is to first atomically read and
79 * exchange a new raw count - then add that new-prev delta
80 * count to the generic event atomically:
83 prev_raw_count
= local64_read(&hwc
->prev_count
);
84 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
86 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
87 new_raw_count
) != prev_raw_count
)
91 * Now we have the new raw value and have updated the prev
92 * timestamp already. We can now calculate the elapsed delta
93 * (event-)time and add that to the generic event.
95 * Careful, not all hw sign-extends above the physical width
98 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
101 local64_add(delta
, &event
->count
);
102 local64_sub(delta
, &hwc
->period_left
);
104 return new_raw_count
;
108 * Find and validate any extra registers to set up.
110 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
112 struct hw_perf_event_extra
*reg
;
113 struct extra_reg
*er
;
115 reg
= &event
->hw
.extra_reg
;
117 if (!x86_pmu
.extra_regs
)
120 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
121 if (er
->event
!= (config
& er
->config_mask
))
123 if (event
->attr
.config1
& ~er
->valid_mask
)
125 /* Check if the extra msrs can be safely accessed*/
126 if (!er
->extra_msr_access
)
130 reg
->config
= event
->attr
.config1
;
137 static atomic_t active_events
;
138 static DEFINE_MUTEX(pmc_reserve_mutex
);
140 #ifdef CONFIG_X86_LOCAL_APIC
142 static bool reserve_pmc_hardware(void)
146 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
147 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
151 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
152 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
159 for (i
--; i
>= 0; i
--)
160 release_evntsel_nmi(x86_pmu_config_addr(i
));
162 i
= x86_pmu
.num_counters
;
165 for (i
--; i
>= 0; i
--)
166 release_perfctr_nmi(x86_pmu_event_addr(i
));
171 static void release_pmc_hardware(void)
175 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
176 release_perfctr_nmi(x86_pmu_event_addr(i
));
177 release_evntsel_nmi(x86_pmu_config_addr(i
));
183 static bool reserve_pmc_hardware(void) { return true; }
184 static void release_pmc_hardware(void) {}
188 static bool check_hw_exists(void)
190 u64 val
, val_fail
, val_new
= ~0;
191 int i
, reg
, reg_fail
, ret
= 0;
196 * Check to see if the BIOS enabled any of the counters, if so
199 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
200 reg
= x86_pmu_config_addr(i
);
201 ret
= rdmsrl_safe(reg
, &val
);
204 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
213 if (x86_pmu
.num_counters_fixed
) {
214 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
215 ret
= rdmsrl_safe(reg
, &val
);
218 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
219 if (val
& (0x03 << i
*4)) {
228 * If all the counters are enabled, the below test will always
229 * fail. The tools will also become useless in this scenario.
230 * Just fail and disable the hardware counters.
233 if (reg_safe
== -1) {
239 * Read the current value, change it and read it back to see if it
240 * matches, this is needed to detect certain hardware emulators
241 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
243 reg
= x86_pmu_event_addr(reg_safe
);
244 if (rdmsrl_safe(reg
, &val
))
247 ret
= wrmsrl_safe(reg
, val
);
248 ret
|= rdmsrl_safe(reg
, &val_new
);
249 if (ret
|| val
!= val_new
)
253 * We still allow the PMU driver to operate:
256 printk(KERN_CONT
"Broken BIOS detected, complain to your hardware vendor.\n");
257 printk(KERN_ERR FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail
, val_fail
);
263 printk(KERN_CONT
"Broken PMU hardware detected, using software events only.\n");
264 printk("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
265 boot_cpu_has(X86_FEATURE_HYPERVISOR
) ? KERN_INFO
: KERN_ERR
,
271 static void hw_perf_event_destroy(struct perf_event
*event
)
273 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
274 release_pmc_hardware();
275 release_ds_buffers();
276 mutex_unlock(&pmc_reserve_mutex
);
280 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
282 hw_perf_event_destroy(event
);
284 /* undo the lbr/bts event accounting */
285 x86_del_exclusive(x86_lbr_exclusive_lbr
);
288 static inline int x86_pmu_initialized(void)
290 return x86_pmu
.handle_irq
!= NULL
;
294 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
296 struct perf_event_attr
*attr
= &event
->attr
;
297 unsigned int cache_type
, cache_op
, cache_result
;
300 config
= attr
->config
;
302 cache_type
= (config
>> 0) & 0xff;
303 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
306 cache_op
= (config
>> 8) & 0xff;
307 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
310 cache_result
= (config
>> 16) & 0xff;
311 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
314 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
323 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
324 return x86_pmu_extra_regs(val
, event
);
328 * Check if we can create event of a certain type (that no conflicting events
331 int x86_add_exclusive(unsigned int what
)
335 if (atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
]))
338 mutex_lock(&pmc_reserve_mutex
);
339 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++)
340 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
343 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
347 mutex_unlock(&pmc_reserve_mutex
);
351 void x86_del_exclusive(unsigned int what
)
353 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
356 int x86_setup_perfctr(struct perf_event
*event
)
358 struct perf_event_attr
*attr
= &event
->attr
;
359 struct hw_perf_event
*hwc
= &event
->hw
;
362 if (!is_sampling_event(event
)) {
363 hwc
->sample_period
= x86_pmu
.max_period
;
364 hwc
->last_period
= hwc
->sample_period
;
365 local64_set(&hwc
->period_left
, hwc
->sample_period
);
368 if (attr
->type
== PERF_TYPE_RAW
)
369 return x86_pmu_extra_regs(event
->attr
.config
, event
);
371 if (attr
->type
== PERF_TYPE_HW_CACHE
)
372 return set_ext_hw_attr(hwc
, event
);
374 if (attr
->config
>= x86_pmu
.max_events
)
380 config
= x86_pmu
.event_map(attr
->config
);
391 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
392 !attr
->freq
&& hwc
->sample_period
== 1) {
393 /* BTS is not supported by this architecture. */
394 if (!x86_pmu
.bts_active
)
397 /* BTS is currently only allowed for user-mode. */
398 if (!attr
->exclude_kernel
)
401 /* disallow bts if conflicting events are present */
402 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
405 event
->destroy
= hw_perf_lbr_event_destroy
;
408 hwc
->config
|= config
;
414 * check that branch_sample_type is compatible with
415 * settings needed for precise_ip > 1 which implies
416 * using the LBR to capture ALL taken branches at the
417 * priv levels of the measurement
419 static inline int precise_br_compat(struct perf_event
*event
)
421 u64 m
= event
->attr
.branch_sample_type
;
424 /* must capture all branches */
425 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
428 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
430 if (!event
->attr
.exclude_user
)
431 b
|= PERF_SAMPLE_BRANCH_USER
;
433 if (!event
->attr
.exclude_kernel
)
434 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
437 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
443 int x86_pmu_hw_config(struct perf_event
*event
)
445 if (event
->attr
.precise_ip
) {
448 /* Support for constant skid */
449 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
452 /* Support for IP fixup */
453 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
457 if (event
->attr
.precise_ip
> precise
)
461 * check that PEBS LBR correction does not conflict with
462 * whatever the user is asking with attr->branch_sample_type
464 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
465 u64
*br_type
= &event
->attr
.branch_sample_type
;
467 if (has_branch_stack(event
)) {
468 if (!precise_br_compat(event
))
471 /* branch_sample_type is compatible */
475 * user did not specify branch_sample_type
477 * For PEBS fixups, we capture all
478 * the branches at the priv level of the
481 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
483 if (!event
->attr
.exclude_user
)
484 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
486 if (!event
->attr
.exclude_kernel
)
487 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
491 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
492 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
496 * (keep 'enabled' bit clear for now)
498 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
501 * Count user and OS events unless requested not to
503 if (!event
->attr
.exclude_user
)
504 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
505 if (!event
->attr
.exclude_kernel
)
506 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
508 if (event
->attr
.type
== PERF_TYPE_RAW
)
509 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
511 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
512 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
513 event
->attr
.sample_period
)
517 return x86_setup_perfctr(event
);
521 * Setup the hardware configuration for a given attr_type
523 static int __x86_pmu_event_init(struct perf_event
*event
)
527 if (!x86_pmu_initialized())
531 if (!atomic_inc_not_zero(&active_events
)) {
532 mutex_lock(&pmc_reserve_mutex
);
533 if (atomic_read(&active_events
) == 0) {
534 if (!reserve_pmc_hardware())
537 reserve_ds_buffers();
540 atomic_inc(&active_events
);
541 mutex_unlock(&pmc_reserve_mutex
);
546 event
->destroy
= hw_perf_event_destroy
;
549 event
->hw
.last_cpu
= -1;
550 event
->hw
.last_tag
= ~0ULL;
553 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
554 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
556 return x86_pmu
.hw_config(event
);
559 void x86_pmu_disable_all(void)
561 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
564 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
567 if (!test_bit(idx
, cpuc
->active_mask
))
569 rdmsrl(x86_pmu_config_addr(idx
), val
);
570 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
572 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
573 wrmsrl(x86_pmu_config_addr(idx
), val
);
577 static void x86_pmu_disable(struct pmu
*pmu
)
579 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
581 if (!x86_pmu_initialized())
591 x86_pmu
.disable_all();
594 void x86_pmu_enable_all(int added
)
596 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
599 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
600 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
602 if (!test_bit(idx
, cpuc
->active_mask
))
605 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
609 static struct pmu pmu
;
611 static inline int is_x86_event(struct perf_event
*event
)
613 return event
->pmu
== &pmu
;
617 * Event scheduler state:
619 * Assign events iterating over all events and counters, beginning
620 * with events with least weights first. Keep the current iterator
621 * state in struct sched_state.
625 int event
; /* event index */
626 int counter
; /* counter index */
627 int unassigned
; /* number of events to be assigned left */
628 int nr_gp
; /* number of GP counters used */
629 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
632 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
633 #define SCHED_STATES_MAX 2
640 struct event_constraint
**constraints
;
641 struct sched_state state
;
642 struct sched_state saved
[SCHED_STATES_MAX
];
646 * Initialize interator that runs through all events and counters.
648 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
649 int num
, int wmin
, int wmax
, int gpmax
)
653 memset(sched
, 0, sizeof(*sched
));
654 sched
->max_events
= num
;
655 sched
->max_weight
= wmax
;
656 sched
->max_gp
= gpmax
;
657 sched
->constraints
= constraints
;
659 for (idx
= 0; idx
< num
; idx
++) {
660 if (constraints
[idx
]->weight
== wmin
)
664 sched
->state
.event
= idx
; /* start with min weight */
665 sched
->state
.weight
= wmin
;
666 sched
->state
.unassigned
= num
;
669 static void perf_sched_save_state(struct perf_sched
*sched
)
671 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
674 sched
->saved
[sched
->saved_states
] = sched
->state
;
675 sched
->saved_states
++;
678 static bool perf_sched_restore_state(struct perf_sched
*sched
)
680 if (!sched
->saved_states
)
683 sched
->saved_states
--;
684 sched
->state
= sched
->saved
[sched
->saved_states
];
686 /* continue with next counter: */
687 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
693 * Select a counter for the current event to schedule. Return true on
696 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
698 struct event_constraint
*c
;
701 if (!sched
->state
.unassigned
)
704 if (sched
->state
.event
>= sched
->max_events
)
707 c
= sched
->constraints
[sched
->state
.event
];
708 /* Prefer fixed purpose counters */
709 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
710 idx
= INTEL_PMC_IDX_FIXED
;
711 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
712 if (!__test_and_set_bit(idx
, sched
->state
.used
))
717 /* Grab the first unused counter starting with idx */
718 idx
= sched
->state
.counter
;
719 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
720 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
721 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
731 sched
->state
.counter
= idx
;
734 perf_sched_save_state(sched
);
739 static bool perf_sched_find_counter(struct perf_sched
*sched
)
741 while (!__perf_sched_find_counter(sched
)) {
742 if (!perf_sched_restore_state(sched
))
750 * Go through all unassigned events and find the next one to schedule.
751 * Take events with the least weight first. Return true on success.
753 static bool perf_sched_next_event(struct perf_sched
*sched
)
755 struct event_constraint
*c
;
757 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
762 sched
->state
.event
++;
763 if (sched
->state
.event
>= sched
->max_events
) {
765 sched
->state
.event
= 0;
766 sched
->state
.weight
++;
767 if (sched
->state
.weight
> sched
->max_weight
)
770 c
= sched
->constraints
[sched
->state
.event
];
771 } while (c
->weight
!= sched
->state
.weight
);
773 sched
->state
.counter
= 0; /* start with first counter */
779 * Assign a counter for each event.
781 int perf_assign_events(struct event_constraint
**constraints
, int n
,
782 int wmin
, int wmax
, int gpmax
, int *assign
)
784 struct perf_sched sched
;
786 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
789 if (!perf_sched_find_counter(&sched
))
792 assign
[sched
.state
.event
] = sched
.state
.counter
;
793 } while (perf_sched_next_event(&sched
));
795 return sched
.state
.unassigned
;
797 EXPORT_SYMBOL_GPL(perf_assign_events
);
799 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
801 struct event_constraint
*c
;
802 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
803 struct perf_event
*e
;
804 int i
, wmin
, wmax
, unsched
= 0;
805 struct hw_perf_event
*hwc
;
807 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
809 if (x86_pmu
.start_scheduling
)
810 x86_pmu
.start_scheduling(cpuc
);
812 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
813 cpuc
->event_constraint
[i
] = NULL
;
814 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
815 cpuc
->event_constraint
[i
] = c
;
817 wmin
= min(wmin
, c
->weight
);
818 wmax
= max(wmax
, c
->weight
);
822 * fastpath, try to reuse previous register
824 for (i
= 0; i
< n
; i
++) {
825 hwc
= &cpuc
->event_list
[i
]->hw
;
826 c
= cpuc
->event_constraint
[i
];
832 /* constraint still honored */
833 if (!test_bit(hwc
->idx
, c
->idxmsk
))
836 /* not already used */
837 if (test_bit(hwc
->idx
, used_mask
))
840 __set_bit(hwc
->idx
, used_mask
);
842 assign
[i
] = hwc
->idx
;
847 int gpmax
= x86_pmu
.num_counters
;
850 * Do not allow scheduling of more than half the available
853 * This helps avoid counter starvation of sibling thread by
854 * ensuring at most half the counters cannot be in exclusive
855 * mode. There is no designated counters for the limits. Any
856 * N/2 counters can be used. This helps with events with
857 * specific counter constraints.
859 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
860 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
863 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
864 wmax
, gpmax
, assign
);
868 * In case of success (unsched = 0), mark events as committed,
869 * so we do not put_constraint() in case new events are added
870 * and fail to be scheduled
872 * We invoke the lower level commit callback to lock the resource
874 * We do not need to do all of this in case we are called to
875 * validate an event group (assign == NULL)
877 if (!unsched
&& assign
) {
878 for (i
= 0; i
< n
; i
++) {
879 e
= cpuc
->event_list
[i
];
880 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
881 if (x86_pmu
.commit_scheduling
)
882 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
886 if (!assign
|| unsched
) {
888 for (i
= 0; i
< n
; i
++) {
889 e
= cpuc
->event_list
[i
];
891 * do not put_constraint() on comitted events,
892 * because they are good to go
894 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
898 * release events that failed scheduling
900 if (x86_pmu
.put_event_constraints
)
901 x86_pmu
.put_event_constraints(cpuc
, e
);
905 if (x86_pmu
.stop_scheduling
)
906 x86_pmu
.stop_scheduling(cpuc
);
908 return unsched
? -EINVAL
: 0;
912 * dogrp: true if must collect siblings events (group)
913 * returns total number of events and error code
915 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
917 struct perf_event
*event
;
920 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
922 /* current number of events already accepted */
925 if (is_x86_event(leader
)) {
928 cpuc
->event_list
[n
] = leader
;
934 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
935 if (!is_x86_event(event
) ||
936 event
->state
<= PERF_EVENT_STATE_OFF
)
942 cpuc
->event_list
[n
] = event
;
948 static inline void x86_assign_hw_event(struct perf_event
*event
,
949 struct cpu_hw_events
*cpuc
, int i
)
951 struct hw_perf_event
*hwc
= &event
->hw
;
953 hwc
->idx
= cpuc
->assign
[i
];
954 hwc
->last_cpu
= smp_processor_id();
955 hwc
->last_tag
= ++cpuc
->tags
[i
];
957 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
958 hwc
->config_base
= 0;
960 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
961 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
962 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
963 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
965 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
966 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
967 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
971 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
972 struct cpu_hw_events
*cpuc
,
975 return hwc
->idx
== cpuc
->assign
[i
] &&
976 hwc
->last_cpu
== smp_processor_id() &&
977 hwc
->last_tag
== cpuc
->tags
[i
];
980 static void x86_pmu_start(struct perf_event
*event
, int flags
);
982 static void x86_pmu_enable(struct pmu
*pmu
)
984 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
985 struct perf_event
*event
;
986 struct hw_perf_event
*hwc
;
987 int i
, added
= cpuc
->n_added
;
989 if (!x86_pmu_initialized())
996 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
998 * apply assignment obtained either from
999 * hw_perf_group_sched_in() or x86_pmu_enable()
1001 * step1: save events moving to new counters
1003 for (i
= 0; i
< n_running
; i
++) {
1004 event
= cpuc
->event_list
[i
];
1008 * we can avoid reprogramming counter if:
1009 * - assigned same counter as last time
1010 * - running on same CPU as last time
1011 * - no other event has used the counter since
1013 if (hwc
->idx
== -1 ||
1014 match_prev_assignment(hwc
, cpuc
, i
))
1018 * Ensure we don't accidentally enable a stopped
1019 * counter simply because we rescheduled.
1021 if (hwc
->state
& PERF_HES_STOPPED
)
1022 hwc
->state
|= PERF_HES_ARCH
;
1024 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1028 * step2: reprogram moved events into new counters
1030 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1031 event
= cpuc
->event_list
[i
];
1034 if (!match_prev_assignment(hwc
, cpuc
, i
))
1035 x86_assign_hw_event(event
, cpuc
, i
);
1036 else if (i
< n_running
)
1039 if (hwc
->state
& PERF_HES_ARCH
)
1042 x86_pmu_start(event
, PERF_EF_RELOAD
);
1045 perf_events_lapic_init();
1051 x86_pmu
.enable_all(added
);
1054 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1057 * Set the next IRQ period, based on the hwc->period_left value.
1058 * To be called with the event disabled in hw:
1060 int x86_perf_event_set_period(struct perf_event
*event
)
1062 struct hw_perf_event
*hwc
= &event
->hw
;
1063 s64 left
= local64_read(&hwc
->period_left
);
1064 s64 period
= hwc
->sample_period
;
1065 int ret
= 0, idx
= hwc
->idx
;
1067 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1071 * If we are way outside a reasonable range then just skip forward:
1073 if (unlikely(left
<= -period
)) {
1075 local64_set(&hwc
->period_left
, left
);
1076 hwc
->last_period
= period
;
1080 if (unlikely(left
<= 0)) {
1082 local64_set(&hwc
->period_left
, left
);
1083 hwc
->last_period
= period
;
1087 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1089 if (unlikely(left
< 2))
1092 if (left
> x86_pmu
.max_period
)
1093 left
= x86_pmu
.max_period
;
1095 if (x86_pmu
.limit_period
)
1096 left
= x86_pmu
.limit_period(event
, left
);
1098 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1101 * The hw event starts counting from this event offset,
1102 * mark it to be able to extra future deltas:
1104 local64_set(&hwc
->prev_count
, (u64
)-left
);
1106 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1109 * Due to erratum on certan cpu we need
1110 * a second write to be sure the register
1111 * is updated properly
1113 if (x86_pmu
.perfctr_second_write
) {
1114 wrmsrl(hwc
->event_base
,
1115 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1118 perf_event_update_userpage(event
);
1123 void x86_pmu_enable_event(struct perf_event
*event
)
1125 if (__this_cpu_read(cpu_hw_events
.enabled
))
1126 __x86_pmu_enable_event(&event
->hw
,
1127 ARCH_PERFMON_EVENTSEL_ENABLE
);
1131 * Add a single event to the PMU.
1133 * The event is added to the group of enabled events
1134 * but only if it can be scehduled with existing events.
1136 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1138 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1139 struct hw_perf_event
*hwc
;
1140 int assign
[X86_PMC_IDX_MAX
];
1145 n0
= cpuc
->n_events
;
1146 ret
= n
= collect_events(cpuc
, event
, false);
1150 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1151 if (!(flags
& PERF_EF_START
))
1152 hwc
->state
|= PERF_HES_ARCH
;
1155 * If group events scheduling transaction was started,
1156 * skip the schedulability test here, it will be performed
1157 * at commit time (->commit_txn) as a whole.
1159 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1162 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1166 * copy new assignment, now we know it is possible
1167 * will be used by hw_perf_enable()
1169 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1173 * Commit the collect_events() state. See x86_pmu_del() and
1177 cpuc
->n_added
+= n
- n0
;
1178 cpuc
->n_txn
+= n
- n0
;
1185 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1187 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1188 int idx
= event
->hw
.idx
;
1190 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1193 if (WARN_ON_ONCE(idx
== -1))
1196 if (flags
& PERF_EF_RELOAD
) {
1197 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1198 x86_perf_event_set_period(event
);
1201 event
->hw
.state
= 0;
1203 cpuc
->events
[idx
] = event
;
1204 __set_bit(idx
, cpuc
->active_mask
);
1205 __set_bit(idx
, cpuc
->running
);
1206 x86_pmu
.enable(event
);
1207 perf_event_update_userpage(event
);
1210 void perf_event_print_debug(void)
1212 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1214 struct cpu_hw_events
*cpuc
;
1215 unsigned long flags
;
1218 if (!x86_pmu
.num_counters
)
1221 local_irq_save(flags
);
1223 cpu
= smp_processor_id();
1224 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1226 if (x86_pmu
.version
>= 2) {
1227 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1228 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1229 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1230 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1233 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1234 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1235 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1236 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1237 if (x86_pmu
.pebs_constraints
) {
1238 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1239 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1241 if (x86_pmu
.lbr_nr
) {
1242 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1243 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1246 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1248 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1249 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1250 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1252 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1254 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1255 cpu
, idx
, pmc_ctrl
);
1256 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1257 cpu
, idx
, pmc_count
);
1258 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1259 cpu
, idx
, prev_left
);
1261 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1262 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1264 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1265 cpu
, idx
, pmc_count
);
1267 local_irq_restore(flags
);
1270 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1272 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1273 struct hw_perf_event
*hwc
= &event
->hw
;
1275 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1276 x86_pmu
.disable(event
);
1277 cpuc
->events
[hwc
->idx
] = NULL
;
1278 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1279 hwc
->state
|= PERF_HES_STOPPED
;
1282 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1284 * Drain the remaining delta count out of a event
1285 * that we are disabling:
1287 x86_perf_event_update(event
);
1288 hwc
->state
|= PERF_HES_UPTODATE
;
1292 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1294 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1298 * event is descheduled
1300 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1303 * If we're called during a txn, we don't need to do anything.
1304 * The events never got scheduled and ->cancel_txn will truncate
1307 * XXX assumes any ->del() called during a TXN will only be on
1308 * an event added during that same TXN.
1310 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1314 * Not a TXN, therefore cleanup properly.
1316 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1318 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1319 if (event
== cpuc
->event_list
[i
])
1323 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1326 /* If we have a newly added event; make sure to decrease n_added. */
1327 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1330 if (x86_pmu
.put_event_constraints
)
1331 x86_pmu
.put_event_constraints(cpuc
, event
);
1333 /* Delete the array entry. */
1334 while (++i
< cpuc
->n_events
) {
1335 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1336 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1340 perf_event_update_userpage(event
);
1343 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1345 struct perf_sample_data data
;
1346 struct cpu_hw_events
*cpuc
;
1347 struct perf_event
*event
;
1348 int idx
, handled
= 0;
1351 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1354 * Some chipsets need to unmask the LVTPC in a particular spot
1355 * inside the nmi handler. As a result, the unmasking was pushed
1356 * into all the nmi handlers.
1358 * This generic handler doesn't seem to have any issues where the
1359 * unmasking occurs so it was left at the top.
1361 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1363 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1364 if (!test_bit(idx
, cpuc
->active_mask
)) {
1366 * Though we deactivated the counter some cpus
1367 * might still deliver spurious interrupts still
1368 * in flight. Catch them:
1370 if (__test_and_clear_bit(idx
, cpuc
->running
))
1375 event
= cpuc
->events
[idx
];
1377 val
= x86_perf_event_update(event
);
1378 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1385 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1387 if (!x86_perf_event_set_period(event
))
1390 if (perf_event_overflow(event
, &data
, regs
))
1391 x86_pmu_stop(event
, 0);
1395 inc_irq_stat(apic_perf_irqs
);
1400 void perf_events_lapic_init(void)
1402 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1406 * Always use NMI for PMU
1408 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1412 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1418 if (!atomic_read(&active_events
))
1421 start_clock
= sched_clock();
1422 ret
= x86_pmu
.handle_irq(regs
);
1423 finish_clock
= sched_clock();
1425 perf_sample_event_took(finish_clock
- start_clock
);
1429 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1431 struct event_constraint emptyconstraint
;
1432 struct event_constraint unconstrained
;
1435 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1437 unsigned int cpu
= (long)hcpu
;
1438 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1439 int i
, ret
= NOTIFY_OK
;
1441 switch (action
& ~CPU_TASKS_FROZEN
) {
1442 case CPU_UP_PREPARE
:
1443 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1444 cpuc
->kfree_on_online
[i
] = NULL
;
1445 if (x86_pmu
.cpu_prepare
)
1446 ret
= x86_pmu
.cpu_prepare(cpu
);
1450 if (x86_pmu
.cpu_starting
)
1451 x86_pmu
.cpu_starting(cpu
);
1455 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1456 kfree(cpuc
->kfree_on_online
[i
]);
1457 cpuc
->kfree_on_online
[i
] = NULL
;
1462 if (x86_pmu
.cpu_dying
)
1463 x86_pmu
.cpu_dying(cpu
);
1466 case CPU_UP_CANCELED
:
1468 if (x86_pmu
.cpu_dead
)
1469 x86_pmu
.cpu_dead(cpu
);
1479 static void __init
pmu_check_apic(void)
1485 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1486 pr_info("no hardware sampling interrupt available.\n");
1489 * If we have a PMU initialized but no APIC
1490 * interrupts, we cannot sample hardware
1491 * events (user-space has to fall back and
1492 * sample via a hrtimer based software event):
1494 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1498 static struct attribute_group x86_pmu_format_group
= {
1504 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1505 * out of events_attr attributes.
1507 static void __init
filter_events(struct attribute
**attrs
)
1509 struct device_attribute
*d
;
1510 struct perf_pmu_events_attr
*pmu_attr
;
1513 for (i
= 0; attrs
[i
]; i
++) {
1514 d
= (struct device_attribute
*)attrs
[i
];
1515 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1517 if (pmu_attr
->event_str
)
1519 if (x86_pmu
.event_map(i
))
1522 for (j
= i
; attrs
[j
]; j
++)
1523 attrs
[j
] = attrs
[j
+ 1];
1525 /* Check the shifted attr. */
1530 /* Merge two pointer arrays */
1531 static __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1533 struct attribute
**new;
1536 for (j
= 0; a
[j
]; j
++)
1538 for (i
= 0; b
[i
]; i
++)
1542 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1547 for (i
= 0; a
[i
]; i
++)
1549 for (i
= 0; b
[i
]; i
++)
1556 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1559 struct perf_pmu_events_attr
*pmu_attr
= \
1560 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1561 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1563 /* string trumps id */
1564 if (pmu_attr
->event_str
)
1565 return sprintf(page
, "%s", pmu_attr
->event_str
);
1567 return x86_pmu
.events_sysfs_show(page
, config
);
1570 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1571 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1572 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1573 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1574 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1575 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1576 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1577 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1578 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1579 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1581 static struct attribute
*empty_attrs
;
1583 static struct attribute
*events_attr
[] = {
1584 EVENT_PTR(CPU_CYCLES
),
1585 EVENT_PTR(INSTRUCTIONS
),
1586 EVENT_PTR(CACHE_REFERENCES
),
1587 EVENT_PTR(CACHE_MISSES
),
1588 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1589 EVENT_PTR(BRANCH_MISSES
),
1590 EVENT_PTR(BUS_CYCLES
),
1591 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1592 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1593 EVENT_PTR(REF_CPU_CYCLES
),
1597 static struct attribute_group x86_pmu_events_group
= {
1599 .attrs
= events_attr
,
1602 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1604 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1605 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1606 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1607 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1608 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1609 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1613 * We have whole page size to spend and just little data
1614 * to write, so we can safely use sprintf.
1616 ret
= sprintf(page
, "event=0x%02llx", event
);
1619 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1622 ret
+= sprintf(page
+ ret
, ",edge");
1625 ret
+= sprintf(page
+ ret
, ",pc");
1628 ret
+= sprintf(page
+ ret
, ",any");
1631 ret
+= sprintf(page
+ ret
, ",inv");
1634 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1636 ret
+= sprintf(page
+ ret
, "\n");
1641 static int __init
init_hw_perf_events(void)
1643 struct x86_pmu_quirk
*quirk
;
1646 pr_info("Performance Events: ");
1648 switch (boot_cpu_data
.x86_vendor
) {
1649 case X86_VENDOR_INTEL
:
1650 err
= intel_pmu_init();
1652 case X86_VENDOR_AMD
:
1653 err
= amd_pmu_init();
1659 pr_cont("no PMU driver, software events only.\n");
1665 /* sanity check that the hardware exists or is emulated */
1666 if (!check_hw_exists())
1669 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1671 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1673 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1676 if (!x86_pmu
.intel_ctrl
)
1677 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1679 perf_events_lapic_init();
1680 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1682 unconstrained
= (struct event_constraint
)
1683 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1684 0, x86_pmu
.num_counters
, 0, 0);
1686 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1688 if (x86_pmu
.event_attrs
)
1689 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1691 if (!x86_pmu
.events_sysfs_show
)
1692 x86_pmu_events_group
.attrs
= &empty_attrs
;
1694 filter_events(x86_pmu_events_group
.attrs
);
1696 if (x86_pmu
.cpu_events
) {
1697 struct attribute
**tmp
;
1699 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1701 x86_pmu_events_group
.attrs
= tmp
;
1704 pr_info("... version: %d\n", x86_pmu
.version
);
1705 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1706 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1707 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1708 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1709 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1710 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1712 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1713 perf_cpu_notifier(x86_pmu_notifier
);
1717 early_initcall(init_hw_perf_events
);
1719 static inline void x86_pmu_read(struct perf_event
*event
)
1721 x86_perf_event_update(event
);
1725 * Start group events scheduling transaction
1726 * Set the flag to make pmu::enable() not perform the
1727 * schedulability test, it will be performed at commit time
1729 static void x86_pmu_start_txn(struct pmu
*pmu
)
1731 perf_pmu_disable(pmu
);
1732 __this_cpu_or(cpu_hw_events
.group_flag
, PERF_EVENT_TXN
);
1733 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1737 * Stop group events scheduling transaction
1738 * Clear the flag and pmu::enable() will perform the
1739 * schedulability test.
1741 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1743 __this_cpu_and(cpu_hw_events
.group_flag
, ~PERF_EVENT_TXN
);
1745 * Truncate collected array by the number of events added in this
1746 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1748 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1749 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1750 perf_pmu_enable(pmu
);
1754 * Commit group events scheduling transaction
1755 * Perform the group schedulability test as a whole
1756 * Return 0 if success
1758 * Does not cancel the transaction on failure; expects the caller to do this.
1760 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1762 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1763 int assign
[X86_PMC_IDX_MAX
];
1768 if (!x86_pmu_initialized())
1771 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1776 * copy new assignment, now we know it is possible
1777 * will be used by hw_perf_enable()
1779 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1781 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1782 perf_pmu_enable(pmu
);
1786 * a fake_cpuc is used to validate event groups. Due to
1787 * the extra reg logic, we need to also allocate a fake
1788 * per_core and per_cpu structure. Otherwise, group events
1789 * using extra reg may conflict without the kernel being
1790 * able to catch this when the last event gets added to
1793 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1795 kfree(cpuc
->shared_regs
);
1799 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1801 struct cpu_hw_events
*cpuc
;
1802 int cpu
= raw_smp_processor_id();
1804 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1806 return ERR_PTR(-ENOMEM
);
1808 /* only needed, if we have extra_regs */
1809 if (x86_pmu
.extra_regs
) {
1810 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1811 if (!cpuc
->shared_regs
)
1817 free_fake_cpuc(cpuc
);
1818 return ERR_PTR(-ENOMEM
);
1822 * validate that we can schedule this event
1824 static int validate_event(struct perf_event
*event
)
1826 struct cpu_hw_events
*fake_cpuc
;
1827 struct event_constraint
*c
;
1830 fake_cpuc
= allocate_fake_cpuc();
1831 if (IS_ERR(fake_cpuc
))
1832 return PTR_ERR(fake_cpuc
);
1834 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
1836 if (!c
|| !c
->weight
)
1839 if (x86_pmu
.put_event_constraints
)
1840 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1842 free_fake_cpuc(fake_cpuc
);
1848 * validate a single event group
1850 * validation include:
1851 * - check events are compatible which each other
1852 * - events do not compete for the same counter
1853 * - number of events <= number of counters
1855 * validation ensures the group can be loaded onto the
1856 * PMU if it was the only group available.
1858 static int validate_group(struct perf_event
*event
)
1860 struct perf_event
*leader
= event
->group_leader
;
1861 struct cpu_hw_events
*fake_cpuc
;
1862 int ret
= -EINVAL
, n
;
1864 fake_cpuc
= allocate_fake_cpuc();
1865 if (IS_ERR(fake_cpuc
))
1866 return PTR_ERR(fake_cpuc
);
1868 * the event is not yet connected with its
1869 * siblings therefore we must first collect
1870 * existing siblings, then add the new event
1871 * before we can simulate the scheduling
1873 n
= collect_events(fake_cpuc
, leader
, true);
1877 fake_cpuc
->n_events
= n
;
1878 n
= collect_events(fake_cpuc
, event
, false);
1882 fake_cpuc
->n_events
= n
;
1884 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1887 free_fake_cpuc(fake_cpuc
);
1891 static int x86_pmu_event_init(struct perf_event
*event
)
1896 switch (event
->attr
.type
) {
1898 case PERF_TYPE_HARDWARE
:
1899 case PERF_TYPE_HW_CACHE
:
1906 err
= __x86_pmu_event_init(event
);
1909 * we temporarily connect event to its pmu
1910 * such that validate_group() can classify
1911 * it as an x86 event using is_x86_event()
1916 if (event
->group_leader
!= event
)
1917 err
= validate_group(event
);
1919 err
= validate_event(event
);
1925 event
->destroy(event
);
1928 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
1929 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
1934 static void refresh_pce(void *ignored
)
1937 load_mm_cr4(current
->mm
);
1940 static void x86_pmu_event_mapped(struct perf_event
*event
)
1942 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1945 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
1946 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
1949 static void x86_pmu_event_unmapped(struct perf_event
*event
)
1954 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1957 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
1958 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
1961 static int x86_pmu_event_idx(struct perf_event
*event
)
1963 int idx
= event
->hw
.idx
;
1965 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
1968 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
1969 idx
-= INTEL_PMC_IDX_FIXED
;
1976 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
1977 struct device_attribute
*attr
,
1980 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
1983 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
1984 struct device_attribute
*attr
,
1985 const char *buf
, size_t count
)
1990 ret
= kstrtoul(buf
, 0, &val
);
1997 if (x86_pmu
.attr_rdpmc_broken
)
2000 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2002 * Changing into or out of always available, aka
2003 * perf-event-bypassing mode. This path is extremely slow,
2004 * but only root can trigger it, so it's okay.
2007 static_key_slow_inc(&rdpmc_always_available
);
2009 static_key_slow_dec(&rdpmc_always_available
);
2010 on_each_cpu(refresh_pce
, NULL
, 1);
2013 x86_pmu
.attr_rdpmc
= val
;
2018 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2020 static struct attribute
*x86_pmu_attrs
[] = {
2021 &dev_attr_rdpmc
.attr
,
2025 static struct attribute_group x86_pmu_attr_group
= {
2026 .attrs
= x86_pmu_attrs
,
2029 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2030 &x86_pmu_attr_group
,
2031 &x86_pmu_format_group
,
2032 &x86_pmu_events_group
,
2036 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2038 if (x86_pmu
.sched_task
)
2039 x86_pmu
.sched_task(ctx
, sched_in
);
2042 void perf_check_microcode(void)
2044 if (x86_pmu
.check_microcode
)
2045 x86_pmu
.check_microcode();
2047 EXPORT_SYMBOL_GPL(perf_check_microcode
);
2049 static struct pmu pmu
= {
2050 .pmu_enable
= x86_pmu_enable
,
2051 .pmu_disable
= x86_pmu_disable
,
2053 .attr_groups
= x86_pmu_attr_groups
,
2055 .event_init
= x86_pmu_event_init
,
2057 .event_mapped
= x86_pmu_event_mapped
,
2058 .event_unmapped
= x86_pmu_event_unmapped
,
2062 .start
= x86_pmu_start
,
2063 .stop
= x86_pmu_stop
,
2064 .read
= x86_pmu_read
,
2066 .start_txn
= x86_pmu_start_txn
,
2067 .cancel_txn
= x86_pmu_cancel_txn
,
2068 .commit_txn
= x86_pmu_commit_txn
,
2070 .event_idx
= x86_pmu_event_idx
,
2071 .sched_task
= x86_pmu_sched_task
,
2072 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2075 void arch_perf_update_userpage(struct perf_event
*event
,
2076 struct perf_event_mmap_page
*userpg
, u64 now
)
2078 struct cyc2ns_data
*data
;
2080 userpg
->cap_user_time
= 0;
2081 userpg
->cap_user_time_zero
= 0;
2082 userpg
->cap_user_rdpmc
=
2083 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2084 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2086 if (!sched_clock_stable())
2089 data
= cyc2ns_read_begin();
2092 * Internal timekeeping for enabled/running/stopped times
2093 * is always in the local_clock domain.
2095 userpg
->cap_user_time
= 1;
2096 userpg
->time_mult
= data
->cyc2ns_mul
;
2097 userpg
->time_shift
= data
->cyc2ns_shift
;
2098 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
2101 * cap_user_time_zero doesn't make sense when we're using a different
2102 * time base for the records.
2104 if (event
->clock
== &local_clock
) {
2105 userpg
->cap_user_time_zero
= 1;
2106 userpg
->time_zero
= data
->cyc2ns_offset
;
2109 cyc2ns_read_end(data
);
2116 static int backtrace_stack(void *data
, char *name
)
2121 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
2123 struct perf_callchain_entry
*entry
= data
;
2125 perf_callchain_store(entry
, addr
);
2128 static const struct stacktrace_ops backtrace_ops
= {
2129 .stack
= backtrace_stack
,
2130 .address
= backtrace_address
,
2131 .walk_stack
= print_context_stack_bp
,
2135 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2137 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2138 /* TODO: We don't support guest os callchain now */
2142 perf_callchain_store(entry
, regs
->ip
);
2144 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
2148 valid_user_frame(const void __user
*fp
, unsigned long size
)
2150 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2153 static unsigned long get_segment_base(unsigned int segment
)
2155 struct desc_struct
*desc
;
2156 int idx
= segment
>> 3;
2158 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2159 if (idx
> LDT_ENTRIES
)
2162 if (idx
> current
->active_mm
->context
.size
)
2165 desc
= current
->active_mm
->context
.ldt
;
2167 if (idx
> GDT_ENTRIES
)
2170 desc
= raw_cpu_ptr(gdt_page
.gdt
);
2173 return get_desc_base(desc
+ idx
);
2176 #ifdef CONFIG_COMPAT
2178 #include <asm/compat.h>
2181 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2183 /* 32-bit process in 64-bit kernel. */
2184 unsigned long ss_base
, cs_base
;
2185 struct stack_frame_ia32 frame
;
2186 const void __user
*fp
;
2188 if (!test_thread_flag(TIF_IA32
))
2191 cs_base
= get_segment_base(regs
->cs
);
2192 ss_base
= get_segment_base(regs
->ss
);
2194 fp
= compat_ptr(ss_base
+ regs
->bp
);
2195 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2196 unsigned long bytes
;
2197 frame
.next_frame
= 0;
2198 frame
.return_address
= 0;
2200 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2204 if (!valid_user_frame(fp
, sizeof(frame
)))
2207 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2208 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2214 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2221 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2223 struct stack_frame frame
;
2224 const void __user
*fp
;
2226 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2227 /* TODO: We don't support guest os callchain now */
2232 * We don't know what to do with VM86 stacks.. ignore them for now.
2234 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2237 fp
= (void __user
*)regs
->bp
;
2239 perf_callchain_store(entry
, regs
->ip
);
2244 if (perf_callchain_user32(regs
, entry
))
2247 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2248 unsigned long bytes
;
2249 frame
.next_frame
= NULL
;
2250 frame
.return_address
= 0;
2252 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
2256 if (!valid_user_frame(fp
, sizeof(frame
)))
2259 perf_callchain_store(entry
, frame
.return_address
);
2260 fp
= frame
.next_frame
;
2265 * Deal with code segment offsets for the various execution modes:
2267 * VM86 - the good olde 16 bit days, where the linear address is
2268 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2270 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2271 * to figure out what the 32bit base address is.
2273 * X32 - has TIF_X32 set, but is running in x86_64
2275 * X86_64 - CS,DS,SS,ES are all zero based.
2277 static unsigned long code_segment_base(struct pt_regs
*regs
)
2280 * For IA32 we look at the GDT/LDT segment base to convert the
2281 * effective IP to a linear address.
2284 #ifdef CONFIG_X86_32
2286 * If we are in VM86 mode, add the segment offset to convert to a
2289 if (regs
->flags
& X86_VM_MASK
)
2290 return 0x10 * regs
->cs
;
2292 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2293 return get_segment_base(regs
->cs
);
2295 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2296 regs
->cs
!= __USER32_CS
)
2297 return get_segment_base(regs
->cs
);
2302 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2304 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2305 return perf_guest_cbs
->get_guest_ip();
2307 return regs
->ip
+ code_segment_base(regs
);
2310 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2314 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2315 if (perf_guest_cbs
->is_user_mode())
2316 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2318 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2320 if (user_mode(regs
))
2321 misc
|= PERF_RECORD_MISC_USER
;
2323 misc
|= PERF_RECORD_MISC_KERNEL
;
2326 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2327 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2332 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2334 cap
->version
= x86_pmu
.version
;
2335 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2336 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2337 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2338 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2339 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2340 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2342 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);