2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
19 #define wrmsrl(msr, val) \
21 unsigned int _msr = (msr); \
23 trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \
24 (unsigned long long)(_val)); \
25 native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \
31 * register -------------------------------
32 * | HT | no HT | HT | no HT |
33 *-----------------------------------------
34 * offcore | core | core | cpu | core |
35 * lbr_sel | core | core | cpu | core |
36 * ld_lat | cpu | core | cpu | core |
37 *-----------------------------------------
39 * Given that there is a small number of shared regs,
40 * we can pre-allocate their slot in the per-cpu
41 * per-core reg tables.
44 EXTRA_REG_NONE
= -1, /* not used */
46 EXTRA_REG_RSP_0
= 0, /* offcore_response_0 */
47 EXTRA_REG_RSP_1
= 1, /* offcore_response_1 */
48 EXTRA_REG_LBR
= 2, /* lbr_select */
49 EXTRA_REG_LDLAT
= 3, /* ld_lat_threshold */
51 EXTRA_REG_MAX
/* number of entries needed */
54 struct event_constraint
{
56 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
66 * struct hw_perf_event.flags flags
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x1 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x2 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x4 /* haswell style datala, store */
71 #define PERF_X86_EVENT_COMMITTED 0x8 /* event passed commit_txn */
72 #define PERF_X86_EVENT_PEBS_LD_HSW 0x10 /* haswell style datala, load */
73 #define PERF_X86_EVENT_PEBS_NA_HSW 0x20 /* haswell style datala, unknown */
74 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x40 /* grant rdpmc permission */
78 int nb_id
; /* NorthBridge id */
79 int refcnt
; /* reference count */
80 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
81 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
84 /* The maximal number of PEBS events: */
85 #define MAX_PEBS_EVENTS 8
88 * A debug store configuration.
90 * We only support architectures that use 64bit fields.
95 u64 bts_absolute_maximum
;
96 u64 bts_interrupt_threshold
;
99 u64 pebs_absolute_maximum
;
100 u64 pebs_interrupt_threshold
;
101 u64 pebs_event_reset
[MAX_PEBS_EVENTS
];
105 * Per register state.
108 raw_spinlock_t lock
; /* per-core: protect structure */
109 u64 config
; /* extra MSR config */
110 u64 reg
; /* extra MSR number */
111 atomic_t ref
; /* reference count */
117 * Used to coordinate shared registers between HT threads or
118 * among events on a single PMU.
120 struct intel_shared_regs
{
121 struct er_account regs
[EXTRA_REG_MAX
];
122 int refcnt
; /* per-core: #HT threads */
123 unsigned core_id
; /* per-core: core id */
126 #define MAX_LBR_ENTRIES 16
128 struct cpu_hw_events
{
130 * Generic x86 PMC bits
132 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
133 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
134 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
137 int n_events
; /* the # of events in the below arrays */
138 int n_added
; /* the # last events in the below arrays;
139 they've never been enabled yet */
140 int n_txn
; /* the # last events in the below arrays;
141 added in the current transaction */
142 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
143 u64 tags
[X86_PMC_IDX_MAX
];
144 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
146 unsigned int group_flag
;
150 * Intel DebugStore bits
152 struct debug_store
*ds
;
160 struct perf_branch_stack lbr_stack
;
161 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
162 struct er_account
*lbr_sel
;
166 * Intel host/guest exclude bits
168 u64 intel_ctrl_guest_mask
;
169 u64 intel_ctrl_host_mask
;
170 struct perf_guest_switch_msr guest_switch_msrs
[X86_PMC_IDX_MAX
];
173 * Intel checkpoint mask
178 * manage shared (per-core, per-cpu) registers
179 * used on Intel NHM/WSM/SNB
181 struct intel_shared_regs
*shared_regs
;
186 struct amd_nb
*amd_nb
;
187 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
188 u64 perf_ctr_virt_mask
;
190 void *kfree_on_online
;
193 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
194 { .idxmsk64 = (n) }, \
202 #define EVENT_CONSTRAINT(c, n, m) \
203 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
206 * The overlap flag marks event constraints with overlapping counter
207 * masks. This is the case if the counter mask of such an event is not
208 * a subset of any other counter mask of a constraint with an equal or
209 * higher weight, e.g.:
211 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
212 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
213 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
215 * The event scheduler may not select the correct counter in the first
216 * cycle because it needs to know which subsequent events will be
217 * scheduled. It may fail to schedule the events then. So we set the
218 * overlap flag for such constraints to give the scheduler a hint which
219 * events to select for counter rescheduling.
221 * Care must be taken as the rescheduling algorithm is O(n!) which
222 * will increase scheduling cycles for an over-commited system
223 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
224 * and its counter masks must be kept at a minimum.
226 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
227 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
230 * Constraint on the Event code.
232 #define INTEL_EVENT_CONSTRAINT(c, n) \
233 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
236 * Constraint on the Event code + UMask + fixed-mask
238 * filter mask to validate fixed counter events.
239 * the following filters disqualify for fixed counters:
244 * - in_tx_checkpointed
245 * The other filters are supported by fixed counters.
246 * The any-thread option is supported starting with v3.
248 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
249 #define FIXED_EVENT_CONSTRAINT(c, n) \
250 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
253 * Constraint on the Event code + UMask
255 #define INTEL_UEVENT_CONSTRAINT(c, n) \
256 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
258 /* Like UEVENT_CONSTRAINT, but match flags too */
259 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
260 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
262 #define INTEL_PLD_CONSTRAINT(c, n) \
263 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
264 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
266 #define INTEL_PST_CONSTRAINT(c, n) \
267 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
268 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
270 /* Event constraint, but match on all event flags too. */
271 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
272 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
274 /* Check only flags, but allow all event/umask */
275 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
276 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
278 /* Check flags and event code, and set the HSW store flag */
279 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
280 __EVENT_CONSTRAINT(code, n, \
281 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
282 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
284 /* Check flags and event code, and set the HSW load flag */
285 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
286 __EVENT_CONSTRAINT(code, n, \
287 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
288 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
290 /* Check flags and event code/umask, and set the HSW store flag */
291 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
292 __EVENT_CONSTRAINT(code, n, \
293 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
294 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
296 /* Check flags and event code/umask, and set the HSW load flag */
297 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
298 __EVENT_CONSTRAINT(code, n, \
299 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
300 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
302 /* Check flags and event code/umask, and set the HSW N/A flag */
303 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
304 __EVENT_CONSTRAINT(code, n, \
305 INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \
306 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
310 * We define the end marker as having a weight of -1
311 * to enable blacklisting of events using a counter bitmask
312 * of zero and thus a weight of zero.
313 * The end marker has a weight that cannot possibly be
314 * obtained from counting the bits in the bitmask.
316 #define EVENT_CONSTRAINT_END { .weight = -1 }
319 * Check for end marker with weight == -1
321 #define for_each_event_constraint(e, c) \
322 for ((e) = (c); (e)->weight != -1; (e)++)
325 * Extra registers for specific events.
327 * Some events need large masks and require external MSRs.
328 * Those extra MSRs end up being shared for all events on
329 * a PMU and sometimes between PMU of sibling HT threads.
330 * In either case, the kernel needs to handle conflicting
331 * accesses to those extra, shared, regs. The data structure
332 * to manage those registers is stored in cpu_hw_event.
339 int idx
; /* per_xxx->regs[] reg index */
340 bool extra_msr_access
;
343 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
346 .config_mask = (m), \
347 .valid_mask = (vm), \
348 .idx = EXTRA_REG_##i, \
349 .extra_msr_access = true, \
352 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
353 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
355 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
356 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
357 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
359 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
360 INTEL_UEVENT_EXTRA_REG(c, \
361 MSR_PEBS_LD_LAT_THRESHOLD, \
365 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
367 union perf_capabilities
{
375 * PMU supports separate counter range for writing
378 u64 full_width_write
:1;
383 struct x86_pmu_quirk
{
384 struct x86_pmu_quirk
*next
;
388 union x86_pmu_config
{
409 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
412 * struct x86_pmu - generic x86 pmu
416 * Generic x86 PMC bits
420 int (*handle_irq
)(struct pt_regs
*);
421 void (*disable_all
)(void);
422 void (*enable_all
)(int added
);
423 void (*enable
)(struct perf_event
*);
424 void (*disable
)(struct perf_event
*);
425 int (*hw_config
)(struct perf_event
*event
);
426 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
429 int (*addr_offset
)(int index
, bool eventsel
);
430 int (*rdpmc_index
)(int index
);
431 u64 (*event_map
)(int);
434 int num_counters_fixed
;
438 unsigned long events_maskl
;
439 unsigned long events_mask
[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT
)];
444 struct event_constraint
*
445 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
446 struct perf_event
*event
);
448 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
449 struct perf_event
*event
);
450 struct event_constraint
*event_constraints
;
451 struct x86_pmu_quirk
*quirks
;
452 int perfctr_second_write
;
458 int attr_rdpmc_broken
;
460 struct attribute
**format_attrs
;
461 struct attribute
**event_attrs
;
463 ssize_t (*events_sysfs_show
)(char *page
, u64 config
);
464 struct attribute
**cpu_events
;
469 int (*cpu_prepare
)(int cpu
);
470 void (*cpu_starting
)(int cpu
);
471 void (*cpu_dying
)(int cpu
);
472 void (*cpu_dead
)(int cpu
);
474 void (*check_microcode
)(void);
475 void (*flush_branch_stack
)(void);
478 * Intel Arch Perfmon v2+
481 union perf_capabilities intel_cap
;
484 * Intel DebugStore bits
491 int pebs_record_size
;
492 void (*drain_pebs
)(struct pt_regs
*regs
);
493 struct event_constraint
*pebs_constraints
;
494 void (*pebs_aliases
)(struct perf_event
*event
);
500 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
501 int lbr_nr
; /* hardware stack size */
502 u64 lbr_sel_mask
; /* LBR_SELECT valid bits */
503 const int *lbr_sel_map
; /* lbr_select mappings */
504 bool lbr_double_abort
; /* duplicated lbr aborts */
507 * Extra registers for events
509 struct extra_reg
*extra_regs
;
510 unsigned int er_flags
;
513 * Intel host/guest support (KVM)
515 struct perf_guest_switch_msr
*(*guest_get_msrs
)(int *nr
);
518 #define x86_add_quirk(func_) \
520 static struct x86_pmu_quirk __quirk __initdata = { \
523 __quirk.next = x86_pmu.quirks; \
524 x86_pmu.quirks = &__quirk; \
527 #define ERF_NO_HT_SHARING 1
528 #define ERF_HAS_RSP_1 2
530 #define EVENT_VAR(_id) event_attr_##_id
531 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
533 #define EVENT_ATTR(_name, _id) \
534 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
535 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
536 .id = PERF_COUNT_HW_##_id, \
540 #define EVENT_ATTR_STR(_name, v, str) \
541 static struct perf_pmu_events_attr event_attr_##v = { \
542 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
547 extern struct x86_pmu x86_pmu __read_mostly
;
549 DECLARE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
551 int x86_perf_event_set_period(struct perf_event
*event
);
554 * Generalized hw caching related hw_event table, filled
555 * in on a per model basis. A value of 0 means
556 * 'not supported', -1 means 'hw_event makes no sense on
557 * this CPU', any other value means the raw hw_event
561 #define C(x) PERF_COUNT_HW_CACHE_##x
563 extern u64 __read_mostly hw_cache_event_ids
564 [PERF_COUNT_HW_CACHE_MAX
]
565 [PERF_COUNT_HW_CACHE_OP_MAX
]
566 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
567 extern u64 __read_mostly hw_cache_extra_regs
568 [PERF_COUNT_HW_CACHE_MAX
]
569 [PERF_COUNT_HW_CACHE_OP_MAX
]
570 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
572 u64
x86_perf_event_update(struct perf_event
*event
);
574 static inline unsigned int x86_pmu_config_addr(int index
)
576 return x86_pmu
.eventsel
+ (x86_pmu
.addr_offset
?
577 x86_pmu
.addr_offset(index
, true) : index
);
580 static inline unsigned int x86_pmu_event_addr(int index
)
582 return x86_pmu
.perfctr
+ (x86_pmu
.addr_offset
?
583 x86_pmu
.addr_offset(index
, false) : index
);
586 static inline int x86_pmu_rdpmc_index(int index
)
588 return x86_pmu
.rdpmc_index
? x86_pmu
.rdpmc_index(index
) : index
;
591 int x86_setup_perfctr(struct perf_event
*event
);
593 int x86_pmu_hw_config(struct perf_event
*event
);
595 void x86_pmu_disable_all(void);
597 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
600 u64 disable_mask
= __this_cpu_read(cpu_hw_events
.perf_ctr_virt_mask
);
602 if (hwc
->extra_reg
.reg
)
603 wrmsrl(hwc
->extra_reg
.reg
, hwc
->extra_reg
.config
);
604 wrmsrl(hwc
->config_base
, (hwc
->config
| enable_mask
) & ~disable_mask
);
607 void x86_pmu_enable_all(int added
);
609 int perf_assign_events(struct perf_event
**events
, int n
,
610 int wmin
, int wmax
, int *assign
);
611 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
613 void x86_pmu_stop(struct perf_event
*event
, int flags
);
615 static inline void x86_pmu_disable_event(struct perf_event
*event
)
617 struct hw_perf_event
*hwc
= &event
->hw
;
619 wrmsrl(hwc
->config_base
, hwc
->config
);
622 void x86_pmu_enable_event(struct perf_event
*event
);
624 int x86_pmu_handle_irq(struct pt_regs
*regs
);
626 extern struct event_constraint emptyconstraint
;
628 extern struct event_constraint unconstrained
;
630 static inline bool kernel_ip(unsigned long ip
)
633 return ip
> PAGE_OFFSET
;
640 * Not all PMUs provide the right context information to place the reported IP
641 * into full context. Specifically segment registers are typically not
644 * Assuming the address is a linear address (it is for IBS), we fake the CS and
645 * vm86 mode using the known zero-based code segment and 'fix up' the registers
648 * Intel PEBS/LBR appear to typically provide the effective address, nothing
649 * much we can do about that but pray and treat it like a linear address.
651 static inline void set_linear_ip(struct pt_regs
*regs
, unsigned long ip
)
653 regs
->cs
= kernel_ip(ip
) ? __KERNEL_CS
: __USER_CS
;
654 if (regs
->flags
& X86_VM_MASK
)
655 regs
->flags
^= (PERF_EFLAGS_VM
| X86_VM_MASK
);
659 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
);
660 ssize_t
intel_event_sysfs_show(char *page
, u64 config
);
662 #ifdef CONFIG_CPU_SUP_AMD
664 int amd_pmu_init(void);
666 #else /* CONFIG_CPU_SUP_AMD */
668 static inline int amd_pmu_init(void)
673 #endif /* CONFIG_CPU_SUP_AMD */
675 #ifdef CONFIG_CPU_SUP_INTEL
677 int intel_pmu_save_and_restart(struct perf_event
*event
);
679 struct event_constraint
*
680 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
);
682 struct intel_shared_regs
*allocate_shared_regs(int cpu
);
684 int intel_pmu_init(void);
686 void init_debug_store_on_cpu(int cpu
);
688 void fini_debug_store_on_cpu(int cpu
);
690 void release_ds_buffers(void);
692 void reserve_ds_buffers(void);
694 extern struct event_constraint bts_constraint
;
696 void intel_pmu_enable_bts(u64 config
);
698 void intel_pmu_disable_bts(void);
700 int intel_pmu_drain_bts_buffer(void);
702 extern struct event_constraint intel_core2_pebs_event_constraints
[];
704 extern struct event_constraint intel_atom_pebs_event_constraints
[];
706 extern struct event_constraint intel_slm_pebs_event_constraints
[];
708 extern struct event_constraint intel_nehalem_pebs_event_constraints
[];
710 extern struct event_constraint intel_westmere_pebs_event_constraints
[];
712 extern struct event_constraint intel_snb_pebs_event_constraints
[];
714 extern struct event_constraint intel_ivb_pebs_event_constraints
[];
716 extern struct event_constraint intel_hsw_pebs_event_constraints
[];
718 struct event_constraint
*intel_pebs_constraints(struct perf_event
*event
);
720 void intel_pmu_pebs_enable(struct perf_event
*event
);
722 void intel_pmu_pebs_disable(struct perf_event
*event
);
724 void intel_pmu_pebs_enable_all(void);
726 void intel_pmu_pebs_disable_all(void);
728 void intel_ds_init(void);
730 void intel_pmu_lbr_reset(void);
732 void intel_pmu_lbr_enable(struct perf_event
*event
);
734 void intel_pmu_lbr_disable(struct perf_event
*event
);
736 void intel_pmu_lbr_enable_all(void);
738 void intel_pmu_lbr_disable_all(void);
740 void intel_pmu_lbr_read(void);
742 void intel_pmu_lbr_init_core(void);
744 void intel_pmu_lbr_init_nhm(void);
746 void intel_pmu_lbr_init_atom(void);
748 void intel_pmu_lbr_init_snb(void);
750 int intel_pmu_setup_lbr_filter(struct perf_event
*event
);
752 int p4_pmu_init(void);
754 int p6_pmu_init(void);
756 int knc_pmu_init(void);
758 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
761 #else /* CONFIG_CPU_SUP_INTEL */
763 static inline void reserve_ds_buffers(void)
767 static inline void release_ds_buffers(void)
771 static inline int intel_pmu_init(void)
776 static inline struct intel_shared_regs
*allocate_shared_regs(int cpu
)
781 #endif /* CONFIG_CPU_SUP_INTEL */