arch/x86/kernel/cpu/perf_event.h

   1 /*
   2  * Performance events x86 architecture header
   3  *
   4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
   6  *  Copyright (C) 2009 Jaswinder Singh Rajput
   7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
   8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
   9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  11  *
  12  *  For licencing details see kernel-base/COPYING
  13  */
  14
  15 #include <linux/perf_event.h>
  16
  17 #if 0
  18 #undef wrmsrl
  19 #define wrmsrl(msr, val)                                                \
  20 do {                                                                    \
  21         unsigned int _msr = (msr);                                      \
  22         u64 _val = (val);                                               \
  23         trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr),         \
  24                         (unsigned long long)(_val));                    \
  25         native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32));       \
  26 } while (0)
  27 #endif
  28
  29 /*
  30  *          |   NHM/WSM    |      SNB     |
  31  * register -------------------------------
  32  *          |  HT  | no HT |  HT  | no HT |
  33  *-----------------------------------------
  34  * offcore  | core | core  | cpu  | core  |
  35  * lbr_sel  | core | core  | cpu  | core  |
  36  * ld_lat   | cpu  | core  | cpu  | core  |
  37  *-----------------------------------------
  38  *
  39  * Given that there is a small number of shared regs,
  40  * we can pre-allocate their slot in the per-cpu
  41  * per-core reg tables.
  42  */
  43 enum extra_reg_type {
  44         EXTRA_REG_NONE  = -1,   /* not used */
  45
  46         EXTRA_REG_RSP_0 = 0,    /* offcore_response_0 */
  47         EXTRA_REG_RSP_1 = 1,    /* offcore_response_1 */
  48         EXTRA_REG_LBR   = 2,    /* lbr_select */
  49         EXTRA_REG_LDLAT = 3,    /* ld_lat_threshold */
  50
  51         EXTRA_REG_MAX           /* number of entries needed */
  52 };
  53
  54 struct event_constraint {
  55         union {
  56                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  57                 u64             idxmsk64;
  58         };
  59         u64     code;
  60         u64     cmask;
  61         int     weight;
  62         int     overlap;
  63         int     flags;
  64 };
  65 /*
  66  * struct hw_perf_event.flags flags
  67  */
  68 #define PERF_X86_EVENT_PEBS_LDLAT       0x1 /* ld+ldlat data address sampling */
  69 #define PERF_X86_EVENT_PEBS_ST          0x2 /* st data address sampling */
  70 #define PERF_X86_EVENT_PEBS_ST_HSW      0x4 /* haswell style datala, store */
  71 #define PERF_X86_EVENT_COMMITTED        0x8 /* event passed commit_txn */
  72 #define PERF_X86_EVENT_PEBS_LD_HSW      0x10 /* haswell style datala, load */
  73 #define PERF_X86_EVENT_PEBS_NA_HSW      0x20 /* haswell style datala, unknown */
  74 #define PERF_X86_EVENT_RDPMC_ALLOWED    0x40 /* grant rdpmc permission */
  75
  76
  77 struct amd_nb {
  78         int nb_id;  /* NorthBridge id */
  79         int refcnt; /* reference count */
  80         struct perf_event *owners[X86_PMC_IDX_MAX];
  81         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  82 };
  83
  84 /* The maximal number of PEBS events: */
  85 #define MAX_PEBS_EVENTS         8
  86
  87 /*
  88  * A debug store configuration.
  89  *
  90  * We only support architectures that use 64bit fields.
  91  */
  92 struct debug_store {
  93         u64     bts_buffer_base;
  94         u64     bts_index;
  95         u64     bts_absolute_maximum;
  96         u64     bts_interrupt_threshold;
  97         u64     pebs_buffer_base;
  98         u64     pebs_index;
  99         u64     pebs_absolute_maximum;
 100         u64     pebs_interrupt_threshold;
 101         u64     pebs_event_reset[MAX_PEBS_EVENTS];
 102 };
 103
 104 /*
 105  * Per register state.
 106  */
 107 struct er_account {
 108         raw_spinlock_t          lock;   /* per-core: protect structure */
 109         u64                 config;     /* extra MSR config */
 110         u64                 reg;        /* extra MSR number */
 111         atomic_t            ref;        /* reference count */
 112 };
 113
 114 /*
 115  * Per core/cpu state
 116  *
 117  * Used to coordinate shared registers between HT threads or
 118  * among events on a single PMU.
 119  */
 120 struct intel_shared_regs {
 121         struct er_account       regs[EXTRA_REG_MAX];
 122         int                     refcnt;         /* per-core: #HT threads */
 123         unsigned                core_id;        /* per-core: core id */
 124 };
 125
 126 #define MAX_LBR_ENTRIES         16
 127
 128 struct cpu_hw_events {
 129         /*
 130          * Generic x86 PMC bits
 131          */
 132         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
 133         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 134         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
 135         int                     enabled;
 136
 137         int                     n_events; /* the # of events in the below arrays */
 138         int                     n_added;  /* the # last events in the below arrays;
 139                                              they've never been enabled yet */
 140         int                     n_txn;    /* the # last events in the below arrays;
 141                                              added in the current transaction */
 142         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
 143         u64                     tags[X86_PMC_IDX_MAX];
 144         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
 145
 146         unsigned int            group_flag;
 147         int                     is_fake;
 148
 149         /*
 150          * Intel DebugStore bits
 151          */
 152         struct debug_store      *ds;
 153         u64                     pebs_enabled;
 154
 155         /*
 156          * Intel LBR bits
 157          */
 158         int                             lbr_users;
 159         void                            *lbr_context;
 160         struct perf_branch_stack        lbr_stack;
 161         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
 162         struct er_account               *lbr_sel;
 163         u64                             br_sel;
 164
 165         /*
 166          * Intel host/guest exclude bits
 167          */
 168         u64                             intel_ctrl_guest_mask;
 169         u64                             intel_ctrl_host_mask;
 170         struct perf_guest_switch_msr    guest_switch_msrs[X86_PMC_IDX_MAX];
 171
 172         /*
 173          * Intel checkpoint mask
 174          */
 175         u64                             intel_cp_status;
 176
 177         /*
 178          * manage shared (per-core, per-cpu) registers
 179          * used on Intel NHM/WSM/SNB
 180          */
 181         struct intel_shared_regs        *shared_regs;
 182
 183         /*
 184          * AMD specific bits
 185          */
 186         struct amd_nb                   *amd_nb;
 187         /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
 188         u64                             perf_ctr_virt_mask;
 189
 190         void                            *kfree_on_online;
 191 };
 192
 193 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
 194         { .idxmsk64 = (n) },            \
 195         .code = (c),                    \
 196         .cmask = (m),                   \
 197         .weight = (w),                  \
 198         .overlap = (o),                 \
 199         .flags = f,                     \
 200 }
 201
 202 #define EVENT_CONSTRAINT(c, n, m)       \
 203         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
 204
 205 /*
 206  * The overlap flag marks event constraints with overlapping counter
 207  * masks. This is the case if the counter mask of such an event is not
 208  * a subset of any other counter mask of a constraint with an equal or
 209  * higher weight, e.g.:
 210  *
 211  *  c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
 212  *  c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
 213  *  c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
 214  *
 215  * The event scheduler may not select the correct counter in the first
 216  * cycle because it needs to know which subsequent events will be
 217  * scheduled. It may fail to schedule the events then. So we set the
 218  * overlap flag for such constraints to give the scheduler a hint which
 219  * events to select for counter rescheduling.
 220  *
 221  * Care must be taken as the rescheduling algorithm is O(n!) which
 222  * will increase scheduling cycles for an over-commited system
 223  * dramatically.  The number of such EVENT_CONSTRAINT_OVERLAP() macros
 224  * and its counter masks must be kept at a minimum.
 225  */
 226 #define EVENT_CONSTRAINT_OVERLAP(c, n, m)       \
 227         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
 228
 229 /*
 230  * Constraint on the Event code.
 231  */
 232 #define INTEL_EVENT_CONSTRAINT(c, n)    \
 233         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
 234
 235 /*
 236  * Constraint on the Event code + UMask + fixed-mask
 237  *
 238  * filter mask to validate fixed counter events.
 239  * the following filters disqualify for fixed counters:
 240  *  - inv
 241  *  - edge
 242  *  - cnt-mask
 243  *  - in_tx
 244  *  - in_tx_checkpointed
 245  *  The other filters are supported by fixed counters.
 246  *  The any-thread option is supported starting with v3.
 247  */
 248 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
 249 #define FIXED_EVENT_CONSTRAINT(c, n)    \
 250         EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
 251
 252 /*
 253  * Constraint on the Event code + UMask
 254  */
 255 #define INTEL_UEVENT_CONSTRAINT(c, n)   \
 256         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
 257
 258 /* Like UEVENT_CONSTRAINT, but match flags too */
 259 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n)     \
 260         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
 261
 262 #define INTEL_PLD_CONSTRAINT(c, n)      \
 263         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 264                            HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
 265
 266 #define INTEL_PST_CONSTRAINT(c, n)      \
 267         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 268                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
 269
 270 /* Event constraint, but match on all event flags too. */
 271 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
 272         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
 273
 274 /* Check only flags, but allow all event/umask */
 275 #define INTEL_ALL_EVENT_CONSTRAINT(code, n)     \
 276         EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
 277
 278 /* Check flags and event code, and set the HSW store flag */
 279 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
 280         __EVENT_CONSTRAINT(code, n,                     \
 281                           ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
 282                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
 283
 284 /* Check flags and event code, and set the HSW load flag */
 285 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
 286         __EVENT_CONSTRAINT(code, n,                     \
 287                           ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
 288                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
 289
 290 /* Check flags and event code/umask, and set the HSW store flag */
 291 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
 292         __EVENT_CONSTRAINT(code, n,                     \
 293                           INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 294                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
 295
 296 /* Check flags and event code/umask, and set the HSW load flag */
 297 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
 298         __EVENT_CONSTRAINT(code, n,                     \
 299                           INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
 300                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
 301
 302 /* Check flags and event code/umask, and set the HSW N/A flag */
 303 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
 304         __EVENT_CONSTRAINT(code, n,                     \
 305                           INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \
 306                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
 307
 308
 309 /*
 310  * We define the end marker as having a weight of -1
 311  * to enable blacklisting of events using a counter bitmask
 312  * of zero and thus a weight of zero.
 313  * The end marker has a weight that cannot possibly be
 314  * obtained from counting the bits in the bitmask.
 315  */
 316 #define EVENT_CONSTRAINT_END { .weight = -1 }
 317
 318 /*
 319  * Check for end marker with weight == -1
 320  */
 321 #define for_each_event_constraint(e, c) \
 322         for ((e) = (c); (e)->weight != -1; (e)++)
 323
 324 /*
 325  * Extra registers for specific events.
 326  *
 327  * Some events need large masks and require external MSRs.
 328  * Those extra MSRs end up being shared for all events on
 329  * a PMU and sometimes between PMU of sibling HT threads.
 330  * In either case, the kernel needs to handle conflicting
 331  * accesses to those extra, shared, regs. The data structure
 332  * to manage those registers is stored in cpu_hw_event.
 333  */
 334 struct extra_reg {
 335         unsigned int            event;
 336         unsigned int            msr;
 337         u64                     config_mask;
 338         u64                     valid_mask;
 339         int                     idx;  /* per_xxx->regs[] reg index */
 340         bool                    extra_msr_access;
 341 };
 342
 343 #define EVENT_EXTRA_REG(e, ms, m, vm, i) {      \
 344         .event = (e),                   \
 345         .msr = (ms),                    \
 346         .config_mask = (m),             \
 347         .valid_mask = (vm),             \
 348         .idx = EXTRA_REG_##i,           \
 349         .extra_msr_access = true,       \
 350         }
 351
 352 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)      \
 353         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
 354
 355 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
 356         EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
 357                         ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
 358
 359 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
 360         INTEL_UEVENT_EXTRA_REG(c, \
 361                                MSR_PEBS_LD_LAT_THRESHOLD, \
 362                                0xffff, \
 363                                LDLAT)
 364
 365 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
 366
 367 union perf_capabilities {
 368         struct {
 369                 u64     lbr_format:6;
 370                 u64     pebs_trap:1;
 371                 u64     pebs_arch_reg:1;
 372                 u64     pebs_format:4;
 373                 u64     smm_freeze:1;
 374                 /*
 375                  * PMU supports separate counter range for writing
 376                  * values > 32bit.
 377                  */
 378                 u64     full_width_write:1;
 379         };
 380         u64     capabilities;
 381 };
 382
 383 struct x86_pmu_quirk {
 384         struct x86_pmu_quirk *next;
 385         void (*func)(void);
 386 };
 387
 388 union x86_pmu_config {
 389         struct {
 390                 u64 event:8,
 391                     umask:8,
 392                     usr:1,
 393                     os:1,
 394                     edge:1,
 395                     pc:1,
 396                     interrupt:1,
 397                     __reserved1:1,
 398                     en:1,
 399                     inv:1,
 400                     cmask:8,
 401                     event2:4,
 402                     __reserved2:4,
 403                     go:1,
 404                     ho:1;
 405         } bits;
 406         u64 value;
 407 };
 408
 409 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
 410
 411 enum {
 412         x86_lbr_exclusive_lbr,
 413         x86_lbr_exclusive_bts,
 414         x86_lbr_exclusive_pt,
 415         x86_lbr_exclusive_max,
 416 };
 417
 418 /*
 419  * struct x86_pmu - generic x86 pmu
 420  */
 421 struct x86_pmu {
 422         /*
 423          * Generic x86 PMC bits
 424          */
 425         const char      *name;
 426         int             version;
 427         int             (*handle_irq)(struct pt_regs *);
 428         void            (*disable_all)(void);
 429         void            (*enable_all)(int added);
 430         void            (*enable)(struct perf_event *);
 431         void            (*disable)(struct perf_event *);
 432         int             (*hw_config)(struct perf_event *event);
 433         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
 434         unsigned        eventsel;
 435         unsigned        perfctr;
 436         int             (*addr_offset)(int index, bool eventsel);
 437         int             (*rdpmc_index)(int index);
 438         u64             (*event_map)(int);
 439         int             max_events;
 440         int             num_counters;
 441         int             num_counters_fixed;
 442         int             cntval_bits;
 443         u64             cntval_mask;
 444         union {
 445                         unsigned long events_maskl;
 446                         unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
 447         };
 448         int             events_mask_len;
 449         int             apic;
 450         u64             max_period;
 451         struct event_constraint *
 452                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
 453                                                  struct perf_event *event);
 454
 455         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
 456                                                  struct perf_event *event);
 457         struct event_constraint *event_constraints;
 458         struct x86_pmu_quirk *quirks;
 459         int             perfctr_second_write;
 460         bool            late_ack;
 461         unsigned        (*limit_period)(struct perf_event *event, unsigned l);
 462
 463         /*
 464          * sysfs attrs
 465          */
 466         int             attr_rdpmc_broken;
 467         int             attr_rdpmc;
 468         struct attribute **format_attrs;
 469         struct attribute **event_attrs;
 470
 471         ssize_t         (*events_sysfs_show)(char *page, u64 config);
 472         struct attribute **cpu_events;
 473
 474         /*
 475          * CPU Hotplug hooks
 476          */
 477         int             (*cpu_prepare)(int cpu);
 478         void            (*cpu_starting)(int cpu);
 479         void            (*cpu_dying)(int cpu);
 480         void            (*cpu_dead)(int cpu);
 481
 482         void            (*check_microcode)(void);
 483         void            (*sched_task)(struct perf_event_context *ctx,
 484                                       bool sched_in);
 485
 486         /*
 487          * Intel Arch Perfmon v2+
 488          */
 489         u64                     intel_ctrl;
 490         union perf_capabilities intel_cap;
 491
 492         /*
 493          * Intel DebugStore bits
 494          */
 495         unsigned int    bts             :1,
 496                         bts_active      :1,
 497                         pebs            :1,
 498                         pebs_active     :1,
 499                         pebs_broken     :1;
 500         int             pebs_record_size;
 501         void            (*drain_pebs)(struct pt_regs *regs);
 502         struct event_constraint *pebs_constraints;
 503         void            (*pebs_aliases)(struct perf_event *event);
 504         int             max_pebs_events;
 505
 506         /*
 507          * Intel LBR
 508          */
 509         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
 510         int             lbr_nr;                    /* hardware stack size */
 511         u64             lbr_sel_mask;              /* LBR_SELECT valid bits */
 512         const int       *lbr_sel_map;              /* lbr_select mappings */
 513         bool            lbr_double_abort;          /* duplicated lbr aborts */
 514
 515         /*
 516          * Intel PT/LBR/BTS are exclusive
 517          */
 518         atomic_t        lbr_exclusive[x86_lbr_exclusive_max];
 519
 520         /*
 521          * Extra registers for events
 522          */
 523         struct extra_reg *extra_regs;
 524         unsigned int flags;
 525
 526         /*
 527          * Intel host/guest support (KVM)
 528          */
 529         struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
 530 };
 531
 532 struct x86_perf_task_context {
 533         u64 lbr_from[MAX_LBR_ENTRIES];
 534         u64 lbr_to[MAX_LBR_ENTRIES];
 535         int lbr_callstack_users;
 536         int lbr_stack_state;
 537 };
 538
 539 #define x86_add_quirk(func_)                                            \
 540 do {                                                                    \
 541         static struct x86_pmu_quirk __quirk __initdata = {              \
 542                 .func = func_,                                          \
 543         };                                                              \
 544         __quirk.next = x86_pmu.quirks;                                  \
 545         x86_pmu.quirks = &__quirk;                                      \
 546 } while (0)
 547
 548 /*
 549  * x86_pmu flags
 550  */
 551 #define PMU_FL_NO_HT_SHARING    0x1 /* no hyper-threading resource sharing */
 552 #define PMU_FL_HAS_RSP_1        0x2 /* has 2 equivalent offcore_rsp regs   */
 553
 554 #define EVENT_VAR(_id)  event_attr_##_id
 555 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
 556
 557 #define EVENT_ATTR(_name, _id)                                          \
 558 static struct perf_pmu_events_attr EVENT_VAR(_id) = {                   \
 559         .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
 560         .id             = PERF_COUNT_HW_##_id,                          \
 561         .event_str      = NULL,                                         \
 562 };
 563
 564 #define EVENT_ATTR_STR(_name, v, str)                                   \
 565 static struct perf_pmu_events_attr event_attr_##v = {                   \
 566         .attr           = __ATTR(_name, 0444, events_sysfs_show, NULL), \
 567         .id             = 0,                                            \
 568         .event_str      = str,                                          \
 569 };
 570
 571 extern struct x86_pmu x86_pmu __read_mostly;
 572
 573 static inline bool x86_pmu_has_lbr_callstack(void)
 574 {
 575         return  x86_pmu.lbr_sel_map &&
 576                 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
 577 }
 578
 579 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 580
 581 int x86_perf_event_set_period(struct perf_event *event);
 582
 583 /*
 584  * Generalized hw caching related hw_event table, filled
 585  * in on a per model basis. A value of 0 means
 586  * 'not supported', -1 means 'hw_event makes no sense on
 587  * this CPU', any other value means the raw hw_event
 588  * ID.
 589  */
 590
 591 #define C(x) PERF_COUNT_HW_CACHE_##x
 592
 593 extern u64 __read_mostly hw_cache_event_ids
 594                                 [PERF_COUNT_HW_CACHE_MAX]
 595                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 596                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 597 extern u64 __read_mostly hw_cache_extra_regs
 598                                 [PERF_COUNT_HW_CACHE_MAX]
 599                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 600                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 601
 602 u64 x86_perf_event_update(struct perf_event *event);
 603
 604 static inline unsigned int x86_pmu_config_addr(int index)
 605 {
 606         return x86_pmu.eventsel + (x86_pmu.addr_offset ?
 607                                    x86_pmu.addr_offset(index, true) : index);
 608 }
 609
 610 static inline unsigned int x86_pmu_event_addr(int index)
 611 {
 612         return x86_pmu.perfctr + (x86_pmu.addr_offset ?
 613                                   x86_pmu.addr_offset(index, false) : index);
 614 }
 615
 616 static inline int x86_pmu_rdpmc_index(int index)
 617 {
 618         return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
 619 }
 620
 621 int x86_add_exclusive(unsigned int what);
 622
 623 void x86_del_exclusive(unsigned int what);
 624
 625 void hw_perf_lbr_event_destroy(struct perf_event *event);
 626
 627 int x86_setup_perfctr(struct perf_event *event);
 628
 629 int x86_pmu_hw_config(struct perf_event *event);
 630
 631 void x86_pmu_disable_all(void);
 632
 633 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 634                                           u64 enable_mask)
 635 {
 636         u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
 637
 638         if (hwc->extra_reg.reg)
 639                 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
 640         wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
 641 }
 642
 643 void x86_pmu_enable_all(int added);
 644
 645 int perf_assign_events(struct perf_event **events, int n,
 646                         int wmin, int wmax, int *assign);
 647 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
 648
 649 void x86_pmu_stop(struct perf_event *event, int flags);
 650
 651 static inline void x86_pmu_disable_event(struct perf_event *event)
 652 {
 653         struct hw_perf_event *hwc = &event->hw;
 654
 655         wrmsrl(hwc->config_base, hwc->config);
 656 }
 657
 658 void x86_pmu_enable_event(struct perf_event *event);
 659
 660 int x86_pmu_handle_irq(struct pt_regs *regs);
 661
 662 extern struct event_constraint emptyconstraint;
 663
 664 extern struct event_constraint unconstrained;
 665
 666 static inline bool kernel_ip(unsigned long ip)
 667 {
 668 #ifdef CONFIG_X86_32
 669         return ip > PAGE_OFFSET;
 670 #else
 671         return (long)ip < 0;
 672 #endif
 673 }
 674
 675 /*
 676  * Not all PMUs provide the right context information to place the reported IP
 677  * into full context. Specifically segment registers are typically not
 678  * supplied.
 679  *
 680  * Assuming the address is a linear address (it is for IBS), we fake the CS and
 681  * vm86 mode using the known zero-based code segment and 'fix up' the registers
 682  * to reflect this.
 683  *
 684  * Intel PEBS/LBR appear to typically provide the effective address, nothing
 685  * much we can do about that but pray and treat it like a linear address.
 686  */
 687 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
 688 {
 689         regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
 690         if (regs->flags & X86_VM_MASK)
 691                 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
 692         regs->ip = ip;
 693 }
 694
 695 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
 696 ssize_t intel_event_sysfs_show(char *page, u64 config);
 697
 698 #ifdef CONFIG_CPU_SUP_AMD
 699
 700 int amd_pmu_init(void);
 701
 702 #else /* CONFIG_CPU_SUP_AMD */
 703
 704 static inline int amd_pmu_init(void)
 705 {
 706         return 0;
 707 }
 708
 709 #endif /* CONFIG_CPU_SUP_AMD */
 710
 711 #ifdef CONFIG_CPU_SUP_INTEL
 712
 713 static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
 714 {
 715         /* user explicitly requested branch sampling */
 716         if (has_branch_stack(event))
 717                 return true;
 718
 719         /* implicit branch sampling to correct PEBS skid */
 720         if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
 721             x86_pmu.intel_cap.pebs_format < 2)
 722                 return true;
 723
 724         return false;
 725 }
 726
 727 static inline bool intel_pmu_has_bts(struct perf_event *event)
 728 {
 729         if (event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
 730             !event->attr.freq && event->hw.sample_period == 1)
 731                 return true;
 732
 733         return false;
 734 }
 735
 736 int intel_pmu_save_and_restart(struct perf_event *event);
 737
 738 struct event_constraint *
 739 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
 740
 741 struct intel_shared_regs *allocate_shared_regs(int cpu);
 742
 743 int intel_pmu_init(void);
 744
 745 void init_debug_store_on_cpu(int cpu);
 746
 747 void fini_debug_store_on_cpu(int cpu);
 748
 749 void release_ds_buffers(void);
 750
 751 void reserve_ds_buffers(void);
 752
 753 extern struct event_constraint bts_constraint;
 754
 755 void intel_pmu_enable_bts(u64 config);
 756
 757 void intel_pmu_disable_bts(void);
 758
 759 int intel_pmu_drain_bts_buffer(void);
 760
 761 extern struct event_constraint intel_core2_pebs_event_constraints[];
 762
 763 extern struct event_constraint intel_atom_pebs_event_constraints[];
 764
 765 extern struct event_constraint intel_slm_pebs_event_constraints[];
 766
 767 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
 768
 769 extern struct event_constraint intel_westmere_pebs_event_constraints[];
 770
 771 extern struct event_constraint intel_snb_pebs_event_constraints[];
 772
 773 extern struct event_constraint intel_ivb_pebs_event_constraints[];
 774
 775 extern struct event_constraint intel_hsw_pebs_event_constraints[];
 776
 777 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
 778
 779 void intel_pmu_pebs_enable(struct perf_event *event);
 780
 781 void intel_pmu_pebs_disable(struct perf_event *event);
 782
 783 void intel_pmu_pebs_enable_all(void);
 784
 785 void intel_pmu_pebs_disable_all(void);
 786
 787 void intel_ds_init(void);
 788
 789 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
 790
 791 void intel_pmu_lbr_reset(void);
 792
 793 void intel_pmu_lbr_enable(struct perf_event *event);
 794
 795 void intel_pmu_lbr_disable(struct perf_event *event);
 796
 797 void intel_pmu_lbr_enable_all(void);
 798
 799 void intel_pmu_lbr_disable_all(void);
 800
 801 void intel_pmu_lbr_read(void);
 802
 803 void intel_pmu_lbr_init_core(void);
 804
 805 void intel_pmu_lbr_init_nhm(void);
 806
 807 void intel_pmu_lbr_init_atom(void);
 808
 809 void intel_pmu_lbr_init_snb(void);
 810
 811 void intel_pmu_lbr_init_hsw(void);
 812
 813 int intel_pmu_setup_lbr_filter(struct perf_event *event);
 814
 815 void intel_pt_interrupt(void);
 816
 817 int intel_bts_interrupt(void);
 818
 819 void intel_bts_enable_local(void);
 820
 821 void intel_bts_disable_local(void);
 822
 823 int p4_pmu_init(void);
 824
 825 int p6_pmu_init(void);
 826
 827 int knc_pmu_init(void);
 828
 829 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
 830                           char *page);
 831
 832 #else /* CONFIG_CPU_SUP_INTEL */
 833
 834 static inline void reserve_ds_buffers(void)
 835 {
 836 }
 837
 838 static inline void release_ds_buffers(void)
 839 {
 840 }
 841
 842 static inline int intel_pmu_init(void)
 843 {
 844         return 0;
 845 }
 846
 847 static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
 848 {
 849         return NULL;
 850 }
 851
 852 #endif /* CONFIG_CPU_SUP_INTEL */