4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15 #include <linux/watchdog.h>
17 #include <asm/cpufeature.h>
18 #include <asm/hardirq.h>
21 #include "perf_event.h"
24 * Intel PerfMon, used on Core and later.
26 static u64 intel_perfmon_event_map
[PERF_COUNT_HW_MAX
] __read_mostly
=
28 [PERF_COUNT_HW_CPU_CYCLES
] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS
] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES
] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES
] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS
] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES
] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES
] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES
] = 0x0300, /* pseudo-encoding */
38 static struct event_constraint intel_core_event_constraints
[] __read_mostly
=
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
49 static struct event_constraint intel_core2_event_constraints
[] __read_mostly
=
51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
67 static struct event_constraint intel_nehalem_event_constraints
[] __read_mostly
=
69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
83 static struct extra_reg intel_nehalem_extra_regs
[] __read_mostly
=
85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0xffff, RSP_0
),
87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
91 static struct event_constraint intel_westmere_event_constraints
[] __read_mostly
=
93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
103 static struct event_constraint intel_snb_event_constraints
[] __read_mostly
=
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
126 static struct event_constraint intel_ivb_event_constraints
[] __read_mostly
=
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
150 static struct extra_reg intel_westmere_extra_regs
[] __read_mostly
=
152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0xffff, RSP_0
),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1
, 0xffff, RSP_1
),
155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
159 static struct event_constraint intel_v1_event_constraints
[] __read_mostly
=
164 static struct event_constraint intel_gen_event_constraints
[] __read_mostly
=
166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
172 static struct event_constraint intel_slm_event_constraints
[] __read_mostly
=
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
180 static struct extra_reg intel_snb_extra_regs
[] __read_mostly
= {
181 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
182 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x3f807f8fffull
, RSP_0
),
183 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1
, 0x3f807f8fffull
, RSP_1
),
184 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
188 static struct extra_reg intel_snbep_extra_regs
[] __read_mostly
= {
189 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
190 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x3fffff8fffull
, RSP_0
),
191 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1
, 0x3fffff8fffull
, RSP_1
),
192 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
196 EVENT_ATTR_STR(mem
-loads
, mem_ld_nhm
, "event=0x0b,umask=0x10,ldlat=3");
197 EVENT_ATTR_STR(mem
-loads
, mem_ld_snb
, "event=0xcd,umask=0x1,ldlat=3");
198 EVENT_ATTR_STR(mem
-stores
, mem_st_snb
, "event=0xcd,umask=0x2");
200 struct attribute
*nhm_events_attrs
[] = {
201 EVENT_PTR(mem_ld_nhm
),
205 struct attribute
*snb_events_attrs
[] = {
206 EVENT_PTR(mem_ld_snb
),
207 EVENT_PTR(mem_st_snb
),
211 static struct event_constraint intel_hsw_event_constraints
[] = {
212 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
213 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
214 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
215 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
216 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
217 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
218 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
219 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
220 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
221 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
222 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
223 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
225 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
226 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
227 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
228 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
233 struct event_constraint intel_bdw_event_constraints
[] = {
234 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
235 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
236 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
237 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
238 INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
242 static u64
intel_pmu_event_map(int hw_event
)
244 return intel_perfmon_event_map
[hw_event
];
247 #define SNB_DMND_DATA_RD (1ULL << 0)
248 #define SNB_DMND_RFO (1ULL << 1)
249 #define SNB_DMND_IFETCH (1ULL << 2)
250 #define SNB_DMND_WB (1ULL << 3)
251 #define SNB_PF_DATA_RD (1ULL << 4)
252 #define SNB_PF_RFO (1ULL << 5)
253 #define SNB_PF_IFETCH (1ULL << 6)
254 #define SNB_LLC_DATA_RD (1ULL << 7)
255 #define SNB_LLC_RFO (1ULL << 8)
256 #define SNB_LLC_IFETCH (1ULL << 9)
257 #define SNB_BUS_LOCKS (1ULL << 10)
258 #define SNB_STRM_ST (1ULL << 11)
259 #define SNB_OTHER (1ULL << 15)
260 #define SNB_RESP_ANY (1ULL << 16)
261 #define SNB_NO_SUPP (1ULL << 17)
262 #define SNB_LLC_HITM (1ULL << 18)
263 #define SNB_LLC_HITE (1ULL << 19)
264 #define SNB_LLC_HITS (1ULL << 20)
265 #define SNB_LLC_HITF (1ULL << 21)
266 #define SNB_LOCAL (1ULL << 22)
267 #define SNB_REMOTE (0xffULL << 23)
268 #define SNB_SNP_NONE (1ULL << 31)
269 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
270 #define SNB_SNP_MISS (1ULL << 33)
271 #define SNB_NO_FWD (1ULL << 34)
272 #define SNB_SNP_FWD (1ULL << 35)
273 #define SNB_HITM (1ULL << 36)
274 #define SNB_NON_DRAM (1ULL << 37)
276 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
277 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
278 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
280 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
281 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
284 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
285 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
287 #define SNB_L3_ACCESS SNB_RESP_ANY
288 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
290 static __initconst
const u64 snb_hw_cache_extra_regs
291 [PERF_COUNT_HW_CACHE_MAX
]
292 [PERF_COUNT_HW_CACHE_OP_MAX
]
293 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
297 [ C(RESULT_ACCESS
) ] = SNB_DMND_READ
|SNB_L3_ACCESS
,
298 [ C(RESULT_MISS
) ] = SNB_DMND_READ
|SNB_L3_MISS
,
301 [ C(RESULT_ACCESS
) ] = SNB_DMND_WRITE
|SNB_L3_ACCESS
,
302 [ C(RESULT_MISS
) ] = SNB_DMND_WRITE
|SNB_L3_MISS
,
304 [ C(OP_PREFETCH
) ] = {
305 [ C(RESULT_ACCESS
) ] = SNB_DMND_PREFETCH
|SNB_L3_ACCESS
,
306 [ C(RESULT_MISS
) ] = SNB_DMND_PREFETCH
|SNB_L3_MISS
,
311 [ C(RESULT_ACCESS
) ] = SNB_DMND_READ
|SNB_DRAM_ANY
,
312 [ C(RESULT_MISS
) ] = SNB_DMND_READ
|SNB_DRAM_REMOTE
,
315 [ C(RESULT_ACCESS
) ] = SNB_DMND_WRITE
|SNB_DRAM_ANY
,
316 [ C(RESULT_MISS
) ] = SNB_DMND_WRITE
|SNB_DRAM_REMOTE
,
318 [ C(OP_PREFETCH
) ] = {
319 [ C(RESULT_ACCESS
) ] = SNB_DMND_PREFETCH
|SNB_DRAM_ANY
,
320 [ C(RESULT_MISS
) ] = SNB_DMND_PREFETCH
|SNB_DRAM_REMOTE
,
325 static __initconst
const u64 snb_hw_cache_event_ids
326 [PERF_COUNT_HW_CACHE_MAX
]
327 [PERF_COUNT_HW_CACHE_OP_MAX
]
328 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
332 [ C(RESULT_ACCESS
) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
333 [ C(RESULT_MISS
) ] = 0x0151, /* L1D.REPLACEMENT */
336 [ C(RESULT_ACCESS
) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
337 [ C(RESULT_MISS
) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
339 [ C(OP_PREFETCH
) ] = {
340 [ C(RESULT_ACCESS
) ] = 0x0,
341 [ C(RESULT_MISS
) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
346 [ C(RESULT_ACCESS
) ] = 0x0,
347 [ C(RESULT_MISS
) ] = 0x0280, /* ICACHE.MISSES */
350 [ C(RESULT_ACCESS
) ] = -1,
351 [ C(RESULT_MISS
) ] = -1,
353 [ C(OP_PREFETCH
) ] = {
354 [ C(RESULT_ACCESS
) ] = 0x0,
355 [ C(RESULT_MISS
) ] = 0x0,
360 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
361 [ C(RESULT_ACCESS
) ] = 0x01b7,
362 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
363 [ C(RESULT_MISS
) ] = 0x01b7,
366 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
367 [ C(RESULT_ACCESS
) ] = 0x01b7,
368 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
369 [ C(RESULT_MISS
) ] = 0x01b7,
371 [ C(OP_PREFETCH
) ] = {
372 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
373 [ C(RESULT_ACCESS
) ] = 0x01b7,
374 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
375 [ C(RESULT_MISS
) ] = 0x01b7,
380 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
381 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
384 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
385 [ C(RESULT_MISS
) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
387 [ C(OP_PREFETCH
) ] = {
388 [ C(RESULT_ACCESS
) ] = 0x0,
389 [ C(RESULT_MISS
) ] = 0x0,
394 [ C(RESULT_ACCESS
) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
395 [ C(RESULT_MISS
) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
398 [ C(RESULT_ACCESS
) ] = -1,
399 [ C(RESULT_MISS
) ] = -1,
401 [ C(OP_PREFETCH
) ] = {
402 [ C(RESULT_ACCESS
) ] = -1,
403 [ C(RESULT_MISS
) ] = -1,
408 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
409 [ C(RESULT_MISS
) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
412 [ C(RESULT_ACCESS
) ] = -1,
413 [ C(RESULT_MISS
) ] = -1,
415 [ C(OP_PREFETCH
) ] = {
416 [ C(RESULT_ACCESS
) ] = -1,
417 [ C(RESULT_MISS
) ] = -1,
422 [ C(RESULT_ACCESS
) ] = 0x01b7,
423 [ C(RESULT_MISS
) ] = 0x01b7,
426 [ C(RESULT_ACCESS
) ] = 0x01b7,
427 [ C(RESULT_MISS
) ] = 0x01b7,
429 [ C(OP_PREFETCH
) ] = {
430 [ C(RESULT_ACCESS
) ] = 0x01b7,
431 [ C(RESULT_MISS
) ] = 0x01b7,
438 * Notes on the events:
439 * - data reads do not include code reads (comparable to earlier tables)
440 * - data counts include speculative execution (except L1 write, dtlb, bpu)
441 * - remote node access includes remote memory, remote cache, remote mmio.
442 * - prefetches are not included in the counts because they are not
446 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
447 #define HSW_DEMAND_RFO BIT_ULL(1)
448 #define HSW_ANY_RESPONSE BIT_ULL(16)
449 #define HSW_SUPPLIER_NONE BIT_ULL(17)
450 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
451 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
452 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
453 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
454 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
455 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
456 HSW_L3_MISS_REMOTE_HOP2P)
457 #define HSW_SNOOP_NONE BIT_ULL(31)
458 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
459 #define HSW_SNOOP_MISS BIT_ULL(33)
460 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
461 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
462 #define HSW_SNOOP_HITM BIT_ULL(36)
463 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
464 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
465 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
466 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
467 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
468 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
469 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
470 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
471 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
472 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
473 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
475 #define BDW_L3_MISS_LOCAL BIT(26)
476 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
477 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
478 HSW_L3_MISS_REMOTE_HOP2P)
481 static __initconst
const u64 hsw_hw_cache_event_ids
482 [PERF_COUNT_HW_CACHE_MAX
]
483 [PERF_COUNT_HW_CACHE_OP_MAX
]
484 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
488 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
489 [ C(RESULT_MISS
) ] = 0x151, /* L1D.REPLACEMENT */
492 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
493 [ C(RESULT_MISS
) ] = 0x0,
495 [ C(OP_PREFETCH
) ] = {
496 [ C(RESULT_ACCESS
) ] = 0x0,
497 [ C(RESULT_MISS
) ] = 0x0,
502 [ C(RESULT_ACCESS
) ] = 0x0,
503 [ C(RESULT_MISS
) ] = 0x280, /* ICACHE.MISSES */
506 [ C(RESULT_ACCESS
) ] = -1,
507 [ C(RESULT_MISS
) ] = -1,
509 [ C(OP_PREFETCH
) ] = {
510 [ C(RESULT_ACCESS
) ] = 0x0,
511 [ C(RESULT_MISS
) ] = 0x0,
516 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
517 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
520 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
521 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
523 [ C(OP_PREFETCH
) ] = {
524 [ C(RESULT_ACCESS
) ] = 0x0,
525 [ C(RESULT_MISS
) ] = 0x0,
530 [ C(RESULT_ACCESS
) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
531 [ C(RESULT_MISS
) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
534 [ C(RESULT_ACCESS
) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
535 [ C(RESULT_MISS
) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
537 [ C(OP_PREFETCH
) ] = {
538 [ C(RESULT_ACCESS
) ] = 0x0,
539 [ C(RESULT_MISS
) ] = 0x0,
544 [ C(RESULT_ACCESS
) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
545 [ C(RESULT_MISS
) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
548 [ C(RESULT_ACCESS
) ] = -1,
549 [ C(RESULT_MISS
) ] = -1,
551 [ C(OP_PREFETCH
) ] = {
552 [ C(RESULT_ACCESS
) ] = -1,
553 [ C(RESULT_MISS
) ] = -1,
558 [ C(RESULT_ACCESS
) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
559 [ C(RESULT_MISS
) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
562 [ C(RESULT_ACCESS
) ] = -1,
563 [ C(RESULT_MISS
) ] = -1,
565 [ C(OP_PREFETCH
) ] = {
566 [ C(RESULT_ACCESS
) ] = -1,
567 [ C(RESULT_MISS
) ] = -1,
572 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
573 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
576 [ C(RESULT_ACCESS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
577 [ C(RESULT_MISS
) ] = 0x1b7, /* OFFCORE_RESPONSE */
579 [ C(OP_PREFETCH
) ] = {
580 [ C(RESULT_ACCESS
) ] = 0x0,
581 [ C(RESULT_MISS
) ] = 0x0,
586 static __initconst
const u64 hsw_hw_cache_extra_regs
587 [PERF_COUNT_HW_CACHE_MAX
]
588 [PERF_COUNT_HW_CACHE_OP_MAX
]
589 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
593 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_READ
|
595 [ C(RESULT_MISS
) ] = HSW_DEMAND_READ
|
596 HSW_L3_MISS
|HSW_ANY_SNOOP
,
599 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_WRITE
|
601 [ C(RESULT_MISS
) ] = HSW_DEMAND_WRITE
|
602 HSW_L3_MISS
|HSW_ANY_SNOOP
,
604 [ C(OP_PREFETCH
) ] = {
605 [ C(RESULT_ACCESS
) ] = 0x0,
606 [ C(RESULT_MISS
) ] = 0x0,
611 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_READ
|
612 HSW_L3_MISS_LOCAL_DRAM
|
614 [ C(RESULT_MISS
) ] = HSW_DEMAND_READ
|
619 [ C(RESULT_ACCESS
) ] = HSW_DEMAND_WRITE
|
620 HSW_L3_MISS_LOCAL_DRAM
|
622 [ C(RESULT_MISS
) ] = HSW_DEMAND_WRITE
|
626 [ C(OP_PREFETCH
) ] = {
627 [ C(RESULT_ACCESS
) ] = 0x0,
628 [ C(RESULT_MISS
) ] = 0x0,
633 static __initconst
const u64 westmere_hw_cache_event_ids
634 [PERF_COUNT_HW_CACHE_MAX
]
635 [PERF_COUNT_HW_CACHE_OP_MAX
]
636 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
640 [ C(RESULT_ACCESS
) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
641 [ C(RESULT_MISS
) ] = 0x0151, /* L1D.REPL */
644 [ C(RESULT_ACCESS
) ] = 0x020b, /* MEM_INST_RETURED.STORES */
645 [ C(RESULT_MISS
) ] = 0x0251, /* L1D.M_REPL */
647 [ C(OP_PREFETCH
) ] = {
648 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
649 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
654 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
655 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
658 [ C(RESULT_ACCESS
) ] = -1,
659 [ C(RESULT_MISS
) ] = -1,
661 [ C(OP_PREFETCH
) ] = {
662 [ C(RESULT_ACCESS
) ] = 0x0,
663 [ C(RESULT_MISS
) ] = 0x0,
668 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
669 [ C(RESULT_ACCESS
) ] = 0x01b7,
670 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
671 [ C(RESULT_MISS
) ] = 0x01b7,
674 * Use RFO, not WRITEBACK, because a write miss would typically occur
678 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
679 [ C(RESULT_ACCESS
) ] = 0x01b7,
680 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
681 [ C(RESULT_MISS
) ] = 0x01b7,
683 [ C(OP_PREFETCH
) ] = {
684 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
685 [ C(RESULT_ACCESS
) ] = 0x01b7,
686 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
687 [ C(RESULT_MISS
) ] = 0x01b7,
692 [ C(RESULT_ACCESS
) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
693 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
696 [ C(RESULT_ACCESS
) ] = 0x020b, /* MEM_INST_RETURED.STORES */
697 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
699 [ C(OP_PREFETCH
) ] = {
700 [ C(RESULT_ACCESS
) ] = 0x0,
701 [ C(RESULT_MISS
) ] = 0x0,
706 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
707 [ C(RESULT_MISS
) ] = 0x0185, /* ITLB_MISSES.ANY */
710 [ C(RESULT_ACCESS
) ] = -1,
711 [ C(RESULT_MISS
) ] = -1,
713 [ C(OP_PREFETCH
) ] = {
714 [ C(RESULT_ACCESS
) ] = -1,
715 [ C(RESULT_MISS
) ] = -1,
720 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
721 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
724 [ C(RESULT_ACCESS
) ] = -1,
725 [ C(RESULT_MISS
) ] = -1,
727 [ C(OP_PREFETCH
) ] = {
728 [ C(RESULT_ACCESS
) ] = -1,
729 [ C(RESULT_MISS
) ] = -1,
734 [ C(RESULT_ACCESS
) ] = 0x01b7,
735 [ C(RESULT_MISS
) ] = 0x01b7,
738 [ C(RESULT_ACCESS
) ] = 0x01b7,
739 [ C(RESULT_MISS
) ] = 0x01b7,
741 [ C(OP_PREFETCH
) ] = {
742 [ C(RESULT_ACCESS
) ] = 0x01b7,
743 [ C(RESULT_MISS
) ] = 0x01b7,
749 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
750 * See IA32 SDM Vol 3B 30.6.1.3
753 #define NHM_DMND_DATA_RD (1 << 0)
754 #define NHM_DMND_RFO (1 << 1)
755 #define NHM_DMND_IFETCH (1 << 2)
756 #define NHM_DMND_WB (1 << 3)
757 #define NHM_PF_DATA_RD (1 << 4)
758 #define NHM_PF_DATA_RFO (1 << 5)
759 #define NHM_PF_IFETCH (1 << 6)
760 #define NHM_OFFCORE_OTHER (1 << 7)
761 #define NHM_UNCORE_HIT (1 << 8)
762 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
763 #define NHM_OTHER_CORE_HITM (1 << 10)
765 #define NHM_REMOTE_CACHE_FWD (1 << 12)
766 #define NHM_REMOTE_DRAM (1 << 13)
767 #define NHM_LOCAL_DRAM (1 << 14)
768 #define NHM_NON_DRAM (1 << 15)
770 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
771 #define NHM_REMOTE (NHM_REMOTE_DRAM)
773 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
774 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
775 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
777 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
778 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
779 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
781 static __initconst
const u64 nehalem_hw_cache_extra_regs
782 [PERF_COUNT_HW_CACHE_MAX
]
783 [PERF_COUNT_HW_CACHE_OP_MAX
]
784 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
788 [ C(RESULT_ACCESS
) ] = NHM_DMND_READ
|NHM_L3_ACCESS
,
789 [ C(RESULT_MISS
) ] = NHM_DMND_READ
|NHM_L3_MISS
,
792 [ C(RESULT_ACCESS
) ] = NHM_DMND_WRITE
|NHM_L3_ACCESS
,
793 [ C(RESULT_MISS
) ] = NHM_DMND_WRITE
|NHM_L3_MISS
,
795 [ C(OP_PREFETCH
) ] = {
796 [ C(RESULT_ACCESS
) ] = NHM_DMND_PREFETCH
|NHM_L3_ACCESS
,
797 [ C(RESULT_MISS
) ] = NHM_DMND_PREFETCH
|NHM_L3_MISS
,
802 [ C(RESULT_ACCESS
) ] = NHM_DMND_READ
|NHM_LOCAL
|NHM_REMOTE
,
803 [ C(RESULT_MISS
) ] = NHM_DMND_READ
|NHM_REMOTE
,
806 [ C(RESULT_ACCESS
) ] = NHM_DMND_WRITE
|NHM_LOCAL
|NHM_REMOTE
,
807 [ C(RESULT_MISS
) ] = NHM_DMND_WRITE
|NHM_REMOTE
,
809 [ C(OP_PREFETCH
) ] = {
810 [ C(RESULT_ACCESS
) ] = NHM_DMND_PREFETCH
|NHM_LOCAL
|NHM_REMOTE
,
811 [ C(RESULT_MISS
) ] = NHM_DMND_PREFETCH
|NHM_REMOTE
,
816 static __initconst
const u64 nehalem_hw_cache_event_ids
817 [PERF_COUNT_HW_CACHE_MAX
]
818 [PERF_COUNT_HW_CACHE_OP_MAX
]
819 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
823 [ C(RESULT_ACCESS
) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
824 [ C(RESULT_MISS
) ] = 0x0151, /* L1D.REPL */
827 [ C(RESULT_ACCESS
) ] = 0x020b, /* MEM_INST_RETURED.STORES */
828 [ C(RESULT_MISS
) ] = 0x0251, /* L1D.M_REPL */
830 [ C(OP_PREFETCH
) ] = {
831 [ C(RESULT_ACCESS
) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
832 [ C(RESULT_MISS
) ] = 0x024e, /* L1D_PREFETCH.MISS */
837 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
838 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
841 [ C(RESULT_ACCESS
) ] = -1,
842 [ C(RESULT_MISS
) ] = -1,
844 [ C(OP_PREFETCH
) ] = {
845 [ C(RESULT_ACCESS
) ] = 0x0,
846 [ C(RESULT_MISS
) ] = 0x0,
851 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
852 [ C(RESULT_ACCESS
) ] = 0x01b7,
853 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
854 [ C(RESULT_MISS
) ] = 0x01b7,
857 * Use RFO, not WRITEBACK, because a write miss would typically occur
861 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
862 [ C(RESULT_ACCESS
) ] = 0x01b7,
863 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
864 [ C(RESULT_MISS
) ] = 0x01b7,
866 [ C(OP_PREFETCH
) ] = {
867 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
868 [ C(RESULT_ACCESS
) ] = 0x01b7,
869 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
870 [ C(RESULT_MISS
) ] = 0x01b7,
875 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
876 [ C(RESULT_MISS
) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
879 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
880 [ C(RESULT_MISS
) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
882 [ C(OP_PREFETCH
) ] = {
883 [ C(RESULT_ACCESS
) ] = 0x0,
884 [ C(RESULT_MISS
) ] = 0x0,
889 [ C(RESULT_ACCESS
) ] = 0x01c0, /* INST_RETIRED.ANY_P */
890 [ C(RESULT_MISS
) ] = 0x20c8, /* ITLB_MISS_RETIRED */
893 [ C(RESULT_ACCESS
) ] = -1,
894 [ C(RESULT_MISS
) ] = -1,
896 [ C(OP_PREFETCH
) ] = {
897 [ C(RESULT_ACCESS
) ] = -1,
898 [ C(RESULT_MISS
) ] = -1,
903 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
904 [ C(RESULT_MISS
) ] = 0x03e8, /* BPU_CLEARS.ANY */
907 [ C(RESULT_ACCESS
) ] = -1,
908 [ C(RESULT_MISS
) ] = -1,
910 [ C(OP_PREFETCH
) ] = {
911 [ C(RESULT_ACCESS
) ] = -1,
912 [ C(RESULT_MISS
) ] = -1,
917 [ C(RESULT_ACCESS
) ] = 0x01b7,
918 [ C(RESULT_MISS
) ] = 0x01b7,
921 [ C(RESULT_ACCESS
) ] = 0x01b7,
922 [ C(RESULT_MISS
) ] = 0x01b7,
924 [ C(OP_PREFETCH
) ] = {
925 [ C(RESULT_ACCESS
) ] = 0x01b7,
926 [ C(RESULT_MISS
) ] = 0x01b7,
931 static __initconst
const u64 core2_hw_cache_event_ids
932 [PERF_COUNT_HW_CACHE_MAX
]
933 [PERF_COUNT_HW_CACHE_OP_MAX
]
934 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
938 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
939 [ C(RESULT_MISS
) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
942 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
943 [ C(RESULT_MISS
) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
945 [ C(OP_PREFETCH
) ] = {
946 [ C(RESULT_ACCESS
) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
947 [ C(RESULT_MISS
) ] = 0,
952 [ C(RESULT_ACCESS
) ] = 0x0080, /* L1I.READS */
953 [ C(RESULT_MISS
) ] = 0x0081, /* L1I.MISSES */
956 [ C(RESULT_ACCESS
) ] = -1,
957 [ C(RESULT_MISS
) ] = -1,
959 [ C(OP_PREFETCH
) ] = {
960 [ C(RESULT_ACCESS
) ] = 0,
961 [ C(RESULT_MISS
) ] = 0,
966 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
967 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
970 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
971 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
973 [ C(OP_PREFETCH
) ] = {
974 [ C(RESULT_ACCESS
) ] = 0,
975 [ C(RESULT_MISS
) ] = 0,
980 [ C(RESULT_ACCESS
) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
981 [ C(RESULT_MISS
) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
984 [ C(RESULT_ACCESS
) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
985 [ C(RESULT_MISS
) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
987 [ C(OP_PREFETCH
) ] = {
988 [ C(RESULT_ACCESS
) ] = 0,
989 [ C(RESULT_MISS
) ] = 0,
994 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
995 [ C(RESULT_MISS
) ] = 0x1282, /* ITLBMISSES */
998 [ C(RESULT_ACCESS
) ] = -1,
999 [ C(RESULT_MISS
) ] = -1,
1001 [ C(OP_PREFETCH
) ] = {
1002 [ C(RESULT_ACCESS
) ] = -1,
1003 [ C(RESULT_MISS
) ] = -1,
1008 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1009 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1012 [ C(RESULT_ACCESS
) ] = -1,
1013 [ C(RESULT_MISS
) ] = -1,
1015 [ C(OP_PREFETCH
) ] = {
1016 [ C(RESULT_ACCESS
) ] = -1,
1017 [ C(RESULT_MISS
) ] = -1,
1022 static __initconst
const u64 atom_hw_cache_event_ids
1023 [PERF_COUNT_HW_CACHE_MAX
]
1024 [PERF_COUNT_HW_CACHE_OP_MAX
]
1025 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1029 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE.LD */
1030 [ C(RESULT_MISS
) ] = 0,
1033 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE.ST */
1034 [ C(RESULT_MISS
) ] = 0,
1036 [ C(OP_PREFETCH
) ] = {
1037 [ C(RESULT_ACCESS
) ] = 0x0,
1038 [ C(RESULT_MISS
) ] = 0,
1043 [ C(RESULT_ACCESS
) ] = 0x0380, /* L1I.READS */
1044 [ C(RESULT_MISS
) ] = 0x0280, /* L1I.MISSES */
1047 [ C(RESULT_ACCESS
) ] = -1,
1048 [ C(RESULT_MISS
) ] = -1,
1050 [ C(OP_PREFETCH
) ] = {
1051 [ C(RESULT_ACCESS
) ] = 0,
1052 [ C(RESULT_MISS
) ] = 0,
1057 [ C(RESULT_ACCESS
) ] = 0x4f29, /* L2_LD.MESI */
1058 [ C(RESULT_MISS
) ] = 0x4129, /* L2_LD.ISTATE */
1061 [ C(RESULT_ACCESS
) ] = 0x4f2A, /* L2_ST.MESI */
1062 [ C(RESULT_MISS
) ] = 0x412A, /* L2_ST.ISTATE */
1064 [ C(OP_PREFETCH
) ] = {
1065 [ C(RESULT_ACCESS
) ] = 0,
1066 [ C(RESULT_MISS
) ] = 0,
1071 [ C(RESULT_ACCESS
) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1072 [ C(RESULT_MISS
) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1075 [ C(RESULT_ACCESS
) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1076 [ C(RESULT_MISS
) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1078 [ C(OP_PREFETCH
) ] = {
1079 [ C(RESULT_ACCESS
) ] = 0,
1080 [ C(RESULT_MISS
) ] = 0,
1085 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1086 [ C(RESULT_MISS
) ] = 0x0282, /* ITLB.MISSES */
1089 [ C(RESULT_ACCESS
) ] = -1,
1090 [ C(RESULT_MISS
) ] = -1,
1092 [ C(OP_PREFETCH
) ] = {
1093 [ C(RESULT_ACCESS
) ] = -1,
1094 [ C(RESULT_MISS
) ] = -1,
1099 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1100 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1103 [ C(RESULT_ACCESS
) ] = -1,
1104 [ C(RESULT_MISS
) ] = -1,
1106 [ C(OP_PREFETCH
) ] = {
1107 [ C(RESULT_ACCESS
) ] = -1,
1108 [ C(RESULT_MISS
) ] = -1,
1113 static struct extra_reg intel_slm_extra_regs
[] __read_mostly
=
1115 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1116 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0
, 0x768005ffffull
, RSP_0
),
1117 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1
, 0x768005ffffull
, RSP_1
),
1121 #define SLM_DMND_READ SNB_DMND_DATA_RD
1122 #define SLM_DMND_WRITE SNB_DMND_RFO
1123 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1125 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1126 #define SLM_LLC_ACCESS SNB_RESP_ANY
1127 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1129 static __initconst
const u64 slm_hw_cache_extra_regs
1130 [PERF_COUNT_HW_CACHE_MAX
]
1131 [PERF_COUNT_HW_CACHE_OP_MAX
]
1132 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1136 [ C(RESULT_ACCESS
) ] = SLM_DMND_READ
|SLM_LLC_ACCESS
,
1137 [ C(RESULT_MISS
) ] = SLM_DMND_READ
|SLM_LLC_MISS
,
1140 [ C(RESULT_ACCESS
) ] = SLM_DMND_WRITE
|SLM_LLC_ACCESS
,
1141 [ C(RESULT_MISS
) ] = SLM_DMND_WRITE
|SLM_LLC_MISS
,
1143 [ C(OP_PREFETCH
) ] = {
1144 [ C(RESULT_ACCESS
) ] = SLM_DMND_PREFETCH
|SLM_LLC_ACCESS
,
1145 [ C(RESULT_MISS
) ] = SLM_DMND_PREFETCH
|SLM_LLC_MISS
,
1150 static __initconst
const u64 slm_hw_cache_event_ids
1151 [PERF_COUNT_HW_CACHE_MAX
]
1152 [PERF_COUNT_HW_CACHE_OP_MAX
]
1153 [PERF_COUNT_HW_CACHE_RESULT_MAX
] =
1157 [ C(RESULT_ACCESS
) ] = 0,
1158 [ C(RESULT_MISS
) ] = 0x0104, /* LD_DCU_MISS */
1161 [ C(RESULT_ACCESS
) ] = 0,
1162 [ C(RESULT_MISS
) ] = 0,
1164 [ C(OP_PREFETCH
) ] = {
1165 [ C(RESULT_ACCESS
) ] = 0,
1166 [ C(RESULT_MISS
) ] = 0,
1171 [ C(RESULT_ACCESS
) ] = 0x0380, /* ICACHE.ACCESSES */
1172 [ C(RESULT_MISS
) ] = 0x0280, /* ICACGE.MISSES */
1175 [ C(RESULT_ACCESS
) ] = -1,
1176 [ C(RESULT_MISS
) ] = -1,
1178 [ C(OP_PREFETCH
) ] = {
1179 [ C(RESULT_ACCESS
) ] = 0,
1180 [ C(RESULT_MISS
) ] = 0,
1185 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1186 [ C(RESULT_ACCESS
) ] = 0x01b7,
1187 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1188 [ C(RESULT_MISS
) ] = 0x01b7,
1191 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1192 [ C(RESULT_ACCESS
) ] = 0x01b7,
1193 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1194 [ C(RESULT_MISS
) ] = 0x01b7,
1196 [ C(OP_PREFETCH
) ] = {
1197 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1198 [ C(RESULT_ACCESS
) ] = 0x01b7,
1199 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1200 [ C(RESULT_MISS
) ] = 0x01b7,
1205 [ C(RESULT_ACCESS
) ] = 0,
1206 [ C(RESULT_MISS
) ] = 0x0804, /* LD_DTLB_MISS */
1209 [ C(RESULT_ACCESS
) ] = 0,
1210 [ C(RESULT_MISS
) ] = 0,
1212 [ C(OP_PREFETCH
) ] = {
1213 [ C(RESULT_ACCESS
) ] = 0,
1214 [ C(RESULT_MISS
) ] = 0,
1219 [ C(RESULT_ACCESS
) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1220 [ C(RESULT_MISS
) ] = 0x0282, /* ITLB.MISSES */
1223 [ C(RESULT_ACCESS
) ] = -1,
1224 [ C(RESULT_MISS
) ] = -1,
1226 [ C(OP_PREFETCH
) ] = {
1227 [ C(RESULT_ACCESS
) ] = -1,
1228 [ C(RESULT_MISS
) ] = -1,
1233 [ C(RESULT_ACCESS
) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1234 [ C(RESULT_MISS
) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1237 [ C(RESULT_ACCESS
) ] = -1,
1238 [ C(RESULT_MISS
) ] = -1,
1240 [ C(OP_PREFETCH
) ] = {
1241 [ C(RESULT_ACCESS
) ] = -1,
1242 [ C(RESULT_MISS
) ] = -1,
1248 * Use from PMIs where the LBRs are already disabled.
1250 static void __intel_pmu_disable_all(void)
1252 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1254 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1256 if (test_bit(INTEL_PMC_IDX_FIXED_BTS
, cpuc
->active_mask
))
1257 intel_pmu_disable_bts();
1259 intel_bts_disable_local();
1261 intel_pmu_pebs_disable_all();
1264 static void intel_pmu_disable_all(void)
1266 __intel_pmu_disable_all();
1267 intel_pmu_lbr_disable_all();
1270 static void __intel_pmu_enable_all(int added
, bool pmi
)
1272 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1274 intel_pmu_pebs_enable_all();
1275 intel_pmu_lbr_enable_all(pmi
);
1276 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
,
1277 x86_pmu
.intel_ctrl
& ~cpuc
->intel_ctrl_guest_mask
);
1279 if (test_bit(INTEL_PMC_IDX_FIXED_BTS
, cpuc
->active_mask
)) {
1280 struct perf_event
*event
=
1281 cpuc
->events
[INTEL_PMC_IDX_FIXED_BTS
];
1283 if (WARN_ON_ONCE(!event
))
1286 intel_pmu_enable_bts(event
->hw
.config
);
1288 intel_bts_enable_local();
1291 static void intel_pmu_enable_all(int added
)
1293 __intel_pmu_enable_all(added
, false);
1298 * Intel Errata AAK100 (model 26)
1299 * Intel Errata AAP53 (model 30)
1300 * Intel Errata BD53 (model 44)
1302 * The official story:
1303 * These chips need to be 'reset' when adding counters by programming the
1304 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1305 * in sequence on the same PMC or on different PMCs.
1307 * In practise it appears some of these events do in fact count, and
1308 * we need to programm all 4 events.
1310 static void intel_pmu_nhm_workaround(void)
1312 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1313 static const unsigned long nhm_magic
[4] = {
1319 struct perf_event
*event
;
1323 * The Errata requires below steps:
1324 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1325 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1326 * the corresponding PMCx;
1327 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1328 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1329 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1333 * The real steps we choose are a little different from above.
1334 * A) To reduce MSR operations, we don't run step 1) as they
1335 * are already cleared before this function is called;
1336 * B) Call x86_perf_event_update to save PMCx before configuring
1337 * PERFEVTSELx with magic number;
1338 * C) With step 5), we do clear only when the PERFEVTSELx is
1339 * not used currently.
1340 * D) Call x86_perf_event_set_period to restore PMCx;
1343 /* We always operate 4 pairs of PERF Counters */
1344 for (i
= 0; i
< 4; i
++) {
1345 event
= cpuc
->events
[i
];
1347 x86_perf_event_update(event
);
1350 for (i
= 0; i
< 4; i
++) {
1351 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ i
, nhm_magic
[i
]);
1352 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0
+ i
, 0x0);
1355 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0xf);
1356 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0x0);
1358 for (i
= 0; i
< 4; i
++) {
1359 event
= cpuc
->events
[i
];
1362 x86_perf_event_set_period(event
);
1363 __x86_pmu_enable_event(&event
->hw
,
1364 ARCH_PERFMON_EVENTSEL_ENABLE
);
1366 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ i
, 0x0);
1370 static void intel_pmu_nhm_enable_all(int added
)
1373 intel_pmu_nhm_workaround();
1374 intel_pmu_enable_all(added
);
1377 static inline u64
intel_pmu_get_status(void)
1381 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1386 static inline void intel_pmu_ack_status(u64 ack
)
1388 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
1391 static void intel_pmu_disable_fixed(struct hw_perf_event
*hwc
)
1393 int idx
= hwc
->idx
- INTEL_PMC_IDX_FIXED
;
1396 mask
= 0xfULL
<< (idx
* 4);
1398 rdmsrl(hwc
->config_base
, ctrl_val
);
1400 wrmsrl(hwc
->config_base
, ctrl_val
);
1403 static inline bool event_is_checkpointed(struct perf_event
*event
)
1405 return (event
->hw
.config
& HSW_IN_TX_CHECKPOINTED
) != 0;
1408 static void intel_pmu_disable_event(struct perf_event
*event
)
1410 struct hw_perf_event
*hwc
= &event
->hw
;
1411 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1413 if (unlikely(hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
)) {
1414 intel_pmu_disable_bts();
1415 intel_pmu_drain_bts_buffer();
1419 cpuc
->intel_ctrl_guest_mask
&= ~(1ull << hwc
->idx
);
1420 cpuc
->intel_ctrl_host_mask
&= ~(1ull << hwc
->idx
);
1421 cpuc
->intel_cp_status
&= ~(1ull << hwc
->idx
);
1424 * must disable before any actual event
1425 * because any event may be combined with LBR
1427 if (needs_branch_stack(event
))
1428 intel_pmu_lbr_disable(event
);
1430 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
1431 intel_pmu_disable_fixed(hwc
);
1435 x86_pmu_disable_event(event
);
1437 if (unlikely(event
->attr
.precise_ip
))
1438 intel_pmu_pebs_disable(event
);
1441 static void intel_pmu_enable_fixed(struct hw_perf_event
*hwc
)
1443 int idx
= hwc
->idx
- INTEL_PMC_IDX_FIXED
;
1444 u64 ctrl_val
, bits
, mask
;
1447 * Enable IRQ generation (0x8),
1448 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1452 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
1454 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
1458 * ANY bit is supported in v3 and up
1460 if (x86_pmu
.version
> 2 && hwc
->config
& ARCH_PERFMON_EVENTSEL_ANY
)
1464 mask
= 0xfULL
<< (idx
* 4);
1466 rdmsrl(hwc
->config_base
, ctrl_val
);
1469 wrmsrl(hwc
->config_base
, ctrl_val
);
1472 static void intel_pmu_enable_event(struct perf_event
*event
)
1474 struct hw_perf_event
*hwc
= &event
->hw
;
1475 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1477 if (unlikely(hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
)) {
1478 if (!__this_cpu_read(cpu_hw_events
.enabled
))
1481 intel_pmu_enable_bts(hwc
->config
);
1485 * must enabled before any actual event
1486 * because any event may be combined with LBR
1488 if (needs_branch_stack(event
))
1489 intel_pmu_lbr_enable(event
);
1491 if (event
->attr
.exclude_host
)
1492 cpuc
->intel_ctrl_guest_mask
|= (1ull << hwc
->idx
);
1493 if (event
->attr
.exclude_guest
)
1494 cpuc
->intel_ctrl_host_mask
|= (1ull << hwc
->idx
);
1496 if (unlikely(event_is_checkpointed(event
)))
1497 cpuc
->intel_cp_status
|= (1ull << hwc
->idx
);
1499 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
)) {
1500 intel_pmu_enable_fixed(hwc
);
1504 if (unlikely(event
->attr
.precise_ip
))
1505 intel_pmu_pebs_enable(event
);
1507 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
1511 * Save and restart an expired event. Called by NMI contexts,
1512 * so it has to be careful about preempting normal event ops:
1514 int intel_pmu_save_and_restart(struct perf_event
*event
)
1516 x86_perf_event_update(event
);
1518 * For a checkpointed counter always reset back to 0. This
1519 * avoids a situation where the counter overflows, aborts the
1520 * transaction and is then set back to shortly before the
1521 * overflow, and overflows and aborts again.
1523 if (unlikely(event_is_checkpointed(event
))) {
1524 /* No race with NMIs because the counter should not be armed */
1525 wrmsrl(event
->hw
.event_base
, 0);
1526 local64_set(&event
->hw
.prev_count
, 0);
1528 return x86_perf_event_set_period(event
);
1531 static void intel_pmu_reset(void)
1533 struct debug_store
*ds
= __this_cpu_read(cpu_hw_events
.ds
);
1534 unsigned long flags
;
1537 if (!x86_pmu
.num_counters
)
1540 local_irq_save(flags
);
1542 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1544 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1545 wrmsrl_safe(x86_pmu_config_addr(idx
), 0ull);
1546 wrmsrl_safe(x86_pmu_event_addr(idx
), 0ull);
1548 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++)
1549 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, 0ull);
1552 ds
->bts_index
= ds
->bts_buffer_base
;
1554 /* Ack all overflows and disable fixed counters */
1555 if (x86_pmu
.version
>= 2) {
1556 intel_pmu_ack_status(intel_pmu_get_status());
1557 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1560 /* Reset LBRs and LBR freezing */
1561 if (x86_pmu
.lbr_nr
) {
1562 update_debugctlmsr(get_debugctlmsr() &
1563 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
|DEBUGCTLMSR_LBR
));
1566 local_irq_restore(flags
);
1570 * This handler is triggered by the local APIC, so the APIC IRQ handling
1573 static int intel_pmu_handle_irq(struct pt_regs
*regs
)
1575 struct perf_sample_data data
;
1576 struct cpu_hw_events
*cpuc
;
1581 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1584 * No known reason to not always do late ACK,
1585 * but just in case do it opt-in.
1587 if (!x86_pmu
.late_ack
)
1588 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1589 __intel_pmu_disable_all();
1590 handled
= intel_pmu_drain_bts_buffer();
1591 handled
+= intel_bts_interrupt();
1592 status
= intel_pmu_get_status();
1598 intel_pmu_ack_status(status
);
1599 if (++loops
> 100) {
1600 static bool warned
= false;
1602 WARN(1, "perfevents: irq loop stuck!\n");
1603 perf_event_print_debug();
1610 inc_irq_stat(apic_perf_irqs
);
1612 intel_pmu_lbr_read();
1615 * CondChgd bit 63 doesn't mean any overflow status. Ignore
1616 * and clear the bit.
1618 if (__test_and_clear_bit(63, (unsigned long *)&status
)) {
1624 * PEBS overflow sets bit 62 in the global status register
1626 if (__test_and_clear_bit(62, (unsigned long *)&status
)) {
1628 x86_pmu
.drain_pebs(regs
);
1634 if (__test_and_clear_bit(55, (unsigned long *)&status
)) {
1636 intel_pt_interrupt();
1640 * Checkpointed counters can lead to 'spurious' PMIs because the
1641 * rollback caused by the PMI will have cleared the overflow status
1642 * bit. Therefore always force probe these counters.
1644 status
|= cpuc
->intel_cp_status
;
1646 for_each_set_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
1647 struct perf_event
*event
= cpuc
->events
[bit
];
1651 if (!test_bit(bit
, cpuc
->active_mask
))
1654 if (!intel_pmu_save_and_restart(event
))
1657 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1659 if (has_branch_stack(event
))
1660 data
.br_stack
= &cpuc
->lbr_stack
;
1662 if (perf_event_overflow(event
, &data
, regs
))
1663 x86_pmu_stop(event
, 0);
1667 * Repeat if there is more work to be done:
1669 status
= intel_pmu_get_status();
1674 __intel_pmu_enable_all(0, true);
1676 * Only unmask the NMI after the overflow counters
1677 * have been reset. This avoids spurious NMIs on
1680 if (x86_pmu
.late_ack
)
1681 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1685 static struct event_constraint
*
1686 intel_bts_constraints(struct perf_event
*event
)
1688 struct hw_perf_event
*hwc
= &event
->hw
;
1689 unsigned int hw_event
, bts_event
;
1691 if (event
->attr
.freq
)
1694 hw_event
= hwc
->config
& INTEL_ARCH_EVENT_MASK
;
1695 bts_event
= x86_pmu
.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS
);
1697 if (unlikely(hw_event
== bts_event
&& hwc
->sample_period
== 1))
1698 return &bts_constraint
;
1703 static int intel_alt_er(int idx
)
1705 if (!(x86_pmu
.flags
& PMU_FL_HAS_RSP_1
))
1708 if (idx
== EXTRA_REG_RSP_0
)
1709 return EXTRA_REG_RSP_1
;
1711 if (idx
== EXTRA_REG_RSP_1
)
1712 return EXTRA_REG_RSP_0
;
1717 static void intel_fixup_er(struct perf_event
*event
, int idx
)
1719 event
->hw
.extra_reg
.idx
= idx
;
1721 if (idx
== EXTRA_REG_RSP_0
) {
1722 event
->hw
.config
&= ~INTEL_ARCH_EVENT_MASK
;
1723 event
->hw
.config
|= x86_pmu
.extra_regs
[EXTRA_REG_RSP_0
].event
;
1724 event
->hw
.extra_reg
.reg
= MSR_OFFCORE_RSP_0
;
1725 } else if (idx
== EXTRA_REG_RSP_1
) {
1726 event
->hw
.config
&= ~INTEL_ARCH_EVENT_MASK
;
1727 event
->hw
.config
|= x86_pmu
.extra_regs
[EXTRA_REG_RSP_1
].event
;
1728 event
->hw
.extra_reg
.reg
= MSR_OFFCORE_RSP_1
;
1733 * manage allocation of shared extra msr for certain events
1736 * per-cpu: to be shared between the various events on a single PMU
1737 * per-core: per-cpu + shared by HT threads
1739 static struct event_constraint
*
1740 __intel_shared_reg_get_constraints(struct cpu_hw_events
*cpuc
,
1741 struct perf_event
*event
,
1742 struct hw_perf_event_extra
*reg
)
1744 struct event_constraint
*c
= &emptyconstraint
;
1745 struct er_account
*era
;
1746 unsigned long flags
;
1750 * reg->alloc can be set due to existing state, so for fake cpuc we
1751 * need to ignore this, otherwise we might fail to allocate proper fake
1752 * state for this extra reg constraint. Also see the comment below.
1754 if (reg
->alloc
&& !cpuc
->is_fake
)
1755 return NULL
; /* call x86_get_event_constraint() */
1758 era
= &cpuc
->shared_regs
->regs
[idx
];
1760 * we use spin_lock_irqsave() to avoid lockdep issues when
1761 * passing a fake cpuc
1763 raw_spin_lock_irqsave(&era
->lock
, flags
);
1765 if (!atomic_read(&era
->ref
) || era
->config
== reg
->config
) {
1768 * If its a fake cpuc -- as per validate_{group,event}() we
1769 * shouldn't touch event state and we can avoid doing so
1770 * since both will only call get_event_constraints() once
1771 * on each event, this avoids the need for reg->alloc.
1773 * Not doing the ER fixup will only result in era->reg being
1774 * wrong, but since we won't actually try and program hardware
1775 * this isn't a problem either.
1777 if (!cpuc
->is_fake
) {
1778 if (idx
!= reg
->idx
)
1779 intel_fixup_er(event
, idx
);
1782 * x86_schedule_events() can call get_event_constraints()
1783 * multiple times on events in the case of incremental
1784 * scheduling(). reg->alloc ensures we only do the ER
1790 /* lock in msr value */
1791 era
->config
= reg
->config
;
1792 era
->reg
= reg
->reg
;
1795 atomic_inc(&era
->ref
);
1798 * need to call x86_get_event_constraint()
1799 * to check if associated event has constraints
1803 idx
= intel_alt_er(idx
);
1804 if (idx
!= reg
->idx
) {
1805 raw_spin_unlock_irqrestore(&era
->lock
, flags
);
1809 raw_spin_unlock_irqrestore(&era
->lock
, flags
);
1815 __intel_shared_reg_put_constraints(struct cpu_hw_events
*cpuc
,
1816 struct hw_perf_event_extra
*reg
)
1818 struct er_account
*era
;
1821 * Only put constraint if extra reg was actually allocated. Also takes
1822 * care of event which do not use an extra shared reg.
1824 * Also, if this is a fake cpuc we shouldn't touch any event state
1825 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1826 * either since it'll be thrown out.
1828 if (!reg
->alloc
|| cpuc
->is_fake
)
1831 era
= &cpuc
->shared_regs
->regs
[reg
->idx
];
1833 /* one fewer user */
1834 atomic_dec(&era
->ref
);
1836 /* allocate again next time */
1840 static struct event_constraint
*
1841 intel_shared_regs_constraints(struct cpu_hw_events
*cpuc
,
1842 struct perf_event
*event
)
1844 struct event_constraint
*c
= NULL
, *d
;
1845 struct hw_perf_event_extra
*xreg
, *breg
;
1847 xreg
= &event
->hw
.extra_reg
;
1848 if (xreg
->idx
!= EXTRA_REG_NONE
) {
1849 c
= __intel_shared_reg_get_constraints(cpuc
, event
, xreg
);
1850 if (c
== &emptyconstraint
)
1853 breg
= &event
->hw
.branch_reg
;
1854 if (breg
->idx
!= EXTRA_REG_NONE
) {
1855 d
= __intel_shared_reg_get_constraints(cpuc
, event
, breg
);
1856 if (d
== &emptyconstraint
) {
1857 __intel_shared_reg_put_constraints(cpuc
, xreg
);
1864 struct event_constraint
*
1865 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
1866 struct perf_event
*event
)
1868 struct event_constraint
*c
;
1870 if (x86_pmu
.event_constraints
) {
1871 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1872 if ((event
->hw
.config
& c
->cmask
) == c
->code
) {
1873 event
->hw
.flags
|= c
->flags
;
1879 return &unconstrained
;
1882 static struct event_constraint
*
1883 __intel_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
1884 struct perf_event
*event
)
1886 struct event_constraint
*c
;
1888 c
= intel_bts_constraints(event
);
1892 c
= intel_shared_regs_constraints(cpuc
, event
);
1896 c
= intel_pebs_constraints(event
);
1900 return x86_get_event_constraints(cpuc
, idx
, event
);
1904 intel_start_scheduling(struct cpu_hw_events
*cpuc
)
1906 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
1907 struct intel_excl_states
*xl
, *xlo
;
1908 int tid
= cpuc
->excl_thread_id
;
1909 int o_tid
= 1 - tid
; /* sibling thread */
1912 * nothing needed if in group validation mode
1914 if (cpuc
->is_fake
|| !is_ht_workaround_enabled())
1918 * no exclusion needed
1923 xlo
= &excl_cntrs
->states
[o_tid
];
1924 xl
= &excl_cntrs
->states
[tid
];
1926 xl
->sched_started
= true;
1927 xl
->num_alloc_cntrs
= 0;
1929 * lock shared state until we are done scheduling
1930 * in stop_event_scheduling()
1931 * makes scheduling appear as a transaction
1933 WARN_ON_ONCE(!irqs_disabled());
1934 raw_spin_lock(&excl_cntrs
->lock
);
1937 * save initial state of sibling thread
1939 memcpy(xlo
->init_state
, xlo
->state
, sizeof(xlo
->init_state
));
1943 intel_stop_scheduling(struct cpu_hw_events
*cpuc
)
1945 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
1946 struct intel_excl_states
*xl
, *xlo
;
1947 int tid
= cpuc
->excl_thread_id
;
1948 int o_tid
= 1 - tid
; /* sibling thread */
1951 * nothing needed if in group validation mode
1953 if (cpuc
->is_fake
|| !is_ht_workaround_enabled())
1956 * no exclusion needed
1961 xlo
= &excl_cntrs
->states
[o_tid
];
1962 xl
= &excl_cntrs
->states
[tid
];
1965 * make new sibling thread state visible
1967 memcpy(xlo
->state
, xlo
->init_state
, sizeof(xlo
->state
));
1969 xl
->sched_started
= false;
1971 * release shared state lock (acquired in intel_start_scheduling())
1973 raw_spin_unlock(&excl_cntrs
->lock
);
1976 static struct event_constraint
*
1977 intel_get_excl_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
,
1978 int idx
, struct event_constraint
*c
)
1980 struct event_constraint
*cx
;
1981 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
1982 struct intel_excl_states
*xl
, *xlo
;
1984 int tid
= cpuc
->excl_thread_id
;
1985 int o_tid
= 1 - tid
; /* alternate */
1988 * validating a group does not require
1989 * enforcing cross-thread exclusion
1991 if (cpuc
->is_fake
|| !is_ht_workaround_enabled())
1995 * no exclusion needed
2000 * event requires exclusive counter access
2003 is_excl
= c
->flags
& PERF_X86_EVENT_EXCL
;
2006 * xl = state of current HT
2007 * xlo = state of sibling HT
2009 xl
= &excl_cntrs
->states
[tid
];
2010 xlo
= &excl_cntrs
->states
[o_tid
];
2013 * do not allow scheduling of more than max_alloc_cntrs
2014 * which is set to half the available generic counters.
2015 * this helps avoid counter starvation of sibling thread
2016 * by ensuring at most half the counters cannot be in
2017 * exclusive mode. There is not designated counters for the
2018 * limits. Any N/2 counters can be used. This helps with
2019 * events with specifix counter constraints
2021 if (xl
->num_alloc_cntrs
++ == xl
->max_alloc_cntrs
)
2022 return &emptyconstraint
;
2027 * because we modify the constraint, we need
2028 * to make a copy. Static constraints come
2029 * from static const tables.
2031 * only needed when constraint has not yet
2032 * been cloned (marked dynamic)
2034 if (!(c
->flags
& PERF_X86_EVENT_DYNAMIC
)) {
2038 return &emptyconstraint
;
2041 * grab pre-allocated constraint entry
2043 cx
= &cpuc
->constraint_list
[idx
];
2046 * initialize dynamic constraint
2047 * with static constraint
2049 memcpy(cx
, c
, sizeof(*cx
));
2052 * mark constraint as dynamic, so we
2053 * can free it later on
2055 cx
->flags
|= PERF_X86_EVENT_DYNAMIC
;
2059 * From here on, the constraint is dynamic.
2060 * Either it was just allocated above, or it
2061 * was allocated during a earlier invocation
2066 * Modify static constraint with current dynamic
2069 * EXCLUSIVE: sibling counter measuring exclusive event
2070 * SHARED : sibling counter measuring non-exclusive event
2071 * UNUSED : sibling counter unused
2073 for_each_set_bit(i
, cx
->idxmsk
, X86_PMC_IDX_MAX
) {
2075 * exclusive event in sibling counter
2076 * our corresponding counter cannot be used
2077 * regardless of our event
2079 if (xl
->state
[i
] == INTEL_EXCL_EXCLUSIVE
)
2080 __clear_bit(i
, cx
->idxmsk
);
2082 * if measuring an exclusive event, sibling
2083 * measuring non-exclusive, then counter cannot
2086 if (is_excl
&& xl
->state
[i
] == INTEL_EXCL_SHARED
)
2087 __clear_bit(i
, cx
->idxmsk
);
2091 * recompute actual bit weight for scheduling algorithm
2093 cx
->weight
= hweight64(cx
->idxmsk64
);
2096 * if we return an empty mask, then switch
2097 * back to static empty constraint to avoid
2098 * the cost of freeing later on
2100 if (cx
->weight
== 0)
2101 cx
= &emptyconstraint
;
2106 static struct event_constraint
*
2107 intel_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
2108 struct perf_event
*event
)
2110 struct event_constraint
*c1
= event
->hw
.constraint
;
2111 struct event_constraint
*c2
;
2115 * - static constraint: no change across incremental scheduling calls
2116 * - dynamic constraint: handled by intel_get_excl_constraints()
2118 c2
= __intel_get_event_constraints(cpuc
, idx
, event
);
2119 if (c1
&& (c1
->flags
& PERF_X86_EVENT_DYNAMIC
)) {
2120 bitmap_copy(c1
->idxmsk
, c2
->idxmsk
, X86_PMC_IDX_MAX
);
2121 c1
->weight
= c2
->weight
;
2125 if (cpuc
->excl_cntrs
)
2126 return intel_get_excl_constraints(cpuc
, event
, idx
, c2
);
2131 static void intel_put_excl_constraints(struct cpu_hw_events
*cpuc
,
2132 struct perf_event
*event
)
2134 struct hw_perf_event
*hwc
= &event
->hw
;
2135 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
2136 struct intel_excl_states
*xlo
, *xl
;
2137 unsigned long flags
= 0; /* keep compiler happy */
2138 int tid
= cpuc
->excl_thread_id
;
2139 int o_tid
= 1 - tid
;
2142 * nothing needed if in group validation mode
2147 WARN_ON_ONCE(!excl_cntrs
);
2152 xl
= &excl_cntrs
->states
[tid
];
2153 xlo
= &excl_cntrs
->states
[o_tid
];
2156 * put_constraint may be called from x86_schedule_events()
2157 * which already has the lock held so here make locking
2160 if (!xl
->sched_started
)
2161 raw_spin_lock_irqsave(&excl_cntrs
->lock
, flags
);
2164 * if event was actually assigned, then mark the
2165 * counter state as unused now
2168 xlo
->state
[hwc
->idx
] = INTEL_EXCL_UNUSED
;
2170 if (!xl
->sched_started
)
2171 raw_spin_unlock_irqrestore(&excl_cntrs
->lock
, flags
);
2175 intel_put_shared_regs_event_constraints(struct cpu_hw_events
*cpuc
,
2176 struct perf_event
*event
)
2178 struct hw_perf_event_extra
*reg
;
2180 reg
= &event
->hw
.extra_reg
;
2181 if (reg
->idx
!= EXTRA_REG_NONE
)
2182 __intel_shared_reg_put_constraints(cpuc
, reg
);
2184 reg
= &event
->hw
.branch_reg
;
2185 if (reg
->idx
!= EXTRA_REG_NONE
)
2186 __intel_shared_reg_put_constraints(cpuc
, reg
);
2189 static void intel_put_event_constraints(struct cpu_hw_events
*cpuc
,
2190 struct perf_event
*event
)
2192 struct event_constraint
*c
= event
->hw
.constraint
;
2194 intel_put_shared_regs_event_constraints(cpuc
, event
);
2197 * is PMU has exclusive counter restrictions, then
2198 * all events are subject to and must call the
2199 * put_excl_constraints() routine
2201 if (c
&& cpuc
->excl_cntrs
)
2202 intel_put_excl_constraints(cpuc
, event
);
2204 /* cleanup dynamic constraint */
2205 if (c
&& (c
->flags
& PERF_X86_EVENT_DYNAMIC
))
2206 event
->hw
.constraint
= NULL
;
2209 static void intel_commit_scheduling(struct cpu_hw_events
*cpuc
,
2210 struct perf_event
*event
, int cntr
)
2212 struct intel_excl_cntrs
*excl_cntrs
= cpuc
->excl_cntrs
;
2213 struct event_constraint
*c
= event
->hw
.constraint
;
2214 struct intel_excl_states
*xlo
, *xl
;
2215 int tid
= cpuc
->excl_thread_id
;
2216 int o_tid
= 1 - tid
;
2219 if (cpuc
->is_fake
|| !c
)
2222 is_excl
= c
->flags
& PERF_X86_EVENT_EXCL
;
2224 if (!(c
->flags
& PERF_X86_EVENT_DYNAMIC
))
2227 WARN_ON_ONCE(!excl_cntrs
);
2232 xl
= &excl_cntrs
->states
[tid
];
2233 xlo
= &excl_cntrs
->states
[o_tid
];
2235 WARN_ON_ONCE(!raw_spin_is_locked(&excl_cntrs
->lock
));
2239 xlo
->init_state
[cntr
] = INTEL_EXCL_EXCLUSIVE
;
2241 xlo
->init_state
[cntr
] = INTEL_EXCL_SHARED
;
2245 static void intel_pebs_aliases_core2(struct perf_event
*event
)
2247 if ((event
->hw
.config
& X86_RAW_EVENT_MASK
) == 0x003c) {
2249 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2250 * (0x003c) so that we can use it with PEBS.
2252 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2253 * PEBS capable. However we can use INST_RETIRED.ANY_P
2254 * (0x00c0), which is a PEBS capable event, to get the same
2257 * INST_RETIRED.ANY_P counts the number of cycles that retires
2258 * CNTMASK instructions. By setting CNTMASK to a value (16)
2259 * larger than the maximum number of instructions that can be
2260 * retired per cycle (4) and then inverting the condition, we
2261 * count all cycles that retire 16 or less instructions, which
2264 * Thereby we gain a PEBS capable cycle counter.
2266 u64 alt_config
= X86_CONFIG(.event
=0xc0, .inv
=1, .cmask
=16);
2268 alt_config
|= (event
->hw
.config
& ~X86_RAW_EVENT_MASK
);
2269 event
->hw
.config
= alt_config
;
2273 static void intel_pebs_aliases_snb(struct perf_event
*event
)
2275 if ((event
->hw
.config
& X86_RAW_EVENT_MASK
) == 0x003c) {
2277 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2278 * (0x003c) so that we can use it with PEBS.
2280 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2281 * PEBS capable. However we can use UOPS_RETIRED.ALL
2282 * (0x01c2), which is a PEBS capable event, to get the same
2285 * UOPS_RETIRED.ALL counts the number of cycles that retires
2286 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2287 * larger than the maximum number of micro-ops that can be
2288 * retired per cycle (4) and then inverting the condition, we
2289 * count all cycles that retire 16 or less micro-ops, which
2292 * Thereby we gain a PEBS capable cycle counter.
2294 u64 alt_config
= X86_CONFIG(.event
=0xc2, .umask
=0x01, .inv
=1, .cmask
=16);
2296 alt_config
|= (event
->hw
.config
& ~X86_RAW_EVENT_MASK
);
2297 event
->hw
.config
= alt_config
;
2301 static int intel_pmu_hw_config(struct perf_event
*event
)
2303 int ret
= x86_pmu_hw_config(event
);
2308 if (event
->attr
.precise_ip
&& x86_pmu
.pebs_aliases
)
2309 x86_pmu
.pebs_aliases(event
);
2311 if (needs_branch_stack(event
)) {
2312 ret
= intel_pmu_setup_lbr_filter(event
);
2317 * BTS is set up earlier in this path, so don't account twice
2319 if (!intel_pmu_has_bts(event
)) {
2320 /* disallow lbr if conflicting events are present */
2321 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
2324 event
->destroy
= hw_perf_lbr_event_destroy
;
2328 if (event
->attr
.type
!= PERF_TYPE_RAW
)
2331 if (!(event
->attr
.config
& ARCH_PERFMON_EVENTSEL_ANY
))
2334 if (x86_pmu
.version
< 3)
2337 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN
))
2340 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_ANY
;
2345 struct perf_guest_switch_msr
*perf_guest_get_msrs(int *nr
)
2347 if (x86_pmu
.guest_get_msrs
)
2348 return x86_pmu
.guest_get_msrs(nr
);
2352 EXPORT_SYMBOL_GPL(perf_guest_get_msrs
);
2354 static struct perf_guest_switch_msr
*intel_guest_get_msrs(int *nr
)
2356 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
2357 struct perf_guest_switch_msr
*arr
= cpuc
->guest_switch_msrs
;
2359 arr
[0].msr
= MSR_CORE_PERF_GLOBAL_CTRL
;
2360 arr
[0].host
= x86_pmu
.intel_ctrl
& ~cpuc
->intel_ctrl_guest_mask
;
2361 arr
[0].guest
= x86_pmu
.intel_ctrl
& ~cpuc
->intel_ctrl_host_mask
;
2363 * If PMU counter has PEBS enabled it is not enough to disable counter
2364 * on a guest entry since PEBS memory write can overshoot guest entry
2365 * and corrupt guest memory. Disabling PEBS solves the problem.
2367 arr
[1].msr
= MSR_IA32_PEBS_ENABLE
;
2368 arr
[1].host
= cpuc
->pebs_enabled
;
2375 static struct perf_guest_switch_msr
*core_guest_get_msrs(int *nr
)
2377 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
2378 struct perf_guest_switch_msr
*arr
= cpuc
->guest_switch_msrs
;
2381 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
2382 struct perf_event
*event
= cpuc
->events
[idx
];
2384 arr
[idx
].msr
= x86_pmu_config_addr(idx
);
2385 arr
[idx
].host
= arr
[idx
].guest
= 0;
2387 if (!test_bit(idx
, cpuc
->active_mask
))
2390 arr
[idx
].host
= arr
[idx
].guest
=
2391 event
->hw
.config
| ARCH_PERFMON_EVENTSEL_ENABLE
;
2393 if (event
->attr
.exclude_host
)
2394 arr
[idx
].host
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
2395 else if (event
->attr
.exclude_guest
)
2396 arr
[idx
].guest
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
2399 *nr
= x86_pmu
.num_counters
;
2403 static void core_pmu_enable_event(struct perf_event
*event
)
2405 if (!event
->attr
.exclude_host
)
2406 x86_pmu_enable_event(event
);
2409 static void core_pmu_enable_all(int added
)
2411 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
2414 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
2415 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
2417 if (!test_bit(idx
, cpuc
->active_mask
) ||
2418 cpuc
->events
[idx
]->attr
.exclude_host
)
2421 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
2425 static int hsw_hw_config(struct perf_event
*event
)
2427 int ret
= intel_pmu_hw_config(event
);
2431 if (!boot_cpu_has(X86_FEATURE_RTM
) && !boot_cpu_has(X86_FEATURE_HLE
))
2433 event
->hw
.config
|= event
->attr
.config
& (HSW_IN_TX
|HSW_IN_TX_CHECKPOINTED
);
2436 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2437 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2440 if ((event
->hw
.config
& (HSW_IN_TX
|HSW_IN_TX_CHECKPOINTED
)) &&
2441 ((event
->hw
.config
& ARCH_PERFMON_EVENTSEL_ANY
) ||
2442 event
->attr
.precise_ip
> 0))
2445 if (event_is_checkpointed(event
)) {
2447 * Sampling of checkpointed events can cause situations where
2448 * the CPU constantly aborts because of a overflow, which is
2449 * then checkpointed back and ignored. Forbid checkpointing
2452 * But still allow a long sampling period, so that perf stat
2455 if (event
->attr
.sample_period
> 0 &&
2456 event
->attr
.sample_period
< 0x7fffffff)
2462 static struct event_constraint counter2_constraint
=
2463 EVENT_CONSTRAINT(0, 0x4, 0);
2465 static struct event_constraint
*
2466 hsw_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
2467 struct perf_event
*event
)
2469 struct event_constraint
*c
;
2471 c
= intel_get_event_constraints(cpuc
, idx
, event
);
2473 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2474 if (event
->hw
.config
& HSW_IN_TX_CHECKPOINTED
) {
2475 if (c
->idxmsk64
& (1U << 2))
2476 return &counter2_constraint
;
2477 return &emptyconstraint
;
2486 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2487 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2488 * the two to enforce a minimum period of 128 (the smallest value that has bits
2489 * 0-5 cleared and >= 100).
2491 * Because of how the code in x86_perf_event_set_period() works, the truncation
2492 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2493 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2495 * Therefore the effective (average) period matches the requested period,
2496 * despite coarser hardware granularity.
2498 static unsigned bdw_limit_period(struct perf_event
*event
, unsigned left
)
2500 if ((event
->hw
.config
& INTEL_ARCH_EVENT_MASK
) ==
2501 X86_CONFIG(.event
=0xc0, .umask
=0x01)) {
2509 PMU_FORMAT_ATTR(event
, "config:0-7" );
2510 PMU_FORMAT_ATTR(umask
, "config:8-15" );
2511 PMU_FORMAT_ATTR(edge
, "config:18" );
2512 PMU_FORMAT_ATTR(pc
, "config:19" );
2513 PMU_FORMAT_ATTR(any
, "config:21" ); /* v3 + */
2514 PMU_FORMAT_ATTR(inv
, "config:23" );
2515 PMU_FORMAT_ATTR(cmask
, "config:24-31" );
2516 PMU_FORMAT_ATTR(in_tx
, "config:32");
2517 PMU_FORMAT_ATTR(in_tx_cp
, "config:33");
2519 static struct attribute
*intel_arch_formats_attr
[] = {
2520 &format_attr_event
.attr
,
2521 &format_attr_umask
.attr
,
2522 &format_attr_edge
.attr
,
2523 &format_attr_pc
.attr
,
2524 &format_attr_inv
.attr
,
2525 &format_attr_cmask
.attr
,
2529 ssize_t
intel_event_sysfs_show(char *page
, u64 config
)
2531 u64 event
= (config
& ARCH_PERFMON_EVENTSEL_EVENT
);
2533 return x86_event_sysfs_show(page
, config
, event
);
2536 struct intel_shared_regs
*allocate_shared_regs(int cpu
)
2538 struct intel_shared_regs
*regs
;
2541 regs
= kzalloc_node(sizeof(struct intel_shared_regs
),
2542 GFP_KERNEL
, cpu_to_node(cpu
));
2545 * initialize the locks to keep lockdep happy
2547 for (i
= 0; i
< EXTRA_REG_MAX
; i
++)
2548 raw_spin_lock_init(®s
->regs
[i
].lock
);
2555 static struct intel_excl_cntrs
*allocate_excl_cntrs(int cpu
)
2557 struct intel_excl_cntrs
*c
;
2560 c
= kzalloc_node(sizeof(struct intel_excl_cntrs
),
2561 GFP_KERNEL
, cpu_to_node(cpu
));
2563 raw_spin_lock_init(&c
->lock
);
2564 for (i
= 0; i
< X86_PMC_IDX_MAX
; i
++) {
2565 c
->states
[0].state
[i
] = INTEL_EXCL_UNUSED
;
2566 c
->states
[0].init_state
[i
] = INTEL_EXCL_UNUSED
;
2568 c
->states
[1].state
[i
] = INTEL_EXCL_UNUSED
;
2569 c
->states
[1].init_state
[i
] = INTEL_EXCL_UNUSED
;
2576 static int intel_pmu_cpu_prepare(int cpu
)
2578 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
2580 if (x86_pmu
.extra_regs
|| x86_pmu
.lbr_sel_map
) {
2581 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
2582 if (!cpuc
->shared_regs
)
2586 if (x86_pmu
.flags
& PMU_FL_EXCL_CNTRS
) {
2587 size_t sz
= X86_PMC_IDX_MAX
* sizeof(struct event_constraint
);
2589 cpuc
->constraint_list
= kzalloc(sz
, GFP_KERNEL
);
2590 if (!cpuc
->constraint_list
)
2593 cpuc
->excl_cntrs
= allocate_excl_cntrs(cpu
);
2594 if (!cpuc
->excl_cntrs
) {
2595 kfree(cpuc
->constraint_list
);
2596 kfree(cpuc
->shared_regs
);
2599 cpuc
->excl_thread_id
= 0;
2605 static void intel_pmu_cpu_starting(int cpu
)
2607 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
2608 int core_id
= topology_core_id(cpu
);
2611 init_debug_store_on_cpu(cpu
);
2613 * Deal with CPUs that don't clear their LBRs on power-up.
2615 intel_pmu_lbr_reset();
2617 cpuc
->lbr_sel
= NULL
;
2619 if (!cpuc
->shared_regs
)
2622 if (!(x86_pmu
.flags
& PMU_FL_NO_HT_SHARING
)) {
2623 void **onln
= &cpuc
->kfree_on_online
[X86_PERF_KFREE_SHARED
];
2625 for_each_cpu(i
, topology_thread_cpumask(cpu
)) {
2626 struct intel_shared_regs
*pc
;
2628 pc
= per_cpu(cpu_hw_events
, i
).shared_regs
;
2629 if (pc
&& pc
->core_id
== core_id
) {
2630 *onln
= cpuc
->shared_regs
;
2631 cpuc
->shared_regs
= pc
;
2635 cpuc
->shared_regs
->core_id
= core_id
;
2636 cpuc
->shared_regs
->refcnt
++;
2639 if (x86_pmu
.lbr_sel_map
)
2640 cpuc
->lbr_sel
= &cpuc
->shared_regs
->regs
[EXTRA_REG_LBR
];
2642 if (x86_pmu
.flags
& PMU_FL_EXCL_CNTRS
) {
2643 int h
= x86_pmu
.num_counters
>> 1;
2645 for_each_cpu(i
, topology_thread_cpumask(cpu
)) {
2646 struct intel_excl_cntrs
*c
;
2648 c
= per_cpu(cpu_hw_events
, i
).excl_cntrs
;
2649 if (c
&& c
->core_id
== core_id
) {
2650 cpuc
->kfree_on_online
[1] = cpuc
->excl_cntrs
;
2651 cpuc
->excl_cntrs
= c
;
2652 cpuc
->excl_thread_id
= 1;
2656 cpuc
->excl_cntrs
->core_id
= core_id
;
2657 cpuc
->excl_cntrs
->refcnt
++;
2659 * set hard limit to half the number of generic counters
2661 cpuc
->excl_cntrs
->states
[0].max_alloc_cntrs
= h
;
2662 cpuc
->excl_cntrs
->states
[1].max_alloc_cntrs
= h
;
2666 static void free_excl_cntrs(int cpu
)
2668 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
2669 struct intel_excl_cntrs
*c
;
2671 c
= cpuc
->excl_cntrs
;
2673 if (c
->core_id
== -1 || --c
->refcnt
== 0)
2675 cpuc
->excl_cntrs
= NULL
;
2676 kfree(cpuc
->constraint_list
);
2677 cpuc
->constraint_list
= NULL
;
2681 static void intel_pmu_cpu_dying(int cpu
)
2683 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
2684 struct intel_shared_regs
*pc
;
2686 pc
= cpuc
->shared_regs
;
2688 if (pc
->core_id
== -1 || --pc
->refcnt
== 0)
2690 cpuc
->shared_regs
= NULL
;
2693 free_excl_cntrs(cpu
);
2695 fini_debug_store_on_cpu(cpu
);
2698 PMU_FORMAT_ATTR(offcore_rsp
, "config1:0-63");
2700 PMU_FORMAT_ATTR(ldlat
, "config1:0-15");
2702 static struct attribute
*intel_arch3_formats_attr
[] = {
2703 &format_attr_event
.attr
,
2704 &format_attr_umask
.attr
,
2705 &format_attr_edge
.attr
,
2706 &format_attr_pc
.attr
,
2707 &format_attr_any
.attr
,
2708 &format_attr_inv
.attr
,
2709 &format_attr_cmask
.attr
,
2710 &format_attr_in_tx
.attr
,
2711 &format_attr_in_tx_cp
.attr
,
2713 &format_attr_offcore_rsp
.attr
, /* XXX do NHM/WSM + SNB breakout */
2714 &format_attr_ldlat
.attr
, /* PEBS load latency */
2718 static __initconst
const struct x86_pmu core_pmu
= {
2720 .handle_irq
= x86_pmu_handle_irq
,
2721 .disable_all
= x86_pmu_disable_all
,
2722 .enable_all
= core_pmu_enable_all
,
2723 .enable
= core_pmu_enable_event
,
2724 .disable
= x86_pmu_disable_event
,
2725 .hw_config
= x86_pmu_hw_config
,
2726 .schedule_events
= x86_schedule_events
,
2727 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
2728 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
2729 .event_map
= intel_pmu_event_map
,
2730 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
2733 * Intel PMCs cannot be accessed sanely above 32-bit width,
2734 * so we install an artificial 1<<31 period regardless of
2735 * the generic event period:
2737 .max_period
= (1ULL<<31) - 1,
2738 .get_event_constraints
= intel_get_event_constraints
,
2739 .put_event_constraints
= intel_put_event_constraints
,
2740 .event_constraints
= intel_core_event_constraints
,
2741 .guest_get_msrs
= core_guest_get_msrs
,
2742 .format_attrs
= intel_arch_formats_attr
,
2743 .events_sysfs_show
= intel_event_sysfs_show
,
2746 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
2747 * together with PMU version 1 and thus be using core_pmu with
2748 * shared_regs. We need following callbacks here to allocate
2751 .cpu_prepare
= intel_pmu_cpu_prepare
,
2752 .cpu_starting
= intel_pmu_cpu_starting
,
2753 .cpu_dying
= intel_pmu_cpu_dying
,
2756 static __initconst
const struct x86_pmu intel_pmu
= {
2758 .handle_irq
= intel_pmu_handle_irq
,
2759 .disable_all
= intel_pmu_disable_all
,
2760 .enable_all
= intel_pmu_enable_all
,
2761 .enable
= intel_pmu_enable_event
,
2762 .disable
= intel_pmu_disable_event
,
2763 .hw_config
= intel_pmu_hw_config
,
2764 .schedule_events
= x86_schedule_events
,
2765 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
2766 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
2767 .event_map
= intel_pmu_event_map
,
2768 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
2771 * Intel PMCs cannot be accessed sanely above 32 bit width,
2772 * so we install an artificial 1<<31 period regardless of
2773 * the generic event period:
2775 .max_period
= (1ULL << 31) - 1,
2776 .get_event_constraints
= intel_get_event_constraints
,
2777 .put_event_constraints
= intel_put_event_constraints
,
2778 .pebs_aliases
= intel_pebs_aliases_core2
,
2780 .format_attrs
= intel_arch3_formats_attr
,
2781 .events_sysfs_show
= intel_event_sysfs_show
,
2783 .cpu_prepare
= intel_pmu_cpu_prepare
,
2784 .cpu_starting
= intel_pmu_cpu_starting
,
2785 .cpu_dying
= intel_pmu_cpu_dying
,
2786 .guest_get_msrs
= intel_guest_get_msrs
,
2787 .sched_task
= intel_pmu_lbr_sched_task
,
2790 static __init
void intel_clovertown_quirk(void)
2793 * PEBS is unreliable due to:
2795 * AJ67 - PEBS may experience CPL leaks
2796 * AJ68 - PEBS PMI may be delayed by one event
2797 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2798 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2800 * AJ67 could be worked around by restricting the OS/USR flags.
2801 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2803 * AJ106 could possibly be worked around by not allowing LBR
2804 * usage from PEBS, including the fixup.
2805 * AJ68 could possibly be worked around by always programming
2806 * a pebs_event_reset[0] value and coping with the lost events.
2808 * But taken together it might just make sense to not enable PEBS on
2811 pr_warn("PEBS disabled due to CPU errata\n");
2813 x86_pmu
.pebs_constraints
= NULL
;
2816 static int intel_snb_pebs_broken(int cpu
)
2818 u32 rev
= UINT_MAX
; /* default to broken for unknown models */
2820 switch (cpu_data(cpu
).x86_model
) {
2825 case 45: /* SNB-EP */
2826 switch (cpu_data(cpu
).x86_mask
) {
2827 case 6: rev
= 0x618; break;
2828 case 7: rev
= 0x70c; break;
2832 return (cpu_data(cpu
).microcode
< rev
);
2835 static void intel_snb_check_microcode(void)
2837 int pebs_broken
= 0;
2841 for_each_online_cpu(cpu
) {
2842 if ((pebs_broken
= intel_snb_pebs_broken(cpu
)))
2847 if (pebs_broken
== x86_pmu
.pebs_broken
)
2851 * Serialized by the microcode lock..
2853 if (x86_pmu
.pebs_broken
) {
2854 pr_info("PEBS enabled due to microcode update\n");
2855 x86_pmu
.pebs_broken
= 0;
2857 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2858 x86_pmu
.pebs_broken
= 1;
2863 * Under certain circumstances, access certain MSR may cause #GP.
2864 * The function tests if the input MSR can be safely accessed.
2866 static bool check_msr(unsigned long msr
, u64 mask
)
2868 u64 val_old
, val_new
, val_tmp
;
2871 * Read the current value, change it and read it back to see if it
2872 * matches, this is needed to detect certain hardware emulators
2873 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2875 if (rdmsrl_safe(msr
, &val_old
))
2879 * Only change the bits which can be updated by wrmsrl.
2881 val_tmp
= val_old
^ mask
;
2882 if (wrmsrl_safe(msr
, val_tmp
) ||
2883 rdmsrl_safe(msr
, &val_new
))
2886 if (val_new
!= val_tmp
)
2889 /* Here it's sure that the MSR can be safely accessed.
2890 * Restore the old value and return.
2892 wrmsrl(msr
, val_old
);
2897 static __init
void intel_sandybridge_quirk(void)
2899 x86_pmu
.check_microcode
= intel_snb_check_microcode
;
2900 intel_snb_check_microcode();
2903 static const struct { int id
; char *name
; } intel_arch_events_map
[] __initconst
= {
2904 { PERF_COUNT_HW_CPU_CYCLES
, "cpu cycles" },
2905 { PERF_COUNT_HW_INSTRUCTIONS
, "instructions" },
2906 { PERF_COUNT_HW_BUS_CYCLES
, "bus cycles" },
2907 { PERF_COUNT_HW_CACHE_REFERENCES
, "cache references" },
2908 { PERF_COUNT_HW_CACHE_MISSES
, "cache misses" },
2909 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS
, "branch instructions" },
2910 { PERF_COUNT_HW_BRANCH_MISSES
, "branch misses" },
2913 static __init
void intel_arch_events_quirk(void)
2917 /* disable event that reported as not presend by cpuid */
2918 for_each_set_bit(bit
, x86_pmu
.events_mask
, ARRAY_SIZE(intel_arch_events_map
)) {
2919 intel_perfmon_event_map
[intel_arch_events_map
[bit
].id
] = 0;
2920 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2921 intel_arch_events_map
[bit
].name
);
2925 static __init
void intel_nehalem_quirk(void)
2927 union cpuid10_ebx ebx
;
2929 ebx
.full
= x86_pmu
.events_maskl
;
2930 if (ebx
.split
.no_branch_misses_retired
) {
2932 * Erratum AAJ80 detected, we work it around by using
2933 * the BR_MISP_EXEC.ANY event. This will over-count
2934 * branch-misses, but it's still much better than the
2935 * architectural event which is often completely bogus:
2937 intel_perfmon_event_map
[PERF_COUNT_HW_BRANCH_MISSES
] = 0x7f89;
2938 ebx
.split
.no_branch_misses_retired
= 0;
2939 x86_pmu
.events_maskl
= ebx
.full
;
2940 pr_info("CPU erratum AAJ80 worked around\n");
2945 * enable software workaround for errata:
2950 * Only needed when HT is enabled. However detecting
2951 * if HT is enabled is difficult (model specific). So instead,
2952 * we enable the workaround in the early boot, and verify if
2953 * it is needed in a later initcall phase once we have valid
2954 * topology information to check if HT is actually enabled
2956 static __init
void intel_ht_bug(void)
2958 x86_pmu
.flags
|= PMU_FL_EXCL_CNTRS
| PMU_FL_EXCL_ENABLED
;
2960 x86_pmu
.commit_scheduling
= intel_commit_scheduling
;
2961 x86_pmu
.start_scheduling
= intel_start_scheduling
;
2962 x86_pmu
.stop_scheduling
= intel_stop_scheduling
;
2965 EVENT_ATTR_STR(mem
-loads
, mem_ld_hsw
, "event=0xcd,umask=0x1,ldlat=3");
2966 EVENT_ATTR_STR(mem
-stores
, mem_st_hsw
, "event=0xd0,umask=0x82")
2968 /* Haswell special events */
2969 EVENT_ATTR_STR(tx
-start
, tx_start
, "event=0xc9,umask=0x1");
2970 EVENT_ATTR_STR(tx
-commit
, tx_commit
, "event=0xc9,umask=0x2");
2971 EVENT_ATTR_STR(tx
-abort
, tx_abort
, "event=0xc9,umask=0x4");
2972 EVENT_ATTR_STR(tx
-capacity
, tx_capacity
, "event=0x54,umask=0x2");
2973 EVENT_ATTR_STR(tx
-conflict
, tx_conflict
, "event=0x54,umask=0x1");
2974 EVENT_ATTR_STR(el
-start
, el_start
, "event=0xc8,umask=0x1");
2975 EVENT_ATTR_STR(el
-commit
, el_commit
, "event=0xc8,umask=0x2");
2976 EVENT_ATTR_STR(el
-abort
, el_abort
, "event=0xc8,umask=0x4");
2977 EVENT_ATTR_STR(el
-capacity
, el_capacity
, "event=0x54,umask=0x2");
2978 EVENT_ATTR_STR(el
-conflict
, el_conflict
, "event=0x54,umask=0x1");
2979 EVENT_ATTR_STR(cycles
-t
, cycles_t
, "event=0x3c,in_tx=1");
2980 EVENT_ATTR_STR(cycles
-ct
, cycles_ct
, "event=0x3c,in_tx=1,in_tx_cp=1");
2982 static struct attribute
*hsw_events_attrs
[] = {
2983 EVENT_PTR(tx_start
),
2984 EVENT_PTR(tx_commit
),
2985 EVENT_PTR(tx_abort
),
2986 EVENT_PTR(tx_capacity
),
2987 EVENT_PTR(tx_conflict
),
2988 EVENT_PTR(el_start
),
2989 EVENT_PTR(el_commit
),
2990 EVENT_PTR(el_abort
),
2991 EVENT_PTR(el_capacity
),
2992 EVENT_PTR(el_conflict
),
2993 EVENT_PTR(cycles_t
),
2994 EVENT_PTR(cycles_ct
),
2995 EVENT_PTR(mem_ld_hsw
),
2996 EVENT_PTR(mem_st_hsw
),
3000 __init
int intel_pmu_init(void)
3002 union cpuid10_edx edx
;
3003 union cpuid10_eax eax
;
3004 union cpuid10_ebx ebx
;
3005 struct event_constraint
*c
;
3006 unsigned int unused
;
3007 struct extra_reg
*er
;
3010 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
)) {
3011 switch (boot_cpu_data
.x86
) {
3013 return p6_pmu_init();
3015 return knc_pmu_init();
3017 return p4_pmu_init();
3023 * Check whether the Architectural PerfMon supports
3024 * Branch Misses Retired hw_event or not.
3026 cpuid(10, &eax
.full
, &ebx
.full
, &unused
, &edx
.full
);
3027 if (eax
.split
.mask_length
< ARCH_PERFMON_EVENTS_COUNT
)
3030 version
= eax
.split
.version_id
;
3034 x86_pmu
= intel_pmu
;
3036 x86_pmu
.version
= version
;
3037 x86_pmu
.num_counters
= eax
.split
.num_counters
;
3038 x86_pmu
.cntval_bits
= eax
.split
.bit_width
;
3039 x86_pmu
.cntval_mask
= (1ULL << eax
.split
.bit_width
) - 1;
3041 x86_pmu
.events_maskl
= ebx
.full
;
3042 x86_pmu
.events_mask_len
= eax
.split
.mask_length
;
3044 x86_pmu
.max_pebs_events
= min_t(unsigned, MAX_PEBS_EVENTS
, x86_pmu
.num_counters
);
3047 * Quirk: v2 perfmon does not report fixed-purpose events, so
3048 * assume at least 3 events:
3051 x86_pmu
.num_counters_fixed
= max((int)edx
.split
.num_counters_fixed
, 3);
3053 if (boot_cpu_has(X86_FEATURE_PDCM
)) {
3056 rdmsrl(MSR_IA32_PERF_CAPABILITIES
, capabilities
);
3057 x86_pmu
.intel_cap
.capabilities
= capabilities
;
3062 x86_add_quirk(intel_arch_events_quirk
); /* Install first, so it runs last */
3065 * Install the hw-cache-events table:
3067 switch (boot_cpu_data
.x86_model
) {
3068 case 14: /* 65nm Core "Yonah" */
3069 pr_cont("Core events, ");
3072 case 15: /* 65nm Core2 "Merom" */
3073 x86_add_quirk(intel_clovertown_quirk
);
3074 case 22: /* 65nm Core2 "Merom-L" */
3075 case 23: /* 45nm Core2 "Penryn" */
3076 case 29: /* 45nm Core2 "Dunnington (MP) */
3077 memcpy(hw_cache_event_ids
, core2_hw_cache_event_ids
,
3078 sizeof(hw_cache_event_ids
));
3080 intel_pmu_lbr_init_core();
3082 x86_pmu
.event_constraints
= intel_core2_event_constraints
;
3083 x86_pmu
.pebs_constraints
= intel_core2_pebs_event_constraints
;
3084 pr_cont("Core2 events, ");
3087 case 30: /* 45nm Nehalem */
3088 case 26: /* 45nm Nehalem-EP */
3089 case 46: /* 45nm Nehalem-EX */
3090 memcpy(hw_cache_event_ids
, nehalem_hw_cache_event_ids
,
3091 sizeof(hw_cache_event_ids
));
3092 memcpy(hw_cache_extra_regs
, nehalem_hw_cache_extra_regs
,
3093 sizeof(hw_cache_extra_regs
));
3095 intel_pmu_lbr_init_nhm();
3097 x86_pmu
.event_constraints
= intel_nehalem_event_constraints
;
3098 x86_pmu
.pebs_constraints
= intel_nehalem_pebs_event_constraints
;
3099 x86_pmu
.enable_all
= intel_pmu_nhm_enable_all
;
3100 x86_pmu
.extra_regs
= intel_nehalem_extra_regs
;
3102 x86_pmu
.cpu_events
= nhm_events_attrs
;
3104 /* UOPS_ISSUED.STALLED_CYCLES */
3105 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
3106 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
3107 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3108 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] =
3109 X86_CONFIG(.event
=0xb1, .umask
=0x3f, .inv
=1, .cmask
=1);
3111 x86_add_quirk(intel_nehalem_quirk
);
3113 pr_cont("Nehalem events, ");
3116 case 28: /* 45nm Atom "Pineview" */
3117 case 38: /* 45nm Atom "Lincroft" */
3118 case 39: /* 32nm Atom "Penwell" */
3119 case 53: /* 32nm Atom "Cloverview" */
3120 case 54: /* 32nm Atom "Cedarview" */
3121 memcpy(hw_cache_event_ids
, atom_hw_cache_event_ids
,
3122 sizeof(hw_cache_event_ids
));
3124 intel_pmu_lbr_init_atom();
3126 x86_pmu
.event_constraints
= intel_gen_event_constraints
;
3127 x86_pmu
.pebs_constraints
= intel_atom_pebs_event_constraints
;
3128 pr_cont("Atom events, ");
3131 case 55: /* 22nm Atom "Silvermont" */
3132 case 76: /* 14nm Atom "Airmont" */
3133 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
3134 memcpy(hw_cache_event_ids
, slm_hw_cache_event_ids
,
3135 sizeof(hw_cache_event_ids
));
3136 memcpy(hw_cache_extra_regs
, slm_hw_cache_extra_regs
,
3137 sizeof(hw_cache_extra_regs
));
3139 intel_pmu_lbr_init_atom();
3141 x86_pmu
.event_constraints
= intel_slm_event_constraints
;
3142 x86_pmu
.pebs_constraints
= intel_slm_pebs_event_constraints
;
3143 x86_pmu
.extra_regs
= intel_slm_extra_regs
;
3144 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
3145 pr_cont("Silvermont events, ");
3148 case 37: /* 32nm Westmere */
3149 case 44: /* 32nm Westmere-EP */
3150 case 47: /* 32nm Westmere-EX */
3151 memcpy(hw_cache_event_ids
, westmere_hw_cache_event_ids
,
3152 sizeof(hw_cache_event_ids
));
3153 memcpy(hw_cache_extra_regs
, nehalem_hw_cache_extra_regs
,
3154 sizeof(hw_cache_extra_regs
));
3156 intel_pmu_lbr_init_nhm();
3158 x86_pmu
.event_constraints
= intel_westmere_event_constraints
;
3159 x86_pmu
.enable_all
= intel_pmu_nhm_enable_all
;
3160 x86_pmu
.pebs_constraints
= intel_westmere_pebs_event_constraints
;
3161 x86_pmu
.extra_regs
= intel_westmere_extra_regs
;
3162 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
3164 x86_pmu
.cpu_events
= nhm_events_attrs
;
3166 /* UOPS_ISSUED.STALLED_CYCLES */
3167 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
3168 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
3169 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
3170 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] =
3171 X86_CONFIG(.event
=0xb1, .umask
=0x3f, .inv
=1, .cmask
=1);
3173 pr_cont("Westmere events, ");
3176 case 42: /* 32nm SandyBridge */
3177 case 45: /* 32nm SandyBridge-E/EN/EP */
3178 x86_add_quirk(intel_sandybridge_quirk
);
3179 x86_add_quirk(intel_ht_bug
);
3180 memcpy(hw_cache_event_ids
, snb_hw_cache_event_ids
,
3181 sizeof(hw_cache_event_ids
));
3182 memcpy(hw_cache_extra_regs
, snb_hw_cache_extra_regs
,
3183 sizeof(hw_cache_extra_regs
));
3185 intel_pmu_lbr_init_snb();
3187 x86_pmu
.event_constraints
= intel_snb_event_constraints
;
3188 x86_pmu
.pebs_constraints
= intel_snb_pebs_event_constraints
;
3189 x86_pmu
.pebs_aliases
= intel_pebs_aliases_snb
;
3190 if (boot_cpu_data
.x86_model
== 45)
3191 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
3193 x86_pmu
.extra_regs
= intel_snb_extra_regs
;
3196 /* all extra regs are per-cpu when HT is on */
3197 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
3198 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
3200 x86_pmu
.cpu_events
= snb_events_attrs
;
3202 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3203 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
3204 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
3205 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
3206 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND
] =
3207 X86_CONFIG(.event
=0xb1, .umask
=0x01, .inv
=1, .cmask
=1);
3209 pr_cont("SandyBridge events, ");
3212 case 58: /* 22nm IvyBridge */
3213 case 62: /* 22nm IvyBridge-EP/EX */
3214 x86_add_quirk(intel_ht_bug
);
3215 memcpy(hw_cache_event_ids
, snb_hw_cache_event_ids
,
3216 sizeof(hw_cache_event_ids
));
3217 /* dTLB-load-misses on IVB is different than SNB */
3218 hw_cache_event_ids
[C(DTLB
)][C(OP_READ
)][C(RESULT_MISS
)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3220 memcpy(hw_cache_extra_regs
, snb_hw_cache_extra_regs
,
3221 sizeof(hw_cache_extra_regs
));
3223 intel_pmu_lbr_init_snb();
3225 x86_pmu
.event_constraints
= intel_ivb_event_constraints
;
3226 x86_pmu
.pebs_constraints
= intel_ivb_pebs_event_constraints
;
3227 x86_pmu
.pebs_aliases
= intel_pebs_aliases_snb
;
3228 if (boot_cpu_data
.x86_model
== 62)
3229 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
3231 x86_pmu
.extra_regs
= intel_snb_extra_regs
;
3232 /* all extra regs are per-cpu when HT is on */
3233 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
3234 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
3236 x86_pmu
.cpu_events
= snb_events_attrs
;
3238 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3239 intel_perfmon_event_map
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
] =
3240 X86_CONFIG(.event
=0x0e, .umask
=0x01, .inv
=1, .cmask
=1);
3242 pr_cont("IvyBridge events, ");
3246 case 60: /* 22nm Haswell Core */
3247 case 63: /* 22nm Haswell Server */
3248 case 69: /* 22nm Haswell ULT */
3249 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
3250 x86_add_quirk(intel_ht_bug
);
3251 x86_pmu
.late_ack
= true;
3252 memcpy(hw_cache_event_ids
, hsw_hw_cache_event_ids
, sizeof(hw_cache_event_ids
));
3253 memcpy(hw_cache_extra_regs
, hsw_hw_cache_extra_regs
, sizeof(hw_cache_extra_regs
));
3255 intel_pmu_lbr_init_hsw();
3257 x86_pmu
.event_constraints
= intel_hsw_event_constraints
;
3258 x86_pmu
.pebs_constraints
= intel_hsw_pebs_event_constraints
;
3259 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
3260 x86_pmu
.pebs_aliases
= intel_pebs_aliases_snb
;
3261 /* all extra regs are per-cpu when HT is on */
3262 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
3263 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
3265 x86_pmu
.hw_config
= hsw_hw_config
;
3266 x86_pmu
.get_event_constraints
= hsw_get_event_constraints
;
3267 x86_pmu
.cpu_events
= hsw_events_attrs
;
3268 x86_pmu
.lbr_double_abort
= true;
3269 pr_cont("Haswell events, ");
3272 case 61: /* 14nm Broadwell Core-M */
3273 case 86: /* 14nm Broadwell Xeon D */
3274 x86_pmu
.late_ack
= true;
3275 memcpy(hw_cache_event_ids
, hsw_hw_cache_event_ids
, sizeof(hw_cache_event_ids
));
3276 memcpy(hw_cache_extra_regs
, hsw_hw_cache_extra_regs
, sizeof(hw_cache_extra_regs
));
3278 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3279 hw_cache_extra_regs
[C(LL
)][C(OP_READ
)][C(RESULT_MISS
)] = HSW_DEMAND_READ
|
3280 BDW_L3_MISS
|HSW_SNOOP_DRAM
;
3281 hw_cache_extra_regs
[C(LL
)][C(OP_WRITE
)][C(RESULT_MISS
)] = HSW_DEMAND_WRITE
|BDW_L3_MISS
|
3283 hw_cache_extra_regs
[C(NODE
)][C(OP_READ
)][C(RESULT_ACCESS
)] = HSW_DEMAND_READ
|
3284 BDW_L3_MISS_LOCAL
|HSW_SNOOP_DRAM
;
3285 hw_cache_extra_regs
[C(NODE
)][C(OP_WRITE
)][C(RESULT_ACCESS
)] = HSW_DEMAND_WRITE
|
3286 BDW_L3_MISS_LOCAL
|HSW_SNOOP_DRAM
;
3288 intel_pmu_lbr_init_hsw();
3290 x86_pmu
.event_constraints
= intel_bdw_event_constraints
;
3291 x86_pmu
.pebs_constraints
= intel_hsw_pebs_event_constraints
;
3292 x86_pmu
.extra_regs
= intel_snbep_extra_regs
;
3293 x86_pmu
.pebs_aliases
= intel_pebs_aliases_snb
;
3294 /* all extra regs are per-cpu when HT is on */
3295 x86_pmu
.flags
|= PMU_FL_HAS_RSP_1
;
3296 x86_pmu
.flags
|= PMU_FL_NO_HT_SHARING
;
3298 x86_pmu
.hw_config
= hsw_hw_config
;
3299 x86_pmu
.get_event_constraints
= hsw_get_event_constraints
;
3300 x86_pmu
.cpu_events
= hsw_events_attrs
;
3301 x86_pmu
.limit_period
= bdw_limit_period
;
3302 pr_cont("Broadwell events, ");
3306 switch (x86_pmu
.version
) {
3308 x86_pmu
.event_constraints
= intel_v1_event_constraints
;
3309 pr_cont("generic architected perfmon v1, ");
3313 * default constraints for v2 and up
3315 x86_pmu
.event_constraints
= intel_gen_event_constraints
;
3316 pr_cont("generic architected perfmon, ");
3321 if (x86_pmu
.num_counters
> INTEL_PMC_MAX_GENERIC
) {
3322 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
3323 x86_pmu
.num_counters
, INTEL_PMC_MAX_GENERIC
);
3324 x86_pmu
.num_counters
= INTEL_PMC_MAX_GENERIC
;
3326 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
3328 if (x86_pmu
.num_counters_fixed
> INTEL_PMC_MAX_FIXED
) {
3329 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
3330 x86_pmu
.num_counters_fixed
, INTEL_PMC_MAX_FIXED
);
3331 x86_pmu
.num_counters_fixed
= INTEL_PMC_MAX_FIXED
;
3334 x86_pmu
.intel_ctrl
|=
3335 ((1LL << x86_pmu
.num_counters_fixed
)-1) << INTEL_PMC_IDX_FIXED
;
3337 if (x86_pmu
.event_constraints
) {
3339 * event on fixed counter2 (REF_CYCLES) only works on this
3340 * counter, so do not extend mask to generic counters
3342 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
3343 if (c
->cmask
!= FIXED_EVENT_FLAGS
3344 || c
->idxmsk64
== INTEL_PMC_MSK_FIXED_REF_CYCLES
) {
3348 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
3349 c
->weight
+= x86_pmu
.num_counters
;
3354 * Access LBR MSR may cause #GP under certain circumstances.
3355 * E.g. KVM doesn't support LBR MSR
3356 * Check all LBT MSR here.
3357 * Disable LBR access if any LBR MSRs can not be accessed.
3359 if (x86_pmu
.lbr_nr
&& !check_msr(x86_pmu
.lbr_tos
, 0x3UL
))
3361 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
3362 if (!(check_msr(x86_pmu
.lbr_from
+ i
, 0xffffUL
) &&
3363 check_msr(x86_pmu
.lbr_to
+ i
, 0xffffUL
)))
3368 * Access extra MSR may cause #GP under certain circumstances.
3369 * E.g. KVM doesn't support offcore event
3370 * Check all extra_regs here.
3372 if (x86_pmu
.extra_regs
) {
3373 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
3374 er
->extra_msr_access
= check_msr(er
->msr
, 0x1ffUL
);
3375 /* Disable LBR select mapping */
3376 if ((er
->idx
== EXTRA_REG_LBR
) && !er
->extra_msr_access
)
3377 x86_pmu
.lbr_sel_map
= NULL
;
3381 /* Support full width counters using alternative MSR range */
3382 if (x86_pmu
.intel_cap
.full_width_write
) {
3383 x86_pmu
.max_period
= x86_pmu
.cntval_mask
;
3384 x86_pmu
.perfctr
= MSR_IA32_PMC0
;
3385 pr_cont("full-width counters, ");
3392 * HT bug: phase 2 init
3393 * Called once we have valid topology information to check
3394 * whether or not HT is enabled
3395 * If HT is off, then we disable the workaround
3397 static __init
int fixup_ht_bug(void)
3399 int cpu
= smp_processor_id();
3402 * problem not present on this CPU model, nothing to do
3404 if (!(x86_pmu
.flags
& PMU_FL_EXCL_ENABLED
))
3407 w
= cpumask_weight(topology_thread_cpumask(cpu
));
3409 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3413 watchdog_nmi_disable_all();
3415 x86_pmu
.flags
&= ~(PMU_FL_EXCL_CNTRS
| PMU_FL_EXCL_ENABLED
);
3417 x86_pmu
.commit_scheduling
= NULL
;
3418 x86_pmu
.start_scheduling
= NULL
;
3419 x86_pmu
.stop_scheduling
= NULL
;
3421 watchdog_nmi_enable_all();
3425 for_each_online_cpu(c
) {
3430 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3433 subsys_initcall(fixup_ht_bug
)