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Merge tag 'perf-core-for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel.c
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15
16 #include <asm/cpufeature.h>
17 #include <asm/hardirq.h>
18 #include <asm/apic.h>
19
20 #include "perf_event.h"
21
22 /*
23 * Intel PerfMon, used on Core and later.
24 */
25 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
26 {
27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
35 };
36
37 static struct event_constraint intel_core_event_constraints[] __read_mostly =
38 {
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46 };
47
48 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
49 {
50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64 };
65
66 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
67 {
68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80 };
81
82 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
83 {
84 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
85 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
86 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
87 EVENT_EXTRA_END
88 };
89
90 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
91 {
92 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
93 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
94 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
95 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
96 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
97 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
98 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
99 EVENT_CONSTRAINT_END
100 };
101
102 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
103 {
104 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
105 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
106 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
107 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
108 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
111 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
113 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
116 EVENT_CONSTRAINT_END
117 };
118
119 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
120 {
121 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
122 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
123 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
124 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
125 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
126 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
127 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
128 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
129 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
133 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
134 /*
135 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
136 * siblings; disable these events because they can corrupt unrelated
137 * counters.
138 */
139 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
141 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
142 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
143 EVENT_CONSTRAINT_END
144 };
145
146 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
147 {
148 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
149 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
150 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
151 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
152 EVENT_EXTRA_END
153 };
154
155 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
156 {
157 EVENT_CONSTRAINT_END
158 };
159
160 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
161 {
162 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
163 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
164 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
165 EVENT_CONSTRAINT_END
166 };
167
168 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
169 {
170 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
171 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
172 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
173 EVENT_CONSTRAINT_END
174 };
175
176 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
177 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
178 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
179 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
180 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
181 EVENT_EXTRA_END
182 };
183
184 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
185 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
186 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
187 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
188 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
189 EVENT_EXTRA_END
190 };
191
192 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
193 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
194 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
195
196 struct attribute *nhm_events_attrs[] = {
197 EVENT_PTR(mem_ld_nhm),
198 NULL,
199 };
200
201 struct attribute *snb_events_attrs[] = {
202 EVENT_PTR(mem_ld_snb),
203 EVENT_PTR(mem_st_snb),
204 NULL,
205 };
206
207 static struct event_constraint intel_hsw_event_constraints[] = {
208 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
209 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
210 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
211 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
212 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
213 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
214 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
215 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
216 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
217 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
218 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
219 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
220 EVENT_CONSTRAINT_END
221 };
222
223 static u64 intel_pmu_event_map(int hw_event)
224 {
225 return intel_perfmon_event_map[hw_event];
226 }
227
228 #define SNB_DMND_DATA_RD (1ULL << 0)
229 #define SNB_DMND_RFO (1ULL << 1)
230 #define SNB_DMND_IFETCH (1ULL << 2)
231 #define SNB_DMND_WB (1ULL << 3)
232 #define SNB_PF_DATA_RD (1ULL << 4)
233 #define SNB_PF_RFO (1ULL << 5)
234 #define SNB_PF_IFETCH (1ULL << 6)
235 #define SNB_LLC_DATA_RD (1ULL << 7)
236 #define SNB_LLC_RFO (1ULL << 8)
237 #define SNB_LLC_IFETCH (1ULL << 9)
238 #define SNB_BUS_LOCKS (1ULL << 10)
239 #define SNB_STRM_ST (1ULL << 11)
240 #define SNB_OTHER (1ULL << 15)
241 #define SNB_RESP_ANY (1ULL << 16)
242 #define SNB_NO_SUPP (1ULL << 17)
243 #define SNB_LLC_HITM (1ULL << 18)
244 #define SNB_LLC_HITE (1ULL << 19)
245 #define SNB_LLC_HITS (1ULL << 20)
246 #define SNB_LLC_HITF (1ULL << 21)
247 #define SNB_LOCAL (1ULL << 22)
248 #define SNB_REMOTE (0xffULL << 23)
249 #define SNB_SNP_NONE (1ULL << 31)
250 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
251 #define SNB_SNP_MISS (1ULL << 33)
252 #define SNB_NO_FWD (1ULL << 34)
253 #define SNB_SNP_FWD (1ULL << 35)
254 #define SNB_HITM (1ULL << 36)
255 #define SNB_NON_DRAM (1ULL << 37)
256
257 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
258 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
259 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
260
261 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
262 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
263 SNB_HITM)
264
265 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
266 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
267
268 #define SNB_L3_ACCESS SNB_RESP_ANY
269 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
270
271 static __initconst const u64 snb_hw_cache_extra_regs
272 [PERF_COUNT_HW_CACHE_MAX]
273 [PERF_COUNT_HW_CACHE_OP_MAX]
274 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
275 {
276 [ C(LL ) ] = {
277 [ C(OP_READ) ] = {
278 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
279 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
280 },
281 [ C(OP_WRITE) ] = {
282 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
283 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
284 },
285 [ C(OP_PREFETCH) ] = {
286 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
287 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
288 },
289 },
290 [ C(NODE) ] = {
291 [ C(OP_READ) ] = {
292 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
293 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
294 },
295 [ C(OP_WRITE) ] = {
296 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
297 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
298 },
299 [ C(OP_PREFETCH) ] = {
300 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
301 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
302 },
303 },
304 };
305
306 static __initconst const u64 snb_hw_cache_event_ids
307 [PERF_COUNT_HW_CACHE_MAX]
308 [PERF_COUNT_HW_CACHE_OP_MAX]
309 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
310 {
311 [ C(L1D) ] = {
312 [ C(OP_READ) ] = {
313 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
314 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
315 },
316 [ C(OP_WRITE) ] = {
317 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
318 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
319 },
320 [ C(OP_PREFETCH) ] = {
321 [ C(RESULT_ACCESS) ] = 0x0,
322 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
323 },
324 },
325 [ C(L1I ) ] = {
326 [ C(OP_READ) ] = {
327 [ C(RESULT_ACCESS) ] = 0x0,
328 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
329 },
330 [ C(OP_WRITE) ] = {
331 [ C(RESULT_ACCESS) ] = -1,
332 [ C(RESULT_MISS) ] = -1,
333 },
334 [ C(OP_PREFETCH) ] = {
335 [ C(RESULT_ACCESS) ] = 0x0,
336 [ C(RESULT_MISS) ] = 0x0,
337 },
338 },
339 [ C(LL ) ] = {
340 [ C(OP_READ) ] = {
341 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
342 [ C(RESULT_ACCESS) ] = 0x01b7,
343 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
344 [ C(RESULT_MISS) ] = 0x01b7,
345 },
346 [ C(OP_WRITE) ] = {
347 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
348 [ C(RESULT_ACCESS) ] = 0x01b7,
349 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
350 [ C(RESULT_MISS) ] = 0x01b7,
351 },
352 [ C(OP_PREFETCH) ] = {
353 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
354 [ C(RESULT_ACCESS) ] = 0x01b7,
355 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
356 [ C(RESULT_MISS) ] = 0x01b7,
357 },
358 },
359 [ C(DTLB) ] = {
360 [ C(OP_READ) ] = {
361 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
362 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
363 },
364 [ C(OP_WRITE) ] = {
365 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
366 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
367 },
368 [ C(OP_PREFETCH) ] = {
369 [ C(RESULT_ACCESS) ] = 0x0,
370 [ C(RESULT_MISS) ] = 0x0,
371 },
372 },
373 [ C(ITLB) ] = {
374 [ C(OP_READ) ] = {
375 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
376 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
377 },
378 [ C(OP_WRITE) ] = {
379 [ C(RESULT_ACCESS) ] = -1,
380 [ C(RESULT_MISS) ] = -1,
381 },
382 [ C(OP_PREFETCH) ] = {
383 [ C(RESULT_ACCESS) ] = -1,
384 [ C(RESULT_MISS) ] = -1,
385 },
386 },
387 [ C(BPU ) ] = {
388 [ C(OP_READ) ] = {
389 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
390 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
391 },
392 [ C(OP_WRITE) ] = {
393 [ C(RESULT_ACCESS) ] = -1,
394 [ C(RESULT_MISS) ] = -1,
395 },
396 [ C(OP_PREFETCH) ] = {
397 [ C(RESULT_ACCESS) ] = -1,
398 [ C(RESULT_MISS) ] = -1,
399 },
400 },
401 [ C(NODE) ] = {
402 [ C(OP_READ) ] = {
403 [ C(RESULT_ACCESS) ] = 0x01b7,
404 [ C(RESULT_MISS) ] = 0x01b7,
405 },
406 [ C(OP_WRITE) ] = {
407 [ C(RESULT_ACCESS) ] = 0x01b7,
408 [ C(RESULT_MISS) ] = 0x01b7,
409 },
410 [ C(OP_PREFETCH) ] = {
411 [ C(RESULT_ACCESS) ] = 0x01b7,
412 [ C(RESULT_MISS) ] = 0x01b7,
413 },
414 },
415
416 };
417
418 static __initconst const u64 westmere_hw_cache_event_ids
419 [PERF_COUNT_HW_CACHE_MAX]
420 [PERF_COUNT_HW_CACHE_OP_MAX]
421 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
422 {
423 [ C(L1D) ] = {
424 [ C(OP_READ) ] = {
425 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
426 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
427 },
428 [ C(OP_WRITE) ] = {
429 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
430 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
431 },
432 [ C(OP_PREFETCH) ] = {
433 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
434 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
435 },
436 },
437 [ C(L1I ) ] = {
438 [ C(OP_READ) ] = {
439 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
440 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
441 },
442 [ C(OP_WRITE) ] = {
443 [ C(RESULT_ACCESS) ] = -1,
444 [ C(RESULT_MISS) ] = -1,
445 },
446 [ C(OP_PREFETCH) ] = {
447 [ C(RESULT_ACCESS) ] = 0x0,
448 [ C(RESULT_MISS) ] = 0x0,
449 },
450 },
451 [ C(LL ) ] = {
452 [ C(OP_READ) ] = {
453 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
454 [ C(RESULT_ACCESS) ] = 0x01b7,
455 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
456 [ C(RESULT_MISS) ] = 0x01b7,
457 },
458 /*
459 * Use RFO, not WRITEBACK, because a write miss would typically occur
460 * on RFO.
461 */
462 [ C(OP_WRITE) ] = {
463 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
464 [ C(RESULT_ACCESS) ] = 0x01b7,
465 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
466 [ C(RESULT_MISS) ] = 0x01b7,
467 },
468 [ C(OP_PREFETCH) ] = {
469 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
470 [ C(RESULT_ACCESS) ] = 0x01b7,
471 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
472 [ C(RESULT_MISS) ] = 0x01b7,
473 },
474 },
475 [ C(DTLB) ] = {
476 [ C(OP_READ) ] = {
477 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
478 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
479 },
480 [ C(OP_WRITE) ] = {
481 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
482 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
483 },
484 [ C(OP_PREFETCH) ] = {
485 [ C(RESULT_ACCESS) ] = 0x0,
486 [ C(RESULT_MISS) ] = 0x0,
487 },
488 },
489 [ C(ITLB) ] = {
490 [ C(OP_READ) ] = {
491 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
492 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
493 },
494 [ C(OP_WRITE) ] = {
495 [ C(RESULT_ACCESS) ] = -1,
496 [ C(RESULT_MISS) ] = -1,
497 },
498 [ C(OP_PREFETCH) ] = {
499 [ C(RESULT_ACCESS) ] = -1,
500 [ C(RESULT_MISS) ] = -1,
501 },
502 },
503 [ C(BPU ) ] = {
504 [ C(OP_READ) ] = {
505 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
506 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
507 },
508 [ C(OP_WRITE) ] = {
509 [ C(RESULT_ACCESS) ] = -1,
510 [ C(RESULT_MISS) ] = -1,
511 },
512 [ C(OP_PREFETCH) ] = {
513 [ C(RESULT_ACCESS) ] = -1,
514 [ C(RESULT_MISS) ] = -1,
515 },
516 },
517 [ C(NODE) ] = {
518 [ C(OP_READ) ] = {
519 [ C(RESULT_ACCESS) ] = 0x01b7,
520 [ C(RESULT_MISS) ] = 0x01b7,
521 },
522 [ C(OP_WRITE) ] = {
523 [ C(RESULT_ACCESS) ] = 0x01b7,
524 [ C(RESULT_MISS) ] = 0x01b7,
525 },
526 [ C(OP_PREFETCH) ] = {
527 [ C(RESULT_ACCESS) ] = 0x01b7,
528 [ C(RESULT_MISS) ] = 0x01b7,
529 },
530 },
531 };
532
533 /*
534 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
535 * See IA32 SDM Vol 3B 30.6.1.3
536 */
537
538 #define NHM_DMND_DATA_RD (1 << 0)
539 #define NHM_DMND_RFO (1 << 1)
540 #define NHM_DMND_IFETCH (1 << 2)
541 #define NHM_DMND_WB (1 << 3)
542 #define NHM_PF_DATA_RD (1 << 4)
543 #define NHM_PF_DATA_RFO (1 << 5)
544 #define NHM_PF_IFETCH (1 << 6)
545 #define NHM_OFFCORE_OTHER (1 << 7)
546 #define NHM_UNCORE_HIT (1 << 8)
547 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
548 #define NHM_OTHER_CORE_HITM (1 << 10)
549 /* reserved */
550 #define NHM_REMOTE_CACHE_FWD (1 << 12)
551 #define NHM_REMOTE_DRAM (1 << 13)
552 #define NHM_LOCAL_DRAM (1 << 14)
553 #define NHM_NON_DRAM (1 << 15)
554
555 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
556 #define NHM_REMOTE (NHM_REMOTE_DRAM)
557
558 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
559 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
560 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
561
562 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
563 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
564 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
565
566 static __initconst const u64 nehalem_hw_cache_extra_regs
567 [PERF_COUNT_HW_CACHE_MAX]
568 [PERF_COUNT_HW_CACHE_OP_MAX]
569 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
570 {
571 [ C(LL ) ] = {
572 [ C(OP_READ) ] = {
573 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
574 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
575 },
576 [ C(OP_WRITE) ] = {
577 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
578 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
579 },
580 [ C(OP_PREFETCH) ] = {
581 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
582 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
583 },
584 },
585 [ C(NODE) ] = {
586 [ C(OP_READ) ] = {
587 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
588 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
589 },
590 [ C(OP_WRITE) ] = {
591 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
592 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
593 },
594 [ C(OP_PREFETCH) ] = {
595 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
596 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
597 },
598 },
599 };
600
601 static __initconst const u64 nehalem_hw_cache_event_ids
602 [PERF_COUNT_HW_CACHE_MAX]
603 [PERF_COUNT_HW_CACHE_OP_MAX]
604 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
605 {
606 [ C(L1D) ] = {
607 [ C(OP_READ) ] = {
608 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
609 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
610 },
611 [ C(OP_WRITE) ] = {
612 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
613 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
614 },
615 [ C(OP_PREFETCH) ] = {
616 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
617 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
618 },
619 },
620 [ C(L1I ) ] = {
621 [ C(OP_READ) ] = {
622 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
623 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
624 },
625 [ C(OP_WRITE) ] = {
626 [ C(RESULT_ACCESS) ] = -1,
627 [ C(RESULT_MISS) ] = -1,
628 },
629 [ C(OP_PREFETCH) ] = {
630 [ C(RESULT_ACCESS) ] = 0x0,
631 [ C(RESULT_MISS) ] = 0x0,
632 },
633 },
634 [ C(LL ) ] = {
635 [ C(OP_READ) ] = {
636 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
637 [ C(RESULT_ACCESS) ] = 0x01b7,
638 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
639 [ C(RESULT_MISS) ] = 0x01b7,
640 },
641 /*
642 * Use RFO, not WRITEBACK, because a write miss would typically occur
643 * on RFO.
644 */
645 [ C(OP_WRITE) ] = {
646 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
647 [ C(RESULT_ACCESS) ] = 0x01b7,
648 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
649 [ C(RESULT_MISS) ] = 0x01b7,
650 },
651 [ C(OP_PREFETCH) ] = {
652 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
653 [ C(RESULT_ACCESS) ] = 0x01b7,
654 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
655 [ C(RESULT_MISS) ] = 0x01b7,
656 },
657 },
658 [ C(DTLB) ] = {
659 [ C(OP_READ) ] = {
660 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
661 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
662 },
663 [ C(OP_WRITE) ] = {
664 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
665 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
666 },
667 [ C(OP_PREFETCH) ] = {
668 [ C(RESULT_ACCESS) ] = 0x0,
669 [ C(RESULT_MISS) ] = 0x0,
670 },
671 },
672 [ C(ITLB) ] = {
673 [ C(OP_READ) ] = {
674 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
675 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
676 },
677 [ C(OP_WRITE) ] = {
678 [ C(RESULT_ACCESS) ] = -1,
679 [ C(RESULT_MISS) ] = -1,
680 },
681 [ C(OP_PREFETCH) ] = {
682 [ C(RESULT_ACCESS) ] = -1,
683 [ C(RESULT_MISS) ] = -1,
684 },
685 },
686 [ C(BPU ) ] = {
687 [ C(OP_READ) ] = {
688 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
689 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
690 },
691 [ C(OP_WRITE) ] = {
692 [ C(RESULT_ACCESS) ] = -1,
693 [ C(RESULT_MISS) ] = -1,
694 },
695 [ C(OP_PREFETCH) ] = {
696 [ C(RESULT_ACCESS) ] = -1,
697 [ C(RESULT_MISS) ] = -1,
698 },
699 },
700 [ C(NODE) ] = {
701 [ C(OP_READ) ] = {
702 [ C(RESULT_ACCESS) ] = 0x01b7,
703 [ C(RESULT_MISS) ] = 0x01b7,
704 },
705 [ C(OP_WRITE) ] = {
706 [ C(RESULT_ACCESS) ] = 0x01b7,
707 [ C(RESULT_MISS) ] = 0x01b7,
708 },
709 [ C(OP_PREFETCH) ] = {
710 [ C(RESULT_ACCESS) ] = 0x01b7,
711 [ C(RESULT_MISS) ] = 0x01b7,
712 },
713 },
714 };
715
716 static __initconst const u64 core2_hw_cache_event_ids
717 [PERF_COUNT_HW_CACHE_MAX]
718 [PERF_COUNT_HW_CACHE_OP_MAX]
719 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
720 {
721 [ C(L1D) ] = {
722 [ C(OP_READ) ] = {
723 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
724 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
725 },
726 [ C(OP_WRITE) ] = {
727 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
728 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
729 },
730 [ C(OP_PREFETCH) ] = {
731 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
732 [ C(RESULT_MISS) ] = 0,
733 },
734 },
735 [ C(L1I ) ] = {
736 [ C(OP_READ) ] = {
737 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
738 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
739 },
740 [ C(OP_WRITE) ] = {
741 [ C(RESULT_ACCESS) ] = -1,
742 [ C(RESULT_MISS) ] = -1,
743 },
744 [ C(OP_PREFETCH) ] = {
745 [ C(RESULT_ACCESS) ] = 0,
746 [ C(RESULT_MISS) ] = 0,
747 },
748 },
749 [ C(LL ) ] = {
750 [ C(OP_READ) ] = {
751 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
752 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
753 },
754 [ C(OP_WRITE) ] = {
755 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
756 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
757 },
758 [ C(OP_PREFETCH) ] = {
759 [ C(RESULT_ACCESS) ] = 0,
760 [ C(RESULT_MISS) ] = 0,
761 },
762 },
763 [ C(DTLB) ] = {
764 [ C(OP_READ) ] = {
765 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
766 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
767 },
768 [ C(OP_WRITE) ] = {
769 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
770 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
771 },
772 [ C(OP_PREFETCH) ] = {
773 [ C(RESULT_ACCESS) ] = 0,
774 [ C(RESULT_MISS) ] = 0,
775 },
776 },
777 [ C(ITLB) ] = {
778 [ C(OP_READ) ] = {
779 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
780 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
781 },
782 [ C(OP_WRITE) ] = {
783 [ C(RESULT_ACCESS) ] = -1,
784 [ C(RESULT_MISS) ] = -1,
785 },
786 [ C(OP_PREFETCH) ] = {
787 [ C(RESULT_ACCESS) ] = -1,
788 [ C(RESULT_MISS) ] = -1,
789 },
790 },
791 [ C(BPU ) ] = {
792 [ C(OP_READ) ] = {
793 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
794 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
795 },
796 [ C(OP_WRITE) ] = {
797 [ C(RESULT_ACCESS) ] = -1,
798 [ C(RESULT_MISS) ] = -1,
799 },
800 [ C(OP_PREFETCH) ] = {
801 [ C(RESULT_ACCESS) ] = -1,
802 [ C(RESULT_MISS) ] = -1,
803 },
804 },
805 };
806
807 static __initconst const u64 atom_hw_cache_event_ids
808 [PERF_COUNT_HW_CACHE_MAX]
809 [PERF_COUNT_HW_CACHE_OP_MAX]
810 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
811 {
812 [ C(L1D) ] = {
813 [ C(OP_READ) ] = {
814 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
815 [ C(RESULT_MISS) ] = 0,
816 },
817 [ C(OP_WRITE) ] = {
818 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
819 [ C(RESULT_MISS) ] = 0,
820 },
821 [ C(OP_PREFETCH) ] = {
822 [ C(RESULT_ACCESS) ] = 0x0,
823 [ C(RESULT_MISS) ] = 0,
824 },
825 },
826 [ C(L1I ) ] = {
827 [ C(OP_READ) ] = {
828 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
829 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
830 },
831 [ C(OP_WRITE) ] = {
832 [ C(RESULT_ACCESS) ] = -1,
833 [ C(RESULT_MISS) ] = -1,
834 },
835 [ C(OP_PREFETCH) ] = {
836 [ C(RESULT_ACCESS) ] = 0,
837 [ C(RESULT_MISS) ] = 0,
838 },
839 },
840 [ C(LL ) ] = {
841 [ C(OP_READ) ] = {
842 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
843 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
844 },
845 [ C(OP_WRITE) ] = {
846 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
847 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
848 },
849 [ C(OP_PREFETCH) ] = {
850 [ C(RESULT_ACCESS) ] = 0,
851 [ C(RESULT_MISS) ] = 0,
852 },
853 },
854 [ C(DTLB) ] = {
855 [ C(OP_READ) ] = {
856 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
857 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
858 },
859 [ C(OP_WRITE) ] = {
860 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
861 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
862 },
863 [ C(OP_PREFETCH) ] = {
864 [ C(RESULT_ACCESS) ] = 0,
865 [ C(RESULT_MISS) ] = 0,
866 },
867 },
868 [ C(ITLB) ] = {
869 [ C(OP_READ) ] = {
870 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
871 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
872 },
873 [ C(OP_WRITE) ] = {
874 [ C(RESULT_ACCESS) ] = -1,
875 [ C(RESULT_MISS) ] = -1,
876 },
877 [ C(OP_PREFETCH) ] = {
878 [ C(RESULT_ACCESS) ] = -1,
879 [ C(RESULT_MISS) ] = -1,
880 },
881 },
882 [ C(BPU ) ] = {
883 [ C(OP_READ) ] = {
884 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
885 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
886 },
887 [ C(OP_WRITE) ] = {
888 [ C(RESULT_ACCESS) ] = -1,
889 [ C(RESULT_MISS) ] = -1,
890 },
891 [ C(OP_PREFETCH) ] = {
892 [ C(RESULT_ACCESS) ] = -1,
893 [ C(RESULT_MISS) ] = -1,
894 },
895 },
896 };
897
898 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
899 {
900 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
901 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
902 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x768005ffffull, RSP_1),
903 EVENT_EXTRA_END
904 };
905
906 #define SLM_DMND_READ SNB_DMND_DATA_RD
907 #define SLM_DMND_WRITE SNB_DMND_RFO
908 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
909
910 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
911 #define SLM_LLC_ACCESS SNB_RESP_ANY
912 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
913
914 static __initconst const u64 slm_hw_cache_extra_regs
915 [PERF_COUNT_HW_CACHE_MAX]
916 [PERF_COUNT_HW_CACHE_OP_MAX]
917 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
918 {
919 [ C(LL ) ] = {
920 [ C(OP_READ) ] = {
921 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
922 [ C(RESULT_MISS) ] = SLM_DMND_READ|SLM_LLC_MISS,
923 },
924 [ C(OP_WRITE) ] = {
925 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
926 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
927 },
928 [ C(OP_PREFETCH) ] = {
929 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
930 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
931 },
932 },
933 };
934
935 static __initconst const u64 slm_hw_cache_event_ids
936 [PERF_COUNT_HW_CACHE_MAX]
937 [PERF_COUNT_HW_CACHE_OP_MAX]
938 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
939 {
940 [ C(L1D) ] = {
941 [ C(OP_READ) ] = {
942 [ C(RESULT_ACCESS) ] = 0,
943 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
944 },
945 [ C(OP_WRITE) ] = {
946 [ C(RESULT_ACCESS) ] = 0,
947 [ C(RESULT_MISS) ] = 0,
948 },
949 [ C(OP_PREFETCH) ] = {
950 [ C(RESULT_ACCESS) ] = 0,
951 [ C(RESULT_MISS) ] = 0,
952 },
953 },
954 [ C(L1I ) ] = {
955 [ C(OP_READ) ] = {
956 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
957 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
958 },
959 [ C(OP_WRITE) ] = {
960 [ C(RESULT_ACCESS) ] = -1,
961 [ C(RESULT_MISS) ] = -1,
962 },
963 [ C(OP_PREFETCH) ] = {
964 [ C(RESULT_ACCESS) ] = 0,
965 [ C(RESULT_MISS) ] = 0,
966 },
967 },
968 [ C(LL ) ] = {
969 [ C(OP_READ) ] = {
970 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
971 [ C(RESULT_ACCESS) ] = 0x01b7,
972 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
973 [ C(RESULT_MISS) ] = 0x01b7,
974 },
975 [ C(OP_WRITE) ] = {
976 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
977 [ C(RESULT_ACCESS) ] = 0x01b7,
978 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
979 [ C(RESULT_MISS) ] = 0x01b7,
980 },
981 [ C(OP_PREFETCH) ] = {
982 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
983 [ C(RESULT_ACCESS) ] = 0x01b7,
984 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
985 [ C(RESULT_MISS) ] = 0x01b7,
986 },
987 },
988 [ C(DTLB) ] = {
989 [ C(OP_READ) ] = {
990 [ C(RESULT_ACCESS) ] = 0,
991 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
992 },
993 [ C(OP_WRITE) ] = {
994 [ C(RESULT_ACCESS) ] = 0,
995 [ C(RESULT_MISS) ] = 0,
996 },
997 [ C(OP_PREFETCH) ] = {
998 [ C(RESULT_ACCESS) ] = 0,
999 [ C(RESULT_MISS) ] = 0,
1000 },
1001 },
1002 [ C(ITLB) ] = {
1003 [ C(OP_READ) ] = {
1004 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1005 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1006 },
1007 [ C(OP_WRITE) ] = {
1008 [ C(RESULT_ACCESS) ] = -1,
1009 [ C(RESULT_MISS) ] = -1,
1010 },
1011 [ C(OP_PREFETCH) ] = {
1012 [ C(RESULT_ACCESS) ] = -1,
1013 [ C(RESULT_MISS) ] = -1,
1014 },
1015 },
1016 [ C(BPU ) ] = {
1017 [ C(OP_READ) ] = {
1018 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1019 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1020 },
1021 [ C(OP_WRITE) ] = {
1022 [ C(RESULT_ACCESS) ] = -1,
1023 [ C(RESULT_MISS) ] = -1,
1024 },
1025 [ C(OP_PREFETCH) ] = {
1026 [ C(RESULT_ACCESS) ] = -1,
1027 [ C(RESULT_MISS) ] = -1,
1028 },
1029 },
1030 };
1031
1032 static void intel_pmu_disable_all(void)
1033 {
1034 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1035
1036 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1037
1038 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1039 intel_pmu_disable_bts();
1040
1041 intel_pmu_pebs_disable_all();
1042 intel_pmu_lbr_disable_all();
1043 }
1044
1045 static void intel_pmu_enable_all(int added)
1046 {
1047 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1048
1049 intel_pmu_pebs_enable_all();
1050 intel_pmu_lbr_enable_all();
1051 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1052 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1053
1054 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1055 struct perf_event *event =
1056 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1057
1058 if (WARN_ON_ONCE(!event))
1059 return;
1060
1061 intel_pmu_enable_bts(event->hw.config);
1062 }
1063 }
1064
1065 /*
1066 * Workaround for:
1067 * Intel Errata AAK100 (model 26)
1068 * Intel Errata AAP53 (model 30)
1069 * Intel Errata BD53 (model 44)
1070 *
1071 * The official story:
1072 * These chips need to be 'reset' when adding counters by programming the
1073 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1074 * in sequence on the same PMC or on different PMCs.
1075 *
1076 * In practise it appears some of these events do in fact count, and
1077 * we need to programm all 4 events.
1078 */
1079 static void intel_pmu_nhm_workaround(void)
1080 {
1081 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1082 static const unsigned long nhm_magic[4] = {
1083 0x4300B5,
1084 0x4300D2,
1085 0x4300B1,
1086 0x4300B1
1087 };
1088 struct perf_event *event;
1089 int i;
1090
1091 /*
1092 * The Errata requires below steps:
1093 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1094 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1095 * the corresponding PMCx;
1096 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1097 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1098 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1099 */
1100
1101 /*
1102 * The real steps we choose are a little different from above.
1103 * A) To reduce MSR operations, we don't run step 1) as they
1104 * are already cleared before this function is called;
1105 * B) Call x86_perf_event_update to save PMCx before configuring
1106 * PERFEVTSELx with magic number;
1107 * C) With step 5), we do clear only when the PERFEVTSELx is
1108 * not used currently.
1109 * D) Call x86_perf_event_set_period to restore PMCx;
1110 */
1111
1112 /* We always operate 4 pairs of PERF Counters */
1113 for (i = 0; i < 4; i++) {
1114 event = cpuc->events[i];
1115 if (event)
1116 x86_perf_event_update(event);
1117 }
1118
1119 for (i = 0; i < 4; i++) {
1120 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1121 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1122 }
1123
1124 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1125 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1126
1127 for (i = 0; i < 4; i++) {
1128 event = cpuc->events[i];
1129
1130 if (event) {
1131 x86_perf_event_set_period(event);
1132 __x86_pmu_enable_event(&event->hw,
1133 ARCH_PERFMON_EVENTSEL_ENABLE);
1134 } else
1135 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1136 }
1137 }
1138
1139 static void intel_pmu_nhm_enable_all(int added)
1140 {
1141 if (added)
1142 intel_pmu_nhm_workaround();
1143 intel_pmu_enable_all(added);
1144 }
1145
1146 static inline u64 intel_pmu_get_status(void)
1147 {
1148 u64 status;
1149
1150 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1151
1152 return status;
1153 }
1154
1155 static inline void intel_pmu_ack_status(u64 ack)
1156 {
1157 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1158 }
1159
1160 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
1161 {
1162 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1163 u64 ctrl_val, mask;
1164
1165 mask = 0xfULL << (idx * 4);
1166
1167 rdmsrl(hwc->config_base, ctrl_val);
1168 ctrl_val &= ~mask;
1169 wrmsrl(hwc->config_base, ctrl_val);
1170 }
1171
1172 static inline bool event_is_checkpointed(struct perf_event *event)
1173 {
1174 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1175 }
1176
1177 static void intel_pmu_disable_event(struct perf_event *event)
1178 {
1179 struct hw_perf_event *hwc = &event->hw;
1180 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1181
1182 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1183 intel_pmu_disable_bts();
1184 intel_pmu_drain_bts_buffer();
1185 return;
1186 }
1187
1188 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1189 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1190 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
1191
1192 /*
1193 * must disable before any actual event
1194 * because any event may be combined with LBR
1195 */
1196 if (needs_branch_stack(event))
1197 intel_pmu_lbr_disable(event);
1198
1199 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1200 intel_pmu_disable_fixed(hwc);
1201 return;
1202 }
1203
1204 x86_pmu_disable_event(event);
1205
1206 if (unlikely(event->attr.precise_ip))
1207 intel_pmu_pebs_disable(event);
1208 }
1209
1210 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
1211 {
1212 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1213 u64 ctrl_val, bits, mask;
1214
1215 /*
1216 * Enable IRQ generation (0x8),
1217 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1218 * if requested:
1219 */
1220 bits = 0x8ULL;
1221 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1222 bits |= 0x2;
1223 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1224 bits |= 0x1;
1225
1226 /*
1227 * ANY bit is supported in v3 and up
1228 */
1229 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1230 bits |= 0x4;
1231
1232 bits <<= (idx * 4);
1233 mask = 0xfULL << (idx * 4);
1234
1235 rdmsrl(hwc->config_base, ctrl_val);
1236 ctrl_val &= ~mask;
1237 ctrl_val |= bits;
1238 wrmsrl(hwc->config_base, ctrl_val);
1239 }
1240
1241 static void intel_pmu_enable_event(struct perf_event *event)
1242 {
1243 struct hw_perf_event *hwc = &event->hw;
1244 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1245
1246 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1247 if (!__this_cpu_read(cpu_hw_events.enabled))
1248 return;
1249
1250 intel_pmu_enable_bts(hwc->config);
1251 return;
1252 }
1253 /*
1254 * must enabled before any actual event
1255 * because any event may be combined with LBR
1256 */
1257 if (needs_branch_stack(event))
1258 intel_pmu_lbr_enable(event);
1259
1260 if (event->attr.exclude_host)
1261 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1262 if (event->attr.exclude_guest)
1263 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1264
1265 if (unlikely(event_is_checkpointed(event)))
1266 cpuc->intel_cp_status |= (1ull << hwc->idx);
1267
1268 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1269 intel_pmu_enable_fixed(hwc);
1270 return;
1271 }
1272
1273 if (unlikely(event->attr.precise_ip))
1274 intel_pmu_pebs_enable(event);
1275
1276 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1277 }
1278
1279 /*
1280 * Save and restart an expired event. Called by NMI contexts,
1281 * so it has to be careful about preempting normal event ops:
1282 */
1283 int intel_pmu_save_and_restart(struct perf_event *event)
1284 {
1285 x86_perf_event_update(event);
1286 /*
1287 * For a checkpointed counter always reset back to 0. This
1288 * avoids a situation where the counter overflows, aborts the
1289 * transaction and is then set back to shortly before the
1290 * overflow, and overflows and aborts again.
1291 */
1292 if (unlikely(event_is_checkpointed(event))) {
1293 /* No race with NMIs because the counter should not be armed */
1294 wrmsrl(event->hw.event_base, 0);
1295 local64_set(&event->hw.prev_count, 0);
1296 }
1297 return x86_perf_event_set_period(event);
1298 }
1299
1300 static void intel_pmu_reset(void)
1301 {
1302 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1303 unsigned long flags;
1304 int idx;
1305
1306 if (!x86_pmu.num_counters)
1307 return;
1308
1309 local_irq_save(flags);
1310
1311 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1312
1313 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1314 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1315 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
1316 }
1317 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1318 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1319
1320 if (ds)
1321 ds->bts_index = ds->bts_buffer_base;
1322
1323 local_irq_restore(flags);
1324 }
1325
1326 /*
1327 * This handler is triggered by the local APIC, so the APIC IRQ handling
1328 * rules apply:
1329 */
1330 static int intel_pmu_handle_irq(struct pt_regs *regs)
1331 {
1332 struct perf_sample_data data;
1333 struct cpu_hw_events *cpuc;
1334 int bit, loops;
1335 u64 status;
1336 int handled;
1337
1338 cpuc = this_cpu_ptr(&cpu_hw_events);
1339
1340 /*
1341 * No known reason to not always do late ACK,
1342 * but just in case do it opt-in.
1343 */
1344 if (!x86_pmu.late_ack)
1345 apic_write(APIC_LVTPC, APIC_DM_NMI);
1346 intel_pmu_disable_all();
1347 handled = intel_pmu_drain_bts_buffer();
1348 status = intel_pmu_get_status();
1349 if (!status)
1350 goto done;
1351
1352 loops = 0;
1353 again:
1354 intel_pmu_ack_status(status);
1355 if (++loops > 100) {
1356 static bool warned = false;
1357 if (!warned) {
1358 WARN(1, "perfevents: irq loop stuck!\n");
1359 perf_event_print_debug();
1360 warned = true;
1361 }
1362 intel_pmu_reset();
1363 goto done;
1364 }
1365
1366 inc_irq_stat(apic_perf_irqs);
1367
1368 intel_pmu_lbr_read();
1369
1370 /*
1371 * CondChgd bit 63 doesn't mean any overflow status. Ignore
1372 * and clear the bit.
1373 */
1374 if (__test_and_clear_bit(63, (unsigned long *)&status)) {
1375 if (!status)
1376 goto done;
1377 }
1378
1379 /*
1380 * PEBS overflow sets bit 62 in the global status register
1381 */
1382 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1383 handled++;
1384 x86_pmu.drain_pebs(regs);
1385 }
1386
1387 /*
1388 * Checkpointed counters can lead to 'spurious' PMIs because the
1389 * rollback caused by the PMI will have cleared the overflow status
1390 * bit. Therefore always force probe these counters.
1391 */
1392 status |= cpuc->intel_cp_status;
1393
1394 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1395 struct perf_event *event = cpuc->events[bit];
1396
1397 handled++;
1398
1399 if (!test_bit(bit, cpuc->active_mask))
1400 continue;
1401
1402 if (!intel_pmu_save_and_restart(event))
1403 continue;
1404
1405 perf_sample_data_init(&data, 0, event->hw.last_period);
1406
1407 if (has_branch_stack(event))
1408 data.br_stack = &cpuc->lbr_stack;
1409
1410 if (perf_event_overflow(event, &data, regs))
1411 x86_pmu_stop(event, 0);
1412 }
1413
1414 /*
1415 * Repeat if there is more work to be done:
1416 */
1417 status = intel_pmu_get_status();
1418 if (status)
1419 goto again;
1420
1421 done:
1422 intel_pmu_enable_all(0);
1423 /*
1424 * Only unmask the NMI after the overflow counters
1425 * have been reset. This avoids spurious NMIs on
1426 * Haswell CPUs.
1427 */
1428 if (x86_pmu.late_ack)
1429 apic_write(APIC_LVTPC, APIC_DM_NMI);
1430 return handled;
1431 }
1432
1433 static struct event_constraint *
1434 intel_bts_constraints(struct perf_event *event)
1435 {
1436 struct hw_perf_event *hwc = &event->hw;
1437 unsigned int hw_event, bts_event;
1438
1439 if (event->attr.freq)
1440 return NULL;
1441
1442 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1443 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1444
1445 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1446 return &bts_constraint;
1447
1448 return NULL;
1449 }
1450
1451 static int intel_alt_er(int idx)
1452 {
1453 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1454 return idx;
1455
1456 if (idx == EXTRA_REG_RSP_0)
1457 return EXTRA_REG_RSP_1;
1458
1459 if (idx == EXTRA_REG_RSP_1)
1460 return EXTRA_REG_RSP_0;
1461
1462 return idx;
1463 }
1464
1465 static void intel_fixup_er(struct perf_event *event, int idx)
1466 {
1467 event->hw.extra_reg.idx = idx;
1468
1469 if (idx == EXTRA_REG_RSP_0) {
1470 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1471 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
1472 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1473 } else if (idx == EXTRA_REG_RSP_1) {
1474 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1475 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
1476 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1477 }
1478 }
1479
1480 /*
1481 * manage allocation of shared extra msr for certain events
1482 *
1483 * sharing can be:
1484 * per-cpu: to be shared between the various events on a single PMU
1485 * per-core: per-cpu + shared by HT threads
1486 */
1487 static struct event_constraint *
1488 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1489 struct perf_event *event,
1490 struct hw_perf_event_extra *reg)
1491 {
1492 struct event_constraint *c = &emptyconstraint;
1493 struct er_account *era;
1494 unsigned long flags;
1495 int idx = reg->idx;
1496
1497 /*
1498 * reg->alloc can be set due to existing state, so for fake cpuc we
1499 * need to ignore this, otherwise we might fail to allocate proper fake
1500 * state for this extra reg constraint. Also see the comment below.
1501 */
1502 if (reg->alloc && !cpuc->is_fake)
1503 return NULL; /* call x86_get_event_constraint() */
1504
1505 again:
1506 era = &cpuc->shared_regs->regs[idx];
1507 /*
1508 * we use spin_lock_irqsave() to avoid lockdep issues when
1509 * passing a fake cpuc
1510 */
1511 raw_spin_lock_irqsave(&era->lock, flags);
1512
1513 if (!atomic_read(&era->ref) || era->config == reg->config) {
1514
1515 /*
1516 * If its a fake cpuc -- as per validate_{group,event}() we
1517 * shouldn't touch event state and we can avoid doing so
1518 * since both will only call get_event_constraints() once
1519 * on each event, this avoids the need for reg->alloc.
1520 *
1521 * Not doing the ER fixup will only result in era->reg being
1522 * wrong, but since we won't actually try and program hardware
1523 * this isn't a problem either.
1524 */
1525 if (!cpuc->is_fake) {
1526 if (idx != reg->idx)
1527 intel_fixup_er(event, idx);
1528
1529 /*
1530 * x86_schedule_events() can call get_event_constraints()
1531 * multiple times on events in the case of incremental
1532 * scheduling(). reg->alloc ensures we only do the ER
1533 * allocation once.
1534 */
1535 reg->alloc = 1;
1536 }
1537
1538 /* lock in msr value */
1539 era->config = reg->config;
1540 era->reg = reg->reg;
1541
1542 /* one more user */
1543 atomic_inc(&era->ref);
1544
1545 /*
1546 * need to call x86_get_event_constraint()
1547 * to check if associated event has constraints
1548 */
1549 c = NULL;
1550 } else {
1551 idx = intel_alt_er(idx);
1552 if (idx != reg->idx) {
1553 raw_spin_unlock_irqrestore(&era->lock, flags);
1554 goto again;
1555 }
1556 }
1557 raw_spin_unlock_irqrestore(&era->lock, flags);
1558
1559 return c;
1560 }
1561
1562 static void
1563 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1564 struct hw_perf_event_extra *reg)
1565 {
1566 struct er_account *era;
1567
1568 /*
1569 * Only put constraint if extra reg was actually allocated. Also takes
1570 * care of event which do not use an extra shared reg.
1571 *
1572 * Also, if this is a fake cpuc we shouldn't touch any event state
1573 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1574 * either since it'll be thrown out.
1575 */
1576 if (!reg->alloc || cpuc->is_fake)
1577 return;
1578
1579 era = &cpuc->shared_regs->regs[reg->idx];
1580
1581 /* one fewer user */
1582 atomic_dec(&era->ref);
1583
1584 /* allocate again next time */
1585 reg->alloc = 0;
1586 }
1587
1588 static struct event_constraint *
1589 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1590 struct perf_event *event)
1591 {
1592 struct event_constraint *c = NULL, *d;
1593 struct hw_perf_event_extra *xreg, *breg;
1594
1595 xreg = &event->hw.extra_reg;
1596 if (xreg->idx != EXTRA_REG_NONE) {
1597 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1598 if (c == &emptyconstraint)
1599 return c;
1600 }
1601 breg = &event->hw.branch_reg;
1602 if (breg->idx != EXTRA_REG_NONE) {
1603 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1604 if (d == &emptyconstraint) {
1605 __intel_shared_reg_put_constraints(cpuc, xreg);
1606 c = d;
1607 }
1608 }
1609 return c;
1610 }
1611
1612 struct event_constraint *
1613 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1614 {
1615 struct event_constraint *c;
1616
1617 if (x86_pmu.event_constraints) {
1618 for_each_event_constraint(c, x86_pmu.event_constraints) {
1619 if ((event->hw.config & c->cmask) == c->code) {
1620 event->hw.flags |= c->flags;
1621 return c;
1622 }
1623 }
1624 }
1625
1626 return &unconstrained;
1627 }
1628
1629 static struct event_constraint *
1630 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1631 {
1632 struct event_constraint *c;
1633
1634 c = intel_bts_constraints(event);
1635 if (c)
1636 return c;
1637
1638 c = intel_pebs_constraints(event);
1639 if (c)
1640 return c;
1641
1642 c = intel_shared_regs_constraints(cpuc, event);
1643 if (c)
1644 return c;
1645
1646 return x86_get_event_constraints(cpuc, event);
1647 }
1648
1649 static void
1650 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1651 struct perf_event *event)
1652 {
1653 struct hw_perf_event_extra *reg;
1654
1655 reg = &event->hw.extra_reg;
1656 if (reg->idx != EXTRA_REG_NONE)
1657 __intel_shared_reg_put_constraints(cpuc, reg);
1658
1659 reg = &event->hw.branch_reg;
1660 if (reg->idx != EXTRA_REG_NONE)
1661 __intel_shared_reg_put_constraints(cpuc, reg);
1662 }
1663
1664 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1665 struct perf_event *event)
1666 {
1667 intel_put_shared_regs_event_constraints(cpuc, event);
1668 }
1669
1670 static void intel_pebs_aliases_core2(struct perf_event *event)
1671 {
1672 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1673 /*
1674 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1675 * (0x003c) so that we can use it with PEBS.
1676 *
1677 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1678 * PEBS capable. However we can use INST_RETIRED.ANY_P
1679 * (0x00c0), which is a PEBS capable event, to get the same
1680 * count.
1681 *
1682 * INST_RETIRED.ANY_P counts the number of cycles that retires
1683 * CNTMASK instructions. By setting CNTMASK to a value (16)
1684 * larger than the maximum number of instructions that can be
1685 * retired per cycle (4) and then inverting the condition, we
1686 * count all cycles that retire 16 or less instructions, which
1687 * is every cycle.
1688 *
1689 * Thereby we gain a PEBS capable cycle counter.
1690 */
1691 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1692
1693 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1694 event->hw.config = alt_config;
1695 }
1696 }
1697
1698 static void intel_pebs_aliases_snb(struct perf_event *event)
1699 {
1700 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1701 /*
1702 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1703 * (0x003c) so that we can use it with PEBS.
1704 *
1705 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1706 * PEBS capable. However we can use UOPS_RETIRED.ALL
1707 * (0x01c2), which is a PEBS capable event, to get the same
1708 * count.
1709 *
1710 * UOPS_RETIRED.ALL counts the number of cycles that retires
1711 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1712 * larger than the maximum number of micro-ops that can be
1713 * retired per cycle (4) and then inverting the condition, we
1714 * count all cycles that retire 16 or less micro-ops, which
1715 * is every cycle.
1716 *
1717 * Thereby we gain a PEBS capable cycle counter.
1718 */
1719 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
1720
1721 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1722 event->hw.config = alt_config;
1723 }
1724 }
1725
1726 static int intel_pmu_hw_config(struct perf_event *event)
1727 {
1728 int ret = x86_pmu_hw_config(event);
1729
1730 if (ret)
1731 return ret;
1732
1733 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1734 x86_pmu.pebs_aliases(event);
1735
1736 if (needs_branch_stack(event)) {
1737 ret = intel_pmu_setup_lbr_filter(event);
1738 if (ret)
1739 return ret;
1740 }
1741
1742 if (event->attr.type != PERF_TYPE_RAW)
1743 return 0;
1744
1745 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1746 return 0;
1747
1748 if (x86_pmu.version < 3)
1749 return -EINVAL;
1750
1751 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1752 return -EACCES;
1753
1754 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1755
1756 return 0;
1757 }
1758
1759 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1760 {
1761 if (x86_pmu.guest_get_msrs)
1762 return x86_pmu.guest_get_msrs(nr);
1763 *nr = 0;
1764 return NULL;
1765 }
1766 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1767
1768 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1769 {
1770 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1771 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1772
1773 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1774 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1775 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1776 /*
1777 * If PMU counter has PEBS enabled it is not enough to disable counter
1778 * on a guest entry since PEBS memory write can overshoot guest entry
1779 * and corrupt guest memory. Disabling PEBS solves the problem.
1780 */
1781 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1782 arr[1].host = cpuc->pebs_enabled;
1783 arr[1].guest = 0;
1784
1785 *nr = 2;
1786 return arr;
1787 }
1788
1789 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1790 {
1791 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1792 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1793 int idx;
1794
1795 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1796 struct perf_event *event = cpuc->events[idx];
1797
1798 arr[idx].msr = x86_pmu_config_addr(idx);
1799 arr[idx].host = arr[idx].guest = 0;
1800
1801 if (!test_bit(idx, cpuc->active_mask))
1802 continue;
1803
1804 arr[idx].host = arr[idx].guest =
1805 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1806
1807 if (event->attr.exclude_host)
1808 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1809 else if (event->attr.exclude_guest)
1810 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1811 }
1812
1813 *nr = x86_pmu.num_counters;
1814 return arr;
1815 }
1816
1817 static void core_pmu_enable_event(struct perf_event *event)
1818 {
1819 if (!event->attr.exclude_host)
1820 x86_pmu_enable_event(event);
1821 }
1822
1823 static void core_pmu_enable_all(int added)
1824 {
1825 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1826 int idx;
1827
1828 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1829 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1830
1831 if (!test_bit(idx, cpuc->active_mask) ||
1832 cpuc->events[idx]->attr.exclude_host)
1833 continue;
1834
1835 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1836 }
1837 }
1838
1839 static int hsw_hw_config(struct perf_event *event)
1840 {
1841 int ret = intel_pmu_hw_config(event);
1842
1843 if (ret)
1844 return ret;
1845 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1846 return 0;
1847 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1848
1849 /*
1850 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1851 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1852 * this combination.
1853 */
1854 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1855 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1856 event->attr.precise_ip > 0))
1857 return -EOPNOTSUPP;
1858
1859 if (event_is_checkpointed(event)) {
1860 /*
1861 * Sampling of checkpointed events can cause situations where
1862 * the CPU constantly aborts because of a overflow, which is
1863 * then checkpointed back and ignored. Forbid checkpointing
1864 * for sampling.
1865 *
1866 * But still allow a long sampling period, so that perf stat
1867 * from KVM works.
1868 */
1869 if (event->attr.sample_period > 0 &&
1870 event->attr.sample_period < 0x7fffffff)
1871 return -EOPNOTSUPP;
1872 }
1873 return 0;
1874 }
1875
1876 static struct event_constraint counter2_constraint =
1877 EVENT_CONSTRAINT(0, 0x4, 0);
1878
1879 static struct event_constraint *
1880 hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1881 {
1882 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1883
1884 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1885 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1886 if (c->idxmsk64 & (1U << 2))
1887 return &counter2_constraint;
1888 return &emptyconstraint;
1889 }
1890
1891 return c;
1892 }
1893
1894 PMU_FORMAT_ATTR(event, "config:0-7" );
1895 PMU_FORMAT_ATTR(umask, "config:8-15" );
1896 PMU_FORMAT_ATTR(edge, "config:18" );
1897 PMU_FORMAT_ATTR(pc, "config:19" );
1898 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1899 PMU_FORMAT_ATTR(inv, "config:23" );
1900 PMU_FORMAT_ATTR(cmask, "config:24-31" );
1901 PMU_FORMAT_ATTR(in_tx, "config:32");
1902 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
1903
1904 static struct attribute *intel_arch_formats_attr[] = {
1905 &format_attr_event.attr,
1906 &format_attr_umask.attr,
1907 &format_attr_edge.attr,
1908 &format_attr_pc.attr,
1909 &format_attr_inv.attr,
1910 &format_attr_cmask.attr,
1911 NULL,
1912 };
1913
1914 ssize_t intel_event_sysfs_show(char *page, u64 config)
1915 {
1916 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1917
1918 return x86_event_sysfs_show(page, config, event);
1919 }
1920
1921 static __initconst const struct x86_pmu core_pmu = {
1922 .name = "core",
1923 .handle_irq = x86_pmu_handle_irq,
1924 .disable_all = x86_pmu_disable_all,
1925 .enable_all = core_pmu_enable_all,
1926 .enable = core_pmu_enable_event,
1927 .disable = x86_pmu_disable_event,
1928 .hw_config = x86_pmu_hw_config,
1929 .schedule_events = x86_schedule_events,
1930 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1931 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1932 .event_map = intel_pmu_event_map,
1933 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1934 .apic = 1,
1935 /*
1936 * Intel PMCs cannot be accessed sanely above 32 bit width,
1937 * so we install an artificial 1<<31 period regardless of
1938 * the generic event period:
1939 */
1940 .max_period = (1ULL << 31) - 1,
1941 .get_event_constraints = intel_get_event_constraints,
1942 .put_event_constraints = intel_put_event_constraints,
1943 .event_constraints = intel_core_event_constraints,
1944 .guest_get_msrs = core_guest_get_msrs,
1945 .format_attrs = intel_arch_formats_attr,
1946 .events_sysfs_show = intel_event_sysfs_show,
1947 };
1948
1949 struct intel_shared_regs *allocate_shared_regs(int cpu)
1950 {
1951 struct intel_shared_regs *regs;
1952 int i;
1953
1954 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1955 GFP_KERNEL, cpu_to_node(cpu));
1956 if (regs) {
1957 /*
1958 * initialize the locks to keep lockdep happy
1959 */
1960 for (i = 0; i < EXTRA_REG_MAX; i++)
1961 raw_spin_lock_init(&regs->regs[i].lock);
1962
1963 regs->core_id = -1;
1964 }
1965 return regs;
1966 }
1967
1968 static int intel_pmu_cpu_prepare(int cpu)
1969 {
1970 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1971
1972 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
1973 return NOTIFY_OK;
1974
1975 cpuc->shared_regs = allocate_shared_regs(cpu);
1976 if (!cpuc->shared_regs)
1977 return NOTIFY_BAD;
1978
1979 return NOTIFY_OK;
1980 }
1981
1982 static void intel_pmu_cpu_starting(int cpu)
1983 {
1984 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1985 int core_id = topology_core_id(cpu);
1986 int i;
1987
1988 init_debug_store_on_cpu(cpu);
1989 /*
1990 * Deal with CPUs that don't clear their LBRs on power-up.
1991 */
1992 intel_pmu_lbr_reset();
1993
1994 cpuc->lbr_sel = NULL;
1995
1996 if (!cpuc->shared_regs)
1997 return;
1998
1999 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
2000 for_each_cpu(i, topology_thread_cpumask(cpu)) {
2001 struct intel_shared_regs *pc;
2002
2003 pc = per_cpu(cpu_hw_events, i).shared_regs;
2004 if (pc && pc->core_id == core_id) {
2005 cpuc->kfree_on_online = cpuc->shared_regs;
2006 cpuc->shared_regs = pc;
2007 break;
2008 }
2009 }
2010 cpuc->shared_regs->core_id = core_id;
2011 cpuc->shared_regs->refcnt++;
2012 }
2013
2014 if (x86_pmu.lbr_sel_map)
2015 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
2016 }
2017
2018 static void intel_pmu_cpu_dying(int cpu)
2019 {
2020 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2021 struct intel_shared_regs *pc;
2022
2023 pc = cpuc->shared_regs;
2024 if (pc) {
2025 if (pc->core_id == -1 || --pc->refcnt == 0)
2026 kfree(pc);
2027 cpuc->shared_regs = NULL;
2028 }
2029
2030 fini_debug_store_on_cpu(cpu);
2031 }
2032
2033 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2034
2035 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2036
2037 static struct attribute *intel_arch3_formats_attr[] = {
2038 &format_attr_event.attr,
2039 &format_attr_umask.attr,
2040 &format_attr_edge.attr,
2041 &format_attr_pc.attr,
2042 &format_attr_any.attr,
2043 &format_attr_inv.attr,
2044 &format_attr_cmask.attr,
2045 &format_attr_in_tx.attr,
2046 &format_attr_in_tx_cp.attr,
2047
2048 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
2049 &format_attr_ldlat.attr, /* PEBS load latency */
2050 NULL,
2051 };
2052
2053 static __initconst const struct x86_pmu intel_pmu = {
2054 .name = "Intel",
2055 .handle_irq = intel_pmu_handle_irq,
2056 .disable_all = intel_pmu_disable_all,
2057 .enable_all = intel_pmu_enable_all,
2058 .enable = intel_pmu_enable_event,
2059 .disable = intel_pmu_disable_event,
2060 .hw_config = intel_pmu_hw_config,
2061 .schedule_events = x86_schedule_events,
2062 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2063 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2064 .event_map = intel_pmu_event_map,
2065 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2066 .apic = 1,
2067 /*
2068 * Intel PMCs cannot be accessed sanely above 32 bit width,
2069 * so we install an artificial 1<<31 period regardless of
2070 * the generic event period:
2071 */
2072 .max_period = (1ULL << 31) - 1,
2073 .get_event_constraints = intel_get_event_constraints,
2074 .put_event_constraints = intel_put_event_constraints,
2075 .pebs_aliases = intel_pebs_aliases_core2,
2076
2077 .format_attrs = intel_arch3_formats_attr,
2078 .events_sysfs_show = intel_event_sysfs_show,
2079
2080 .cpu_prepare = intel_pmu_cpu_prepare,
2081 .cpu_starting = intel_pmu_cpu_starting,
2082 .cpu_dying = intel_pmu_cpu_dying,
2083 .guest_get_msrs = intel_guest_get_msrs,
2084 .sched_task = intel_pmu_lbr_sched_task,
2085 };
2086
2087 static __init void intel_clovertown_quirk(void)
2088 {
2089 /*
2090 * PEBS is unreliable due to:
2091 *
2092 * AJ67 - PEBS may experience CPL leaks
2093 * AJ68 - PEBS PMI may be delayed by one event
2094 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2095 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2096 *
2097 * AJ67 could be worked around by restricting the OS/USR flags.
2098 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2099 *
2100 * AJ106 could possibly be worked around by not allowing LBR
2101 * usage from PEBS, including the fixup.
2102 * AJ68 could possibly be worked around by always programming
2103 * a pebs_event_reset[0] value and coping with the lost events.
2104 *
2105 * But taken together it might just make sense to not enable PEBS on
2106 * these chips.
2107 */
2108 pr_warn("PEBS disabled due to CPU errata\n");
2109 x86_pmu.pebs = 0;
2110 x86_pmu.pebs_constraints = NULL;
2111 }
2112
2113 static int intel_snb_pebs_broken(int cpu)
2114 {
2115 u32 rev = UINT_MAX; /* default to broken for unknown models */
2116
2117 switch (cpu_data(cpu).x86_model) {
2118 case 42: /* SNB */
2119 rev = 0x28;
2120 break;
2121
2122 case 45: /* SNB-EP */
2123 switch (cpu_data(cpu).x86_mask) {
2124 case 6: rev = 0x618; break;
2125 case 7: rev = 0x70c; break;
2126 }
2127 }
2128
2129 return (cpu_data(cpu).microcode < rev);
2130 }
2131
2132 static void intel_snb_check_microcode(void)
2133 {
2134 int pebs_broken = 0;
2135 int cpu;
2136
2137 get_online_cpus();
2138 for_each_online_cpu(cpu) {
2139 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
2140 break;
2141 }
2142 put_online_cpus();
2143
2144 if (pebs_broken == x86_pmu.pebs_broken)
2145 return;
2146
2147 /*
2148 * Serialized by the microcode lock..
2149 */
2150 if (x86_pmu.pebs_broken) {
2151 pr_info("PEBS enabled due to microcode update\n");
2152 x86_pmu.pebs_broken = 0;
2153 } else {
2154 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
2155 x86_pmu.pebs_broken = 1;
2156 }
2157 }
2158
2159 /*
2160 * Under certain circumstances, access certain MSR may cause #GP.
2161 * The function tests if the input MSR can be safely accessed.
2162 */
2163 static bool check_msr(unsigned long msr, u64 mask)
2164 {
2165 u64 val_old, val_new, val_tmp;
2166
2167 /*
2168 * Read the current value, change it and read it back to see if it
2169 * matches, this is needed to detect certain hardware emulators
2170 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
2171 */
2172 if (rdmsrl_safe(msr, &val_old))
2173 return false;
2174
2175 /*
2176 * Only change the bits which can be updated by wrmsrl.
2177 */
2178 val_tmp = val_old ^ mask;
2179 if (wrmsrl_safe(msr, val_tmp) ||
2180 rdmsrl_safe(msr, &val_new))
2181 return false;
2182
2183 if (val_new != val_tmp)
2184 return false;
2185
2186 /* Here it's sure that the MSR can be safely accessed.
2187 * Restore the old value and return.
2188 */
2189 wrmsrl(msr, val_old);
2190
2191 return true;
2192 }
2193
2194 static __init void intel_sandybridge_quirk(void)
2195 {
2196 x86_pmu.check_microcode = intel_snb_check_microcode;
2197 intel_snb_check_microcode();
2198 }
2199
2200 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2201 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2202 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2203 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2204 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2205 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2206 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2207 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
2208 };
2209
2210 static __init void intel_arch_events_quirk(void)
2211 {
2212 int bit;
2213
2214 /* disable event that reported as not presend by cpuid */
2215 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2216 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
2217 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2218 intel_arch_events_map[bit].name);
2219 }
2220 }
2221
2222 static __init void intel_nehalem_quirk(void)
2223 {
2224 union cpuid10_ebx ebx;
2225
2226 ebx.full = x86_pmu.events_maskl;
2227 if (ebx.split.no_branch_misses_retired) {
2228 /*
2229 * Erratum AAJ80 detected, we work it around by using
2230 * the BR_MISP_EXEC.ANY event. This will over-count
2231 * branch-misses, but it's still much better than the
2232 * architectural event which is often completely bogus:
2233 */
2234 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2235 ebx.split.no_branch_misses_retired = 0;
2236 x86_pmu.events_maskl = ebx.full;
2237 pr_info("CPU erratum AAJ80 worked around\n");
2238 }
2239 }
2240
2241 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2242 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
2243
2244 /* Haswell special events */
2245 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
2246 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
2247 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
2248 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
2249 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
2250 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
2251 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
2252 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
2253 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
2254 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
2255 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
2256 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
2257
2258 static struct attribute *hsw_events_attrs[] = {
2259 EVENT_PTR(tx_start),
2260 EVENT_PTR(tx_commit),
2261 EVENT_PTR(tx_abort),
2262 EVENT_PTR(tx_capacity),
2263 EVENT_PTR(tx_conflict),
2264 EVENT_PTR(el_start),
2265 EVENT_PTR(el_commit),
2266 EVENT_PTR(el_abort),
2267 EVENT_PTR(el_capacity),
2268 EVENT_PTR(el_conflict),
2269 EVENT_PTR(cycles_t),
2270 EVENT_PTR(cycles_ct),
2271 EVENT_PTR(mem_ld_hsw),
2272 EVENT_PTR(mem_st_hsw),
2273 NULL
2274 };
2275
2276 __init int intel_pmu_init(void)
2277 {
2278 union cpuid10_edx edx;
2279 union cpuid10_eax eax;
2280 union cpuid10_ebx ebx;
2281 struct event_constraint *c;
2282 unsigned int unused;
2283 struct extra_reg *er;
2284 int version, i;
2285
2286 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2287 switch (boot_cpu_data.x86) {
2288 case 0x6:
2289 return p6_pmu_init();
2290 case 0xb:
2291 return knc_pmu_init();
2292 case 0xf:
2293 return p4_pmu_init();
2294 }
2295 return -ENODEV;
2296 }
2297
2298 /*
2299 * Check whether the Architectural PerfMon supports
2300 * Branch Misses Retired hw_event or not.
2301 */
2302 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2303 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
2304 return -ENODEV;
2305
2306 version = eax.split.version_id;
2307 if (version < 2)
2308 x86_pmu = core_pmu;
2309 else
2310 x86_pmu = intel_pmu;
2311
2312 x86_pmu.version = version;
2313 x86_pmu.num_counters = eax.split.num_counters;
2314 x86_pmu.cntval_bits = eax.split.bit_width;
2315 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
2316
2317 x86_pmu.events_maskl = ebx.full;
2318 x86_pmu.events_mask_len = eax.split.mask_length;
2319
2320 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2321
2322 /*
2323 * Quirk: v2 perfmon does not report fixed-purpose events, so
2324 * assume at least 3 events:
2325 */
2326 if (version > 1)
2327 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
2328
2329 if (boot_cpu_has(X86_FEATURE_PDCM)) {
2330 u64 capabilities;
2331
2332 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2333 x86_pmu.intel_cap.capabilities = capabilities;
2334 }
2335
2336 intel_ds_init();
2337
2338 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2339
2340 /*
2341 * Install the hw-cache-events table:
2342 */
2343 switch (boot_cpu_data.x86_model) {
2344 case 14: /* 65nm Core "Yonah" */
2345 pr_cont("Core events, ");
2346 break;
2347
2348 case 15: /* 65nm Core2 "Merom" */
2349 x86_add_quirk(intel_clovertown_quirk);
2350 case 22: /* 65nm Core2 "Merom-L" */
2351 case 23: /* 45nm Core2 "Penryn" */
2352 case 29: /* 45nm Core2 "Dunnington (MP) */
2353 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2354 sizeof(hw_cache_event_ids));
2355
2356 intel_pmu_lbr_init_core();
2357
2358 x86_pmu.event_constraints = intel_core2_event_constraints;
2359 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
2360 pr_cont("Core2 events, ");
2361 break;
2362
2363 case 30: /* 45nm Nehalem */
2364 case 26: /* 45nm Nehalem-EP */
2365 case 46: /* 45nm Nehalem-EX */
2366 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2367 sizeof(hw_cache_event_ids));
2368 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2369 sizeof(hw_cache_extra_regs));
2370
2371 intel_pmu_lbr_init_nhm();
2372
2373 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2374 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
2375 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2376 x86_pmu.extra_regs = intel_nehalem_extra_regs;
2377
2378 x86_pmu.cpu_events = nhm_events_attrs;
2379
2380 /* UOPS_ISSUED.STALLED_CYCLES */
2381 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2382 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2383 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2384 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2385 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2386
2387 x86_add_quirk(intel_nehalem_quirk);
2388
2389 pr_cont("Nehalem events, ");
2390 break;
2391
2392 case 28: /* 45nm Atom "Pineview" */
2393 case 38: /* 45nm Atom "Lincroft" */
2394 case 39: /* 32nm Atom "Penwell" */
2395 case 53: /* 32nm Atom "Cloverview" */
2396 case 54: /* 32nm Atom "Cedarview" */
2397 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2398 sizeof(hw_cache_event_ids));
2399
2400 intel_pmu_lbr_init_atom();
2401
2402 x86_pmu.event_constraints = intel_gen_event_constraints;
2403 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
2404 pr_cont("Atom events, ");
2405 break;
2406
2407 case 55: /* 22nm Atom "Silvermont" */
2408 case 76: /* 14nm Atom "Airmont" */
2409 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
2410 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
2411 sizeof(hw_cache_event_ids));
2412 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
2413 sizeof(hw_cache_extra_regs));
2414
2415 intel_pmu_lbr_init_atom();
2416
2417 x86_pmu.event_constraints = intel_slm_event_constraints;
2418 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
2419 x86_pmu.extra_regs = intel_slm_extra_regs;
2420 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2421 pr_cont("Silvermont events, ");
2422 break;
2423
2424 case 37: /* 32nm Westmere */
2425 case 44: /* 32nm Westmere-EP */
2426 case 47: /* 32nm Westmere-EX */
2427 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2428 sizeof(hw_cache_event_ids));
2429 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2430 sizeof(hw_cache_extra_regs));
2431
2432 intel_pmu_lbr_init_nhm();
2433
2434 x86_pmu.event_constraints = intel_westmere_event_constraints;
2435 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2436 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
2437 x86_pmu.extra_regs = intel_westmere_extra_regs;
2438 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2439
2440 x86_pmu.cpu_events = nhm_events_attrs;
2441
2442 /* UOPS_ISSUED.STALLED_CYCLES */
2443 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2444 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2445 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2446 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2447 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2448
2449 pr_cont("Westmere events, ");
2450 break;
2451
2452 case 42: /* 32nm SandyBridge */
2453 case 45: /* 32nm SandyBridge-E/EN/EP */
2454 x86_add_quirk(intel_sandybridge_quirk);
2455 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2456 sizeof(hw_cache_event_ids));
2457 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2458 sizeof(hw_cache_extra_regs));
2459
2460 intel_pmu_lbr_init_snb();
2461
2462 x86_pmu.event_constraints = intel_snb_event_constraints;
2463 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
2464 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2465 if (boot_cpu_data.x86_model == 45)
2466 x86_pmu.extra_regs = intel_snbep_extra_regs;
2467 else
2468 x86_pmu.extra_regs = intel_snb_extra_regs;
2469 /* all extra regs are per-cpu when HT is on */
2470 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2471 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2472
2473 x86_pmu.cpu_events = snb_events_attrs;
2474
2475 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2476 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2477 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2478 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
2479 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2480 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
2481
2482 pr_cont("SandyBridge events, ");
2483 break;
2484
2485 case 58: /* 22nm IvyBridge */
2486 case 62: /* 22nm IvyBridge-EP/EX */
2487 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2488 sizeof(hw_cache_event_ids));
2489 /* dTLB-load-misses on IVB is different than SNB */
2490 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
2491
2492 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2493 sizeof(hw_cache_extra_regs));
2494
2495 intel_pmu_lbr_init_snb();
2496
2497 x86_pmu.event_constraints = intel_ivb_event_constraints;
2498 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2499 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2500 if (boot_cpu_data.x86_model == 62)
2501 x86_pmu.extra_regs = intel_snbep_extra_regs;
2502 else
2503 x86_pmu.extra_regs = intel_snb_extra_regs;
2504 /* all extra regs are per-cpu when HT is on */
2505 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2506 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2507
2508 x86_pmu.cpu_events = snb_events_attrs;
2509
2510 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2511 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2512 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2513
2514 pr_cont("IvyBridge events, ");
2515 break;
2516
2517
2518 case 60: /* 22nm Haswell Core */
2519 case 63: /* 22nm Haswell Server */
2520 case 69: /* 22nm Haswell ULT */
2521 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
2522 x86_pmu.late_ack = true;
2523 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2524 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2525
2526 intel_pmu_lbr_init_hsw();
2527
2528 x86_pmu.event_constraints = intel_hsw_event_constraints;
2529 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
2530 x86_pmu.extra_regs = intel_snbep_extra_regs;
2531 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2532 /* all extra regs are per-cpu when HT is on */
2533 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2534 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2535
2536 x86_pmu.hw_config = hsw_hw_config;
2537 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2538 x86_pmu.cpu_events = hsw_events_attrs;
2539 x86_pmu.lbr_double_abort = true;
2540 pr_cont("Haswell events, ");
2541 break;
2542
2543 default:
2544 switch (x86_pmu.version) {
2545 case 1:
2546 x86_pmu.event_constraints = intel_v1_event_constraints;
2547 pr_cont("generic architected perfmon v1, ");
2548 break;
2549 default:
2550 /*
2551 * default constraints for v2 and up
2552 */
2553 x86_pmu.event_constraints = intel_gen_event_constraints;
2554 pr_cont("generic architected perfmon, ");
2555 break;
2556 }
2557 }
2558
2559 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2560 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2561 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2562 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2563 }
2564 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2565
2566 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2567 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2568 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2569 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2570 }
2571
2572 x86_pmu.intel_ctrl |=
2573 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2574
2575 if (x86_pmu.event_constraints) {
2576 /*
2577 * event on fixed counter2 (REF_CYCLES) only works on this
2578 * counter, so do not extend mask to generic counters
2579 */
2580 for_each_event_constraint(c, x86_pmu.event_constraints) {
2581 if (c->cmask != FIXED_EVENT_FLAGS
2582 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2583 continue;
2584 }
2585
2586 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2587 c->weight += x86_pmu.num_counters;
2588 }
2589 }
2590
2591 /*
2592 * Access LBR MSR may cause #GP under certain circumstances.
2593 * E.g. KVM doesn't support LBR MSR
2594 * Check all LBT MSR here.
2595 * Disable LBR access if any LBR MSRs can not be accessed.
2596 */
2597 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
2598 x86_pmu.lbr_nr = 0;
2599 for (i = 0; i < x86_pmu.lbr_nr; i++) {
2600 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
2601 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
2602 x86_pmu.lbr_nr = 0;
2603 }
2604
2605 /*
2606 * Access extra MSR may cause #GP under certain circumstances.
2607 * E.g. KVM doesn't support offcore event
2608 * Check all extra_regs here.
2609 */
2610 if (x86_pmu.extra_regs) {
2611 for (er = x86_pmu.extra_regs; er->msr; er++) {
2612 er->extra_msr_access = check_msr(er->msr, 0x1ffUL);
2613 /* Disable LBR select mapping */
2614 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
2615 x86_pmu.lbr_sel_map = NULL;
2616 }
2617 }
2618
2619 /* Support full width counters using alternative MSR range */
2620 if (x86_pmu.intel_cap.full_width_write) {
2621 x86_pmu.max_period = x86_pmu.cntval_mask;
2622 x86_pmu.perfctr = MSR_IA32_PMC0;
2623 pr_cont("full-width counters, ");
2624 }
2625
2626 return 0;
2627 }
Linux kernel - Deliverables
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