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perf/x86: Don't mark DataLA addresses as store
[deliverable/linux.git] / arch / x86 / kernel / cpu / perf_event_intel_ds.c
1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
4
5 #include <asm/perf_event.h>
6 #include <asm/insn.h>
7
8 #include "perf_event.h"
9
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
12
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE PAGE_SIZE
15 #define PEBS_FIXUP_SIZE PAGE_SIZE
16
17 /*
18 * pebs_record_32 for p4 and core not supported
19
20 struct pebs_record_32 {
21 u32 flags, ip;
22 u32 ax, bc, cx, dx;
23 u32 si, di, bp, sp;
24 };
25
26 */
27
28 union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43 };
44
45
46 /*
47 * Map PEBS Load Latency Data Source encodings to generic
48 * memory data source information
49 */
50 #define P(a, b) PERF_MEM_S(a, b)
51 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54 static const u64 pebs_data_source[] = {
55 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
56 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
57 OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
58 OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
60 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
61 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
62 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
63 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
65 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
66 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
67 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */
68 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */
69 OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */
70 OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */
71 };
72
73 static u64 precise_store_data(u64 status)
74 {
75 union intel_x86_pebs_dse dse;
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
77
78 dse.val = status;
79
80 /*
81 * bit 4: TLB access
82 * 1 = stored missed 2nd level TLB
83 *
84 * so it either hit the walker or the OS
85 * otherwise hit 2nd level TLB
86 */
87 if (dse.st_stlb_miss)
88 val |= P(TLB, MISS);
89 else
90 val |= P(TLB, HIT);
91
92 /*
93 * bit 0: hit L1 data cache
94 * if not set, then all we know is that
95 * it missed L1D
96 */
97 if (dse.st_l1d_hit)
98 val |= P(LVL, HIT);
99 else
100 val |= P(LVL, MISS);
101
102 /*
103 * bit 5: Locked prefix
104 */
105 if (dse.st_locked)
106 val |= P(LOCK, LOCKED);
107
108 return val;
109 }
110
111 static u64 precise_store_data_hsw(struct perf_event *event, u64 status)
112 {
113 union perf_mem_data_src dse;
114 u64 cfg = event->hw.config & INTEL_ARCH_EVENT_MASK;
115
116 dse.val = 0;
117 dse.mem_op = PERF_MEM_OP_NA;
118 dse.mem_lvl = PERF_MEM_LVL_NA;
119
120 /*
121 * L1 info only valid for following events:
122 *
123 * MEM_UOPS_RETIRED.STLB_MISS_STORES
124 * MEM_UOPS_RETIRED.LOCK_STORES
125 * MEM_UOPS_RETIRED.SPLIT_STORES
126 * MEM_UOPS_RETIRED.ALL_STORES
127 */
128 if (cfg != 0x12d0 && cfg != 0x22d0 && cfg != 0x42d0 && cfg != 0x82d0)
129 return dse.mem_lvl;
130
131 if (status & 1)
132 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
133 else
134 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
135
136 /* Nothing else supported. Sorry. */
137 return dse.val;
138 }
139
140 static u64 load_latency_data(u64 status)
141 {
142 union intel_x86_pebs_dse dse;
143 u64 val;
144 int model = boot_cpu_data.x86_model;
145 int fam = boot_cpu_data.x86;
146
147 dse.val = status;
148
149 /*
150 * use the mapping table for bit 0-3
151 */
152 val = pebs_data_source[dse.ld_dse];
153
154 /*
155 * Nehalem models do not support TLB, Lock infos
156 */
157 if (fam == 0x6 && (model == 26 || model == 30
158 || model == 31 || model == 46)) {
159 val |= P(TLB, NA) | P(LOCK, NA);
160 return val;
161 }
162 /*
163 * bit 4: TLB access
164 * 0 = did not miss 2nd level TLB
165 * 1 = missed 2nd level TLB
166 */
167 if (dse.ld_stlb_miss)
168 val |= P(TLB, MISS) | P(TLB, L2);
169 else
170 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
171
172 /*
173 * bit 5: locked prefix
174 */
175 if (dse.ld_locked)
176 val |= P(LOCK, LOCKED);
177
178 return val;
179 }
180
181 struct pebs_record_core {
182 u64 flags, ip;
183 u64 ax, bx, cx, dx;
184 u64 si, di, bp, sp;
185 u64 r8, r9, r10, r11;
186 u64 r12, r13, r14, r15;
187 };
188
189 struct pebs_record_nhm {
190 u64 flags, ip;
191 u64 ax, bx, cx, dx;
192 u64 si, di, bp, sp;
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
195 u64 status, dla, dse, lat;
196 };
197
198 /*
199 * Same as pebs_record_nhm, with two additional fields.
200 */
201 struct pebs_record_hsw {
202 u64 flags, ip;
203 u64 ax, bx, cx, dx;
204 u64 si, di, bp, sp;
205 u64 r8, r9, r10, r11;
206 u64 r12, r13, r14, r15;
207 u64 status, dla, dse, lat;
208 u64 real_ip, tsx_tuning;
209 };
210
211 union hsw_tsx_tuning {
212 struct {
213 u32 cycles_last_block : 32,
214 hle_abort : 1,
215 rtm_abort : 1,
216 instruction_abort : 1,
217 non_instruction_abort : 1,
218 retry : 1,
219 data_conflict : 1,
220 capacity_writes : 1,
221 capacity_reads : 1;
222 };
223 u64 value;
224 };
225
226 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
227
228 void init_debug_store_on_cpu(int cpu)
229 {
230 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
231
232 if (!ds)
233 return;
234
235 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
236 (u32)((u64)(unsigned long)ds),
237 (u32)((u64)(unsigned long)ds >> 32));
238 }
239
240 void fini_debug_store_on_cpu(int cpu)
241 {
242 if (!per_cpu(cpu_hw_events, cpu).ds)
243 return;
244
245 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
246 }
247
248 static DEFINE_PER_CPU(void *, insn_buffer);
249
250 static int alloc_pebs_buffer(int cpu)
251 {
252 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
253 int node = cpu_to_node(cpu);
254 int max, thresh = 1; /* always use a single PEBS record */
255 void *buffer, *ibuffer;
256
257 if (!x86_pmu.pebs)
258 return 0;
259
260 buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node);
261 if (unlikely(!buffer))
262 return -ENOMEM;
263
264 /*
265 * HSW+ already provides us the eventing ip; no need to allocate this
266 * buffer then.
267 */
268 if (x86_pmu.intel_cap.pebs_format < 2) {
269 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
270 if (!ibuffer) {
271 kfree(buffer);
272 return -ENOMEM;
273 }
274 per_cpu(insn_buffer, cpu) = ibuffer;
275 }
276
277 max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
278
279 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
280 ds->pebs_index = ds->pebs_buffer_base;
281 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
282 max * x86_pmu.pebs_record_size;
283
284 ds->pebs_interrupt_threshold = ds->pebs_buffer_base +
285 thresh * x86_pmu.pebs_record_size;
286
287 return 0;
288 }
289
290 static void release_pebs_buffer(int cpu)
291 {
292 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
293
294 if (!ds || !x86_pmu.pebs)
295 return;
296
297 kfree(per_cpu(insn_buffer, cpu));
298 per_cpu(insn_buffer, cpu) = NULL;
299
300 kfree((void *)(unsigned long)ds->pebs_buffer_base);
301 ds->pebs_buffer_base = 0;
302 }
303
304 static int alloc_bts_buffer(int cpu)
305 {
306 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
307 int node = cpu_to_node(cpu);
308 int max, thresh;
309 void *buffer;
310
311 if (!x86_pmu.bts)
312 return 0;
313
314 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
315 if (unlikely(!buffer)) {
316 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
317 return -ENOMEM;
318 }
319
320 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
321 thresh = max / 16;
322
323 ds->bts_buffer_base = (u64)(unsigned long)buffer;
324 ds->bts_index = ds->bts_buffer_base;
325 ds->bts_absolute_maximum = ds->bts_buffer_base +
326 max * BTS_RECORD_SIZE;
327 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
328 thresh * BTS_RECORD_SIZE;
329
330 return 0;
331 }
332
333 static void release_bts_buffer(int cpu)
334 {
335 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
336
337 if (!ds || !x86_pmu.bts)
338 return;
339
340 kfree((void *)(unsigned long)ds->bts_buffer_base);
341 ds->bts_buffer_base = 0;
342 }
343
344 static int alloc_ds_buffer(int cpu)
345 {
346 int node = cpu_to_node(cpu);
347 struct debug_store *ds;
348
349 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
350 if (unlikely(!ds))
351 return -ENOMEM;
352
353 per_cpu(cpu_hw_events, cpu).ds = ds;
354
355 return 0;
356 }
357
358 static void release_ds_buffer(int cpu)
359 {
360 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
361
362 if (!ds)
363 return;
364
365 per_cpu(cpu_hw_events, cpu).ds = NULL;
366 kfree(ds);
367 }
368
369 void release_ds_buffers(void)
370 {
371 int cpu;
372
373 if (!x86_pmu.bts && !x86_pmu.pebs)
374 return;
375
376 get_online_cpus();
377 for_each_online_cpu(cpu)
378 fini_debug_store_on_cpu(cpu);
379
380 for_each_possible_cpu(cpu) {
381 release_pebs_buffer(cpu);
382 release_bts_buffer(cpu);
383 release_ds_buffer(cpu);
384 }
385 put_online_cpus();
386 }
387
388 void reserve_ds_buffers(void)
389 {
390 int bts_err = 0, pebs_err = 0;
391 int cpu;
392
393 x86_pmu.bts_active = 0;
394 x86_pmu.pebs_active = 0;
395
396 if (!x86_pmu.bts && !x86_pmu.pebs)
397 return;
398
399 if (!x86_pmu.bts)
400 bts_err = 1;
401
402 if (!x86_pmu.pebs)
403 pebs_err = 1;
404
405 get_online_cpus();
406
407 for_each_possible_cpu(cpu) {
408 if (alloc_ds_buffer(cpu)) {
409 bts_err = 1;
410 pebs_err = 1;
411 }
412
413 if (!bts_err && alloc_bts_buffer(cpu))
414 bts_err = 1;
415
416 if (!pebs_err && alloc_pebs_buffer(cpu))
417 pebs_err = 1;
418
419 if (bts_err && pebs_err)
420 break;
421 }
422
423 if (bts_err) {
424 for_each_possible_cpu(cpu)
425 release_bts_buffer(cpu);
426 }
427
428 if (pebs_err) {
429 for_each_possible_cpu(cpu)
430 release_pebs_buffer(cpu);
431 }
432
433 if (bts_err && pebs_err) {
434 for_each_possible_cpu(cpu)
435 release_ds_buffer(cpu);
436 } else {
437 if (x86_pmu.bts && !bts_err)
438 x86_pmu.bts_active = 1;
439
440 if (x86_pmu.pebs && !pebs_err)
441 x86_pmu.pebs_active = 1;
442
443 for_each_online_cpu(cpu)
444 init_debug_store_on_cpu(cpu);
445 }
446
447 put_online_cpus();
448 }
449
450 /*
451 * BTS
452 */
453
454 struct event_constraint bts_constraint =
455 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
456
457 void intel_pmu_enable_bts(u64 config)
458 {
459 unsigned long debugctlmsr;
460
461 debugctlmsr = get_debugctlmsr();
462
463 debugctlmsr |= DEBUGCTLMSR_TR;
464 debugctlmsr |= DEBUGCTLMSR_BTS;
465 debugctlmsr |= DEBUGCTLMSR_BTINT;
466
467 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
468 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
469
470 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
471 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
472
473 update_debugctlmsr(debugctlmsr);
474 }
475
476 void intel_pmu_disable_bts(void)
477 {
478 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
479 unsigned long debugctlmsr;
480
481 if (!cpuc->ds)
482 return;
483
484 debugctlmsr = get_debugctlmsr();
485
486 debugctlmsr &=
487 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
488 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
489
490 update_debugctlmsr(debugctlmsr);
491 }
492
493 int intel_pmu_drain_bts_buffer(void)
494 {
495 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
496 struct debug_store *ds = cpuc->ds;
497 struct bts_record {
498 u64 from;
499 u64 to;
500 u64 flags;
501 };
502 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
503 struct bts_record *at, *top;
504 struct perf_output_handle handle;
505 struct perf_event_header header;
506 struct perf_sample_data data;
507 struct pt_regs regs;
508
509 if (!event)
510 return 0;
511
512 if (!x86_pmu.bts_active)
513 return 0;
514
515 at = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
516 top = (struct bts_record *)(unsigned long)ds->bts_index;
517
518 if (top <= at)
519 return 0;
520
521 memset(&regs, 0, sizeof(regs));
522
523 ds->bts_index = ds->bts_buffer_base;
524
525 perf_sample_data_init(&data, 0, event->hw.last_period);
526
527 /*
528 * Prepare a generic sample, i.e. fill in the invariant fields.
529 * We will overwrite the from and to address before we output
530 * the sample.
531 */
532 perf_prepare_sample(&header, &data, event, &regs);
533
534 if (perf_output_begin(&handle, event, header.size * (top - at)))
535 return 1;
536
537 for (; at < top; at++) {
538 data.ip = at->from;
539 data.addr = at->to;
540
541 perf_output_sample(&handle, &header, &data, event);
542 }
543
544 perf_output_end(&handle);
545
546 /* There's new data available. */
547 event->hw.interrupts++;
548 event->pending_kill = POLL_IN;
549 return 1;
550 }
551
552 /*
553 * PEBS
554 */
555 struct event_constraint intel_core2_pebs_event_constraints[] = {
556 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
557 INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
558 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
559 INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
560 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
561 EVENT_CONSTRAINT_END
562 };
563
564 struct event_constraint intel_atom_pebs_event_constraints[] = {
565 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
566 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
567 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
568 EVENT_CONSTRAINT_END
569 };
570
571 struct event_constraint intel_slm_pebs_event_constraints[] = {
572 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
573 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
574 /* Allow all events as PEBS with no flags */
575 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
576 EVENT_CONSTRAINT_END
577 };
578
579 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
580 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
581 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
582 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
583 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
584 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
585 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
586 INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
587 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
588 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
589 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
590 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
591 EVENT_CONSTRAINT_END
592 };
593
594 struct event_constraint intel_westmere_pebs_event_constraints[] = {
595 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
596 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
597 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
598 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
599 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
600 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
601 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
602 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
603 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
604 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
605 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
606 EVENT_CONSTRAINT_END
607 };
608
609 struct event_constraint intel_snb_pebs_event_constraints[] = {
610 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
611 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
612 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
613 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
614 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
615 /* Allow all events as PEBS with no flags */
616 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
617 EVENT_CONSTRAINT_END
618 };
619
620 struct event_constraint intel_ivb_pebs_event_constraints[] = {
621 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
622 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
623 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
624 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
625 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
626 /* Allow all events as PEBS with no flags */
627 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
628 EVENT_CONSTRAINT_END
629 };
630
631 struct event_constraint intel_hsw_pebs_event_constraints[] = {
632 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
633 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
634 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
635 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
636 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
637 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
638 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
639 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
640 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
641 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
642 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
643 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
644 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
645 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
646 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
647 /* Allow all events as PEBS with no flags */
648 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
649 EVENT_CONSTRAINT_END
650 };
651
652 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
653 {
654 struct event_constraint *c;
655
656 if (!event->attr.precise_ip)
657 return NULL;
658
659 if (x86_pmu.pebs_constraints) {
660 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
661 if ((event->hw.config & c->cmask) == c->code) {
662 event->hw.flags |= c->flags;
663 return c;
664 }
665 }
666 }
667
668 return &emptyconstraint;
669 }
670
671 void intel_pmu_pebs_enable(struct perf_event *event)
672 {
673 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
674 struct hw_perf_event *hwc = &event->hw;
675
676 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
677
678 cpuc->pebs_enabled |= 1ULL << hwc->idx;
679
680 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
681 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
682 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
683 cpuc->pebs_enabled |= 1ULL << 63;
684 }
685
686 void intel_pmu_pebs_disable(struct perf_event *event)
687 {
688 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
689 struct hw_perf_event *hwc = &event->hw;
690
691 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
692
693 if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
694 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
695 else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
696 cpuc->pebs_enabled &= ~(1ULL << 63);
697
698 if (cpuc->enabled)
699 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
700
701 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
702 }
703
704 void intel_pmu_pebs_enable_all(void)
705 {
706 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
707
708 if (cpuc->pebs_enabled)
709 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
710 }
711
712 void intel_pmu_pebs_disable_all(void)
713 {
714 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
715
716 if (cpuc->pebs_enabled)
717 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
718 }
719
720 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
721 {
722 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
723 unsigned long from = cpuc->lbr_entries[0].from;
724 unsigned long old_to, to = cpuc->lbr_entries[0].to;
725 unsigned long ip = regs->ip;
726 int is_64bit = 0;
727 void *kaddr;
728
729 /*
730 * We don't need to fixup if the PEBS assist is fault like
731 */
732 if (!x86_pmu.intel_cap.pebs_trap)
733 return 1;
734
735 /*
736 * No LBR entry, no basic block, no rewinding
737 */
738 if (!cpuc->lbr_stack.nr || !from || !to)
739 return 0;
740
741 /*
742 * Basic blocks should never cross user/kernel boundaries
743 */
744 if (kernel_ip(ip) != kernel_ip(to))
745 return 0;
746
747 /*
748 * unsigned math, either ip is before the start (impossible) or
749 * the basic block is larger than 1 page (sanity)
750 */
751 if ((ip - to) > PEBS_FIXUP_SIZE)
752 return 0;
753
754 /*
755 * We sampled a branch insn, rewind using the LBR stack
756 */
757 if (ip == to) {
758 set_linear_ip(regs, from);
759 return 1;
760 }
761
762 if (!kernel_ip(ip)) {
763 int size, bytes;
764 u8 *buf = this_cpu_read(insn_buffer);
765
766 size = ip - to; /* Must fit our buffer, see above */
767 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
768 if (bytes != 0)
769 return 0;
770
771 kaddr = buf;
772 } else {
773 kaddr = (void *)to;
774 }
775
776 do {
777 struct insn insn;
778
779 old_to = to;
780
781 #ifdef CONFIG_X86_64
782 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
783 #endif
784 insn_init(&insn, kaddr, is_64bit);
785 insn_get_length(&insn);
786
787 to += insn.length;
788 kaddr += insn.length;
789 } while (to < ip);
790
791 if (to == ip) {
792 set_linear_ip(regs, old_to);
793 return 1;
794 }
795
796 /*
797 * Even though we decoded the basic block, the instruction stream
798 * never matched the given IP, either the TO or the IP got corrupted.
799 */
800 return 0;
801 }
802
803 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
804 {
805 if (pebs->tsx_tuning) {
806 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
807 return tsx.cycles_last_block;
808 }
809 return 0;
810 }
811
812 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
813 {
814 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
815
816 /* For RTM XABORTs also log the abort code from AX */
817 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
818 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
819 return txn;
820 }
821
822 static void __intel_pmu_pebs_event(struct perf_event *event,
823 struct pt_regs *iregs, void *__pebs)
824 {
825 /*
826 * We cast to the biggest pebs_record but are careful not to
827 * unconditionally access the 'extra' entries.
828 */
829 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
830 struct pebs_record_hsw *pebs = __pebs;
831 struct perf_sample_data data;
832 struct pt_regs regs;
833 u64 sample_type;
834 int fll, fst;
835
836 if (!intel_pmu_save_and_restart(event))
837 return;
838
839 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
840 fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
841 PERF_X86_EVENT_PEBS_ST_HSW |
842 PERF_X86_EVENT_PEBS_LD_HSW |
843 PERF_X86_EVENT_PEBS_NA_HSW);
844
845 perf_sample_data_init(&data, 0, event->hw.last_period);
846
847 data.period = event->hw.last_period;
848 sample_type = event->attr.sample_type;
849
850 /*
851 * if PEBS-LL or PreciseStore
852 */
853 if (fll || fst) {
854 /*
855 * Use latency for weight (only avail with PEBS-LL)
856 */
857 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
858 data.weight = pebs->lat;
859
860 /*
861 * data.data_src encodes the data source
862 */
863 if (sample_type & PERF_SAMPLE_DATA_SRC) {
864 if (fll)
865 data.data_src.val = load_latency_data(pebs->dse);
866 else if (event->hw.flags &
867 (PERF_X86_EVENT_PEBS_ST_HSW|
868 PERF_X86_EVENT_PEBS_LD_HSW|
869 PERF_X86_EVENT_PEBS_NA_HSW))
870 data.data_src.val =
871 precise_store_data_hsw(event, pebs->dse);
872 else
873 data.data_src.val = precise_store_data(pebs->dse);
874 }
875 }
876
877 /*
878 * We use the interrupt regs as a base because the PEBS record
879 * does not contain a full regs set, specifically it seems to
880 * lack segment descriptors, which get used by things like
881 * user_mode().
882 *
883 * In the simple case fix up only the IP and BP,SP regs, for
884 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
885 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
886 */
887 regs = *iregs;
888 regs.flags = pebs->flags;
889 set_linear_ip(&regs, pebs->ip);
890 regs.bp = pebs->bp;
891 regs.sp = pebs->sp;
892
893 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
894 regs.ip = pebs->real_ip;
895 regs.flags |= PERF_EFLAGS_EXACT;
896 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
897 regs.flags |= PERF_EFLAGS_EXACT;
898 else
899 regs.flags &= ~PERF_EFLAGS_EXACT;
900
901 if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
902 x86_pmu.intel_cap.pebs_format >= 1)
903 data.addr = pebs->dla;
904
905 if (x86_pmu.intel_cap.pebs_format >= 2) {
906 /* Only set the TSX weight when no memory weight. */
907 if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll)
908 data.weight = intel_hsw_weight(pebs);
909
910 if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION)
911 data.txn = intel_hsw_transaction(pebs);
912 }
913
914 if (has_branch_stack(event))
915 data.br_stack = &cpuc->lbr_stack;
916
917 if (perf_event_overflow(event, &data, &regs))
918 x86_pmu_stop(event, 0);
919 }
920
921 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
922 {
923 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
924 struct debug_store *ds = cpuc->ds;
925 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
926 struct pebs_record_core *at, *top;
927 int n;
928
929 if (!x86_pmu.pebs_active)
930 return;
931
932 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
933 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
934
935 /*
936 * Whatever else happens, drain the thing
937 */
938 ds->pebs_index = ds->pebs_buffer_base;
939
940 if (!test_bit(0, cpuc->active_mask))
941 return;
942
943 WARN_ON_ONCE(!event);
944
945 if (!event->attr.precise_ip)
946 return;
947
948 n = top - at;
949 if (n <= 0)
950 return;
951
952 /*
953 * Should not happen, we program the threshold at 1 and do not
954 * set a reset value.
955 */
956 WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
957 at += n - 1;
958
959 __intel_pmu_pebs_event(event, iregs, at);
960 }
961
962 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
963 {
964 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
965 struct debug_store *ds = cpuc->ds;
966 struct perf_event *event = NULL;
967 void *at, *top;
968 u64 status = 0;
969 int bit;
970
971 if (!x86_pmu.pebs_active)
972 return;
973
974 at = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
975 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
976
977 ds->pebs_index = ds->pebs_buffer_base;
978
979 if (unlikely(at > top))
980 return;
981
982 /*
983 * Should not happen, we program the threshold at 1 and do not
984 * set a reset value.
985 */
986 WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
987 "Unexpected number of pebs records %ld\n",
988 (long)(top - at) / x86_pmu.pebs_record_size);
989
990 for (; at < top; at += x86_pmu.pebs_record_size) {
991 struct pebs_record_nhm *p = at;
992
993 for_each_set_bit(bit, (unsigned long *)&p->status,
994 x86_pmu.max_pebs_events) {
995 event = cpuc->events[bit];
996 if (!test_bit(bit, cpuc->active_mask))
997 continue;
998
999 WARN_ON_ONCE(!event);
1000
1001 if (!event->attr.precise_ip)
1002 continue;
1003
1004 if (__test_and_set_bit(bit, (unsigned long *)&status))
1005 continue;
1006
1007 break;
1008 }
1009
1010 if (!event || bit >= x86_pmu.max_pebs_events)
1011 continue;
1012
1013 __intel_pmu_pebs_event(event, iregs, at);
1014 }
1015 }
1016
1017 /*
1018 * BTS, PEBS probe and setup
1019 */
1020
1021 void intel_ds_init(void)
1022 {
1023 /*
1024 * No support for 32bit formats
1025 */
1026 if (!boot_cpu_has(X86_FEATURE_DTES64))
1027 return;
1028
1029 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1030 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1031 if (x86_pmu.pebs) {
1032 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1033 int format = x86_pmu.intel_cap.pebs_format;
1034
1035 switch (format) {
1036 case 0:
1037 printk(KERN_CONT "PEBS fmt0%c, ", pebs_type);
1038 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1039 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1040 break;
1041
1042 case 1:
1043 printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
1044 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1045 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1046 break;
1047
1048 case 2:
1049 pr_cont("PEBS fmt2%c, ", pebs_type);
1050 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1051 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1052 break;
1053
1054 default:
1055 printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
1056 x86_pmu.pebs = 0;
1057 }
1058 }
1059 }
1060
1061 void perf_restore_debug_store(void)
1062 {
1063 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1064
1065 if (!x86_pmu.bts && !x86_pmu.pebs)
1066 return;
1067
1068 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1069 }
Linux kernel - Deliverables
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