1 #include <linux/perf_event.h>
2 #include <linux/types.h>
4 #include <asm/perf_event.h>
8 #include "perf_event.h"
12 LBR_FORMAT_LIP
= 0x01,
13 LBR_FORMAT_EIP
= 0x02,
14 LBR_FORMAT_EIP_FLAGS
= 0x03,
15 LBR_FORMAT_EIP_FLAGS2
= 0x04,
16 LBR_FORMAT_MAX_KNOWN
= LBR_FORMAT_EIP_FLAGS2
,
22 } lbr_desc
[LBR_FORMAT_MAX_KNOWN
+ 1] = {
23 [LBR_FORMAT_EIP_FLAGS
] = LBR_EIP_FLAGS
,
24 [LBR_FORMAT_EIP_FLAGS2
] = LBR_EIP_FLAGS
| LBR_TSX
,
28 * Intel LBR_SELECT bits
29 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
31 * Hardware branch filter (not available on all CPUs)
33 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
34 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
35 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
36 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
37 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
38 #define LBR_RETURN_BIT 5 /* do not capture near returns */
39 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
40 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
41 #define LBR_FAR_BIT 8 /* do not capture far branches */
42 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
44 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
45 #define LBR_USER (1 << LBR_USER_BIT)
46 #define LBR_JCC (1 << LBR_JCC_BIT)
47 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
48 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
49 #define LBR_RETURN (1 << LBR_RETURN_BIT)
50 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
51 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
52 #define LBR_FAR (1 << LBR_FAR_BIT)
53 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
55 #define LBR_PLM (LBR_KERNEL | LBR_USER)
57 #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */
58 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
59 #define LBR_IGN 0 /* ignored */
70 #define LBR_FROM_FLAG_MISPRED (1ULL << 63)
71 #define LBR_FROM_FLAG_IN_TX (1ULL << 62)
72 #define LBR_FROM_FLAG_ABORT (1ULL << 61)
75 * x86control flow change classification
76 * x86control flow changes include branches, interrupts, traps, faults
79 X86_BR_NONE
= 0, /* unknown */
81 X86_BR_USER
= 1 << 0, /* branch target is user */
82 X86_BR_KERNEL
= 1 << 1, /* branch target is kernel */
84 X86_BR_CALL
= 1 << 2, /* call */
85 X86_BR_RET
= 1 << 3, /* return */
86 X86_BR_SYSCALL
= 1 << 4, /* syscall */
87 X86_BR_SYSRET
= 1 << 5, /* syscall return */
88 X86_BR_INT
= 1 << 6, /* sw interrupt */
89 X86_BR_IRET
= 1 << 7, /* return from interrupt */
90 X86_BR_JCC
= 1 << 8, /* conditional */
91 X86_BR_JMP
= 1 << 9, /* jump */
92 X86_BR_IRQ
= 1 << 10,/* hw interrupt or trap or fault */
93 X86_BR_IND_CALL
= 1 << 11,/* indirect calls */
94 X86_BR_ABORT
= 1 << 12,/* transaction abort */
95 X86_BR_IN_TX
= 1 << 13,/* in transaction */
96 X86_BR_NO_TX
= 1 << 14,/* not in transaction */
97 X86_BR_ZERO_CALL
= 1 << 15,/* zero length call */
98 X86_BR_CALL_STACK
= 1 << 16,/* call stack */
101 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
102 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
118 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
120 #define X86_BR_ANY_CALL \
128 static void intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
);
131 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
132 * otherwise it becomes near impossible to get a reliable stack.
135 static void __intel_pmu_lbr_enable(bool pmi
)
137 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
138 u64 debugctl
, lbr_select
= 0;
141 * No need to reprogram LBR_SELECT in a PMI, as it
144 if (cpuc
->lbr_sel
&& !pmi
) {
145 lbr_select
= cpuc
->lbr_sel
->config
;
146 wrmsrl(MSR_LBR_SELECT
, lbr_select
);
149 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
150 debugctl
|= DEBUGCTLMSR_LBR
;
152 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
153 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
154 * may cause superfluous increase/decrease of LBR_TOS.
156 if (!(lbr_select
& LBR_CALL_STACK
))
157 debugctl
|= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
;
158 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
161 static void __intel_pmu_lbr_disable(void)
165 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
166 debugctl
&= ~(DEBUGCTLMSR_LBR
| DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
);
167 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
170 static void intel_pmu_lbr_reset_32(void)
174 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++)
175 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
178 static void intel_pmu_lbr_reset_64(void)
182 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
183 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
184 wrmsrl(x86_pmu
.lbr_to
+ i
, 0);
188 void intel_pmu_lbr_reset(void)
193 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
194 intel_pmu_lbr_reset_32();
196 intel_pmu_lbr_reset_64();
200 * TOS = most recently recorded branch
202 static inline u64
intel_pmu_lbr_tos(void)
206 rdmsrl(x86_pmu
.lbr_tos
, tos
);
215 static void __intel_pmu_lbr_restore(struct x86_perf_task_context
*task_ctx
)
218 unsigned lbr_idx
, mask
;
221 if (task_ctx
->lbr_callstack_users
== 0 ||
222 task_ctx
->lbr_stack_state
== LBR_NONE
) {
223 intel_pmu_lbr_reset();
227 mask
= x86_pmu
.lbr_nr
- 1;
228 tos
= intel_pmu_lbr_tos();
229 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
230 lbr_idx
= (tos
- i
) & mask
;
231 wrmsrl(x86_pmu
.lbr_from
+ lbr_idx
, task_ctx
->lbr_from
[i
]);
232 wrmsrl(x86_pmu
.lbr_to
+ lbr_idx
, task_ctx
->lbr_to
[i
]);
234 task_ctx
->lbr_stack_state
= LBR_NONE
;
237 static void __intel_pmu_lbr_save(struct x86_perf_task_context
*task_ctx
)
240 unsigned lbr_idx
, mask
;
243 if (task_ctx
->lbr_callstack_users
== 0) {
244 task_ctx
->lbr_stack_state
= LBR_NONE
;
248 mask
= x86_pmu
.lbr_nr
- 1;
249 tos
= intel_pmu_lbr_tos();
250 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
251 lbr_idx
= (tos
- i
) & mask
;
252 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, task_ctx
->lbr_from
[i
]);
253 rdmsrl(x86_pmu
.lbr_to
+ lbr_idx
, task_ctx
->lbr_to
[i
]);
255 task_ctx
->lbr_stack_state
= LBR_VALID
;
258 void intel_pmu_lbr_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
260 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
261 struct x86_perf_task_context
*task_ctx
;
267 * If LBR callstack feature is enabled and the stack was saved when
268 * the task was scheduled out, restore the stack. Otherwise flush
271 task_ctx
= ctx
? ctx
->task_ctx_data
: NULL
;
274 __intel_pmu_lbr_restore(task_ctx
);
275 cpuc
->lbr_context
= ctx
;
277 __intel_pmu_lbr_save(task_ctx
);
283 * When sampling the branck stack in system-wide, it may be
284 * necessary to flush the stack on context switch. This happens
285 * when the branch stack does not tag its entries with the pid
286 * of the current task. Otherwise it becomes impossible to
287 * associate a branch entry with a task. This ambiguity is more
288 * likely to appear when the branch stack supports priv level
289 * filtering and the user sets it to monitor only at the user
290 * level (which could be a useful measurement in system-wide
291 * mode). In that case, the risk is high of having a branch
292 * stack with branch from multiple tasks.
295 intel_pmu_lbr_reset();
296 cpuc
->lbr_context
= ctx
;
300 static inline bool branch_user_callstack(unsigned br_sel
)
302 return (br_sel
& X86_BR_USER
) && (br_sel
& X86_BR_CALL_STACK
);
305 void intel_pmu_lbr_enable(struct perf_event
*event
)
307 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
308 struct x86_perf_task_context
*task_ctx
;
314 * Reset the LBR stack if we changed task context to
317 if (event
->ctx
->task
&& cpuc
->lbr_context
!= event
->ctx
) {
318 intel_pmu_lbr_reset();
319 cpuc
->lbr_context
= event
->ctx
;
321 cpuc
->br_sel
= event
->hw
.branch_reg
.reg
;
323 if (branch_user_callstack(cpuc
->br_sel
) && event
->ctx
&&
324 event
->ctx
->task_ctx_data
) {
325 task_ctx
= event
->ctx
->task_ctx_data
;
326 task_ctx
->lbr_callstack_users
++;
330 perf_sched_cb_inc(event
->ctx
->pmu
);
333 void intel_pmu_lbr_disable(struct perf_event
*event
)
335 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
336 struct x86_perf_task_context
*task_ctx
;
341 if (branch_user_callstack(cpuc
->br_sel
) && event
->ctx
&&
342 event
->ctx
->task_ctx_data
) {
343 task_ctx
= event
->ctx
->task_ctx_data
;
344 task_ctx
->lbr_callstack_users
--;
348 WARN_ON_ONCE(cpuc
->lbr_users
< 0);
349 perf_sched_cb_dec(event
->ctx
->pmu
);
351 if (cpuc
->enabled
&& !cpuc
->lbr_users
) {
352 __intel_pmu_lbr_disable();
353 /* avoid stale pointer */
354 cpuc
->lbr_context
= NULL
;
358 void intel_pmu_lbr_enable_all(bool pmi
)
360 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
363 __intel_pmu_lbr_enable(pmi
);
366 void intel_pmu_lbr_disable_all(void)
368 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
371 __intel_pmu_lbr_disable();
374 static void intel_pmu_lbr_read_32(struct cpu_hw_events
*cpuc
)
376 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
377 u64 tos
= intel_pmu_lbr_tos();
380 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
381 unsigned long lbr_idx
= (tos
- i
) & mask
;
390 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, msr_lastbranch
.lbr
);
392 cpuc
->lbr_entries
[i
].from
= msr_lastbranch
.from
;
393 cpuc
->lbr_entries
[i
].to
= msr_lastbranch
.to
;
394 cpuc
->lbr_entries
[i
].mispred
= 0;
395 cpuc
->lbr_entries
[i
].predicted
= 0;
396 cpuc
->lbr_entries
[i
].reserved
= 0;
398 cpuc
->lbr_stack
.nr
= i
;
402 * Due to lack of segmentation in Linux the effective address (offset)
403 * is the same as the linear address, allowing us to merge the LIP and EIP
406 static void intel_pmu_lbr_read_64(struct cpu_hw_events
*cpuc
)
408 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
409 int lbr_format
= x86_pmu
.intel_cap
.lbr_format
;
410 u64 tos
= intel_pmu_lbr_tos();
414 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
415 unsigned long lbr_idx
= (tos
- i
) & mask
;
416 u64 from
, to
, mis
= 0, pred
= 0, in_tx
= 0, abort
= 0;
418 int lbr_flags
= lbr_desc
[lbr_format
];
420 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, from
);
421 rdmsrl(x86_pmu
.lbr_to
+ lbr_idx
, to
);
423 if (lbr_flags
& LBR_EIP_FLAGS
) {
424 mis
= !!(from
& LBR_FROM_FLAG_MISPRED
);
428 if (lbr_flags
& LBR_TSX
) {
429 in_tx
= !!(from
& LBR_FROM_FLAG_IN_TX
);
430 abort
= !!(from
& LBR_FROM_FLAG_ABORT
);
433 from
= (u64
)((((s64
)from
) << skip
) >> skip
);
436 * Some CPUs report duplicated abort records,
437 * with the second entry not having an abort bit set.
438 * Skip them here. This loop runs backwards,
439 * so we need to undo the previous record.
440 * If the abort just happened outside the window
441 * the extra entry cannot be removed.
443 if (abort
&& x86_pmu
.lbr_double_abort
&& out
> 0)
446 cpuc
->lbr_entries
[out
].from
= from
;
447 cpuc
->lbr_entries
[out
].to
= to
;
448 cpuc
->lbr_entries
[out
].mispred
= mis
;
449 cpuc
->lbr_entries
[out
].predicted
= pred
;
450 cpuc
->lbr_entries
[out
].in_tx
= in_tx
;
451 cpuc
->lbr_entries
[out
].abort
= abort
;
452 cpuc
->lbr_entries
[out
].reserved
= 0;
455 cpuc
->lbr_stack
.nr
= out
;
458 void intel_pmu_lbr_read(void)
460 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
462 if (!cpuc
->lbr_users
)
465 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
466 intel_pmu_lbr_read_32(cpuc
);
468 intel_pmu_lbr_read_64(cpuc
);
470 intel_pmu_lbr_filter(cpuc
);
475 * - in case there is no HW filter
476 * - in case the HW filter has errata or limitations
478 static int intel_pmu_setup_sw_lbr_filter(struct perf_event
*event
)
480 u64 br_type
= event
->attr
.branch_sample_type
;
483 if (br_type
& PERF_SAMPLE_BRANCH_USER
)
486 if (br_type
& PERF_SAMPLE_BRANCH_KERNEL
)
487 mask
|= X86_BR_KERNEL
;
489 /* we ignore BRANCH_HV here */
491 if (br_type
& PERF_SAMPLE_BRANCH_ANY
)
494 if (br_type
& PERF_SAMPLE_BRANCH_ANY_CALL
)
495 mask
|= X86_BR_ANY_CALL
;
497 if (br_type
& PERF_SAMPLE_BRANCH_ANY_RETURN
)
498 mask
|= X86_BR_RET
| X86_BR_IRET
| X86_BR_SYSRET
;
500 if (br_type
& PERF_SAMPLE_BRANCH_IND_CALL
)
501 mask
|= X86_BR_IND_CALL
;
503 if (br_type
& PERF_SAMPLE_BRANCH_ABORT_TX
)
504 mask
|= X86_BR_ABORT
;
506 if (br_type
& PERF_SAMPLE_BRANCH_IN_TX
)
507 mask
|= X86_BR_IN_TX
;
509 if (br_type
& PERF_SAMPLE_BRANCH_NO_TX
)
510 mask
|= X86_BR_NO_TX
;
512 if (br_type
& PERF_SAMPLE_BRANCH_COND
)
515 if (br_type
& PERF_SAMPLE_BRANCH_CALL_STACK
) {
516 if (!x86_pmu_has_lbr_callstack())
518 if (mask
& ~(X86_BR_USER
| X86_BR_KERNEL
))
520 mask
|= X86_BR_CALL
| X86_BR_IND_CALL
| X86_BR_RET
|
525 * stash actual user request into reg, it may
526 * be used by fixup code for some CPU
528 event
->hw
.branch_reg
.reg
= mask
;
533 * setup the HW LBR filter
534 * Used only when available, may not be enough to disambiguate
535 * all branches, may need the help of the SW filter
537 static int intel_pmu_setup_hw_lbr_filter(struct perf_event
*event
)
539 struct hw_perf_event_extra
*reg
;
540 u64 br_type
= event
->attr
.branch_sample_type
;
544 for (i
= 0; i
< PERF_SAMPLE_BRANCH_MAX_SHIFT
; i
++) {
545 if (!(br_type
& (1ULL << i
)))
548 v
= x86_pmu
.lbr_sel_map
[i
];
549 if (v
== LBR_NOT_SUPP
)
555 reg
= &event
->hw
.branch_reg
;
556 reg
->idx
= EXTRA_REG_LBR
;
559 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
560 * in suppress mode. So LBR_SELECT should be set to
561 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
563 reg
->config
= mask
^ x86_pmu
.lbr_sel_mask
;
568 int intel_pmu_setup_lbr_filter(struct perf_event
*event
)
579 * setup SW LBR filter
581 ret
= intel_pmu_setup_sw_lbr_filter(event
);
586 * setup HW LBR filter, if any
588 if (x86_pmu
.lbr_sel_map
)
589 ret
= intel_pmu_setup_hw_lbr_filter(event
);
595 * return the type of control flow change at address "from"
596 * intruction is not necessarily a branch (in case of interrupt).
598 * The branch type returned also includes the priv level of the
599 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
601 * If a branch type is unknown OR the instruction cannot be
602 * decoded (e.g., text page not present), then X86_BR_NONE is
605 static int branch_type(unsigned long from
, unsigned long to
, int abort
)
609 int bytes_read
, bytes_left
;
610 int ret
= X86_BR_NONE
;
611 int ext
, to_plm
, from_plm
;
612 u8 buf
[MAX_INSN_SIZE
];
615 to_plm
= kernel_ip(to
) ? X86_BR_KERNEL
: X86_BR_USER
;
616 from_plm
= kernel_ip(from
) ? X86_BR_KERNEL
: X86_BR_USER
;
619 * maybe zero if lbr did not fill up after a reset by the time
620 * we get a PMU interrupt
622 if (from
== 0 || to
== 0)
626 return X86_BR_ABORT
| to_plm
;
628 if (from_plm
== X86_BR_USER
) {
630 * can happen if measuring at the user level only
631 * and we interrupt in a kernel thread, e.g., idle.
636 /* may fail if text not present */
637 bytes_left
= copy_from_user_nmi(buf
, (void __user
*)from
,
639 bytes_read
= MAX_INSN_SIZE
- bytes_left
;
646 * The LBR logs any address in the IP, even if the IP just
647 * faulted. This means userspace can control the from address.
648 * Ensure we don't blindy read any address by validating it is
649 * a known text address.
651 if (kernel_text_address(from
)) {
654 * Assume we can get the maximum possible size
655 * when grabbing kernel data. This is not
656 * _strictly_ true since we could possibly be
657 * executing up next to a memory hole, but
658 * it is very unlikely to be a problem.
660 bytes_read
= MAX_INSN_SIZE
;
667 * decoder needs to know the ABI especially
668 * on 64-bit systems running 32-bit apps
671 is64
= kernel_ip((unsigned long)addr
) || !test_thread_flag(TIF_IA32
);
673 insn_init(&insn
, addr
, bytes_read
, is64
);
674 insn_get_opcode(&insn
);
675 if (!insn
.opcode
.got
)
678 switch (insn
.opcode
.bytes
[0]) {
680 switch (insn
.opcode
.bytes
[1]) {
681 case 0x05: /* syscall */
682 case 0x34: /* sysenter */
683 ret
= X86_BR_SYSCALL
;
685 case 0x07: /* sysret */
686 case 0x35: /* sysexit */
689 case 0x80 ... 0x8f: /* conditional */
696 case 0x70 ... 0x7f: /* conditional */
699 case 0xc2: /* near ret */
700 case 0xc3: /* near ret */
701 case 0xca: /* far ret */
702 case 0xcb: /* far ret */
705 case 0xcf: /* iret */
708 case 0xcc ... 0xce: /* int */
711 case 0xe8: /* call near rel */
712 insn_get_immediate(&insn
);
713 if (insn
.immediate1
.value
== 0) {
714 /* zero length call */
715 ret
= X86_BR_ZERO_CALL
;
718 case 0x9a: /* call far absolute */
721 case 0xe0 ... 0xe3: /* loop jmp */
724 case 0xe9 ... 0xeb: /* jmp */
727 case 0xff: /* call near absolute, call far absolute ind */
728 insn_get_modrm(&insn
);
729 ext
= (insn
.modrm
.bytes
[0] >> 3) & 0x7;
731 case 2: /* near ind call */
732 case 3: /* far ind call */
733 ret
= X86_BR_IND_CALL
;
745 * interrupts, traps, faults (and thus ring transition) may
746 * occur on any instructions. Thus, to classify them correctly,
747 * we need to first look at the from and to priv levels. If they
748 * are different and to is in the kernel, then it indicates
749 * a ring transition. If the from instruction is not a ring
750 * transition instr (syscall, systenter, int), then it means
751 * it was a irq, trap or fault.
753 * we have no way of detecting kernel to kernel faults.
755 if (from_plm
== X86_BR_USER
&& to_plm
== X86_BR_KERNEL
756 && ret
!= X86_BR_SYSCALL
&& ret
!= X86_BR_INT
)
760 * branch priv level determined by target as
761 * is done by HW when LBR_SELECT is implemented
763 if (ret
!= X86_BR_NONE
)
770 * implement actual branch filter based on user demand.
771 * Hardware may not exactly satisfy that request, thus
772 * we need to inspect opcodes. Mismatched branches are
773 * discarded. Therefore, the number of branches returned
774 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
777 intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
)
780 int br_sel
= cpuc
->br_sel
;
782 bool compress
= false;
784 /* if sampling all branches, then nothing to filter */
785 if ((br_sel
& X86_BR_ALL
) == X86_BR_ALL
)
788 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; i
++) {
790 from
= cpuc
->lbr_entries
[i
].from
;
791 to
= cpuc
->lbr_entries
[i
].to
;
793 type
= branch_type(from
, to
, cpuc
->lbr_entries
[i
].abort
);
794 if (type
!= X86_BR_NONE
&& (br_sel
& X86_BR_ANYTX
)) {
795 if (cpuc
->lbr_entries
[i
].in_tx
)
796 type
|= X86_BR_IN_TX
;
798 type
|= X86_BR_NO_TX
;
801 /* if type does not correspond, then discard */
802 if (type
== X86_BR_NONE
|| (br_sel
& type
) != type
) {
803 cpuc
->lbr_entries
[i
].from
= 0;
811 /* remove all entries with from=0 */
812 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; ) {
813 if (!cpuc
->lbr_entries
[i
].from
) {
815 while (++j
< cpuc
->lbr_stack
.nr
)
816 cpuc
->lbr_entries
[j
-1] = cpuc
->lbr_entries
[j
];
817 cpuc
->lbr_stack
.nr
--;
818 if (!cpuc
->lbr_entries
[i
].from
)
826 * Map interface branch filters onto LBR filters
828 static const int nhm_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
829 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
830 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
831 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
832 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
833 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_REL_JMP
834 | LBR_IND_JMP
| LBR_FAR
,
836 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
838 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] =
839 LBR_REL_CALL
| LBR_IND_CALL
| LBR_REL_JMP
| LBR_IND_JMP
| LBR_FAR
,
841 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
843 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
| LBR_IND_JMP
,
844 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
847 static const int snb_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
848 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
849 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
850 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
851 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
852 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
853 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
855 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
856 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
859 static const int hsw_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
860 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
861 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
862 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
863 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
864 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
865 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
867 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
868 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
869 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
870 | LBR_RETURN
| LBR_CALL_STACK
,
874 void __init
intel_pmu_lbr_init_core(void)
877 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
878 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
879 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
882 * SW branch filter usage:
883 * - compensate for lack of HW filter
885 pr_cont("4-deep LBR, ");
888 /* nehalem/westmere */
889 void __init
intel_pmu_lbr_init_nhm(void)
892 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
893 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
894 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
896 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
897 x86_pmu
.lbr_sel_map
= nhm_lbr_sel_map
;
900 * SW branch filter usage:
901 * - workaround LBR_SEL errata (see above)
902 * - support syscall, sysret capture.
903 * That requires LBR_FAR but that means far
904 * jmp need to be filtered out
906 pr_cont("16-deep LBR, ");
910 void __init
intel_pmu_lbr_init_snb(void)
913 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
914 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
915 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
917 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
918 x86_pmu
.lbr_sel_map
= snb_lbr_sel_map
;
921 * SW branch filter usage:
922 * - support syscall, sysret capture.
923 * That requires LBR_FAR but that means far
924 * jmp need to be filtered out
926 pr_cont("16-deep LBR, ");
930 void intel_pmu_lbr_init_hsw(void)
933 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
934 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
935 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
937 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
938 x86_pmu
.lbr_sel_map
= hsw_lbr_sel_map
;
940 pr_cont("16-deep LBR, ");
944 void __init
intel_pmu_lbr_init_atom(void)
947 * only models starting at stepping 10 seems
948 * to have an operational LBR which can freeze
951 if (boot_cpu_data
.x86_model
== 28
952 && boot_cpu_data
.x86_mask
< 10) {
953 pr_cont("LBR disabled due to erratum");
958 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
959 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
960 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
963 * SW branch filter usage:
964 * - compensate for lack of HW filter
966 pr_cont("8-deep LBR, ");