1 #include "perf_event_intel_uncore.h"
3 static struct intel_uncore_type
*empty_uncore
[] = { NULL
, };
4 static struct intel_uncore_type
**msr_uncores
= empty_uncore
;
5 static struct intel_uncore_type
**pci_uncores
= empty_uncore
;
6 /* pci bus to socket mapping */
7 static int pcibus_to_physid
[256] = { [0 ... 255] = -1, };
9 static struct pci_dev
*extra_pci_dev
[UNCORE_SOCKET_MAX
][UNCORE_EXTRA_PCI_DEV_MAX
];
11 static DEFINE_RAW_SPINLOCK(uncore_box_lock
);
13 /* mask of cpus that collect uncore events */
14 static cpumask_t uncore_cpu_mask
;
16 /* constraint for the fixed counter */
17 static struct event_constraint constraint_fixed
=
18 EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED
, ~0ULL);
19 static struct event_constraint constraint_empty
=
20 EVENT_CONSTRAINT(0, 0, 0);
22 #define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
25 DEFINE_UNCORE_FORMAT_ATTR(event
, event
, "config:0-7");
26 DEFINE_UNCORE_FORMAT_ATTR(event_ext
, event
, "config:0-7,21");
27 DEFINE_UNCORE_FORMAT_ATTR(umask
, umask
, "config:8-15");
28 DEFINE_UNCORE_FORMAT_ATTR(edge
, edge
, "config:18");
29 DEFINE_UNCORE_FORMAT_ATTR(tid_en
, tid_en
, "config:19");
30 DEFINE_UNCORE_FORMAT_ATTR(inv
, inv
, "config:23");
31 DEFINE_UNCORE_FORMAT_ATTR(cmask5
, cmask
, "config:24-28");
32 DEFINE_UNCORE_FORMAT_ATTR(cmask8
, cmask
, "config:24-31");
33 DEFINE_UNCORE_FORMAT_ATTR(thresh8
, thresh
, "config:24-31");
34 DEFINE_UNCORE_FORMAT_ATTR(thresh5
, thresh
, "config:24-28");
35 DEFINE_UNCORE_FORMAT_ATTR(occ_sel
, occ_sel
, "config:14-15");
36 DEFINE_UNCORE_FORMAT_ATTR(occ_invert
, occ_invert
, "config:30");
37 DEFINE_UNCORE_FORMAT_ATTR(occ_edge
, occ_edge
, "config:14-51");
38 DEFINE_UNCORE_FORMAT_ATTR(filter_tid
, filter_tid
, "config1:0-4");
39 DEFINE_UNCORE_FORMAT_ATTR(filter_link
, filter_link
, "config1:5-8");
40 DEFINE_UNCORE_FORMAT_ATTR(filter_nid
, filter_nid
, "config1:10-17");
41 DEFINE_UNCORE_FORMAT_ATTR(filter_nid2
, filter_nid
, "config1:32-47");
42 DEFINE_UNCORE_FORMAT_ATTR(filter_state
, filter_state
, "config1:18-22");
43 DEFINE_UNCORE_FORMAT_ATTR(filter_state2
, filter_state
, "config1:17-22");
44 DEFINE_UNCORE_FORMAT_ATTR(filter_opc
, filter_opc
, "config1:23-31");
45 DEFINE_UNCORE_FORMAT_ATTR(filter_opc2
, filter_opc
, "config1:52-60");
46 DEFINE_UNCORE_FORMAT_ATTR(filter_band0
, filter_band0
, "config1:0-7");
47 DEFINE_UNCORE_FORMAT_ATTR(filter_band1
, filter_band1
, "config1:8-15");
48 DEFINE_UNCORE_FORMAT_ATTR(filter_band2
, filter_band2
, "config1:16-23");
49 DEFINE_UNCORE_FORMAT_ATTR(filter_band3
, filter_band3
, "config1:24-31");
50 DEFINE_UNCORE_FORMAT_ATTR(match_rds
, match_rds
, "config1:48-51");
51 DEFINE_UNCORE_FORMAT_ATTR(match_rnid30
, match_rnid30
, "config1:32-35");
52 DEFINE_UNCORE_FORMAT_ATTR(match_rnid4
, match_rnid4
, "config1:31");
53 DEFINE_UNCORE_FORMAT_ATTR(match_dnid
, match_dnid
, "config1:13-17");
54 DEFINE_UNCORE_FORMAT_ATTR(match_mc
, match_mc
, "config1:9-12");
55 DEFINE_UNCORE_FORMAT_ATTR(match_opc
, match_opc
, "config1:5-8");
56 DEFINE_UNCORE_FORMAT_ATTR(match_vnw
, match_vnw
, "config1:3-4");
57 DEFINE_UNCORE_FORMAT_ATTR(match0
, match0
, "config1:0-31");
58 DEFINE_UNCORE_FORMAT_ATTR(match1
, match1
, "config1:32-63");
59 DEFINE_UNCORE_FORMAT_ATTR(mask_rds
, mask_rds
, "config2:48-51");
60 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid30
, mask_rnid30
, "config2:32-35");
61 DEFINE_UNCORE_FORMAT_ATTR(mask_rnid4
, mask_rnid4
, "config2:31");
62 DEFINE_UNCORE_FORMAT_ATTR(mask_dnid
, mask_dnid
, "config2:13-17");
63 DEFINE_UNCORE_FORMAT_ATTR(mask_mc
, mask_mc
, "config2:9-12");
64 DEFINE_UNCORE_FORMAT_ATTR(mask_opc
, mask_opc
, "config2:5-8");
65 DEFINE_UNCORE_FORMAT_ATTR(mask_vnw
, mask_vnw
, "config2:3-4");
66 DEFINE_UNCORE_FORMAT_ATTR(mask0
, mask0
, "config2:0-31");
67 DEFINE_UNCORE_FORMAT_ATTR(mask1
, mask1
, "config2:32-63");
69 static u64
uncore_msr_read_counter(struct intel_uncore_box
*box
, struct perf_event
*event
)
73 rdmsrl(event
->hw
.event_base
, count
);
79 * generic get constraint function for shared match/mask registers.
81 static struct event_constraint
*
82 uncore_get_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
84 struct intel_uncore_extra_reg
*er
;
85 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
86 struct hw_perf_event_extra
*reg2
= &event
->hw
.branch_reg
;
91 * reg->alloc can be set due to existing state, so for fake box we
92 * need to ignore this, otherwise we might fail to allocate proper
93 * fake state for this extra reg constraint.
95 if (reg1
->idx
== EXTRA_REG_NONE
||
96 (!uncore_box_is_fake(box
) && reg1
->alloc
))
99 er
= &box
->shared_regs
[reg1
->idx
];
100 raw_spin_lock_irqsave(&er
->lock
, flags
);
101 if (!atomic_read(&er
->ref
) ||
102 (er
->config1
== reg1
->config
&& er
->config2
== reg2
->config
)) {
103 atomic_inc(&er
->ref
);
104 er
->config1
= reg1
->config
;
105 er
->config2
= reg2
->config
;
108 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
111 if (!uncore_box_is_fake(box
))
116 return &constraint_empty
;
119 static void uncore_put_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
121 struct intel_uncore_extra_reg
*er
;
122 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
125 * Only put constraint if extra reg was actually allocated. Also
126 * takes care of event which do not use an extra shared reg.
128 * Also, if this is a fake box we shouldn't touch any event state
129 * (reg->alloc) and we don't care about leaving inconsistent box
130 * state either since it will be thrown out.
132 if (uncore_box_is_fake(box
) || !reg1
->alloc
)
135 er
= &box
->shared_regs
[reg1
->idx
];
136 atomic_dec(&er
->ref
);
140 static u64
uncore_shared_reg_config(struct intel_uncore_box
*box
, int idx
)
142 struct intel_uncore_extra_reg
*er
;
146 er
= &box
->shared_regs
[idx
];
148 raw_spin_lock_irqsave(&er
->lock
, flags
);
150 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
155 /* Sandy Bridge-EP uncore support */
156 static struct intel_uncore_type snbep_uncore_cbox
;
157 static struct intel_uncore_type snbep_uncore_pcu
;
159 static void snbep_uncore_pci_disable_box(struct intel_uncore_box
*box
)
161 struct pci_dev
*pdev
= box
->pci_dev
;
162 int box_ctl
= uncore_pci_box_ctl(box
);
165 if (!pci_read_config_dword(pdev
, box_ctl
, &config
)) {
166 config
|= SNBEP_PMON_BOX_CTL_FRZ
;
167 pci_write_config_dword(pdev
, box_ctl
, config
);
171 static void snbep_uncore_pci_enable_box(struct intel_uncore_box
*box
)
173 struct pci_dev
*pdev
= box
->pci_dev
;
174 int box_ctl
= uncore_pci_box_ctl(box
);
177 if (!pci_read_config_dword(pdev
, box_ctl
, &config
)) {
178 config
&= ~SNBEP_PMON_BOX_CTL_FRZ
;
179 pci_write_config_dword(pdev
, box_ctl
, config
);
183 static void snbep_uncore_pci_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
185 struct pci_dev
*pdev
= box
->pci_dev
;
186 struct hw_perf_event
*hwc
= &event
->hw
;
188 pci_write_config_dword(pdev
, hwc
->config_base
, hwc
->config
| SNBEP_PMON_CTL_EN
);
191 static void snbep_uncore_pci_disable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
193 struct pci_dev
*pdev
= box
->pci_dev
;
194 struct hw_perf_event
*hwc
= &event
->hw
;
196 pci_write_config_dword(pdev
, hwc
->config_base
, hwc
->config
);
199 static u64
snbep_uncore_pci_read_counter(struct intel_uncore_box
*box
, struct perf_event
*event
)
201 struct pci_dev
*pdev
= box
->pci_dev
;
202 struct hw_perf_event
*hwc
= &event
->hw
;
205 pci_read_config_dword(pdev
, hwc
->event_base
, (u32
*)&count
);
206 pci_read_config_dword(pdev
, hwc
->event_base
+ 4, (u32
*)&count
+ 1);
211 static void snbep_uncore_pci_init_box(struct intel_uncore_box
*box
)
213 struct pci_dev
*pdev
= box
->pci_dev
;
215 pci_write_config_dword(pdev
, SNBEP_PCI_PMON_BOX_CTL
, SNBEP_PMON_BOX_CTL_INT
);
218 static void snbep_uncore_msr_disable_box(struct intel_uncore_box
*box
)
223 msr
= uncore_msr_box_ctl(box
);
226 config
|= SNBEP_PMON_BOX_CTL_FRZ
;
231 static void snbep_uncore_msr_enable_box(struct intel_uncore_box
*box
)
236 msr
= uncore_msr_box_ctl(box
);
239 config
&= ~SNBEP_PMON_BOX_CTL_FRZ
;
244 static void snbep_uncore_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
246 struct hw_perf_event
*hwc
= &event
->hw
;
247 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
249 if (reg1
->idx
!= EXTRA_REG_NONE
)
250 wrmsrl(reg1
->reg
, uncore_shared_reg_config(box
, 0));
252 wrmsrl(hwc
->config_base
, hwc
->config
| SNBEP_PMON_CTL_EN
);
255 static void snbep_uncore_msr_disable_event(struct intel_uncore_box
*box
,
256 struct perf_event
*event
)
258 struct hw_perf_event
*hwc
= &event
->hw
;
260 wrmsrl(hwc
->config_base
, hwc
->config
);
263 static void snbep_uncore_msr_init_box(struct intel_uncore_box
*box
)
265 unsigned msr
= uncore_msr_box_ctl(box
);
268 wrmsrl(msr
, SNBEP_PMON_BOX_CTL_INT
);
271 static struct attribute
*snbep_uncore_formats_attr
[] = {
272 &format_attr_event
.attr
,
273 &format_attr_umask
.attr
,
274 &format_attr_edge
.attr
,
275 &format_attr_inv
.attr
,
276 &format_attr_thresh8
.attr
,
280 static struct attribute
*snbep_uncore_ubox_formats_attr
[] = {
281 &format_attr_event
.attr
,
282 &format_attr_umask
.attr
,
283 &format_attr_edge
.attr
,
284 &format_attr_inv
.attr
,
285 &format_attr_thresh5
.attr
,
289 static struct attribute
*snbep_uncore_cbox_formats_attr
[] = {
290 &format_attr_event
.attr
,
291 &format_attr_umask
.attr
,
292 &format_attr_edge
.attr
,
293 &format_attr_tid_en
.attr
,
294 &format_attr_inv
.attr
,
295 &format_attr_thresh8
.attr
,
296 &format_attr_filter_tid
.attr
,
297 &format_attr_filter_nid
.attr
,
298 &format_attr_filter_state
.attr
,
299 &format_attr_filter_opc
.attr
,
303 static struct attribute
*snbep_uncore_pcu_formats_attr
[] = {
304 &format_attr_event_ext
.attr
,
305 &format_attr_occ_sel
.attr
,
306 &format_attr_edge
.attr
,
307 &format_attr_inv
.attr
,
308 &format_attr_thresh5
.attr
,
309 &format_attr_occ_invert
.attr
,
310 &format_attr_occ_edge
.attr
,
311 &format_attr_filter_band0
.attr
,
312 &format_attr_filter_band1
.attr
,
313 &format_attr_filter_band2
.attr
,
314 &format_attr_filter_band3
.attr
,
318 static struct attribute
*snbep_uncore_qpi_formats_attr
[] = {
319 &format_attr_event_ext
.attr
,
320 &format_attr_umask
.attr
,
321 &format_attr_edge
.attr
,
322 &format_attr_inv
.attr
,
323 &format_attr_thresh8
.attr
,
324 &format_attr_match_rds
.attr
,
325 &format_attr_match_rnid30
.attr
,
326 &format_attr_match_rnid4
.attr
,
327 &format_attr_match_dnid
.attr
,
328 &format_attr_match_mc
.attr
,
329 &format_attr_match_opc
.attr
,
330 &format_attr_match_vnw
.attr
,
331 &format_attr_match0
.attr
,
332 &format_attr_match1
.attr
,
333 &format_attr_mask_rds
.attr
,
334 &format_attr_mask_rnid30
.attr
,
335 &format_attr_mask_rnid4
.attr
,
336 &format_attr_mask_dnid
.attr
,
337 &format_attr_mask_mc
.attr
,
338 &format_attr_mask_opc
.attr
,
339 &format_attr_mask_vnw
.attr
,
340 &format_attr_mask0
.attr
,
341 &format_attr_mask1
.attr
,
345 static struct uncore_event_desc snbep_uncore_imc_events
[] = {
346 INTEL_UNCORE_EVENT_DESC(clockticks
, "event=0xff,umask=0x00"),
347 INTEL_UNCORE_EVENT_DESC(cas_count_read
, "event=0x04,umask=0x03"),
348 INTEL_UNCORE_EVENT_DESC(cas_count_write
, "event=0x04,umask=0x0c"),
349 { /* end: all zeroes */ },
352 static struct uncore_event_desc snbep_uncore_qpi_events
[] = {
353 INTEL_UNCORE_EVENT_DESC(clockticks
, "event=0x14"),
354 INTEL_UNCORE_EVENT_DESC(txl_flits_active
, "event=0x00,umask=0x06"),
355 INTEL_UNCORE_EVENT_DESC(drs_data
, "event=0x102,umask=0x08"),
356 INTEL_UNCORE_EVENT_DESC(ncb_data
, "event=0x103,umask=0x04"),
357 { /* end: all zeroes */ },
360 static struct attribute_group snbep_uncore_format_group
= {
362 .attrs
= snbep_uncore_formats_attr
,
365 static struct attribute_group snbep_uncore_ubox_format_group
= {
367 .attrs
= snbep_uncore_ubox_formats_attr
,
370 static struct attribute_group snbep_uncore_cbox_format_group
= {
372 .attrs
= snbep_uncore_cbox_formats_attr
,
375 static struct attribute_group snbep_uncore_pcu_format_group
= {
377 .attrs
= snbep_uncore_pcu_formats_attr
,
380 static struct attribute_group snbep_uncore_qpi_format_group
= {
382 .attrs
= snbep_uncore_qpi_formats_attr
,
385 #define SNBEP_UNCORE_MSR_OPS_COMMON_INIT() \
386 .init_box = snbep_uncore_msr_init_box, \
387 .disable_box = snbep_uncore_msr_disable_box, \
388 .enable_box = snbep_uncore_msr_enable_box, \
389 .disable_event = snbep_uncore_msr_disable_event, \
390 .enable_event = snbep_uncore_msr_enable_event, \
391 .read_counter = uncore_msr_read_counter
393 static struct intel_uncore_ops snbep_uncore_msr_ops
= {
394 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
397 #define SNBEP_UNCORE_PCI_OPS_COMMON_INIT() \
398 .init_box = snbep_uncore_pci_init_box, \
399 .disable_box = snbep_uncore_pci_disable_box, \
400 .enable_box = snbep_uncore_pci_enable_box, \
401 .disable_event = snbep_uncore_pci_disable_event, \
402 .read_counter = snbep_uncore_pci_read_counter
404 static struct intel_uncore_ops snbep_uncore_pci_ops
= {
405 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
406 .enable_event
= snbep_uncore_pci_enable_event
, \
409 static struct event_constraint snbep_uncore_cbox_constraints
[] = {
410 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
411 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
412 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
413 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
414 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
415 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
416 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
417 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
418 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
419 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
420 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
421 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
422 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
423 EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff),
424 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
425 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
426 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
427 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
428 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
429 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
430 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
431 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
432 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
433 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
434 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
435 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
439 static struct event_constraint snbep_uncore_r2pcie_constraints
[] = {
440 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
441 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
442 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
443 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
444 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
445 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
446 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
447 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
448 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
449 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
453 static struct event_constraint snbep_uncore_r3qpi_constraints
[] = {
454 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
455 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
456 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
457 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
458 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
459 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
460 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
461 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
462 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
463 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
464 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
465 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
466 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
467 UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
468 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
469 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
470 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
471 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
472 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
473 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
474 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
475 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
476 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
477 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
478 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
479 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
480 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
481 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
485 static struct intel_uncore_type snbep_uncore_ubox
= {
490 .fixed_ctr_bits
= 48,
491 .perf_ctr
= SNBEP_U_MSR_PMON_CTR0
,
492 .event_ctl
= SNBEP_U_MSR_PMON_CTL0
,
493 .event_mask
= SNBEP_U_MSR_PMON_RAW_EVENT_MASK
,
494 .fixed_ctr
= SNBEP_U_MSR_PMON_UCLK_FIXED_CTR
,
495 .fixed_ctl
= SNBEP_U_MSR_PMON_UCLK_FIXED_CTL
,
496 .ops
= &snbep_uncore_msr_ops
,
497 .format_group
= &snbep_uncore_ubox_format_group
,
500 static struct extra_reg snbep_uncore_cbox_extra_regs
[] = {
501 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN
,
502 SNBEP_CBO_PMON_CTL_TID_EN
, 0x1),
503 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
504 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
505 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
506 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
507 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
508 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
509 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xc),
510 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xc),
511 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
512 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
513 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
514 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
515 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
516 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
517 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xc),
518 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xc),
519 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
520 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
521 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
522 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
526 static void snbep_cbox_put_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
528 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
529 struct intel_uncore_extra_reg
*er
= &box
->shared_regs
[0];
532 if (uncore_box_is_fake(box
))
535 for (i
= 0; i
< 5; i
++) {
536 if (reg1
->alloc
& (0x1 << i
))
537 atomic_sub(1 << (i
* 6), &er
->ref
);
542 static struct event_constraint
*
543 __snbep_cbox_get_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
,
544 u64 (*cbox_filter_mask
)(int fields
))
546 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
547 struct intel_uncore_extra_reg
*er
= &box
->shared_regs
[0];
552 if (reg1
->idx
== EXTRA_REG_NONE
)
555 raw_spin_lock_irqsave(&er
->lock
, flags
);
556 for (i
= 0; i
< 5; i
++) {
557 if (!(reg1
->idx
& (0x1 << i
)))
559 if (!uncore_box_is_fake(box
) && (reg1
->alloc
& (0x1 << i
)))
562 mask
= cbox_filter_mask(0x1 << i
);
563 if (!__BITS_VALUE(atomic_read(&er
->ref
), i
, 6) ||
564 !((reg1
->config
^ er
->config
) & mask
)) {
565 atomic_add(1 << (i
* 6), &er
->ref
);
567 er
->config
|= reg1
->config
& mask
;
573 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
577 if (!uncore_box_is_fake(box
))
578 reg1
->alloc
|= alloc
;
582 for (; i
>= 0; i
--) {
583 if (alloc
& (0x1 << i
))
584 atomic_sub(1 << (i
* 6), &er
->ref
);
586 return &constraint_empty
;
589 static u64
snbep_cbox_filter_mask(int fields
)
594 mask
|= SNBEP_CB0_MSR_PMON_BOX_FILTER_TID
;
596 mask
|= SNBEP_CB0_MSR_PMON_BOX_FILTER_NID
;
598 mask
|= SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE
;
600 mask
|= SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC
;
605 static struct event_constraint
*
606 snbep_cbox_get_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
608 return __snbep_cbox_get_constraint(box
, event
, snbep_cbox_filter_mask
);
611 static int snbep_cbox_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
613 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
614 struct extra_reg
*er
;
617 for (er
= snbep_uncore_cbox_extra_regs
; er
->msr
; er
++) {
618 if (er
->event
!= (event
->hw
.config
& er
->config_mask
))
624 reg1
->reg
= SNBEP_C0_MSR_PMON_BOX_FILTER
+
625 SNBEP_CBO_MSR_OFFSET
* box
->pmu
->pmu_idx
;
626 reg1
->config
= event
->attr
.config1
& snbep_cbox_filter_mask(idx
);
632 static struct intel_uncore_ops snbep_uncore_cbox_ops
= {
633 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
634 .hw_config
= snbep_cbox_hw_config
,
635 .get_constraint
= snbep_cbox_get_constraint
,
636 .put_constraint
= snbep_cbox_put_constraint
,
639 static struct intel_uncore_type snbep_uncore_cbox
= {
644 .event_ctl
= SNBEP_C0_MSR_PMON_CTL0
,
645 .perf_ctr
= SNBEP_C0_MSR_PMON_CTR0
,
646 .event_mask
= SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK
,
647 .box_ctl
= SNBEP_C0_MSR_PMON_BOX_CTL
,
648 .msr_offset
= SNBEP_CBO_MSR_OFFSET
,
649 .num_shared_regs
= 1,
650 .constraints
= snbep_uncore_cbox_constraints
,
651 .ops
= &snbep_uncore_cbox_ops
,
652 .format_group
= &snbep_uncore_cbox_format_group
,
655 static u64
snbep_pcu_alter_er(struct perf_event
*event
, int new_idx
, bool modify
)
657 struct hw_perf_event
*hwc
= &event
->hw
;
658 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
659 u64 config
= reg1
->config
;
661 if (new_idx
> reg1
->idx
)
662 config
<<= 8 * (new_idx
- reg1
->idx
);
664 config
>>= 8 * (reg1
->idx
- new_idx
);
667 hwc
->config
+= new_idx
- reg1
->idx
;
668 reg1
->config
= config
;
674 static struct event_constraint
*
675 snbep_pcu_get_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
677 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
678 struct intel_uncore_extra_reg
*er
= &box
->shared_regs
[0];
681 u64 mask
, config1
= reg1
->config
;
684 if (reg1
->idx
== EXTRA_REG_NONE
||
685 (!uncore_box_is_fake(box
) && reg1
->alloc
))
688 mask
= 0xffULL
<< (idx
* 8);
689 raw_spin_lock_irqsave(&er
->lock
, flags
);
690 if (!__BITS_VALUE(atomic_read(&er
->ref
), idx
, 8) ||
691 !((config1
^ er
->config
) & mask
)) {
692 atomic_add(1 << (idx
* 8), &er
->ref
);
694 er
->config
|= config1
& mask
;
697 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
701 if (idx
!= reg1
->idx
) {
702 config1
= snbep_pcu_alter_er(event
, idx
, false);
705 return &constraint_empty
;
708 if (!uncore_box_is_fake(box
)) {
709 if (idx
!= reg1
->idx
)
710 snbep_pcu_alter_er(event
, idx
, true);
716 static void snbep_pcu_put_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
718 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
719 struct intel_uncore_extra_reg
*er
= &box
->shared_regs
[0];
721 if (uncore_box_is_fake(box
) || !reg1
->alloc
)
724 atomic_sub(1 << (reg1
->idx
* 8), &er
->ref
);
728 static int snbep_pcu_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
730 struct hw_perf_event
*hwc
= &event
->hw
;
731 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
732 int ev_sel
= hwc
->config
& SNBEP_PMON_CTL_EV_SEL_MASK
;
734 if (ev_sel
>= 0xb && ev_sel
<= 0xe) {
735 reg1
->reg
= SNBEP_PCU_MSR_PMON_BOX_FILTER
;
736 reg1
->idx
= ev_sel
- 0xb;
737 reg1
->config
= event
->attr
.config1
& (0xff << reg1
->idx
);
742 static struct intel_uncore_ops snbep_uncore_pcu_ops
= {
743 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
744 .hw_config
= snbep_pcu_hw_config
,
745 .get_constraint
= snbep_pcu_get_constraint
,
746 .put_constraint
= snbep_pcu_put_constraint
,
749 static struct intel_uncore_type snbep_uncore_pcu
= {
754 .perf_ctr
= SNBEP_PCU_MSR_PMON_CTR0
,
755 .event_ctl
= SNBEP_PCU_MSR_PMON_CTL0
,
756 .event_mask
= SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK
,
757 .box_ctl
= SNBEP_PCU_MSR_PMON_BOX_CTL
,
758 .num_shared_regs
= 1,
759 .ops
= &snbep_uncore_pcu_ops
,
760 .format_group
= &snbep_uncore_pcu_format_group
,
763 static struct intel_uncore_type
*snbep_msr_uncores
[] = {
771 SNBEP_PCI_QPI_PORT0_FILTER
,
772 SNBEP_PCI_QPI_PORT1_FILTER
,
775 static int snbep_qpi_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
777 struct hw_perf_event
*hwc
= &event
->hw
;
778 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
779 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
781 if ((hwc
->config
& SNBEP_PMON_CTL_EV_SEL_MASK
) == 0x38) {
783 reg1
->reg
= SNBEP_Q_Py_PCI_PMON_PKT_MATCH0
;
784 reg1
->config
= event
->attr
.config1
;
785 reg2
->reg
= SNBEP_Q_Py_PCI_PMON_PKT_MASK0
;
786 reg2
->config
= event
->attr
.config2
;
791 static void snbep_qpi_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
793 struct pci_dev
*pdev
= box
->pci_dev
;
794 struct hw_perf_event
*hwc
= &event
->hw
;
795 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
796 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
798 if (reg1
->idx
!= EXTRA_REG_NONE
) {
799 int idx
= box
->pmu
->pmu_idx
+ SNBEP_PCI_QPI_PORT0_FILTER
;
800 struct pci_dev
*filter_pdev
= extra_pci_dev
[box
->phys_id
][idx
];
801 WARN_ON_ONCE(!filter_pdev
);
803 pci_write_config_dword(filter_pdev
, reg1
->reg
,
805 pci_write_config_dword(filter_pdev
, reg1
->reg
+ 4,
806 (u32
)(reg1
->config
>> 32));
807 pci_write_config_dword(filter_pdev
, reg2
->reg
,
809 pci_write_config_dword(filter_pdev
, reg2
->reg
+ 4,
810 (u32
)(reg2
->config
>> 32));
814 pci_write_config_dword(pdev
, hwc
->config_base
, hwc
->config
| SNBEP_PMON_CTL_EN
);
817 static struct intel_uncore_ops snbep_uncore_qpi_ops
= {
818 SNBEP_UNCORE_PCI_OPS_COMMON_INIT(),
819 .enable_event
= snbep_qpi_enable_event
,
820 .hw_config
= snbep_qpi_hw_config
,
821 .get_constraint
= uncore_get_constraint
,
822 .put_constraint
= uncore_put_constraint
,
825 #define SNBEP_UNCORE_PCI_COMMON_INIT() \
826 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
827 .event_ctl = SNBEP_PCI_PMON_CTL0, \
828 .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \
829 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
830 .ops = &snbep_uncore_pci_ops, \
831 .format_group = &snbep_uncore_format_group
833 static struct intel_uncore_type snbep_uncore_ha
= {
838 SNBEP_UNCORE_PCI_COMMON_INIT(),
841 static struct intel_uncore_type snbep_uncore_imc
= {
846 .fixed_ctr_bits
= 48,
847 .fixed_ctr
= SNBEP_MC_CHy_PCI_PMON_FIXED_CTR
,
848 .fixed_ctl
= SNBEP_MC_CHy_PCI_PMON_FIXED_CTL
,
849 .event_descs
= snbep_uncore_imc_events
,
850 SNBEP_UNCORE_PCI_COMMON_INIT(),
853 static struct intel_uncore_type snbep_uncore_qpi
= {
858 .perf_ctr
= SNBEP_PCI_PMON_CTR0
,
859 .event_ctl
= SNBEP_PCI_PMON_CTL0
,
860 .event_mask
= SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK
,
861 .box_ctl
= SNBEP_PCI_PMON_BOX_CTL
,
862 .num_shared_regs
= 1,
863 .ops
= &snbep_uncore_qpi_ops
,
864 .event_descs
= snbep_uncore_qpi_events
,
865 .format_group
= &snbep_uncore_qpi_format_group
,
869 static struct intel_uncore_type snbep_uncore_r2pcie
= {
874 .constraints
= snbep_uncore_r2pcie_constraints
,
875 SNBEP_UNCORE_PCI_COMMON_INIT(),
878 static struct intel_uncore_type snbep_uncore_r3qpi
= {
883 .constraints
= snbep_uncore_r3qpi_constraints
,
884 SNBEP_UNCORE_PCI_COMMON_INIT(),
889 SNBEP_PCI_UNCORE_IMC
,
890 SNBEP_PCI_UNCORE_QPI
,
891 SNBEP_PCI_UNCORE_R2PCIE
,
892 SNBEP_PCI_UNCORE_R3QPI
,
895 static struct intel_uncore_type
*snbep_pci_uncores
[] = {
896 [SNBEP_PCI_UNCORE_HA
] = &snbep_uncore_ha
,
897 [SNBEP_PCI_UNCORE_IMC
] = &snbep_uncore_imc
,
898 [SNBEP_PCI_UNCORE_QPI
] = &snbep_uncore_qpi
,
899 [SNBEP_PCI_UNCORE_R2PCIE
] = &snbep_uncore_r2pcie
,
900 [SNBEP_PCI_UNCORE_R3QPI
] = &snbep_uncore_r3qpi
,
904 static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids
) = {
906 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_HA
),
907 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA
, 0),
910 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_IMC0
),
911 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC
, 0),
914 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_IMC1
),
915 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC
, 1),
918 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_IMC2
),
919 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC
, 2),
922 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_IMC3
),
923 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC
, 3),
926 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_QPI0
),
927 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI
, 0),
930 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_QPI1
),
931 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI
, 1),
934 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_R2PCIE
),
935 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE
, 0),
938 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_R3QPI0
),
939 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI
, 0),
942 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_UNC_R3QPI1
),
943 .driver_data
= UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI
, 1),
945 { /* QPI Port 0 filter */
946 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x3c86),
947 .driver_data
= UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV
,
948 SNBEP_PCI_QPI_PORT0_FILTER
),
950 { /* QPI Port 0 filter */
951 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x3c96),
952 .driver_data
= UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV
,
953 SNBEP_PCI_QPI_PORT1_FILTER
),
955 { /* end: all zeroes */ }
958 static struct pci_driver snbep_uncore_pci_driver
= {
959 .name
= "snbep_uncore",
960 .id_table
= snbep_uncore_pci_ids
,
964 * build pci bus to socket mapping
966 static int snbep_pci2phy_map_init(int devid
)
968 struct pci_dev
*ubox_dev
= NULL
;
974 /* find the UBOX device */
975 ubox_dev
= pci_get_device(PCI_VENDOR_ID_INTEL
, devid
, ubox_dev
);
978 bus
= ubox_dev
->bus
->number
;
979 /* get the Node ID of the local register */
980 err
= pci_read_config_dword(ubox_dev
, 0x40, &config
);
984 /* get the Node ID mapping */
985 err
= pci_read_config_dword(ubox_dev
, 0x54, &config
);
989 * every three bits in the Node ID mapping register maps
990 * to a particular node.
992 for (i
= 0; i
< 8; i
++) {
993 if (nodeid
== ((config
>> (3 * i
)) & 0x7)) {
994 pcibus_to_physid
[bus
] = i
;
1002 * For PCI bus with no UBOX device, find the next bus
1003 * that has UBOX device and use its mapping.
1006 for (bus
= 255; bus
>= 0; bus
--) {
1007 if (pcibus_to_physid
[bus
] >= 0)
1008 i
= pcibus_to_physid
[bus
];
1010 pcibus_to_physid
[bus
] = i
;
1015 pci_dev_put(ubox_dev
);
1017 return err
? pcibios_err_to_errno(err
) : 0;
1019 /* end of Sandy Bridge-EP uncore support */
1021 /* IvyTown uncore support */
1022 static void ivt_uncore_msr_init_box(struct intel_uncore_box
*box
)
1024 unsigned msr
= uncore_msr_box_ctl(box
);
1026 wrmsrl(msr
, IVT_PMON_BOX_CTL_INT
);
1029 static void ivt_uncore_pci_init_box(struct intel_uncore_box
*box
)
1031 struct pci_dev
*pdev
= box
->pci_dev
;
1033 pci_write_config_dword(pdev
, SNBEP_PCI_PMON_BOX_CTL
, IVT_PMON_BOX_CTL_INT
);
1036 #define IVT_UNCORE_MSR_OPS_COMMON_INIT() \
1037 .init_box = ivt_uncore_msr_init_box, \
1038 .disable_box = snbep_uncore_msr_disable_box, \
1039 .enable_box = snbep_uncore_msr_enable_box, \
1040 .disable_event = snbep_uncore_msr_disable_event, \
1041 .enable_event = snbep_uncore_msr_enable_event, \
1042 .read_counter = uncore_msr_read_counter
1044 static struct intel_uncore_ops ivt_uncore_msr_ops
= {
1045 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
1048 static struct intel_uncore_ops ivt_uncore_pci_ops
= {
1049 .init_box
= ivt_uncore_pci_init_box
,
1050 .disable_box
= snbep_uncore_pci_disable_box
,
1051 .enable_box
= snbep_uncore_pci_enable_box
,
1052 .disable_event
= snbep_uncore_pci_disable_event
,
1053 .enable_event
= snbep_uncore_pci_enable_event
,
1054 .read_counter
= snbep_uncore_pci_read_counter
,
1057 #define IVT_UNCORE_PCI_COMMON_INIT() \
1058 .perf_ctr = SNBEP_PCI_PMON_CTR0, \
1059 .event_ctl = SNBEP_PCI_PMON_CTL0, \
1060 .event_mask = IVT_PMON_RAW_EVENT_MASK, \
1061 .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \
1062 .ops = &ivt_uncore_pci_ops, \
1063 .format_group = &ivt_uncore_format_group
1065 static struct attribute
*ivt_uncore_formats_attr
[] = {
1066 &format_attr_event
.attr
,
1067 &format_attr_umask
.attr
,
1068 &format_attr_edge
.attr
,
1069 &format_attr_inv
.attr
,
1070 &format_attr_thresh8
.attr
,
1074 static struct attribute
*ivt_uncore_ubox_formats_attr
[] = {
1075 &format_attr_event
.attr
,
1076 &format_attr_umask
.attr
,
1077 &format_attr_edge
.attr
,
1078 &format_attr_inv
.attr
,
1079 &format_attr_thresh5
.attr
,
1083 static struct attribute
*ivt_uncore_cbox_formats_attr
[] = {
1084 &format_attr_event
.attr
,
1085 &format_attr_umask
.attr
,
1086 &format_attr_edge
.attr
,
1087 &format_attr_tid_en
.attr
,
1088 &format_attr_thresh8
.attr
,
1089 &format_attr_filter_tid
.attr
,
1090 &format_attr_filter_link
.attr
,
1091 &format_attr_filter_state2
.attr
,
1092 &format_attr_filter_nid2
.attr
,
1093 &format_attr_filter_opc2
.attr
,
1097 static struct attribute
*ivt_uncore_pcu_formats_attr
[] = {
1098 &format_attr_event_ext
.attr
,
1099 &format_attr_occ_sel
.attr
,
1100 &format_attr_edge
.attr
,
1101 &format_attr_thresh5
.attr
,
1102 &format_attr_occ_invert
.attr
,
1103 &format_attr_occ_edge
.attr
,
1104 &format_attr_filter_band0
.attr
,
1105 &format_attr_filter_band1
.attr
,
1106 &format_attr_filter_band2
.attr
,
1107 &format_attr_filter_band3
.attr
,
1111 static struct attribute
*ivt_uncore_qpi_formats_attr
[] = {
1112 &format_attr_event_ext
.attr
,
1113 &format_attr_umask
.attr
,
1114 &format_attr_edge
.attr
,
1115 &format_attr_thresh8
.attr
,
1116 &format_attr_match_rds
.attr
,
1117 &format_attr_match_rnid30
.attr
,
1118 &format_attr_match_rnid4
.attr
,
1119 &format_attr_match_dnid
.attr
,
1120 &format_attr_match_mc
.attr
,
1121 &format_attr_match_opc
.attr
,
1122 &format_attr_match_vnw
.attr
,
1123 &format_attr_match0
.attr
,
1124 &format_attr_match1
.attr
,
1125 &format_attr_mask_rds
.attr
,
1126 &format_attr_mask_rnid30
.attr
,
1127 &format_attr_mask_rnid4
.attr
,
1128 &format_attr_mask_dnid
.attr
,
1129 &format_attr_mask_mc
.attr
,
1130 &format_attr_mask_opc
.attr
,
1131 &format_attr_mask_vnw
.attr
,
1132 &format_attr_mask0
.attr
,
1133 &format_attr_mask1
.attr
,
1137 static struct attribute_group ivt_uncore_format_group
= {
1139 .attrs
= ivt_uncore_formats_attr
,
1142 static struct attribute_group ivt_uncore_ubox_format_group
= {
1144 .attrs
= ivt_uncore_ubox_formats_attr
,
1147 static struct attribute_group ivt_uncore_cbox_format_group
= {
1149 .attrs
= ivt_uncore_cbox_formats_attr
,
1152 static struct attribute_group ivt_uncore_pcu_format_group
= {
1154 .attrs
= ivt_uncore_pcu_formats_attr
,
1157 static struct attribute_group ivt_uncore_qpi_format_group
= {
1159 .attrs
= ivt_uncore_qpi_formats_attr
,
1162 static struct intel_uncore_type ivt_uncore_ubox
= {
1166 .perf_ctr_bits
= 44,
1167 .fixed_ctr_bits
= 48,
1168 .perf_ctr
= SNBEP_U_MSR_PMON_CTR0
,
1169 .event_ctl
= SNBEP_U_MSR_PMON_CTL0
,
1170 .event_mask
= IVT_U_MSR_PMON_RAW_EVENT_MASK
,
1171 .fixed_ctr
= SNBEP_U_MSR_PMON_UCLK_FIXED_CTR
,
1172 .fixed_ctl
= SNBEP_U_MSR_PMON_UCLK_FIXED_CTL
,
1173 .ops
= &ivt_uncore_msr_ops
,
1174 .format_group
= &ivt_uncore_ubox_format_group
,
1177 static struct extra_reg ivt_uncore_cbox_extra_regs
[] = {
1178 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN
,
1179 SNBEP_CBO_PMON_CTL_TID_EN
, 0x1),
1180 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
1181 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1182 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1183 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1184 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
1185 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
1186 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1187 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1188 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1189 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1190 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1191 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1192 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1193 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1194 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1195 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1196 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1197 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1198 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1199 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1200 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1201 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1202 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1203 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1204 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1205 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1206 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1207 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1208 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1209 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1213 static u64
ivt_cbox_filter_mask(int fields
)
1218 mask
|= IVT_CB0_MSR_PMON_BOX_FILTER_TID
;
1220 mask
|= IVT_CB0_MSR_PMON_BOX_FILTER_LINK
;
1222 mask
|= IVT_CB0_MSR_PMON_BOX_FILTER_STATE
;
1224 mask
|= IVT_CB0_MSR_PMON_BOX_FILTER_NID
;
1226 mask
|= IVT_CB0_MSR_PMON_BOX_FILTER_OPC
;
1231 static struct event_constraint
*
1232 ivt_cbox_get_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
1234 return __snbep_cbox_get_constraint(box
, event
, ivt_cbox_filter_mask
);
1237 static int ivt_cbox_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
1239 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
1240 struct extra_reg
*er
;
1243 for (er
= ivt_uncore_cbox_extra_regs
; er
->msr
; er
++) {
1244 if (er
->event
!= (event
->hw
.config
& er
->config_mask
))
1250 reg1
->reg
= SNBEP_C0_MSR_PMON_BOX_FILTER
+
1251 SNBEP_CBO_MSR_OFFSET
* box
->pmu
->pmu_idx
;
1252 reg1
->config
= event
->attr
.config1
& ivt_cbox_filter_mask(idx
);
1258 static void ivt_cbox_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1260 struct hw_perf_event
*hwc
= &event
->hw
;
1261 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
1263 if (reg1
->idx
!= EXTRA_REG_NONE
) {
1264 u64 filter
= uncore_shared_reg_config(box
, 0);
1265 wrmsrl(reg1
->reg
, filter
& 0xffffffff);
1266 wrmsrl(reg1
->reg
+ 6, filter
>> 32);
1269 wrmsrl(hwc
->config_base
, hwc
->config
| SNBEP_PMON_CTL_EN
);
1272 static struct intel_uncore_ops ivt_uncore_cbox_ops
= {
1273 .init_box
= ivt_uncore_msr_init_box
,
1274 .disable_box
= snbep_uncore_msr_disable_box
,
1275 .enable_box
= snbep_uncore_msr_enable_box
,
1276 .disable_event
= snbep_uncore_msr_disable_event
,
1277 .enable_event
= ivt_cbox_enable_event
,
1278 .read_counter
= uncore_msr_read_counter
,
1279 .hw_config
= ivt_cbox_hw_config
,
1280 .get_constraint
= ivt_cbox_get_constraint
,
1281 .put_constraint
= snbep_cbox_put_constraint
,
1284 static struct intel_uncore_type ivt_uncore_cbox
= {
1288 .perf_ctr_bits
= 44,
1289 .event_ctl
= SNBEP_C0_MSR_PMON_CTL0
,
1290 .perf_ctr
= SNBEP_C0_MSR_PMON_CTR0
,
1291 .event_mask
= IVT_CBO_MSR_PMON_RAW_EVENT_MASK
,
1292 .box_ctl
= SNBEP_C0_MSR_PMON_BOX_CTL
,
1293 .msr_offset
= SNBEP_CBO_MSR_OFFSET
,
1294 .num_shared_regs
= 1,
1295 .constraints
= snbep_uncore_cbox_constraints
,
1296 .ops
= &ivt_uncore_cbox_ops
,
1297 .format_group
= &ivt_uncore_cbox_format_group
,
1300 static struct intel_uncore_ops ivt_uncore_pcu_ops
= {
1301 IVT_UNCORE_MSR_OPS_COMMON_INIT(),
1302 .hw_config
= snbep_pcu_hw_config
,
1303 .get_constraint
= snbep_pcu_get_constraint
,
1304 .put_constraint
= snbep_pcu_put_constraint
,
1307 static struct intel_uncore_type ivt_uncore_pcu
= {
1311 .perf_ctr_bits
= 48,
1312 .perf_ctr
= SNBEP_PCU_MSR_PMON_CTR0
,
1313 .event_ctl
= SNBEP_PCU_MSR_PMON_CTL0
,
1314 .event_mask
= IVT_PCU_MSR_PMON_RAW_EVENT_MASK
,
1315 .box_ctl
= SNBEP_PCU_MSR_PMON_BOX_CTL
,
1316 .num_shared_regs
= 1,
1317 .ops
= &ivt_uncore_pcu_ops
,
1318 .format_group
= &ivt_uncore_pcu_format_group
,
1321 static struct intel_uncore_type
*ivt_msr_uncores
[] = {
1328 static struct intel_uncore_type ivt_uncore_ha
= {
1332 .perf_ctr_bits
= 48,
1333 IVT_UNCORE_PCI_COMMON_INIT(),
1336 static struct intel_uncore_type ivt_uncore_imc
= {
1340 .perf_ctr_bits
= 48,
1341 .fixed_ctr_bits
= 48,
1342 .fixed_ctr
= SNBEP_MC_CHy_PCI_PMON_FIXED_CTR
,
1343 .fixed_ctl
= SNBEP_MC_CHy_PCI_PMON_FIXED_CTL
,
1344 IVT_UNCORE_PCI_COMMON_INIT(),
1347 /* registers in IRP boxes are not properly aligned */
1348 static unsigned ivt_uncore_irp_ctls
[] = {0xd8, 0xdc, 0xe0, 0xe4};
1349 static unsigned ivt_uncore_irp_ctrs
[] = {0xa0, 0xb0, 0xb8, 0xc0};
1351 static void ivt_uncore_irp_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1353 struct pci_dev
*pdev
= box
->pci_dev
;
1354 struct hw_perf_event
*hwc
= &event
->hw
;
1356 pci_write_config_dword(pdev
, ivt_uncore_irp_ctls
[hwc
->idx
],
1357 hwc
->config
| SNBEP_PMON_CTL_EN
);
1360 static void ivt_uncore_irp_disable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1362 struct pci_dev
*pdev
= box
->pci_dev
;
1363 struct hw_perf_event
*hwc
= &event
->hw
;
1365 pci_write_config_dword(pdev
, ivt_uncore_irp_ctls
[hwc
->idx
], hwc
->config
);
1368 static u64
ivt_uncore_irp_read_counter(struct intel_uncore_box
*box
, struct perf_event
*event
)
1370 struct pci_dev
*pdev
= box
->pci_dev
;
1371 struct hw_perf_event
*hwc
= &event
->hw
;
1374 pci_read_config_dword(pdev
, ivt_uncore_irp_ctrs
[hwc
->idx
], (u32
*)&count
);
1375 pci_read_config_dword(pdev
, ivt_uncore_irp_ctrs
[hwc
->idx
] + 4, (u32
*)&count
+ 1);
1380 static struct intel_uncore_ops ivt_uncore_irp_ops
= {
1381 .init_box
= ivt_uncore_pci_init_box
,
1382 .disable_box
= snbep_uncore_pci_disable_box
,
1383 .enable_box
= snbep_uncore_pci_enable_box
,
1384 .disable_event
= ivt_uncore_irp_disable_event
,
1385 .enable_event
= ivt_uncore_irp_enable_event
,
1386 .read_counter
= ivt_uncore_irp_read_counter
,
1389 static struct intel_uncore_type ivt_uncore_irp
= {
1393 .perf_ctr_bits
= 48,
1394 .event_mask
= IVT_PMON_RAW_EVENT_MASK
,
1395 .box_ctl
= SNBEP_PCI_PMON_BOX_CTL
,
1396 .ops
= &ivt_uncore_irp_ops
,
1397 .format_group
= &ivt_uncore_format_group
,
1400 static struct intel_uncore_ops ivt_uncore_qpi_ops
= {
1401 .init_box
= ivt_uncore_pci_init_box
,
1402 .disable_box
= snbep_uncore_pci_disable_box
,
1403 .enable_box
= snbep_uncore_pci_enable_box
,
1404 .disable_event
= snbep_uncore_pci_disable_event
,
1405 .enable_event
= snbep_qpi_enable_event
,
1406 .read_counter
= snbep_uncore_pci_read_counter
,
1407 .hw_config
= snbep_qpi_hw_config
,
1408 .get_constraint
= uncore_get_constraint
,
1409 .put_constraint
= uncore_put_constraint
,
1412 static struct intel_uncore_type ivt_uncore_qpi
= {
1416 .perf_ctr_bits
= 48,
1417 .perf_ctr
= SNBEP_PCI_PMON_CTR0
,
1418 .event_ctl
= SNBEP_PCI_PMON_CTL0
,
1419 .event_mask
= IVT_QPI_PCI_PMON_RAW_EVENT_MASK
,
1420 .box_ctl
= SNBEP_PCI_PMON_BOX_CTL
,
1421 .num_shared_regs
= 1,
1422 .ops
= &ivt_uncore_qpi_ops
,
1423 .format_group
= &ivt_uncore_qpi_format_group
,
1426 static struct intel_uncore_type ivt_uncore_r2pcie
= {
1430 .perf_ctr_bits
= 44,
1431 .constraints
= snbep_uncore_r2pcie_constraints
,
1432 IVT_UNCORE_PCI_COMMON_INIT(),
1435 static struct intel_uncore_type ivt_uncore_r3qpi
= {
1439 .perf_ctr_bits
= 44,
1440 .constraints
= snbep_uncore_r3qpi_constraints
,
1441 IVT_UNCORE_PCI_COMMON_INIT(),
1449 IVT_PCI_UNCORE_R2PCIE
,
1450 IVT_PCI_UNCORE_R3QPI
,
1453 static struct intel_uncore_type
*ivt_pci_uncores
[] = {
1454 [IVT_PCI_UNCORE_HA
] = &ivt_uncore_ha
,
1455 [IVT_PCI_UNCORE_IMC
] = &ivt_uncore_imc
,
1456 [IVT_PCI_UNCORE_IRP
] = &ivt_uncore_irp
,
1457 [IVT_PCI_UNCORE_QPI
] = &ivt_uncore_qpi
,
1458 [IVT_PCI_UNCORE_R2PCIE
] = &ivt_uncore_r2pcie
,
1459 [IVT_PCI_UNCORE_R3QPI
] = &ivt_uncore_r3qpi
,
1463 static DEFINE_PCI_DEVICE_TABLE(ivt_uncore_pci_ids
) = {
1464 { /* Home Agent 0 */
1465 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe30),
1466 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_HA
, 0),
1468 { /* Home Agent 1 */
1469 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe38),
1470 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_HA
, 1),
1472 { /* MC0 Channel 0 */
1473 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xeb4),
1474 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 0),
1476 { /* MC0 Channel 1 */
1477 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xeb5),
1478 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 1),
1480 { /* MC0 Channel 3 */
1481 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xeb0),
1482 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 2),
1484 { /* MC0 Channel 4 */
1485 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xeb1),
1486 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 3),
1488 { /* MC1 Channel 0 */
1489 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xef4),
1490 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 4),
1492 { /* MC1 Channel 1 */
1493 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xef5),
1494 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 5),
1496 { /* MC1 Channel 3 */
1497 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xef0),
1498 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 6),
1500 { /* MC1 Channel 4 */
1501 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xef1),
1502 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC
, 7),
1505 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe39),
1506 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IRP
, 0),
1509 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe32),
1510 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI
, 0),
1513 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe33),
1514 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI
, 1),
1517 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe3a),
1518 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI
, 2),
1521 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe34),
1522 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R2PCIE
, 0),
1524 { /* R3QPI0 Link 0 */
1525 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe36),
1526 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI
, 0),
1528 { /* R3QPI0 Link 1 */
1529 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe37),
1530 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI
, 1),
1532 { /* R3QPI1 Link 2 */
1533 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe3e),
1534 .driver_data
= UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI
, 2),
1536 { /* QPI Port 0 filter */
1537 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe86),
1538 .driver_data
= UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV
,
1539 SNBEP_PCI_QPI_PORT0_FILTER
),
1541 { /* QPI Port 0 filter */
1542 PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0xe96),
1543 .driver_data
= UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV
,
1544 SNBEP_PCI_QPI_PORT1_FILTER
),
1546 { /* end: all zeroes */ }
1549 static struct pci_driver ivt_uncore_pci_driver
= {
1550 .name
= "ivt_uncore",
1551 .id_table
= ivt_uncore_pci_ids
,
1553 /* end of IvyTown uncore support */
1555 /* Sandy Bridge uncore support */
1556 static void snb_uncore_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1558 struct hw_perf_event
*hwc
= &event
->hw
;
1560 if (hwc
->idx
< UNCORE_PMC_IDX_FIXED
)
1561 wrmsrl(hwc
->config_base
, hwc
->config
| SNB_UNC_CTL_EN
);
1563 wrmsrl(hwc
->config_base
, SNB_UNC_CTL_EN
);
1566 static void snb_uncore_msr_disable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1568 wrmsrl(event
->hw
.config_base
, 0);
1571 static void snb_uncore_msr_init_box(struct intel_uncore_box
*box
)
1573 if (box
->pmu
->pmu_idx
== 0) {
1574 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL
,
1575 SNB_UNC_GLOBAL_CTL_EN
| SNB_UNC_GLOBAL_CTL_CORE_ALL
);
1579 static struct uncore_event_desc snb_uncore_events
[] = {
1580 INTEL_UNCORE_EVENT_DESC(clockticks
, "event=0xff,umask=0x00"),
1581 { /* end: all zeroes */ },
1584 static struct attribute
*snb_uncore_formats_attr
[] = {
1585 &format_attr_event
.attr
,
1586 &format_attr_umask
.attr
,
1587 &format_attr_edge
.attr
,
1588 &format_attr_inv
.attr
,
1589 &format_attr_cmask5
.attr
,
1593 static struct attribute_group snb_uncore_format_group
= {
1595 .attrs
= snb_uncore_formats_attr
,
1598 static struct intel_uncore_ops snb_uncore_msr_ops
= {
1599 .init_box
= snb_uncore_msr_init_box
,
1600 .disable_event
= snb_uncore_msr_disable_event
,
1601 .enable_event
= snb_uncore_msr_enable_event
,
1602 .read_counter
= uncore_msr_read_counter
,
1605 static struct event_constraint snb_uncore_cbox_constraints
[] = {
1606 UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
1607 UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
1608 EVENT_CONSTRAINT_END
1611 static struct intel_uncore_type snb_uncore_cbox
= {
1615 .perf_ctr_bits
= 44,
1616 .fixed_ctr_bits
= 48,
1617 .perf_ctr
= SNB_UNC_CBO_0_PER_CTR0
,
1618 .event_ctl
= SNB_UNC_CBO_0_PERFEVTSEL0
,
1619 .fixed_ctr
= SNB_UNC_FIXED_CTR
,
1620 .fixed_ctl
= SNB_UNC_FIXED_CTR_CTRL
,
1622 .event_mask
= SNB_UNC_RAW_EVENT_MASK
,
1623 .msr_offset
= SNB_UNC_CBO_MSR_OFFSET
,
1624 .constraints
= snb_uncore_cbox_constraints
,
1625 .ops
= &snb_uncore_msr_ops
,
1626 .format_group
= &snb_uncore_format_group
,
1627 .event_descs
= snb_uncore_events
,
1630 static struct intel_uncore_type
*snb_msr_uncores
[] = {
1634 /* end of Sandy Bridge uncore support */
1636 /* Nehalem uncore support */
1637 static void nhm_uncore_msr_disable_box(struct intel_uncore_box
*box
)
1639 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL
, 0);
1642 static void nhm_uncore_msr_enable_box(struct intel_uncore_box
*box
)
1644 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL
, NHM_UNC_GLOBAL_CTL_EN_PC_ALL
| NHM_UNC_GLOBAL_CTL_EN_FC
);
1647 static void nhm_uncore_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1649 struct hw_perf_event
*hwc
= &event
->hw
;
1651 if (hwc
->idx
< UNCORE_PMC_IDX_FIXED
)
1652 wrmsrl(hwc
->config_base
, hwc
->config
| SNB_UNC_CTL_EN
);
1654 wrmsrl(hwc
->config_base
, NHM_UNC_FIXED_CTR_CTL_EN
);
1657 static struct attribute
*nhm_uncore_formats_attr
[] = {
1658 &format_attr_event
.attr
,
1659 &format_attr_umask
.attr
,
1660 &format_attr_edge
.attr
,
1661 &format_attr_inv
.attr
,
1662 &format_attr_cmask8
.attr
,
1666 static struct attribute_group nhm_uncore_format_group
= {
1668 .attrs
= nhm_uncore_formats_attr
,
1671 static struct uncore_event_desc nhm_uncore_events
[] = {
1672 INTEL_UNCORE_EVENT_DESC(clockticks
, "event=0xff,umask=0x00"),
1673 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any
, "event=0x2f,umask=0x0f"),
1674 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any
, "event=0x2c,umask=0x0f"),
1675 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads
, "event=0x20,umask=0x01"),
1676 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes
, "event=0x20,umask=0x02"),
1677 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads
, "event=0x20,umask=0x04"),
1678 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes
, "event=0x20,umask=0x08"),
1679 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads
, "event=0x20,umask=0x10"),
1680 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes
, "event=0x20,umask=0x20"),
1681 { /* end: all zeroes */ },
1684 static struct intel_uncore_ops nhm_uncore_msr_ops
= {
1685 .disable_box
= nhm_uncore_msr_disable_box
,
1686 .enable_box
= nhm_uncore_msr_enable_box
,
1687 .disable_event
= snb_uncore_msr_disable_event
,
1688 .enable_event
= nhm_uncore_msr_enable_event
,
1689 .read_counter
= uncore_msr_read_counter
,
1692 static struct intel_uncore_type nhm_uncore
= {
1696 .perf_ctr_bits
= 48,
1697 .fixed_ctr_bits
= 48,
1698 .event_ctl
= NHM_UNC_PERFEVTSEL0
,
1699 .perf_ctr
= NHM_UNC_UNCORE_PMC0
,
1700 .fixed_ctr
= NHM_UNC_FIXED_CTR
,
1701 .fixed_ctl
= NHM_UNC_FIXED_CTR_CTRL
,
1702 .event_mask
= NHM_UNC_RAW_EVENT_MASK
,
1703 .event_descs
= nhm_uncore_events
,
1704 .ops
= &nhm_uncore_msr_ops
,
1705 .format_group
= &nhm_uncore_format_group
,
1708 static struct intel_uncore_type
*nhm_msr_uncores
[] = {
1712 /* end of Nehalem uncore support */
1714 /* Nehalem-EX uncore support */
1715 DEFINE_UNCORE_FORMAT_ATTR(event5
, event
, "config:1-5");
1716 DEFINE_UNCORE_FORMAT_ATTR(counter
, counter
, "config:6-7");
1717 DEFINE_UNCORE_FORMAT_ATTR(match
, match
, "config1:0-63");
1718 DEFINE_UNCORE_FORMAT_ATTR(mask
, mask
, "config2:0-63");
1720 static void nhmex_uncore_msr_init_box(struct intel_uncore_box
*box
)
1722 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL
, NHMEX_U_PMON_GLOBAL_EN_ALL
);
1725 static void nhmex_uncore_msr_disable_box(struct intel_uncore_box
*box
)
1727 unsigned msr
= uncore_msr_box_ctl(box
);
1731 rdmsrl(msr
, config
);
1732 config
&= ~((1ULL << uncore_num_counters(box
)) - 1);
1733 /* WBox has a fixed counter */
1734 if (uncore_msr_fixed_ctl(box
))
1735 config
&= ~NHMEX_W_PMON_GLOBAL_FIXED_EN
;
1736 wrmsrl(msr
, config
);
1740 static void nhmex_uncore_msr_enable_box(struct intel_uncore_box
*box
)
1742 unsigned msr
= uncore_msr_box_ctl(box
);
1746 rdmsrl(msr
, config
);
1747 config
|= (1ULL << uncore_num_counters(box
)) - 1;
1748 /* WBox has a fixed counter */
1749 if (uncore_msr_fixed_ctl(box
))
1750 config
|= NHMEX_W_PMON_GLOBAL_FIXED_EN
;
1751 wrmsrl(msr
, config
);
1755 static void nhmex_uncore_msr_disable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1757 wrmsrl(event
->hw
.config_base
, 0);
1760 static void nhmex_uncore_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1762 struct hw_perf_event
*hwc
= &event
->hw
;
1764 if (hwc
->idx
>= UNCORE_PMC_IDX_FIXED
)
1765 wrmsrl(hwc
->config_base
, NHMEX_PMON_CTL_EN_BIT0
);
1766 else if (box
->pmu
->type
->event_mask
& NHMEX_PMON_CTL_EN_BIT0
)
1767 wrmsrl(hwc
->config_base
, hwc
->config
| NHMEX_PMON_CTL_EN_BIT22
);
1769 wrmsrl(hwc
->config_base
, hwc
->config
| NHMEX_PMON_CTL_EN_BIT0
);
1772 #define NHMEX_UNCORE_OPS_COMMON_INIT() \
1773 .init_box = nhmex_uncore_msr_init_box, \
1774 .disable_box = nhmex_uncore_msr_disable_box, \
1775 .enable_box = nhmex_uncore_msr_enable_box, \
1776 .disable_event = nhmex_uncore_msr_disable_event, \
1777 .read_counter = uncore_msr_read_counter
1779 static struct intel_uncore_ops nhmex_uncore_ops
= {
1780 NHMEX_UNCORE_OPS_COMMON_INIT(),
1781 .enable_event
= nhmex_uncore_msr_enable_event
,
1784 static struct attribute
*nhmex_uncore_ubox_formats_attr
[] = {
1785 &format_attr_event
.attr
,
1786 &format_attr_edge
.attr
,
1790 static struct attribute_group nhmex_uncore_ubox_format_group
= {
1792 .attrs
= nhmex_uncore_ubox_formats_attr
,
1795 static struct intel_uncore_type nhmex_uncore_ubox
= {
1799 .perf_ctr_bits
= 48,
1800 .event_ctl
= NHMEX_U_MSR_PMON_EV_SEL
,
1801 .perf_ctr
= NHMEX_U_MSR_PMON_CTR
,
1802 .event_mask
= NHMEX_U_PMON_RAW_EVENT_MASK
,
1803 .box_ctl
= NHMEX_U_MSR_PMON_GLOBAL_CTL
,
1804 .ops
= &nhmex_uncore_ops
,
1805 .format_group
= &nhmex_uncore_ubox_format_group
1808 static struct attribute
*nhmex_uncore_cbox_formats_attr
[] = {
1809 &format_attr_event
.attr
,
1810 &format_attr_umask
.attr
,
1811 &format_attr_edge
.attr
,
1812 &format_attr_inv
.attr
,
1813 &format_attr_thresh8
.attr
,
1817 static struct attribute_group nhmex_uncore_cbox_format_group
= {
1819 .attrs
= nhmex_uncore_cbox_formats_attr
,
1822 /* msr offset for each instance of cbox */
1823 static unsigned nhmex_cbox_msr_offsets
[] = {
1824 0x0, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x240, 0x2c0,
1827 static struct intel_uncore_type nhmex_uncore_cbox
= {
1831 .perf_ctr_bits
= 48,
1832 .event_ctl
= NHMEX_C0_MSR_PMON_EV_SEL0
,
1833 .perf_ctr
= NHMEX_C0_MSR_PMON_CTR0
,
1834 .event_mask
= NHMEX_PMON_RAW_EVENT_MASK
,
1835 .box_ctl
= NHMEX_C0_MSR_PMON_GLOBAL_CTL
,
1836 .msr_offsets
= nhmex_cbox_msr_offsets
,
1838 .ops
= &nhmex_uncore_ops
,
1839 .format_group
= &nhmex_uncore_cbox_format_group
1842 static struct uncore_event_desc nhmex_uncore_wbox_events
[] = {
1843 INTEL_UNCORE_EVENT_DESC(clockticks
, "event=0xff,umask=0"),
1844 { /* end: all zeroes */ },
1847 static struct intel_uncore_type nhmex_uncore_wbox
= {
1851 .perf_ctr_bits
= 48,
1852 .event_ctl
= NHMEX_W_MSR_PMON_CNT0
,
1853 .perf_ctr
= NHMEX_W_MSR_PMON_EVT_SEL0
,
1854 .fixed_ctr
= NHMEX_W_MSR_PMON_FIXED_CTR
,
1855 .fixed_ctl
= NHMEX_W_MSR_PMON_FIXED_CTL
,
1856 .event_mask
= NHMEX_PMON_RAW_EVENT_MASK
,
1857 .box_ctl
= NHMEX_W_MSR_GLOBAL_CTL
,
1859 .event_descs
= nhmex_uncore_wbox_events
,
1860 .ops
= &nhmex_uncore_ops
,
1861 .format_group
= &nhmex_uncore_cbox_format_group
1864 static int nhmex_bbox_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
1866 struct hw_perf_event
*hwc
= &event
->hw
;
1867 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
1868 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
1871 ctr
= (hwc
->config
& NHMEX_B_PMON_CTR_MASK
) >>
1872 NHMEX_B_PMON_CTR_SHIFT
;
1873 ev_sel
= (hwc
->config
& NHMEX_B_PMON_CTL_EV_SEL_MASK
) >>
1874 NHMEX_B_PMON_CTL_EV_SEL_SHIFT
;
1876 /* events that do not use the match/mask registers */
1877 if ((ctr
== 0 && ev_sel
> 0x3) || (ctr
== 1 && ev_sel
> 0x6) ||
1878 (ctr
== 2 && ev_sel
!= 0x4) || ctr
== 3)
1881 if (box
->pmu
->pmu_idx
== 0)
1882 reg1
->reg
= NHMEX_B0_MSR_MATCH
;
1884 reg1
->reg
= NHMEX_B1_MSR_MATCH
;
1886 reg1
->config
= event
->attr
.config1
;
1887 reg2
->config
= event
->attr
.config2
;
1891 static void nhmex_bbox_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1893 struct hw_perf_event
*hwc
= &event
->hw
;
1894 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
1895 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
1897 if (reg1
->idx
!= EXTRA_REG_NONE
) {
1898 wrmsrl(reg1
->reg
, reg1
->config
);
1899 wrmsrl(reg1
->reg
+ 1, reg2
->config
);
1901 wrmsrl(hwc
->config_base
, NHMEX_PMON_CTL_EN_BIT0
|
1902 (hwc
->config
& NHMEX_B_PMON_CTL_EV_SEL_MASK
));
1906 * The Bbox has 4 counters, but each counter monitors different events.
1907 * Use bits 6-7 in the event config to select counter.
1909 static struct event_constraint nhmex_uncore_bbox_constraints
[] = {
1910 EVENT_CONSTRAINT(0 , 1, 0xc0),
1911 EVENT_CONSTRAINT(0x40, 2, 0xc0),
1912 EVENT_CONSTRAINT(0x80, 4, 0xc0),
1913 EVENT_CONSTRAINT(0xc0, 8, 0xc0),
1914 EVENT_CONSTRAINT_END
,
1917 static struct attribute
*nhmex_uncore_bbox_formats_attr
[] = {
1918 &format_attr_event5
.attr
,
1919 &format_attr_counter
.attr
,
1920 &format_attr_match
.attr
,
1921 &format_attr_mask
.attr
,
1925 static struct attribute_group nhmex_uncore_bbox_format_group
= {
1927 .attrs
= nhmex_uncore_bbox_formats_attr
,
1930 static struct intel_uncore_ops nhmex_uncore_bbox_ops
= {
1931 NHMEX_UNCORE_OPS_COMMON_INIT(),
1932 .enable_event
= nhmex_bbox_msr_enable_event
,
1933 .hw_config
= nhmex_bbox_hw_config
,
1934 .get_constraint
= uncore_get_constraint
,
1935 .put_constraint
= uncore_put_constraint
,
1938 static struct intel_uncore_type nhmex_uncore_bbox
= {
1942 .perf_ctr_bits
= 48,
1943 .event_ctl
= NHMEX_B0_MSR_PMON_CTL0
,
1944 .perf_ctr
= NHMEX_B0_MSR_PMON_CTR0
,
1945 .event_mask
= NHMEX_B_PMON_RAW_EVENT_MASK
,
1946 .box_ctl
= NHMEX_B0_MSR_PMON_GLOBAL_CTL
,
1947 .msr_offset
= NHMEX_B_MSR_OFFSET
,
1949 .num_shared_regs
= 1,
1950 .constraints
= nhmex_uncore_bbox_constraints
,
1951 .ops
= &nhmex_uncore_bbox_ops
,
1952 .format_group
= &nhmex_uncore_bbox_format_group
1955 static int nhmex_sbox_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
1957 struct hw_perf_event
*hwc
= &event
->hw
;
1958 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
1959 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
1961 /* only TO_R_PROG_EV event uses the match/mask register */
1962 if ((hwc
->config
& NHMEX_PMON_CTL_EV_SEL_MASK
) !=
1963 NHMEX_S_EVENT_TO_R_PROG_EV
)
1966 if (box
->pmu
->pmu_idx
== 0)
1967 reg1
->reg
= NHMEX_S0_MSR_MM_CFG
;
1969 reg1
->reg
= NHMEX_S1_MSR_MM_CFG
;
1971 reg1
->config
= event
->attr
.config1
;
1972 reg2
->config
= event
->attr
.config2
;
1976 static void nhmex_sbox_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
1978 struct hw_perf_event
*hwc
= &event
->hw
;
1979 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
1980 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
1982 if (reg1
->idx
!= EXTRA_REG_NONE
) {
1983 wrmsrl(reg1
->reg
, 0);
1984 wrmsrl(reg1
->reg
+ 1, reg1
->config
);
1985 wrmsrl(reg1
->reg
+ 2, reg2
->config
);
1986 wrmsrl(reg1
->reg
, NHMEX_S_PMON_MM_CFG_EN
);
1988 wrmsrl(hwc
->config_base
, hwc
->config
| NHMEX_PMON_CTL_EN_BIT22
);
1991 static struct attribute
*nhmex_uncore_sbox_formats_attr
[] = {
1992 &format_attr_event
.attr
,
1993 &format_attr_umask
.attr
,
1994 &format_attr_edge
.attr
,
1995 &format_attr_inv
.attr
,
1996 &format_attr_thresh8
.attr
,
1997 &format_attr_match
.attr
,
1998 &format_attr_mask
.attr
,
2002 static struct attribute_group nhmex_uncore_sbox_format_group
= {
2004 .attrs
= nhmex_uncore_sbox_formats_attr
,
2007 static struct intel_uncore_ops nhmex_uncore_sbox_ops
= {
2008 NHMEX_UNCORE_OPS_COMMON_INIT(),
2009 .enable_event
= nhmex_sbox_msr_enable_event
,
2010 .hw_config
= nhmex_sbox_hw_config
,
2011 .get_constraint
= uncore_get_constraint
,
2012 .put_constraint
= uncore_put_constraint
,
2015 static struct intel_uncore_type nhmex_uncore_sbox
= {
2019 .perf_ctr_bits
= 48,
2020 .event_ctl
= NHMEX_S0_MSR_PMON_CTL0
,
2021 .perf_ctr
= NHMEX_S0_MSR_PMON_CTR0
,
2022 .event_mask
= NHMEX_PMON_RAW_EVENT_MASK
,
2023 .box_ctl
= NHMEX_S0_MSR_PMON_GLOBAL_CTL
,
2024 .msr_offset
= NHMEX_S_MSR_OFFSET
,
2026 .num_shared_regs
= 1,
2027 .ops
= &nhmex_uncore_sbox_ops
,
2028 .format_group
= &nhmex_uncore_sbox_format_group
2032 EXTRA_REG_NHMEX_M_FILTER
,
2033 EXTRA_REG_NHMEX_M_DSP
,
2034 EXTRA_REG_NHMEX_M_ISS
,
2035 EXTRA_REG_NHMEX_M_MAP
,
2036 EXTRA_REG_NHMEX_M_MSC_THR
,
2037 EXTRA_REG_NHMEX_M_PGT
,
2038 EXTRA_REG_NHMEX_M_PLD
,
2039 EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
,
2042 static struct extra_reg nhmex_uncore_mbox_extra_regs
[] = {
2043 MBOX_INC_SEL_EXTAR_REG(0x0, DSP
),
2044 MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR
),
2045 MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR
),
2046 MBOX_INC_SEL_EXTAR_REG(0x9, ISS
),
2047 /* event 0xa uses two extra registers */
2048 MBOX_INC_SEL_EXTAR_REG(0xa, ISS
),
2049 MBOX_INC_SEL_EXTAR_REG(0xa, PLD
),
2050 MBOX_INC_SEL_EXTAR_REG(0xb, PLD
),
2051 /* events 0xd ~ 0x10 use the same extra register */
2052 MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC
),
2053 MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC
),
2054 MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC
),
2055 MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC
),
2056 MBOX_INC_SEL_EXTAR_REG(0x16, PGT
),
2057 MBOX_SET_FLAG_SEL_EXTRA_REG(0x0, DSP
),
2058 MBOX_SET_FLAG_SEL_EXTRA_REG(0x1, ISS
),
2059 MBOX_SET_FLAG_SEL_EXTRA_REG(0x5, PGT
),
2060 MBOX_SET_FLAG_SEL_EXTRA_REG(0x6, MAP
),
2064 /* Nehalem-EX or Westmere-EX ? */
2065 static bool uncore_nhmex
;
2067 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box
*box
, int idx
, u64 config
)
2069 struct intel_uncore_extra_reg
*er
;
2070 unsigned long flags
;
2074 if (idx
< EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
) {
2075 er
= &box
->shared_regs
[idx
];
2076 raw_spin_lock_irqsave(&er
->lock
, flags
);
2077 if (!atomic_read(&er
->ref
) || er
->config
== config
) {
2078 atomic_inc(&er
->ref
);
2079 er
->config
= config
;
2082 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
2087 * The ZDP_CTL_FVC MSR has 4 fields which are used to control
2088 * events 0xd ~ 0x10. Besides these 4 fields, there are additional
2089 * fields which are shared.
2091 idx
-= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
;
2092 if (WARN_ON_ONCE(idx
>= 4))
2095 /* mask of the shared fields */
2097 mask
= NHMEX_M_PMON_ZDP_CTL_FVC_MASK
;
2099 mask
= WSMEX_M_PMON_ZDP_CTL_FVC_MASK
;
2100 er
= &box
->shared_regs
[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
];
2102 raw_spin_lock_irqsave(&er
->lock
, flags
);
2103 /* add mask of the non-shared field if it's in use */
2104 if (__BITS_VALUE(atomic_read(&er
->ref
), idx
, 8)) {
2106 mask
|= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx
);
2108 mask
|= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx
);
2111 if (!atomic_read(&er
->ref
) || !((er
->config
^ config
) & mask
)) {
2112 atomic_add(1 << (idx
* 8), &er
->ref
);
2114 mask
= NHMEX_M_PMON_ZDP_CTL_FVC_MASK
|
2115 NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx
);
2117 mask
= WSMEX_M_PMON_ZDP_CTL_FVC_MASK
|
2118 WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx
);
2119 er
->config
&= ~mask
;
2120 er
->config
|= (config
& mask
);
2123 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
2128 static void nhmex_mbox_put_shared_reg(struct intel_uncore_box
*box
, int idx
)
2130 struct intel_uncore_extra_reg
*er
;
2132 if (idx
< EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
) {
2133 er
= &box
->shared_regs
[idx
];
2134 atomic_dec(&er
->ref
);
2138 idx
-= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
;
2139 er
= &box
->shared_regs
[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
];
2140 atomic_sub(1 << (idx
* 8), &er
->ref
);
2143 static u64
nhmex_mbox_alter_er(struct perf_event
*event
, int new_idx
, bool modify
)
2145 struct hw_perf_event
*hwc
= &event
->hw
;
2146 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
2147 u64 idx
, orig_idx
= __BITS_VALUE(reg1
->idx
, 0, 8);
2148 u64 config
= reg1
->config
;
2150 /* get the non-shared control bits and shift them */
2151 idx
= orig_idx
- EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
;
2153 config
&= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx
);
2155 config
&= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx
);
2156 if (new_idx
> orig_idx
) {
2157 idx
= new_idx
- orig_idx
;
2160 idx
= orig_idx
- new_idx
;
2164 /* add the shared control bits back */
2166 config
|= NHMEX_M_PMON_ZDP_CTL_FVC_MASK
& reg1
->config
;
2168 config
|= WSMEX_M_PMON_ZDP_CTL_FVC_MASK
& reg1
->config
;
2169 config
|= NHMEX_M_PMON_ZDP_CTL_FVC_MASK
& reg1
->config
;
2171 /* adjust the main event selector */
2172 if (new_idx
> orig_idx
)
2173 hwc
->config
+= idx
<< NHMEX_M_PMON_CTL_INC_SEL_SHIFT
;
2175 hwc
->config
-= idx
<< NHMEX_M_PMON_CTL_INC_SEL_SHIFT
;
2176 reg1
->config
= config
;
2177 reg1
->idx
= ~0xff | new_idx
;
2182 static struct event_constraint
*
2183 nhmex_mbox_get_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
2185 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
2186 struct hw_perf_event_extra
*reg2
= &event
->hw
.branch_reg
;
2187 int i
, idx
[2], alloc
= 0;
2188 u64 config1
= reg1
->config
;
2190 idx
[0] = __BITS_VALUE(reg1
->idx
, 0, 8);
2191 idx
[1] = __BITS_VALUE(reg1
->idx
, 1, 8);
2193 for (i
= 0; i
< 2; i
++) {
2194 if (!uncore_box_is_fake(box
) && (reg1
->alloc
& (0x1 << i
)))
2200 if (!nhmex_mbox_get_shared_reg(box
, idx
[i
],
2201 __BITS_VALUE(config1
, i
, 32)))
2203 alloc
|= (0x1 << i
);
2206 /* for the match/mask registers */
2207 if (reg2
->idx
!= EXTRA_REG_NONE
&&
2208 (uncore_box_is_fake(box
) || !reg2
->alloc
) &&
2209 !nhmex_mbox_get_shared_reg(box
, reg2
->idx
, reg2
->config
))
2213 * If it's a fake box -- as per validate_{group,event}() we
2214 * shouldn't touch event state and we can avoid doing so
2215 * since both will only call get_event_constraints() once
2216 * on each event, this avoids the need for reg->alloc.
2218 if (!uncore_box_is_fake(box
)) {
2219 if (idx
[0] != 0xff && idx
[0] != __BITS_VALUE(reg1
->idx
, 0, 8))
2220 nhmex_mbox_alter_er(event
, idx
[0], true);
2221 reg1
->alloc
|= alloc
;
2222 if (reg2
->idx
!= EXTRA_REG_NONE
)
2227 if (idx
[0] != 0xff && !(alloc
& 0x1) &&
2228 idx
[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
) {
2230 * events 0xd ~ 0x10 are functional identical, but are
2231 * controlled by different fields in the ZDP_CTL_FVC
2232 * register. If we failed to take one field, try the
2235 BUG_ON(__BITS_VALUE(reg1
->idx
, 1, 8) != 0xff);
2236 idx
[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
;
2237 idx
[0] = (idx
[0] + 1) % 4;
2238 idx
[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
;
2239 if (idx
[0] != __BITS_VALUE(reg1
->idx
, 0, 8)) {
2240 config1
= nhmex_mbox_alter_er(event
, idx
[0], false);
2246 nhmex_mbox_put_shared_reg(box
, idx
[0]);
2248 nhmex_mbox_put_shared_reg(box
, idx
[1]);
2249 return &constraint_empty
;
2252 static void nhmex_mbox_put_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
2254 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
2255 struct hw_perf_event_extra
*reg2
= &event
->hw
.branch_reg
;
2257 if (uncore_box_is_fake(box
))
2260 if (reg1
->alloc
& 0x1)
2261 nhmex_mbox_put_shared_reg(box
, __BITS_VALUE(reg1
->idx
, 0, 8));
2262 if (reg1
->alloc
& 0x2)
2263 nhmex_mbox_put_shared_reg(box
, __BITS_VALUE(reg1
->idx
, 1, 8));
2267 nhmex_mbox_put_shared_reg(box
, reg2
->idx
);
2272 static int nhmex_mbox_extra_reg_idx(struct extra_reg
*er
)
2274 if (er
->idx
< EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
)
2276 return er
->idx
+ (er
->event
>> NHMEX_M_PMON_CTL_INC_SEL_SHIFT
) - 0xd;
2279 static int nhmex_mbox_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
2281 struct intel_uncore_type
*type
= box
->pmu
->type
;
2282 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
2283 struct hw_perf_event_extra
*reg2
= &event
->hw
.branch_reg
;
2284 struct extra_reg
*er
;
2288 * The mbox events may require 2 extra MSRs at the most. But only
2289 * the lower 32 bits in these MSRs are significant, so we can use
2290 * config1 to pass two MSRs' config.
2292 for (er
= nhmex_uncore_mbox_extra_regs
; er
->msr
; er
++) {
2293 if (er
->event
!= (event
->hw
.config
& er
->config_mask
))
2295 if (event
->attr
.config1
& ~er
->valid_mask
)
2298 msr
= er
->msr
+ type
->msr_offset
* box
->pmu
->pmu_idx
;
2299 if (WARN_ON_ONCE(msr
>= 0xffff || er
->idx
>= 0xff))
2302 /* always use the 32~63 bits to pass the PLD config */
2303 if (er
->idx
== EXTRA_REG_NHMEX_M_PLD
)
2305 else if (WARN_ON_ONCE(reg_idx
> 0))
2308 reg1
->idx
&= ~(0xff << (reg_idx
* 8));
2309 reg1
->reg
&= ~(0xffff << (reg_idx
* 16));
2310 reg1
->idx
|= nhmex_mbox_extra_reg_idx(er
) << (reg_idx
* 8);
2311 reg1
->reg
|= msr
<< (reg_idx
* 16);
2312 reg1
->config
= event
->attr
.config1
;
2316 * The mbox only provides ability to perform address matching
2317 * for the PLD events.
2320 reg2
->idx
= EXTRA_REG_NHMEX_M_FILTER
;
2321 if (event
->attr
.config2
& NHMEX_M_PMON_MM_CFG_EN
)
2322 reg2
->config
= event
->attr
.config2
;
2324 reg2
->config
= ~0ULL;
2325 if (box
->pmu
->pmu_idx
== 0)
2326 reg2
->reg
= NHMEX_M0_MSR_PMU_MM_CFG
;
2328 reg2
->reg
= NHMEX_M1_MSR_PMU_MM_CFG
;
2333 static u64
nhmex_mbox_shared_reg_config(struct intel_uncore_box
*box
, int idx
)
2335 struct intel_uncore_extra_reg
*er
;
2336 unsigned long flags
;
2339 if (idx
< EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
)
2340 return box
->shared_regs
[idx
].config
;
2342 er
= &box
->shared_regs
[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC
];
2343 raw_spin_lock_irqsave(&er
->lock
, flags
);
2344 config
= er
->config
;
2345 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
2349 static void nhmex_mbox_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
2351 struct hw_perf_event
*hwc
= &event
->hw
;
2352 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
2353 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
2356 idx
= __BITS_VALUE(reg1
->idx
, 0, 8);
2358 wrmsrl(__BITS_VALUE(reg1
->reg
, 0, 16),
2359 nhmex_mbox_shared_reg_config(box
, idx
));
2360 idx
= __BITS_VALUE(reg1
->idx
, 1, 8);
2362 wrmsrl(__BITS_VALUE(reg1
->reg
, 1, 16),
2363 nhmex_mbox_shared_reg_config(box
, idx
));
2365 if (reg2
->idx
!= EXTRA_REG_NONE
) {
2366 wrmsrl(reg2
->reg
, 0);
2367 if (reg2
->config
!= ~0ULL) {
2368 wrmsrl(reg2
->reg
+ 1,
2369 reg2
->config
& NHMEX_M_PMON_ADDR_MATCH_MASK
);
2370 wrmsrl(reg2
->reg
+ 2, NHMEX_M_PMON_ADDR_MASK_MASK
&
2371 (reg2
->config
>> NHMEX_M_PMON_ADDR_MASK_SHIFT
));
2372 wrmsrl(reg2
->reg
, NHMEX_M_PMON_MM_CFG_EN
);
2376 wrmsrl(hwc
->config_base
, hwc
->config
| NHMEX_PMON_CTL_EN_BIT0
);
2379 DEFINE_UNCORE_FORMAT_ATTR(count_mode
, count_mode
, "config:2-3");
2380 DEFINE_UNCORE_FORMAT_ATTR(storage_mode
, storage_mode
, "config:4-5");
2381 DEFINE_UNCORE_FORMAT_ATTR(wrap_mode
, wrap_mode
, "config:6");
2382 DEFINE_UNCORE_FORMAT_ATTR(flag_mode
, flag_mode
, "config:7");
2383 DEFINE_UNCORE_FORMAT_ATTR(inc_sel
, inc_sel
, "config:9-13");
2384 DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel
, set_flag_sel
, "config:19-21");
2385 DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en
, filter_cfg_en
, "config2:63");
2386 DEFINE_UNCORE_FORMAT_ATTR(filter_match
, filter_match
, "config2:0-33");
2387 DEFINE_UNCORE_FORMAT_ATTR(filter_mask
, filter_mask
, "config2:34-61");
2388 DEFINE_UNCORE_FORMAT_ATTR(dsp
, dsp
, "config1:0-31");
2389 DEFINE_UNCORE_FORMAT_ATTR(thr
, thr
, "config1:0-31");
2390 DEFINE_UNCORE_FORMAT_ATTR(fvc
, fvc
, "config1:0-31");
2391 DEFINE_UNCORE_FORMAT_ATTR(pgt
, pgt
, "config1:0-31");
2392 DEFINE_UNCORE_FORMAT_ATTR(map
, map
, "config1:0-31");
2393 DEFINE_UNCORE_FORMAT_ATTR(iss
, iss
, "config1:0-31");
2394 DEFINE_UNCORE_FORMAT_ATTR(pld
, pld
, "config1:32-63");
2396 static struct attribute
*nhmex_uncore_mbox_formats_attr
[] = {
2397 &format_attr_count_mode
.attr
,
2398 &format_attr_storage_mode
.attr
,
2399 &format_attr_wrap_mode
.attr
,
2400 &format_attr_flag_mode
.attr
,
2401 &format_attr_inc_sel
.attr
,
2402 &format_attr_set_flag_sel
.attr
,
2403 &format_attr_filter_cfg_en
.attr
,
2404 &format_attr_filter_match
.attr
,
2405 &format_attr_filter_mask
.attr
,
2406 &format_attr_dsp
.attr
,
2407 &format_attr_thr
.attr
,
2408 &format_attr_fvc
.attr
,
2409 &format_attr_pgt
.attr
,
2410 &format_attr_map
.attr
,
2411 &format_attr_iss
.attr
,
2412 &format_attr_pld
.attr
,
2416 static struct attribute_group nhmex_uncore_mbox_format_group
= {
2418 .attrs
= nhmex_uncore_mbox_formats_attr
,
2421 static struct uncore_event_desc nhmex_uncore_mbox_events
[] = {
2422 INTEL_UNCORE_EVENT_DESC(bbox_cmds_read
, "inc_sel=0xd,fvc=0x2800"),
2423 INTEL_UNCORE_EVENT_DESC(bbox_cmds_write
, "inc_sel=0xd,fvc=0x2820"),
2424 { /* end: all zeroes */ },
2427 static struct uncore_event_desc wsmex_uncore_mbox_events
[] = {
2428 INTEL_UNCORE_EVENT_DESC(bbox_cmds_read
, "inc_sel=0xd,fvc=0x5000"),
2429 INTEL_UNCORE_EVENT_DESC(bbox_cmds_write
, "inc_sel=0xd,fvc=0x5040"),
2430 { /* end: all zeroes */ },
2433 static struct intel_uncore_ops nhmex_uncore_mbox_ops
= {
2434 NHMEX_UNCORE_OPS_COMMON_INIT(),
2435 .enable_event
= nhmex_mbox_msr_enable_event
,
2436 .hw_config
= nhmex_mbox_hw_config
,
2437 .get_constraint
= nhmex_mbox_get_constraint
,
2438 .put_constraint
= nhmex_mbox_put_constraint
,
2441 static struct intel_uncore_type nhmex_uncore_mbox
= {
2445 .perf_ctr_bits
= 48,
2446 .event_ctl
= NHMEX_M0_MSR_PMU_CTL0
,
2447 .perf_ctr
= NHMEX_M0_MSR_PMU_CNT0
,
2448 .event_mask
= NHMEX_M_PMON_RAW_EVENT_MASK
,
2449 .box_ctl
= NHMEX_M0_MSR_GLOBAL_CTL
,
2450 .msr_offset
= NHMEX_M_MSR_OFFSET
,
2452 .num_shared_regs
= 8,
2453 .event_descs
= nhmex_uncore_mbox_events
,
2454 .ops
= &nhmex_uncore_mbox_ops
,
2455 .format_group
= &nhmex_uncore_mbox_format_group
,
2458 static void nhmex_rbox_alter_er(struct intel_uncore_box
*box
, struct perf_event
*event
)
2460 struct hw_perf_event
*hwc
= &event
->hw
;
2461 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
2463 /* adjust the main event selector and extra register index */
2464 if (reg1
->idx
% 2) {
2466 hwc
->config
-= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT
;
2469 hwc
->config
+= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT
;
2472 /* adjust extra register config */
2473 switch (reg1
->idx
% 6) {
2475 /* shift the 8~15 bits to the 0~7 bits */
2479 /* shift the 0~7 bits to the 8~15 bits */
2486 * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7.
2487 * An event set consists of 6 events, the 3rd and 4th events in
2488 * an event set use the same extra register. So an event set uses
2489 * 5 extra registers.
2491 static struct event_constraint
*
2492 nhmex_rbox_get_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
2494 struct hw_perf_event
*hwc
= &event
->hw
;
2495 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
2496 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
2497 struct intel_uncore_extra_reg
*er
;
2498 unsigned long flags
;
2503 if (!uncore_box_is_fake(box
) && reg1
->alloc
)
2506 idx
= reg1
->idx
% 6;
2507 config1
= reg1
->config
;
2510 /* the 3rd and 4th events use the same extra register */
2513 er_idx
+= (reg1
->idx
/ 6) * 5;
2515 er
= &box
->shared_regs
[er_idx
];
2516 raw_spin_lock_irqsave(&er
->lock
, flags
);
2518 if (!atomic_read(&er
->ref
) || er
->config
== reg1
->config
) {
2519 atomic_inc(&er
->ref
);
2520 er
->config
= reg1
->config
;
2523 } else if (idx
== 2 || idx
== 3) {
2525 * these two events use different fields in a extra register,
2526 * the 0~7 bits and the 8~15 bits respectively.
2528 u64 mask
= 0xff << ((idx
- 2) * 8);
2529 if (!__BITS_VALUE(atomic_read(&er
->ref
), idx
- 2, 8) ||
2530 !((er
->config
^ config1
) & mask
)) {
2531 atomic_add(1 << ((idx
- 2) * 8), &er
->ref
);
2532 er
->config
&= ~mask
;
2533 er
->config
|= config1
& mask
;
2537 if (!atomic_read(&er
->ref
) ||
2538 (er
->config
== (hwc
->config
>> 32) &&
2539 er
->config1
== reg1
->config
&&
2540 er
->config2
== reg2
->config
)) {
2541 atomic_inc(&er
->ref
);
2542 er
->config
= (hwc
->config
>> 32);
2543 er
->config1
= reg1
->config
;
2544 er
->config2
= reg2
->config
;
2548 raw_spin_unlock_irqrestore(&er
->lock
, flags
);
2552 * The Rbox events are always in pairs. The paired
2553 * events are functional identical, but use different
2554 * extra registers. If we failed to take an extra
2555 * register, try the alternative.
2561 if (idx
!= reg1
->idx
% 6) {
2569 if (!uncore_box_is_fake(box
)) {
2570 if (idx
!= reg1
->idx
% 6)
2571 nhmex_rbox_alter_er(box
, event
);
2576 return &constraint_empty
;
2579 static void nhmex_rbox_put_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
2581 struct intel_uncore_extra_reg
*er
;
2582 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
2585 if (uncore_box_is_fake(box
) || !reg1
->alloc
)
2588 idx
= reg1
->idx
% 6;
2592 er_idx
+= (reg1
->idx
/ 6) * 5;
2594 er
= &box
->shared_regs
[er_idx
];
2595 if (idx
== 2 || idx
== 3)
2596 atomic_sub(1 << ((idx
- 2) * 8), &er
->ref
);
2598 atomic_dec(&er
->ref
);
2603 static int nhmex_rbox_hw_config(struct intel_uncore_box
*box
, struct perf_event
*event
)
2605 struct hw_perf_event
*hwc
= &event
->hw
;
2606 struct hw_perf_event_extra
*reg1
= &event
->hw
.extra_reg
;
2607 struct hw_perf_event_extra
*reg2
= &event
->hw
.branch_reg
;
2610 idx
= (event
->hw
.config
& NHMEX_R_PMON_CTL_EV_SEL_MASK
) >>
2611 NHMEX_R_PMON_CTL_EV_SEL_SHIFT
;
2616 reg1
->config
= event
->attr
.config1
;
2621 hwc
->config
|= event
->attr
.config
& (~0ULL << 32);
2622 reg2
->config
= event
->attr
.config2
;
2628 static void nhmex_rbox_msr_enable_event(struct intel_uncore_box
*box
, struct perf_event
*event
)
2630 struct hw_perf_event
*hwc
= &event
->hw
;
2631 struct hw_perf_event_extra
*reg1
= &hwc
->extra_reg
;
2632 struct hw_perf_event_extra
*reg2
= &hwc
->branch_reg
;
2636 port
= idx
/ 6 + box
->pmu
->pmu_idx
* 4;
2640 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port
), reg1
->config
);
2643 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port
), reg1
->config
);
2647 wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port
),
2648 uncore_shared_reg_config(box
, 2 + (idx
/ 6) * 5));
2651 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port
),
2653 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port
), reg1
->config
);
2654 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port
), reg2
->config
);
2657 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port
),
2659 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port
), reg1
->config
);
2660 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port
), reg2
->config
);
2664 wrmsrl(hwc
->config_base
, NHMEX_PMON_CTL_EN_BIT0
|
2665 (hwc
->config
& NHMEX_R_PMON_CTL_EV_SEL_MASK
));
2668 DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg
, xbr_mm_cfg
, "config:32-63");
2669 DEFINE_UNCORE_FORMAT_ATTR(xbr_match
, xbr_match
, "config1:0-63");
2670 DEFINE_UNCORE_FORMAT_ATTR(xbr_mask
, xbr_mask
, "config2:0-63");
2671 DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg
, qlx_cfg
, "config1:0-15");
2672 DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg
, iperf_cfg
, "config1:0-31");
2674 static struct attribute
*nhmex_uncore_rbox_formats_attr
[] = {
2675 &format_attr_event5
.attr
,
2676 &format_attr_xbr_mm_cfg
.attr
,
2677 &format_attr_xbr_match
.attr
,
2678 &format_attr_xbr_mask
.attr
,
2679 &format_attr_qlx_cfg
.attr
,
2680 &format_attr_iperf_cfg
.attr
,
2684 static struct attribute_group nhmex_uncore_rbox_format_group
= {
2686 .attrs
= nhmex_uncore_rbox_formats_attr
,
2689 static struct uncore_event_desc nhmex_uncore_rbox_events
[] = {
2690 INTEL_UNCORE_EVENT_DESC(qpi0_flit_send
, "event=0x0,iperf_cfg=0x80000000"),
2691 INTEL_UNCORE_EVENT_DESC(qpi1_filt_send
, "event=0x6,iperf_cfg=0x80000000"),
2692 INTEL_UNCORE_EVENT_DESC(qpi0_idle_filt
, "event=0x0,iperf_cfg=0x40000000"),
2693 INTEL_UNCORE_EVENT_DESC(qpi1_idle_filt
, "event=0x6,iperf_cfg=0x40000000"),
2694 INTEL_UNCORE_EVENT_DESC(qpi0_date_response
, "event=0x0,iperf_cfg=0xc4"),
2695 INTEL_UNCORE_EVENT_DESC(qpi1_date_response
, "event=0x6,iperf_cfg=0xc4"),
2696 { /* end: all zeroes */ },
2699 static struct intel_uncore_ops nhmex_uncore_rbox_ops
= {
2700 NHMEX_UNCORE_OPS_COMMON_INIT(),
2701 .enable_event
= nhmex_rbox_msr_enable_event
,
2702 .hw_config
= nhmex_rbox_hw_config
,
2703 .get_constraint
= nhmex_rbox_get_constraint
,
2704 .put_constraint
= nhmex_rbox_put_constraint
,
2707 static struct intel_uncore_type nhmex_uncore_rbox
= {
2711 .perf_ctr_bits
= 48,
2712 .event_ctl
= NHMEX_R_MSR_PMON_CTL0
,
2713 .perf_ctr
= NHMEX_R_MSR_PMON_CNT0
,
2714 .event_mask
= NHMEX_R_PMON_RAW_EVENT_MASK
,
2715 .box_ctl
= NHMEX_R_MSR_GLOBAL_CTL
,
2716 .msr_offset
= NHMEX_R_MSR_OFFSET
,
2718 .num_shared_regs
= 20,
2719 .event_descs
= nhmex_uncore_rbox_events
,
2720 .ops
= &nhmex_uncore_rbox_ops
,
2721 .format_group
= &nhmex_uncore_rbox_format_group
2724 static struct intel_uncore_type
*nhmex_msr_uncores
[] = {
2734 /* end of Nehalem-EX uncore support */
2736 static void uncore_assign_hw_event(struct intel_uncore_box
*box
, struct perf_event
*event
, int idx
)
2738 struct hw_perf_event
*hwc
= &event
->hw
;
2741 hwc
->last_tag
= ++box
->tags
[idx
];
2743 if (hwc
->idx
== UNCORE_PMC_IDX_FIXED
) {
2744 hwc
->event_base
= uncore_fixed_ctr(box
);
2745 hwc
->config_base
= uncore_fixed_ctl(box
);
2749 hwc
->config_base
= uncore_event_ctl(box
, hwc
->idx
);
2750 hwc
->event_base
= uncore_perf_ctr(box
, hwc
->idx
);
2753 static void uncore_perf_event_update(struct intel_uncore_box
*box
, struct perf_event
*event
)
2755 u64 prev_count
, new_count
, delta
;
2758 if (event
->hw
.idx
>= UNCORE_PMC_IDX_FIXED
)
2759 shift
= 64 - uncore_fixed_ctr_bits(box
);
2761 shift
= 64 - uncore_perf_ctr_bits(box
);
2763 /* the hrtimer might modify the previous event value */
2765 prev_count
= local64_read(&event
->hw
.prev_count
);
2766 new_count
= uncore_read_counter(box
, event
);
2767 if (local64_xchg(&event
->hw
.prev_count
, new_count
) != prev_count
)
2770 delta
= (new_count
<< shift
) - (prev_count
<< shift
);
2773 local64_add(delta
, &event
->count
);
2777 * The overflow interrupt is unavailable for SandyBridge-EP, is broken
2778 * for SandyBridge. So we use hrtimer to periodically poll the counter
2779 * to avoid overflow.
2781 static enum hrtimer_restart
uncore_pmu_hrtimer(struct hrtimer
*hrtimer
)
2783 struct intel_uncore_box
*box
;
2784 unsigned long flags
;
2787 box
= container_of(hrtimer
, struct intel_uncore_box
, hrtimer
);
2788 if (!box
->n_active
|| box
->cpu
!= smp_processor_id())
2789 return HRTIMER_NORESTART
;
2791 * disable local interrupt to prevent uncore_pmu_event_start/stop
2792 * to interrupt the update process
2794 local_irq_save(flags
);
2796 for_each_set_bit(bit
, box
->active_mask
, UNCORE_PMC_IDX_MAX
)
2797 uncore_perf_event_update(box
, box
->events
[bit
]);
2799 local_irq_restore(flags
);
2801 hrtimer_forward_now(hrtimer
, ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL
));
2802 return HRTIMER_RESTART
;
2805 static void uncore_pmu_start_hrtimer(struct intel_uncore_box
*box
)
2807 __hrtimer_start_range_ns(&box
->hrtimer
,
2808 ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL
), 0,
2809 HRTIMER_MODE_REL_PINNED
, 0);
2812 static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box
*box
)
2814 hrtimer_cancel(&box
->hrtimer
);
2817 static void uncore_pmu_init_hrtimer(struct intel_uncore_box
*box
)
2819 hrtimer_init(&box
->hrtimer
, CLOCK_MONOTONIC
, HRTIMER_MODE_REL
);
2820 box
->hrtimer
.function
= uncore_pmu_hrtimer
;
2823 static struct intel_uncore_box
*uncore_alloc_box(struct intel_uncore_type
*type
, int node
)
2825 struct intel_uncore_box
*box
;
2828 size
= sizeof(*box
) + type
->num_shared_regs
* sizeof(struct intel_uncore_extra_reg
);
2830 box
= kzalloc_node(size
, GFP_KERNEL
, node
);
2834 for (i
= 0; i
< type
->num_shared_regs
; i
++)
2835 raw_spin_lock_init(&box
->shared_regs
[i
].lock
);
2837 uncore_pmu_init_hrtimer(box
);
2838 atomic_set(&box
->refcnt
, 1);
2845 static struct intel_uncore_box
*
2846 uncore_pmu_to_box(struct intel_uncore_pmu
*pmu
, int cpu
)
2848 struct intel_uncore_box
*box
;
2850 box
= *per_cpu_ptr(pmu
->box
, cpu
);
2854 raw_spin_lock(&uncore_box_lock
);
2855 list_for_each_entry(box
, &pmu
->box_list
, list
) {
2856 if (box
->phys_id
== topology_physical_package_id(cpu
)) {
2857 atomic_inc(&box
->refcnt
);
2858 *per_cpu_ptr(pmu
->box
, cpu
) = box
;
2862 raw_spin_unlock(&uncore_box_lock
);
2864 return *per_cpu_ptr(pmu
->box
, cpu
);
2867 static struct intel_uncore_pmu
*uncore_event_to_pmu(struct perf_event
*event
)
2869 return container_of(event
->pmu
, struct intel_uncore_pmu
, pmu
);
2872 static struct intel_uncore_box
*uncore_event_to_box(struct perf_event
*event
)
2875 * perf core schedules event on the basis of cpu, uncore events are
2876 * collected by one of the cpus inside a physical package.
2878 return uncore_pmu_to_box(uncore_event_to_pmu(event
), smp_processor_id());
2882 uncore_collect_events(struct intel_uncore_box
*box
, struct perf_event
*leader
, bool dogrp
)
2884 struct perf_event
*event
;
2887 max_count
= box
->pmu
->type
->num_counters
;
2888 if (box
->pmu
->type
->fixed_ctl
)
2891 if (box
->n_events
>= max_count
)
2895 box
->event_list
[n
] = leader
;
2900 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
2901 if (event
->state
<= PERF_EVENT_STATE_OFF
)
2907 box
->event_list
[n
] = event
;
2913 static struct event_constraint
*
2914 uncore_get_event_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
2916 struct intel_uncore_type
*type
= box
->pmu
->type
;
2917 struct event_constraint
*c
;
2919 if (type
->ops
->get_constraint
) {
2920 c
= type
->ops
->get_constraint(box
, event
);
2925 if (event
->attr
.config
== UNCORE_FIXED_EVENT
)
2926 return &constraint_fixed
;
2928 if (type
->constraints
) {
2929 for_each_event_constraint(c
, type
->constraints
) {
2930 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
2935 return &type
->unconstrainted
;
2938 static void uncore_put_event_constraint(struct intel_uncore_box
*box
, struct perf_event
*event
)
2940 if (box
->pmu
->type
->ops
->put_constraint
)
2941 box
->pmu
->type
->ops
->put_constraint(box
, event
);
2944 static int uncore_assign_events(struct intel_uncore_box
*box
, int assign
[], int n
)
2946 unsigned long used_mask
[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX
)];
2947 struct event_constraint
*c
;
2948 int i
, wmin
, wmax
, ret
= 0;
2949 struct hw_perf_event
*hwc
;
2951 bitmap_zero(used_mask
, UNCORE_PMC_IDX_MAX
);
2953 for (i
= 0, wmin
= UNCORE_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
2954 hwc
= &box
->event_list
[i
]->hw
;
2955 c
= uncore_get_event_constraint(box
, box
->event_list
[i
]);
2956 hwc
->constraint
= c
;
2957 wmin
= min(wmin
, c
->weight
);
2958 wmax
= max(wmax
, c
->weight
);
2961 /* fastpath, try to reuse previous register */
2962 for (i
= 0; i
< n
; i
++) {
2963 hwc
= &box
->event_list
[i
]->hw
;
2964 c
= hwc
->constraint
;
2966 /* never assigned */
2970 /* constraint still honored */
2971 if (!test_bit(hwc
->idx
, c
->idxmsk
))
2974 /* not already used */
2975 if (test_bit(hwc
->idx
, used_mask
))
2978 __set_bit(hwc
->idx
, used_mask
);
2980 assign
[i
] = hwc
->idx
;
2984 ret
= perf_assign_events(box
->event_list
, n
,
2985 wmin
, wmax
, assign
);
2987 if (!assign
|| ret
) {
2988 for (i
= 0; i
< n
; i
++)
2989 uncore_put_event_constraint(box
, box
->event_list
[i
]);
2991 return ret
? -EINVAL
: 0;
2994 static void uncore_pmu_event_start(struct perf_event
*event
, int flags
)
2996 struct intel_uncore_box
*box
= uncore_event_to_box(event
);
2997 int idx
= event
->hw
.idx
;
2999 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
3002 if (WARN_ON_ONCE(idx
== -1 || idx
>= UNCORE_PMC_IDX_MAX
))
3005 event
->hw
.state
= 0;
3006 box
->events
[idx
] = event
;
3008 __set_bit(idx
, box
->active_mask
);
3010 local64_set(&event
->hw
.prev_count
, uncore_read_counter(box
, event
));
3011 uncore_enable_event(box
, event
);
3013 if (box
->n_active
== 1) {
3014 uncore_enable_box(box
);
3015 uncore_pmu_start_hrtimer(box
);
3019 static void uncore_pmu_event_stop(struct perf_event
*event
, int flags
)
3021 struct intel_uncore_box
*box
= uncore_event_to_box(event
);
3022 struct hw_perf_event
*hwc
= &event
->hw
;
3024 if (__test_and_clear_bit(hwc
->idx
, box
->active_mask
)) {
3025 uncore_disable_event(box
, event
);
3027 box
->events
[hwc
->idx
] = NULL
;
3028 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
3029 hwc
->state
|= PERF_HES_STOPPED
;
3031 if (box
->n_active
== 0) {
3032 uncore_disable_box(box
);
3033 uncore_pmu_cancel_hrtimer(box
);
3037 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
3039 * Drain the remaining delta count out of a event
3040 * that we are disabling:
3042 uncore_perf_event_update(box
, event
);
3043 hwc
->state
|= PERF_HES_UPTODATE
;
3047 static int uncore_pmu_event_add(struct perf_event
*event
, int flags
)
3049 struct intel_uncore_box
*box
= uncore_event_to_box(event
);
3050 struct hw_perf_event
*hwc
= &event
->hw
;
3051 int assign
[UNCORE_PMC_IDX_MAX
];
3057 ret
= n
= uncore_collect_events(box
, event
, false);
3061 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
3062 if (!(flags
& PERF_EF_START
))
3063 hwc
->state
|= PERF_HES_ARCH
;
3065 ret
= uncore_assign_events(box
, assign
, n
);
3069 /* save events moving to new counters */
3070 for (i
= 0; i
< box
->n_events
; i
++) {
3071 event
= box
->event_list
[i
];
3074 if (hwc
->idx
== assign
[i
] &&
3075 hwc
->last_tag
== box
->tags
[assign
[i
]])
3078 * Ensure we don't accidentally enable a stopped
3079 * counter simply because we rescheduled.
3081 if (hwc
->state
& PERF_HES_STOPPED
)
3082 hwc
->state
|= PERF_HES_ARCH
;
3084 uncore_pmu_event_stop(event
, PERF_EF_UPDATE
);
3087 /* reprogram moved events into new counters */
3088 for (i
= 0; i
< n
; i
++) {
3089 event
= box
->event_list
[i
];
3092 if (hwc
->idx
!= assign
[i
] ||
3093 hwc
->last_tag
!= box
->tags
[assign
[i
]])
3094 uncore_assign_hw_event(box
, event
, assign
[i
]);
3095 else if (i
< box
->n_events
)
3098 if (hwc
->state
& PERF_HES_ARCH
)
3101 uncore_pmu_event_start(event
, 0);
3108 static void uncore_pmu_event_del(struct perf_event
*event
, int flags
)
3110 struct intel_uncore_box
*box
= uncore_event_to_box(event
);
3113 uncore_pmu_event_stop(event
, PERF_EF_UPDATE
);
3115 for (i
= 0; i
< box
->n_events
; i
++) {
3116 if (event
== box
->event_list
[i
]) {
3117 uncore_put_event_constraint(box
, event
);
3119 while (++i
< box
->n_events
)
3120 box
->event_list
[i
- 1] = box
->event_list
[i
];
3128 event
->hw
.last_tag
= ~0ULL;
3131 static void uncore_pmu_event_read(struct perf_event
*event
)
3133 struct intel_uncore_box
*box
= uncore_event_to_box(event
);
3134 uncore_perf_event_update(box
, event
);
3138 * validation ensures the group can be loaded onto the
3139 * PMU if it was the only group available.
3141 static int uncore_validate_group(struct intel_uncore_pmu
*pmu
,
3142 struct perf_event
*event
)
3144 struct perf_event
*leader
= event
->group_leader
;
3145 struct intel_uncore_box
*fake_box
;
3146 int ret
= -EINVAL
, n
;
3148 fake_box
= uncore_alloc_box(pmu
->type
, NUMA_NO_NODE
);
3152 fake_box
->pmu
= pmu
;
3154 * the event is not yet connected with its
3155 * siblings therefore we must first collect
3156 * existing siblings, then add the new event
3157 * before we can simulate the scheduling
3159 n
= uncore_collect_events(fake_box
, leader
, true);
3163 fake_box
->n_events
= n
;
3164 n
= uncore_collect_events(fake_box
, event
, false);
3168 fake_box
->n_events
= n
;
3170 ret
= uncore_assign_events(fake_box
, NULL
, n
);
3176 static int uncore_pmu_event_init(struct perf_event
*event
)
3178 struct intel_uncore_pmu
*pmu
;
3179 struct intel_uncore_box
*box
;
3180 struct hw_perf_event
*hwc
= &event
->hw
;
3183 if (event
->attr
.type
!= event
->pmu
->type
)
3186 pmu
= uncore_event_to_pmu(event
);
3187 /* no device found for this pmu */
3188 if (pmu
->func_id
< 0)
3192 * Uncore PMU does measure at all privilege level all the time.
3193 * So it doesn't make sense to specify any exclude bits.
3195 if (event
->attr
.exclude_user
|| event
->attr
.exclude_kernel
||
3196 event
->attr
.exclude_hv
|| event
->attr
.exclude_idle
)
3199 /* Sampling not supported yet */
3200 if (hwc
->sample_period
)
3204 * Place all uncore events for a particular physical package
3209 box
= uncore_pmu_to_box(pmu
, event
->cpu
);
3210 if (!box
|| box
->cpu
< 0)
3212 event
->cpu
= box
->cpu
;
3215 event
->hw
.last_tag
= ~0ULL;
3216 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
3217 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
3219 if (event
->attr
.config
== UNCORE_FIXED_EVENT
) {
3220 /* no fixed counter */
3221 if (!pmu
->type
->fixed_ctl
)
3224 * if there is only one fixed counter, only the first pmu
3225 * can access the fixed counter
3227 if (pmu
->type
->single_fixed
&& pmu
->pmu_idx
> 0)
3230 /* fixed counters have event field hardcoded to zero */
3233 hwc
->config
= event
->attr
.config
& pmu
->type
->event_mask
;
3234 if (pmu
->type
->ops
->hw_config
) {
3235 ret
= pmu
->type
->ops
->hw_config(box
, event
);
3241 if (event
->group_leader
!= event
)
3242 ret
= uncore_validate_group(pmu
, event
);
3249 static ssize_t
uncore_get_attr_cpumask(struct device
*dev
,
3250 struct device_attribute
*attr
, char *buf
)
3252 int n
= cpulist_scnprintf(buf
, PAGE_SIZE
- 2, &uncore_cpu_mask
);
3259 static DEVICE_ATTR(cpumask
, S_IRUGO
, uncore_get_attr_cpumask
, NULL
);
3261 static struct attribute
*uncore_pmu_attrs
[] = {
3262 &dev_attr_cpumask
.attr
,
3266 static struct attribute_group uncore_pmu_attr_group
= {
3267 .attrs
= uncore_pmu_attrs
,
3270 static int __init
uncore_pmu_register(struct intel_uncore_pmu
*pmu
)
3274 pmu
->pmu
= (struct pmu
) {
3275 .attr_groups
= pmu
->type
->attr_groups
,
3276 .task_ctx_nr
= perf_invalid_context
,
3277 .event_init
= uncore_pmu_event_init
,
3278 .add
= uncore_pmu_event_add
,
3279 .del
= uncore_pmu_event_del
,
3280 .start
= uncore_pmu_event_start
,
3281 .stop
= uncore_pmu_event_stop
,
3282 .read
= uncore_pmu_event_read
,
3285 if (pmu
->type
->num_boxes
== 1) {
3286 if (strlen(pmu
->type
->name
) > 0)
3287 sprintf(pmu
->name
, "uncore_%s", pmu
->type
->name
);
3289 sprintf(pmu
->name
, "uncore");
3291 sprintf(pmu
->name
, "uncore_%s_%d", pmu
->type
->name
,
3295 ret
= perf_pmu_register(&pmu
->pmu
, pmu
->name
, -1);
3299 static void __init
uncore_type_exit(struct intel_uncore_type
*type
)
3303 for (i
= 0; i
< type
->num_boxes
; i
++)
3304 free_percpu(type
->pmus
[i
].box
);
3307 kfree(type
->events_group
);
3308 type
->events_group
= NULL
;
3311 static void __init
uncore_types_exit(struct intel_uncore_type
**types
)
3314 for (i
= 0; types
[i
]; i
++)
3315 uncore_type_exit(types
[i
]);
3318 static int __init
uncore_type_init(struct intel_uncore_type
*type
)
3320 struct intel_uncore_pmu
*pmus
;
3321 struct attribute_group
*attr_group
;
3322 struct attribute
**attrs
;
3325 pmus
= kzalloc(sizeof(*pmus
) * type
->num_boxes
, GFP_KERNEL
);
3329 type
->unconstrainted
= (struct event_constraint
)
3330 __EVENT_CONSTRAINT(0, (1ULL << type
->num_counters
) - 1,
3331 0, type
->num_counters
, 0, 0);
3333 for (i
= 0; i
< type
->num_boxes
; i
++) {
3334 pmus
[i
].func_id
= -1;
3335 pmus
[i
].pmu_idx
= i
;
3336 pmus
[i
].type
= type
;
3337 INIT_LIST_HEAD(&pmus
[i
].box_list
);
3338 pmus
[i
].box
= alloc_percpu(struct intel_uncore_box
*);
3343 if (type
->event_descs
) {
3345 while (type
->event_descs
[i
].attr
.attr
.name
)
3348 attr_group
= kzalloc(sizeof(struct attribute
*) * (i
+ 1) +
3349 sizeof(*attr_group
), GFP_KERNEL
);
3353 attrs
= (struct attribute
**)(attr_group
+ 1);
3354 attr_group
->name
= "events";
3355 attr_group
->attrs
= attrs
;
3357 for (j
= 0; j
< i
; j
++)
3358 attrs
[j
] = &type
->event_descs
[j
].attr
.attr
;
3360 type
->events_group
= attr_group
;
3363 type
->pmu_group
= &uncore_pmu_attr_group
;
3367 uncore_type_exit(type
);
3371 static int __init
uncore_types_init(struct intel_uncore_type
**types
)
3375 for (i
= 0; types
[i
]; i
++) {
3376 ret
= uncore_type_init(types
[i
]);
3383 uncore_type_exit(types
[i
]);
3387 static struct pci_driver
*uncore_pci_driver
;
3388 static bool pcidrv_registered
;
3391 * add a pci uncore device
3393 static int uncore_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
3395 struct intel_uncore_pmu
*pmu
;
3396 struct intel_uncore_box
*box
;
3397 struct intel_uncore_type
*type
;
3400 phys_id
= pcibus_to_physid
[pdev
->bus
->number
];
3404 if (UNCORE_PCI_DEV_TYPE(id
->driver_data
) == UNCORE_EXTRA_PCI_DEV
) {
3405 extra_pci_dev
[phys_id
][UNCORE_PCI_DEV_IDX(id
->driver_data
)] = pdev
;
3406 pci_set_drvdata(pdev
, NULL
);
3410 type
= pci_uncores
[UNCORE_PCI_DEV_TYPE(id
->driver_data
)];
3411 box
= uncore_alloc_box(type
, NUMA_NO_NODE
);
3416 * for performance monitoring unit with multiple boxes,
3417 * each box has a different function id.
3419 pmu
= &type
->pmus
[UNCORE_PCI_DEV_IDX(id
->driver_data
)];
3420 if (pmu
->func_id
< 0)
3421 pmu
->func_id
= pdev
->devfn
;
3423 WARN_ON_ONCE(pmu
->func_id
!= pdev
->devfn
);
3425 box
->phys_id
= phys_id
;
3426 box
->pci_dev
= pdev
;
3428 uncore_box_init(box
);
3429 pci_set_drvdata(pdev
, box
);
3431 raw_spin_lock(&uncore_box_lock
);
3432 list_add_tail(&box
->list
, &pmu
->box_list
);
3433 raw_spin_unlock(&uncore_box_lock
);
3438 static void uncore_pci_remove(struct pci_dev
*pdev
)
3440 struct intel_uncore_box
*box
= pci_get_drvdata(pdev
);
3441 struct intel_uncore_pmu
*pmu
;
3442 int i
, cpu
, phys_id
= pcibus_to_physid
[pdev
->bus
->number
];
3444 box
= pci_get_drvdata(pdev
);
3446 for (i
= 0; i
< UNCORE_EXTRA_PCI_DEV_MAX
; i
++) {
3447 if (extra_pci_dev
[phys_id
][i
] == pdev
) {
3448 extra_pci_dev
[phys_id
][i
] = NULL
;
3452 WARN_ON_ONCE(i
>= UNCORE_EXTRA_PCI_DEV_MAX
);
3457 if (WARN_ON_ONCE(phys_id
!= box
->phys_id
))
3460 pci_set_drvdata(pdev
, NULL
);
3462 raw_spin_lock(&uncore_box_lock
);
3463 list_del(&box
->list
);
3464 raw_spin_unlock(&uncore_box_lock
);
3466 for_each_possible_cpu(cpu
) {
3467 if (*per_cpu_ptr(pmu
->box
, cpu
) == box
) {
3468 *per_cpu_ptr(pmu
->box
, cpu
) = NULL
;
3469 atomic_dec(&box
->refcnt
);
3473 WARN_ON_ONCE(atomic_read(&box
->refcnt
) != 1);
3477 static int __init
uncore_pci_init(void)
3481 switch (boot_cpu_data
.x86_model
) {
3482 case 45: /* Sandy Bridge-EP */
3483 ret
= snbep_pci2phy_map_init(0x3ce0);
3486 pci_uncores
= snbep_pci_uncores
;
3487 uncore_pci_driver
= &snbep_uncore_pci_driver
;
3489 case 62: /* IvyTown */
3490 ret
= snbep_pci2phy_map_init(0x0e1e);
3493 pci_uncores
= ivt_pci_uncores
;
3494 uncore_pci_driver
= &ivt_uncore_pci_driver
;
3500 ret
= uncore_types_init(pci_uncores
);
3504 uncore_pci_driver
->probe
= uncore_pci_probe
;
3505 uncore_pci_driver
->remove
= uncore_pci_remove
;
3507 ret
= pci_register_driver(uncore_pci_driver
);
3509 pcidrv_registered
= true;
3511 uncore_types_exit(pci_uncores
);
3516 static void __init
uncore_pci_exit(void)
3518 if (pcidrv_registered
) {
3519 pcidrv_registered
= false;
3520 pci_unregister_driver(uncore_pci_driver
);
3521 uncore_types_exit(pci_uncores
);
3525 /* CPU hot plug/unplug are serialized by cpu_add_remove_lock mutex */
3526 static LIST_HEAD(boxes_to_free
);
3528 static void uncore_kfree_boxes(void)
3530 struct intel_uncore_box
*box
;
3532 while (!list_empty(&boxes_to_free
)) {
3533 box
= list_entry(boxes_to_free
.next
,
3534 struct intel_uncore_box
, list
);
3535 list_del(&box
->list
);
3540 static void uncore_cpu_dying(int cpu
)
3542 struct intel_uncore_type
*type
;
3543 struct intel_uncore_pmu
*pmu
;
3544 struct intel_uncore_box
*box
;
3547 for (i
= 0; msr_uncores
[i
]; i
++) {
3548 type
= msr_uncores
[i
];
3549 for (j
= 0; j
< type
->num_boxes
; j
++) {
3550 pmu
= &type
->pmus
[j
];
3551 box
= *per_cpu_ptr(pmu
->box
, cpu
);
3552 *per_cpu_ptr(pmu
->box
, cpu
) = NULL
;
3553 if (box
&& atomic_dec_and_test(&box
->refcnt
))
3554 list_add(&box
->list
, &boxes_to_free
);
3559 static int uncore_cpu_starting(int cpu
)
3561 struct intel_uncore_type
*type
;
3562 struct intel_uncore_pmu
*pmu
;
3563 struct intel_uncore_box
*box
, *exist
;
3564 int i
, j
, k
, phys_id
;
3566 phys_id
= topology_physical_package_id(cpu
);
3568 for (i
= 0; msr_uncores
[i
]; i
++) {
3569 type
= msr_uncores
[i
];
3570 for (j
= 0; j
< type
->num_boxes
; j
++) {
3571 pmu
= &type
->pmus
[j
];
3572 box
= *per_cpu_ptr(pmu
->box
, cpu
);
3573 /* called by uncore_cpu_init? */
3574 if (box
&& box
->phys_id
>= 0) {
3575 uncore_box_init(box
);
3579 for_each_online_cpu(k
) {
3580 exist
= *per_cpu_ptr(pmu
->box
, k
);
3581 if (exist
&& exist
->phys_id
== phys_id
) {
3582 atomic_inc(&exist
->refcnt
);
3583 *per_cpu_ptr(pmu
->box
, cpu
) = exist
;
3585 list_add(&box
->list
,
3594 box
->phys_id
= phys_id
;
3595 uncore_box_init(box
);
3602 static int uncore_cpu_prepare(int cpu
, int phys_id
)
3604 struct intel_uncore_type
*type
;
3605 struct intel_uncore_pmu
*pmu
;
3606 struct intel_uncore_box
*box
;
3609 for (i
= 0; msr_uncores
[i
]; i
++) {
3610 type
= msr_uncores
[i
];
3611 for (j
= 0; j
< type
->num_boxes
; j
++) {
3612 pmu
= &type
->pmus
[j
];
3613 if (pmu
->func_id
< 0)
3616 box
= uncore_alloc_box(type
, cpu_to_node(cpu
));
3621 box
->phys_id
= phys_id
;
3622 *per_cpu_ptr(pmu
->box
, cpu
) = box
;
3629 uncore_change_context(struct intel_uncore_type
**uncores
, int old_cpu
, int new_cpu
)
3631 struct intel_uncore_type
*type
;
3632 struct intel_uncore_pmu
*pmu
;
3633 struct intel_uncore_box
*box
;
3636 for (i
= 0; uncores
[i
]; i
++) {
3638 for (j
= 0; j
< type
->num_boxes
; j
++) {
3639 pmu
= &type
->pmus
[j
];
3641 box
= uncore_pmu_to_box(pmu
, new_cpu
);
3643 box
= uncore_pmu_to_box(pmu
, old_cpu
);
3648 WARN_ON_ONCE(box
->cpu
!= -1);
3653 WARN_ON_ONCE(box
->cpu
!= old_cpu
);
3655 uncore_pmu_cancel_hrtimer(box
);
3656 perf_pmu_migrate_context(&pmu
->pmu
,
3666 static void uncore_event_exit_cpu(int cpu
)
3668 int i
, phys_id
, target
;
3670 /* if exiting cpu is used for collecting uncore events */
3671 if (!cpumask_test_and_clear_cpu(cpu
, &uncore_cpu_mask
))
3674 /* find a new cpu to collect uncore events */
3675 phys_id
= topology_physical_package_id(cpu
);
3677 for_each_online_cpu(i
) {
3680 if (phys_id
== topology_physical_package_id(i
)) {
3686 /* migrate uncore events to the new cpu */
3688 cpumask_set_cpu(target
, &uncore_cpu_mask
);
3690 uncore_change_context(msr_uncores
, cpu
, target
);
3691 uncore_change_context(pci_uncores
, cpu
, target
);
3694 static void uncore_event_init_cpu(int cpu
)
3698 phys_id
= topology_physical_package_id(cpu
);
3699 for_each_cpu(i
, &uncore_cpu_mask
) {
3700 if (phys_id
== topology_physical_package_id(i
))
3704 cpumask_set_cpu(cpu
, &uncore_cpu_mask
);
3706 uncore_change_context(msr_uncores
, -1, cpu
);
3707 uncore_change_context(pci_uncores
, -1, cpu
);
3710 static int uncore_cpu_notifier(struct notifier_block
*self
,
3711 unsigned long action
, void *hcpu
)
3713 unsigned int cpu
= (long)hcpu
;
3715 /* allocate/free data structure for uncore box */
3716 switch (action
& ~CPU_TASKS_FROZEN
) {
3717 case CPU_UP_PREPARE
:
3718 uncore_cpu_prepare(cpu
, -1);
3721 uncore_cpu_starting(cpu
);
3723 case CPU_UP_CANCELED
:
3725 uncore_cpu_dying(cpu
);
3729 uncore_kfree_boxes();
3735 /* select the cpu that collects uncore events */
3736 switch (action
& ~CPU_TASKS_FROZEN
) {
3737 case CPU_DOWN_FAILED
:
3739 uncore_event_init_cpu(cpu
);
3741 case CPU_DOWN_PREPARE
:
3742 uncore_event_exit_cpu(cpu
);
3751 static struct notifier_block uncore_cpu_nb
= {
3752 .notifier_call
= uncore_cpu_notifier
,
3754 * to migrate uncore events, our notifier should be executed
3755 * before perf core's notifier.
3757 .priority
= CPU_PRI_PERF
+ 1,
3760 static void __init
uncore_cpu_setup(void *dummy
)
3762 uncore_cpu_starting(smp_processor_id());
3765 static int __init
uncore_cpu_init(void)
3767 int ret
, cpu
, max_cores
;
3769 max_cores
= boot_cpu_data
.x86_max_cores
;
3770 switch (boot_cpu_data
.x86_model
) {
3771 case 26: /* Nehalem */
3773 case 37: /* Westmere */
3775 msr_uncores
= nhm_msr_uncores
;
3777 case 42: /* Sandy Bridge */
3778 case 58: /* Ivy Bridge */
3779 if (snb_uncore_cbox
.num_boxes
> max_cores
)
3780 snb_uncore_cbox
.num_boxes
= max_cores
;
3781 msr_uncores
= snb_msr_uncores
;
3783 case 45: /* Sandy Bridge-EP */
3784 if (snbep_uncore_cbox
.num_boxes
> max_cores
)
3785 snbep_uncore_cbox
.num_boxes
= max_cores
;
3786 msr_uncores
= snbep_msr_uncores
;
3788 case 46: /* Nehalem-EX */
3789 uncore_nhmex
= true;
3790 case 47: /* Westmere-EX aka. Xeon E7 */
3792 nhmex_uncore_mbox
.event_descs
= wsmex_uncore_mbox_events
;
3793 if (nhmex_uncore_cbox
.num_boxes
> max_cores
)
3794 nhmex_uncore_cbox
.num_boxes
= max_cores
;
3795 msr_uncores
= nhmex_msr_uncores
;
3797 case 62: /* IvyTown */
3798 if (ivt_uncore_cbox
.num_boxes
> max_cores
)
3799 ivt_uncore_cbox
.num_boxes
= max_cores
;
3800 msr_uncores
= ivt_msr_uncores
;
3807 ret
= uncore_types_init(msr_uncores
);
3813 for_each_online_cpu(cpu
) {
3814 int i
, phys_id
= topology_physical_package_id(cpu
);
3816 for_each_cpu(i
, &uncore_cpu_mask
) {
3817 if (phys_id
== topology_physical_package_id(i
)) {
3825 uncore_cpu_prepare(cpu
, phys_id
);
3826 uncore_event_init_cpu(cpu
);
3828 on_each_cpu(uncore_cpu_setup
, NULL
, 1);
3830 register_cpu_notifier(&uncore_cpu_nb
);
3837 static int __init
uncore_pmus_register(void)
3839 struct intel_uncore_pmu
*pmu
;
3840 struct intel_uncore_type
*type
;
3843 for (i
= 0; msr_uncores
[i
]; i
++) {
3844 type
= msr_uncores
[i
];
3845 for (j
= 0; j
< type
->num_boxes
; j
++) {
3846 pmu
= &type
->pmus
[j
];
3847 uncore_pmu_register(pmu
);
3851 for (i
= 0; pci_uncores
[i
]; i
++) {
3852 type
= pci_uncores
[i
];
3853 for (j
= 0; j
< type
->num_boxes
; j
++) {
3854 pmu
= &type
->pmus
[j
];
3855 uncore_pmu_register(pmu
);
3862 static int __init
intel_uncore_init(void)
3866 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
)
3869 if (cpu_has_hypervisor
)
3872 ret
= uncore_pci_init();
3875 ret
= uncore_cpu_init();
3881 uncore_pmus_register();
3886 device_initcall(intel_uncore_init
);