arch/x86/kernel/head_64.S

   1 /*
   2  *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
   3  *
   4  *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
   5  *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
   6  *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
   7  *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
   8  *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
   9  */
  10
  11
  12 #include <linux/linkage.h>
  13 #include <linux/threads.h>
  14 #include <linux/init.h>
  15 #include <asm/desc.h>
  16 #include <asm/segment.h>
  17 #include <asm/pgtable.h>
  18 #include <asm/page.h>
  19 #include <asm/msr.h>
  20 #include <asm/cache.h>
  21
  22 #ifdef CONFIG_PARAVIRT
  23 #include <asm/asm-offsets.h>
  24 #include <asm/paravirt.h>
  25 #else
  26 #define GET_CR2_INTO_RCX movq %cr2, %rcx
  27 #endif
  28
  29 /* we are not able to switch in one step to the final KERNEL ADRESS SPACE
  30  * because we need identity-mapped pages.
  31  *
  32  */
  33
  34         .text
  35         .section .text.head
  36         .code64
  37         .globl startup_64
  38 startup_64:
  39
  40         /*
  41          * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
  42          * and someone has loaded an identity mapped page table
  43          * for us.  These identity mapped page tables map all of the
  44          * kernel pages and possibly all of memory.
  45          *
  46          * %esi holds a physical pointer to real_mode_data.
  47          *
  48          * We come here either directly from a 64bit bootloader, or from
  49          * arch/x86_64/boot/compressed/head.S.
  50          *
  51          * We only come here initially at boot nothing else comes here.
  52          *
  53          * Since we may be loaded at an address different from what we were
  54          * compiled to run at we first fixup the physical addresses in our page
  55          * tables and then reload them.
  56          */
  57
  58         /* Compute the delta between the address I am compiled to run at and the
  59          * address I am actually running at.
  60          */
  61         leaq    _text(%rip), %rbp
  62         subq    $_text - __START_KERNEL_map, %rbp
  63
  64         /* Is the address not 2M aligned? */
  65         movq    %rbp, %rax
  66         andl    $~LARGE_PAGE_MASK, %eax
  67         testl   %eax, %eax
  68         jnz     bad_address
  69
  70         /* Is the address too large? */
  71         leaq    _text(%rip), %rdx
  72         movq    $PGDIR_SIZE, %rax
  73         cmpq    %rax, %rdx
  74         jae     bad_address
  75
  76         /* Fixup the physical addresses in the page table
  77          */
  78         addq    %rbp, init_level4_pgt + 0(%rip)
  79         addq    %rbp, init_level4_pgt + (258*8)(%rip)
  80         addq    %rbp, init_level4_pgt + (511*8)(%rip)
  81
  82         addq    %rbp, level3_ident_pgt + 0(%rip)
  83
  84         addq    %rbp, level3_kernel_pgt + (510*8)(%rip)
  85         addq    %rbp, level3_kernel_pgt + (511*8)(%rip)
  86
  87         addq    %rbp, level2_fixmap_pgt + (506*8)(%rip)
  88
  89         /* Add an Identity mapping if I am above 1G */
  90         leaq    _text(%rip), %rdi
  91         andq    $LARGE_PAGE_MASK, %rdi
  92
  93         movq    %rdi, %rax
  94         shrq    $PUD_SHIFT, %rax
  95         andq    $(PTRS_PER_PUD - 1), %rax
  96         jz      ident_complete
  97
  98         leaq    (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
  99         leaq    level3_ident_pgt(%rip), %rbx
 100         movq    %rdx, 0(%rbx, %rax, 8)
 101
 102         movq    %rdi, %rax
 103         shrq    $PMD_SHIFT, %rax
 104         andq    $(PTRS_PER_PMD - 1), %rax
 105         leaq    __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
 106         leaq    level2_spare_pgt(%rip), %rbx
 107         movq    %rdx, 0(%rbx, %rax, 8)
 108 ident_complete:
 109
 110         /* Fixup the kernel text+data virtual addresses
 111          */
 112         leaq    level2_kernel_pgt(%rip), %rdi
 113         leaq    4096(%rdi), %r8
 114         /* See if it is a valid page table entry */
 115 1:      testq   $1, 0(%rdi)
 116         jz      2f
 117         addq    %rbp, 0(%rdi)
 118         /* Go to the next page */
 119 2:      addq    $8, %rdi
 120         cmp     %r8, %rdi
 121         jne     1b
 122
 123         /* Fixup phys_base */
 124         addq    %rbp, phys_base(%rip)
 125
 126 #ifdef CONFIG_SMP
 127         addq    %rbp, trampoline_level4_pgt + 0(%rip)
 128         addq    %rbp, trampoline_level4_pgt + (511*8)(%rip)
 129 #endif
 130 #ifdef CONFIG_ACPI_SLEEP
 131         addq    %rbp, wakeup_level4_pgt + 0(%rip)
 132         addq    %rbp, wakeup_level4_pgt + (511*8)(%rip)
 133 #endif
 134
 135         /* Due to ENTRY(), sometimes the empty space gets filled with
 136          * zeros. Better take a jmp than relying on empty space being
 137          * filled with 0x90 (nop)
 138          */
 139         jmp secondary_startup_64
 140 ENTRY(secondary_startup_64)
 141         /*
 142          * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
 143          * and someone has loaded a mapped page table.
 144          *
 145          * %esi holds a physical pointer to real_mode_data.
 146          *
 147          * We come here either from startup_64 (using physical addresses)
 148          * or from trampoline.S (using virtual addresses).
 149          *
 150          * Using virtual addresses from trampoline.S removes the need
 151          * to have any identity mapped pages in the kernel page table
 152          * after the boot processor executes this code.
 153          */
 154
 155         /* Enable PAE mode and PGE */
 156         xorq    %rax, %rax
 157         btsq    $5, %rax
 158         btsq    $7, %rax
 159         movq    %rax, %cr4
 160
 161         /* Setup early boot stage 4 level pagetables. */
 162         movq    $(init_level4_pgt - __START_KERNEL_map), %rax
 163         addq    phys_base(%rip), %rax
 164         movq    %rax, %cr3
 165
 166         /* Ensure I am executing from virtual addresses */
 167         movq    $1f, %rax
 168         jmp     *%rax
 169 1:
 170
 171         /* Check if nx is implemented */
 172         movl    $0x80000001, %eax
 173         cpuid
 174         movl    %edx,%edi
 175
 176         /* Setup EFER (Extended Feature Enable Register) */
 177         movl    $MSR_EFER, %ecx
 178         rdmsr
 179         btsl    $_EFER_SCE, %eax        /* Enable System Call */
 180         btl     $20,%edi                /* No Execute supported? */
 181         jnc     1f
 182         btsl    $_EFER_NX, %eax
 183 1:      wrmsr                           /* Make changes effective */
 184
 185         /* Setup cr0 */
 186 #define CR0_PM                          1               /* protected mode */
 187 #define CR0_MP                          (1<<1)
 188 #define CR0_ET                          (1<<4)
 189 #define CR0_NE                          (1<<5)
 190 #define CR0_WP                          (1<<16)
 191 #define CR0_AM                          (1<<18)
 192 #define CR0_PAGING                      (1<<31)
 193         movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
 194         /* Make changes effective */
 195         movq    %rax, %cr0
 196
 197         /* Setup a boot time stack */
 198         movq init_rsp(%rip),%rsp
 199
 200         /* zero EFLAGS after setting rsp */
 201         pushq $0
 202         popfq
 203
 204         /*
 205          * We must switch to a new descriptor in kernel space for the GDT
 206          * because soon the kernel won't have access anymore to the userspace
 207          * addresses where we're currently running on. We have to do that here
 208          * because in 32bit we couldn't load a 64bit linear address.
 209          */
 210         lgdt    cpu_gdt_descr(%rip)
 211
 212         /* set up data segments. actually 0 would do too */
 213         movl $__KERNEL_DS,%eax
 214         movl %eax,%ds
 215         movl %eax,%ss
 216         movl %eax,%es
 217
 218         /*
 219          * We don't really need to load %fs or %gs, but load them anyway
 220          * to kill any stale realmode selectors.  This allows execution
 221          * under VT hardware.
 222          */
 223         movl %eax,%fs
 224         movl %eax,%gs
 225
 226         /*
 227          * Setup up a dummy PDA. this is just for some early bootup code
 228          * that does in_interrupt()
 229          */
 230         movl    $MSR_GS_BASE,%ecx
 231         movq    $empty_zero_page,%rax
 232         movq    %rax,%rdx
 233         shrq    $32,%rdx
 234         wrmsr
 235
 236         /* esi is pointer to real mode structure with interesting info.
 237            pass it to C */
 238         movl    %esi, %edi
 239
 240         /* Finally jump to run C code and to be on real kernel address
 241          * Since we are running on identity-mapped space we have to jump
 242          * to the full 64bit address, this is only possible as indirect
 243          * jump.  In addition we need to ensure %cs is set so we make this
 244          * a far return.
 245          */
 246         movq    initial_code(%rip),%rax
 247         pushq   $0              # fake return address to stop unwinder
 248         pushq   $__KERNEL_CS    # set correct cs
 249         pushq   %rax            # target address in negative space
 250         lretq
 251
 252         /* SMP bootup changes these two */
 253 #ifndef CONFIG_HOTPLUG_CPU
 254         .pushsection .init.data
 255 #endif
 256         .align  8
 257         .globl  initial_code
 258 initial_code:
 259         .quad   x86_64_start_kernel
 260 #ifndef CONFIG_HOTPLUG_CPU
 261         .popsection
 262 #endif
 263         .globl init_rsp
 264 init_rsp:
 265         .quad  init_thread_union+THREAD_SIZE-8
 266
 267 bad_address:
 268         jmp bad_address
 269
 270 #ifdef CONFIG_EARLY_PRINTK
 271 .macro early_idt_tramp first, last
 272         .ifgt \last-\first
 273         early_idt_tramp \first, \last-1
 274         .endif
 275         movl $\last,%esi
 276         jmp early_idt_handler
 277 .endm
 278
 279         .globl early_idt_handlers
 280 early_idt_handlers:
 281         early_idt_tramp 0, 63
 282         early_idt_tramp 64, 127
 283         early_idt_tramp 128, 191
 284         early_idt_tramp 192, 255
 285 #endif
 286
 287 ENTRY(early_idt_handler)
 288 #ifdef CONFIG_EARLY_PRINTK
 289         cmpl $2,early_recursion_flag(%rip)
 290         jz  1f
 291         incl early_recursion_flag(%rip)
 292         GET_CR2_INTO_RCX
 293         movq %rcx,%r9
 294         xorl %r8d,%r8d          # zero for error code
 295         movl %esi,%ecx          # get vector number
 296         # Test %ecx against mask of vectors that push error code.
 297         cmpl $31,%ecx
 298         ja 0f
 299         movl $1,%eax
 300         salq %cl,%rax
 301         testl $0x27d00,%eax
 302         je 0f
 303         popq %r8                # get error code
 304 0:      movq 0(%rsp),%rcx       # get ip
 305         movq 8(%rsp),%rdx       # get cs
 306         xorl %eax,%eax
 307         leaq early_idt_msg(%rip),%rdi
 308         call early_printk
 309         cmpl $2,early_recursion_flag(%rip)
 310         jz  1f
 311         call dump_stack
 312 #ifdef CONFIG_KALLSYMS
 313         leaq early_idt_ripmsg(%rip),%rdi
 314         movq 8(%rsp),%rsi       # get rip again
 315         call __print_symbol
 316 #endif
 317 #endif /* EARLY_PRINTK */
 318 1:      hlt
 319         jmp 1b
 320
 321 #ifdef CONFIG_EARLY_PRINTK
 322 early_recursion_flag:
 323         .long 0
 324
 325 early_idt_msg:
 326         .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
 327 early_idt_ripmsg:
 328         .asciz "RIP %s\n"
 329 #endif /* CONFIG_EARLY_PRINTK */
 330
 331 .balign PAGE_SIZE
 332
 333 #define NEXT_PAGE(name) \
 334         .balign PAGE_SIZE; \
 335 ENTRY(name)
 336
 337 /* Automate the creation of 1 to 1 mapping pmd entries */
 338 #define PMDS(START, PERM, COUNT)                \
 339         i = 0 ;                                 \
 340         .rept (COUNT) ;                         \
 341         .quad   (START) + (i << 21) + (PERM) ;  \
 342         i = i + 1 ;                             \
 343         .endr
 344
 345         /*
 346          * This default setting generates an ident mapping at address 0x100000
 347          * and a mapping for the kernel that precisely maps virtual address
 348          * 0xffffffff80000000 to physical address 0x000000. (always using
 349          * 2Mbyte large pages provided by PAE mode)
 350          */
 351 NEXT_PAGE(init_level4_pgt)
 352         .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
 353         .fill   257,8,0
 354         .quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
 355         .fill   252,8,0
 356         /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
 357         .quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
 358
 359 NEXT_PAGE(level3_ident_pgt)
 360         .quad   level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
 361         .fill   511,8,0
 362
 363 NEXT_PAGE(level3_kernel_pgt)
 364         .fill   510,8,0
 365         /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
 366         .quad   level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
 367         .quad   level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
 368
 369 NEXT_PAGE(level2_fixmap_pgt)
 370         .fill   506,8,0
 371         .quad   level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
 372         /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
 373         .fill   5,8,0
 374
 375 NEXT_PAGE(level1_fixmap_pgt)
 376         .fill   512,8,0
 377
 378 NEXT_PAGE(level2_ident_pgt)
 379         /* Since I easily can, map the first 1G.
 380          * Don't set NX because code runs from these pages.
 381          */
 382         PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)
 383
 384 NEXT_PAGE(level2_kernel_pgt)
 385         /* 40MB kernel mapping. The kernel code cannot be bigger than that.
 386            When you change this change KERNEL_TEXT_SIZE in page.h too. */
 387         /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
 388         PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL, KERNEL_TEXT_SIZE/PMD_SIZE)
 389         /* Module mapping starts here */
 390         .fill   (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0
 391
 392 NEXT_PAGE(level2_spare_pgt)
 393         .fill   512,8,0
 394
 395 #undef PMDS
 396 #undef NEXT_PAGE
 397
 398         .data
 399         .align 16
 400         .globl cpu_gdt_descr
 401 cpu_gdt_descr:
 402         .word   gdt_end-cpu_gdt_table-1
 403 gdt:
 404         .quad   cpu_gdt_table
 405 #ifdef CONFIG_SMP
 406         .rept   NR_CPUS-1
 407         .word   0
 408         .quad   0
 409         .endr
 410 #endif
 411
 412 ENTRY(phys_base)
 413         /* This must match the first entry in level2_kernel_pgt */
 414         .quad   0x0000000000000000
 415
 416 /* We need valid kernel segments for data and code in long mode too
 417  * IRET will check the segment types  kkeil 2000/10/28
 418  * Also sysret mandates a special GDT layout
 419  */
 420
 421         .section .data.page_aligned, "aw"
 422         .align PAGE_SIZE
 423
 424 /* The TLS descriptors are currently at a different place compared to i386.
 425    Hopefully nobody expects them at a fixed place (Wine?) */
 426
 427 ENTRY(cpu_gdt_table)
 428         .quad   0x0000000000000000      /* NULL descriptor */
 429         .quad   0x00cf9b000000ffff      /* __KERNEL32_CS */
 430         .quad   0x00af9b000000ffff      /* __KERNEL_CS */
 431         .quad   0x00cf93000000ffff      /* __KERNEL_DS */
 432         .quad   0x00cffb000000ffff      /* __USER32_CS */
 433         .quad   0x00cff3000000ffff      /* __USER_DS, __USER32_DS  */
 434         .quad   0x00affb000000ffff      /* __USER_CS */
 435         .quad   0x0                     /* unused */
 436         .quad   0,0                     /* TSS */
 437         .quad   0,0                     /* LDT */
 438         .quad   0,0,0                   /* three TLS descriptors */
 439         .quad   0x0000f40000000000      /* node/CPU stored in limit */
 440 gdt_end:
 441         /* asm/segment.h:GDT_ENTRIES must match this */
 442         /* This should be a multiple of the cache line size */
 443         /* GDTs of other CPUs are now dynamically allocated */
 444
 445         /* zero the remaining page */
 446         .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
 447
 448         .section .bss, "aw", @nobits
 449         .align L1_CACHE_BYTES
 450 ENTRY(idt_table)
 451         .skip 256 * 16
 452
 453         .section .bss.page_aligned, "aw", @nobits
 454         .align PAGE_SIZE
 455 ENTRY(empty_zero_page)
 456         .skip PAGE_SIZE