arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/delay.h>
   4 #include <linux/errno.h>
   5 #include <linux/hpet.h>
   6 #include <linux/init.h>
   7 #include <linux/sysdev.h>
   8 #include <linux/pm.h>
   9 #include <linux/delay.h>
  10
  11 #include <asm/fixmap.h>
  12 #include <asm/hpet.h>
  13 #include <asm/i8253.h>
  14 #include <asm/io.h>
  15
  16 #define HPET_MASK       CLOCKSOURCE_MASK(32)
  17 #define HPET_SHIFT      22
  18
  19 /* FSEC = 10^-15 NSEC = 10^-9 */
  20 #define FSEC_PER_NSEC   1000000
  21
  22 /*
  23  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  24  */
  25 unsigned long hpet_address;
  26 static void __iomem *hpet_virt_address;
  27
  28 unsigned long hpet_readl(unsigned long a)
  29 {
  30         return readl(hpet_virt_address + a);
  31 }
  32
  33 static inline void hpet_writel(unsigned long d, unsigned long a)
  34 {
  35         writel(d, hpet_virt_address + a);
  36 }
  37
  38 #ifdef CONFIG_X86_64
  39
  40 #include <asm/pgtable.h>
  41
  42 static inline void hpet_set_mapping(void)
  43 {
  44         set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
  45         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
  46         hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
  47 }
  48
  49 static inline void hpet_clear_mapping(void)
  50 {
  51         hpet_virt_address = NULL;
  52 }
  53
  54 #else
  55
  56 static inline void hpet_set_mapping(void)
  57 {
  58         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  59 }
  60
  61 static inline void hpet_clear_mapping(void)
  62 {
  63         iounmap(hpet_virt_address);
  64         hpet_virt_address = NULL;
  65 }
  66 #endif
  67
  68 /*
  69  * HPET command line enable / disable
  70  */
  71 static int boot_hpet_disable;
  72
  73 static int __init hpet_setup(char* str)
  74 {
  75         if (str) {
  76                 if (!strncmp("disable", str, 7))
  77                         boot_hpet_disable = 1;
  78         }
  79         return 1;
  80 }
  81 __setup("hpet=", hpet_setup);
  82
  83 static int __init disable_hpet(char *str)
  84 {
  85         boot_hpet_disable = 1;
  86         return 1;
  87 }
  88 __setup("nohpet", disable_hpet);
  89
  90 static inline int is_hpet_capable(void)
  91 {
  92         return (!boot_hpet_disable && hpet_address);
  93 }
  94
  95 /*
  96  * HPET timer interrupt enable / disable
  97  */
  98 static int hpet_legacy_int_enabled;
  99
 100 /**
 101  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 102  */
 103 int is_hpet_enabled(void)
 104 {
 105         return is_hpet_capable() && hpet_legacy_int_enabled;
 106 }
 107
 108 /*
 109  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 110  * timer 0 and timer 1 in case of RTC emulation.
 111  */
 112 #ifdef CONFIG_HPET
 113 static void hpet_reserve_platform_timers(unsigned long id)
 114 {
 115         struct hpet __iomem *hpet = hpet_virt_address;
 116         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 117         unsigned int nrtimers, i;
 118         struct hpet_data hd;
 119
 120         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 121
 122         memset(&hd, 0, sizeof (hd));
 123         hd.hd_phys_address = hpet_address;
 124         hd.hd_address = hpet;
 125         hd.hd_nirqs = nrtimers;
 126         hd.hd_flags = HPET_DATA_PLATFORM;
 127         hpet_reserve_timer(&hd, 0);
 128
 129 #ifdef CONFIG_HPET_EMULATE_RTC
 130         hpet_reserve_timer(&hd, 1);
 131 #endif
 132
 133         hd.hd_irq[0] = HPET_LEGACY_8254;
 134         hd.hd_irq[1] = HPET_LEGACY_RTC;
 135
 136         for (i = 2; i < nrtimers; timer++, i++)
 137                 hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
 138                         Tn_INT_ROUTE_CNF_SHIFT;
 139
 140         hpet_alloc(&hd);
 141
 142 }
 143 #else
 144 static void hpet_reserve_platform_timers(unsigned long id) { }
 145 #endif
 146
 147 /*
 148  * Common hpet info
 149  */
 150 static unsigned long hpet_period;
 151
 152 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 153                           struct clock_event_device *evt);
 154 static int hpet_legacy_next_event(unsigned long delta,
 155                            struct clock_event_device *evt);
 156
 157 /*
 158  * The hpet clock event device
 159  */
 160 static struct clock_event_device hpet_clockevent = {
 161         .name           = "hpet",
 162         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 163         .set_mode       = hpet_legacy_set_mode,
 164         .set_next_event = hpet_legacy_next_event,
 165         .shift          = 32,
 166         .irq            = 0,
 167 };
 168
 169 static void hpet_start_counter(void)
 170 {
 171         unsigned long cfg = hpet_readl(HPET_CFG);
 172
 173         cfg &= ~HPET_CFG_ENABLE;
 174         hpet_writel(cfg, HPET_CFG);
 175         hpet_writel(0, HPET_COUNTER);
 176         hpet_writel(0, HPET_COUNTER + 4);
 177         cfg |= HPET_CFG_ENABLE;
 178         hpet_writel(cfg, HPET_CFG);
 179 }
 180
 181 static void hpet_enable_legacy_int(void)
 182 {
 183         unsigned long cfg = hpet_readl(HPET_CFG);
 184
 185         cfg |= HPET_CFG_LEGACY;
 186         hpet_writel(cfg, HPET_CFG);
 187         hpet_legacy_int_enabled = 1;
 188 }
 189
 190 static void hpet_legacy_clockevent_register(void)
 191 {
 192         uint64_t hpet_freq;
 193
 194         /* Start HPET legacy interrupts */
 195         hpet_enable_legacy_int();
 196
 197         /*
 198          * The period is a femto seconds value. We need to calculate the
 199          * scaled math multiplication factor for nanosecond to hpet tick
 200          * conversion.
 201          */
 202         hpet_freq = 1000000000000000ULL;
 203         do_div(hpet_freq, hpet_period);
 204         hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
 205                                       NSEC_PER_SEC, 32);
 206         /* Calculate the min / max delta */
 207         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
 208                                                            &hpet_clockevent);
 209         hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
 210                                                            &hpet_clockevent);
 211
 212         /*
 213          * Start hpet with the boot cpu mask and make it
 214          * global after the IO_APIC has been initialized.
 215          */
 216         hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
 217         clockevents_register_device(&hpet_clockevent);
 218         global_clock_event = &hpet_clockevent;
 219         printk(KERN_DEBUG "hpet clockevent registered\n");
 220 }
 221
 222 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 223                           struct clock_event_device *evt)
 224 {
 225         unsigned long cfg, cmp, now;
 226         uint64_t delta;
 227
 228         switch(mode) {
 229         case CLOCK_EVT_MODE_PERIODIC:
 230                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
 231                 delta >>= hpet_clockevent.shift;
 232                 now = hpet_readl(HPET_COUNTER);
 233                 cmp = now + (unsigned long) delta;
 234                 cfg = hpet_readl(HPET_T0_CFG);
 235                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 236                        HPET_TN_SETVAL | HPET_TN_32BIT;
 237                 hpet_writel(cfg, HPET_T0_CFG);
 238                 /*
 239                  * The first write after writing TN_SETVAL to the
 240                  * config register sets the counter value, the second
 241                  * write sets the period.
 242                  */
 243                 hpet_writel(cmp, HPET_T0_CMP);
 244                 udelay(1);
 245                 hpet_writel((unsigned long) delta, HPET_T0_CMP);
 246                 break;
 247
 248         case CLOCK_EVT_MODE_ONESHOT:
 249                 cfg = hpet_readl(HPET_T0_CFG);
 250                 cfg &= ~HPET_TN_PERIODIC;
 251                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 252                 hpet_writel(cfg, HPET_T0_CFG);
 253                 break;
 254
 255         case CLOCK_EVT_MODE_UNUSED:
 256         case CLOCK_EVT_MODE_SHUTDOWN:
 257                 cfg = hpet_readl(HPET_T0_CFG);
 258                 cfg &= ~HPET_TN_ENABLE;
 259                 hpet_writel(cfg, HPET_T0_CFG);
 260                 break;
 261
 262         case CLOCK_EVT_MODE_RESUME:
 263                 hpet_enable_legacy_int();
 264                 break;
 265         }
 266 }
 267
 268 static int hpet_legacy_next_event(unsigned long delta,
 269                            struct clock_event_device *evt)
 270 {
 271         unsigned long cnt;
 272
 273         cnt = hpet_readl(HPET_COUNTER);
 274         cnt += delta;
 275         hpet_writel(cnt, HPET_T0_CMP);
 276
 277         return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
 278 }
 279
 280 /*
 281  * Clock source related code
 282  */
 283 static cycle_t read_hpet(void)
 284 {
 285         return (cycle_t)hpet_readl(HPET_COUNTER);
 286 }
 287
 288 #ifdef CONFIG_X86_64
 289 static cycle_t __vsyscall_fn vread_hpet(void)
 290 {
 291         return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
 292 }
 293 #endif
 294
 295 static struct clocksource clocksource_hpet = {
 296         .name           = "hpet",
 297         .rating         = 250,
 298         .read           = read_hpet,
 299         .mask           = HPET_MASK,
 300         .shift          = HPET_SHIFT,
 301         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 302         .resume         = hpet_start_counter,
 303 #ifdef CONFIG_X86_64
 304         .vread          = vread_hpet,
 305 #endif
 306 };
 307
 308 static int hpet_clocksource_register(void)
 309 {
 310         u64 tmp, start, now;
 311         cycle_t t1;
 312
 313         /* Start the counter */
 314         hpet_start_counter();
 315
 316         /* Verify whether hpet counter works */
 317         t1 = read_hpet();
 318         rdtscll(start);
 319
 320         /*
 321          * We don't know the TSC frequency yet, but waiting for
 322          * 200000 TSC cycles is safe:
 323          * 4 GHz == 50us
 324          * 1 GHz == 200us
 325          */
 326         do {
 327                 rep_nop();
 328                 rdtscll(now);
 329         } while ((now - start) < 200000UL);
 330
 331         if (t1 == read_hpet()) {
 332                 printk(KERN_WARNING
 333                        "HPET counter not counting. HPET disabled\n");
 334                 return -ENODEV;
 335         }
 336
 337         /* Initialize and register HPET clocksource
 338          *
 339          * hpet period is in femto seconds per cycle
 340          * so we need to convert this to ns/cyc units
 341          * aproximated by mult/2^shift
 342          *
 343          *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
 344          *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
 345          *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
 346          *  (fsec/cyc << shift)/1000000 = mult
 347          *  (hpet_period << shift)/FSEC_PER_NSEC = mult
 348          */
 349         tmp = (u64)hpet_period << HPET_SHIFT;
 350         do_div(tmp, FSEC_PER_NSEC);
 351         clocksource_hpet.mult = (u32)tmp;
 352
 353         clocksource_register(&clocksource_hpet);
 354
 355         return 0;
 356 }
 357
 358 /*
 359  * Try to setup the HPET timer
 360  */
 361 int __init hpet_enable(void)
 362 {
 363         unsigned long id;
 364
 365         if (!is_hpet_capable())
 366                 return 0;
 367
 368         hpet_set_mapping();
 369
 370         /*
 371          * Read the period and check for a sane value:
 372          */
 373         hpet_period = hpet_readl(HPET_PERIOD);
 374         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 375                 goto out_nohpet;
 376
 377         /*
 378          * Read the HPET ID register to retrieve the IRQ routing
 379          * information and the number of channels
 380          */
 381         id = hpet_readl(HPET_ID);
 382
 383 #ifdef CONFIG_HPET_EMULATE_RTC
 384         /*
 385          * The legacy routing mode needs at least two channels, tick timer
 386          * and the rtc emulation channel.
 387          */
 388         if (!(id & HPET_ID_NUMBER))
 389                 goto out_nohpet;
 390 #endif
 391
 392         if (hpet_clocksource_register())
 393                 goto out_nohpet;
 394
 395         if (id & HPET_ID_LEGSUP) {
 396                 hpet_legacy_clockevent_register();
 397                 return 1;
 398         }
 399         return 0;
 400
 401 out_nohpet:
 402         hpet_clear_mapping();
 403         boot_hpet_disable = 1;
 404         return 0;
 405 }
 406
 407 /*
 408  * Needs to be late, as the reserve_timer code calls kalloc !
 409  *
 410  * Not a problem on i386 as hpet_enable is called from late_time_init,
 411  * but on x86_64 it is necessary !
 412  */
 413 static __init int hpet_late_init(void)
 414 {
 415         if (!is_hpet_capable())
 416                 return -ENODEV;
 417
 418         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 419         return 0;
 420 }
 421 fs_initcall(hpet_late_init);
 422
 423 #ifdef CONFIG_HPET_EMULATE_RTC
 424
 425 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 426  * is enabled, we support RTC interrupt functionality in software.
 427  * RTC has 3 kinds of interrupts:
 428  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 429  *    is updated
 430  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 431  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 432  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 433  * (1) and (2) above are implemented using polling at a frequency of
 434  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 435  * overhead. (DEFAULT_RTC_INT_FREQ)
 436  * For (3), we use interrupts at 64Hz or user specified periodic
 437  * frequency, whichever is higher.
 438  */
 439 #include <linux/mc146818rtc.h>
 440 #include <linux/rtc.h>
 441
 442 #define DEFAULT_RTC_INT_FREQ    64
 443 #define DEFAULT_RTC_SHIFT       6
 444 #define RTC_NUM_INTS            1
 445
 446 static unsigned long hpet_rtc_flags;
 447 static unsigned long hpet_prev_update_sec;
 448 static struct rtc_time hpet_alarm_time;
 449 static unsigned long hpet_pie_count;
 450 static unsigned long hpet_t1_cmp;
 451 static unsigned long hpet_default_delta;
 452 static unsigned long hpet_pie_delta;
 453 static unsigned long hpet_pie_limit;
 454
 455 /*
 456  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 457  * is not supported by all HPET implementations for timer 1.
 458  *
 459  * hpet_rtc_timer_init() is called when the rtc is initialized.
 460  */
 461 int hpet_rtc_timer_init(void)
 462 {
 463         unsigned long cfg, cnt, delta, flags;
 464
 465         if (!is_hpet_enabled())
 466                 return 0;
 467
 468         if (!hpet_default_delta) {
 469                 uint64_t clc;
 470
 471                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 472                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
 473                 hpet_default_delta = (unsigned long) clc;
 474         }
 475
 476         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 477                 delta = hpet_default_delta;
 478         else
 479                 delta = hpet_pie_delta;
 480
 481         local_irq_save(flags);
 482
 483         cnt = delta + hpet_readl(HPET_COUNTER);
 484         hpet_writel(cnt, HPET_T1_CMP);
 485         hpet_t1_cmp = cnt;
 486
 487         cfg = hpet_readl(HPET_T1_CFG);
 488         cfg &= ~HPET_TN_PERIODIC;
 489         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 490         hpet_writel(cfg, HPET_T1_CFG);
 491
 492         local_irq_restore(flags);
 493
 494         return 1;
 495 }
 496
 497 /*
 498  * The functions below are called from rtc driver.
 499  * Return 0 if HPET is not being used.
 500  * Otherwise do the necessary changes and return 1.
 501  */
 502 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
 503 {
 504         if (!is_hpet_enabled())
 505                 return 0;
 506
 507         hpet_rtc_flags &= ~bit_mask;
 508         return 1;
 509 }
 510
 511 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
 512 {
 513         unsigned long oldbits = hpet_rtc_flags;
 514
 515         if (!is_hpet_enabled())
 516                 return 0;
 517
 518         hpet_rtc_flags |= bit_mask;
 519
 520         if (!oldbits)
 521                 hpet_rtc_timer_init();
 522
 523         return 1;
 524 }
 525
 526 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
 527                         unsigned char sec)
 528 {
 529         if (!is_hpet_enabled())
 530                 return 0;
 531
 532         hpet_alarm_time.tm_hour = hrs;
 533         hpet_alarm_time.tm_min = min;
 534         hpet_alarm_time.tm_sec = sec;
 535
 536         return 1;
 537 }
 538
 539 int hpet_set_periodic_freq(unsigned long freq)
 540 {
 541         uint64_t clc;
 542
 543         if (!is_hpet_enabled())
 544                 return 0;
 545
 546         if (freq <= DEFAULT_RTC_INT_FREQ)
 547                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
 548         else {
 549                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
 550                 do_div(clc, freq);
 551                 clc >>= hpet_clockevent.shift;
 552                 hpet_pie_delta = (unsigned long) clc;
 553         }
 554         return 1;
 555 }
 556
 557 int hpet_rtc_dropped_irq(void)
 558 {
 559         return is_hpet_enabled();
 560 }
 561
 562 static void hpet_rtc_timer_reinit(void)
 563 {
 564         unsigned long cfg, delta;
 565         int lost_ints = -1;
 566
 567         if (unlikely(!hpet_rtc_flags)) {
 568                 cfg = hpet_readl(HPET_T1_CFG);
 569                 cfg &= ~HPET_TN_ENABLE;
 570                 hpet_writel(cfg, HPET_T1_CFG);
 571                 return;
 572         }
 573
 574         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
 575                 delta = hpet_default_delta;
 576         else
 577                 delta = hpet_pie_delta;
 578
 579         /*
 580          * Increment the comparator value until we are ahead of the
 581          * current count.
 582          */
 583         do {
 584                 hpet_t1_cmp += delta;
 585                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
 586                 lost_ints++;
 587         } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
 588
 589         if (lost_ints) {
 590                 if (hpet_rtc_flags & RTC_PIE)
 591                         hpet_pie_count += lost_ints;
 592                 if (printk_ratelimit())
 593                         printk(KERN_WARNING "rtc: lost %d interrupts\n",
 594                                 lost_ints);
 595         }
 596 }
 597
 598 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
 599 {
 600         struct rtc_time curr_time;
 601         unsigned long rtc_int_flag = 0;
 602
 603         hpet_rtc_timer_reinit();
 604
 605         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
 606                 rtc_get_rtc_time(&curr_time);
 607
 608         if (hpet_rtc_flags & RTC_UIE &&
 609             curr_time.tm_sec != hpet_prev_update_sec) {
 610                 rtc_int_flag = RTC_UF;
 611                 hpet_prev_update_sec = curr_time.tm_sec;
 612         }
 613
 614         if (hpet_rtc_flags & RTC_PIE &&
 615             ++hpet_pie_count >= hpet_pie_limit) {
 616                 rtc_int_flag |= RTC_PF;
 617                 hpet_pie_count = 0;
 618         }
 619
 620         if (hpet_rtc_flags & RTC_PIE &&
 621             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
 622             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
 623             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
 624                         rtc_int_flag |= RTC_AF;
 625
 626         if (rtc_int_flag) {
 627                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
 628                 rtc_interrupt(rtc_int_flag, dev_id);
 629         }
 630         return IRQ_HANDLED;
 631 }
 632 #endif