2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
61 #include <mach_apic.h>
62 #include <mach_apicdef.h>
64 #define __apicdebuginit(type) static type __init
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
70 int sis_apic_bug
= -1;
72 static DEFINE_SPINLOCK(ioapic_lock
);
73 static DEFINE_SPINLOCK(vector_lock
);
77 * Rough estimation of how many shared IRQs there are, can
83 * # of IRQ routing registers
85 int nr_ioapic_registers
[MAX_IO_APICS
];
87 /* I/O APIC entries */
88 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
91 /* MP IRQ source entries */
92 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
94 /* # of MP IRQ source entries */
97 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
98 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
101 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
103 int skip_ioapic_setup
;
105 static int __init
parse_noapic(char *str
)
107 /* disable IO-APIC */
108 disable_ioapic_setup();
111 early_param("noapic", parse_noapic
);
117 struct irq_cfg
*next
;
118 struct irq_pin_list
*irq_2_pin
;
120 cpumask_t old_domain
;
121 unsigned move_cleanup_count
;
123 u8 move_in_progress
: 1;
126 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
127 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
128 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
129 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
130 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
131 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
132 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
133 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
134 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
135 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
136 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
137 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
138 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
139 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
140 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
141 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
142 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
143 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
146 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
147 /* need to be biger than size of irq_cfg_legacy */
148 static int nr_irq_cfg
= 32;
150 static int __init
parse_nr_irq_cfg(char *arg
)
153 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
160 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
162 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
164 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
167 static struct irq_cfg
*irq_cfgx
;
168 static struct irq_cfg
*irq_cfgx_free
;
169 static void __init
init_work(void *data
)
171 struct dyn_array
*da
= data
;
178 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
180 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
181 for (i
= legacy_count
; i
< *da
->nr
; i
++)
182 init_one_irq_cfg(&cfg
[i
]);
184 for (i
= 1; i
< *da
->nr
; i
++)
185 cfg
[i
-1].next
= &cfg
[i
];
187 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
188 irq_cfgx
[legacy_count
- 1].next
= NULL
;
191 #define for_each_irq_cfg(cfg) \
192 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
194 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
196 static struct irq_cfg
*irq_cfg(unsigned int irq
)
211 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
213 struct irq_cfg
*cfg
, *cfg_pri
;
217 cfg_pri
= cfg
= irq_cfgx
;
227 if (!irq_cfgx_free
) {
229 unsigned long total_bytes
;
231 * we run out of pre-allocate ones, allocate more
233 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
235 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
237 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
239 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
242 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
245 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
247 for (i
= 0; i
< nr_irq_cfg
; i
++)
248 init_one_irq_cfg(&cfg
[i
]);
250 for (i
= 1; i
< nr_irq_cfg
; i
++)
251 cfg
[i
-1].next
= &cfg
[i
];
257 irq_cfgx_free
= irq_cfgx_free
->next
;
264 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
265 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
267 /* dump the results */
270 unsigned long bytes
= sizeof(struct irq_cfg
);
272 printk(KERN_DEBUG
"=========================== %d\n", irq
);
273 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
274 for_each_irq_cfg(cfg
) {
276 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
278 printk(KERN_DEBUG
"===========================\n");
285 * This is performance-critical, we want to do it O(1)
287 * the indexing order of this array favors 1:1 mappings
288 * between pins and IRQs.
291 struct irq_pin_list
{
293 struct irq_pin_list
*next
;
296 static struct irq_pin_list
*irq_2_pin_head
;
297 /* fill one page ? */
298 static int nr_irq_2_pin
= 0x100;
299 static struct irq_pin_list
*irq_2_pin_ptr
;
300 static void __init
irq_2_pin_init_work(void *data
)
302 struct dyn_array
*da
= data
;
303 struct irq_pin_list
*pin
;
308 for (i
= 1; i
< *da
->nr
; i
++)
309 pin
[i
-1].next
= &pin
[i
];
311 irq_2_pin_ptr
= &pin
[0];
313 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
315 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
317 struct irq_pin_list
*pin
;
323 irq_2_pin_ptr
= pin
->next
;
329 * we run out of pre-allocate ones, allocate more
331 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
334 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
337 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
338 nr_irq_2_pin
, PAGE_SIZE
, 0);
341 panic("can not get more irq_2_pin\n");
343 for (i
= 1; i
< nr_irq_2_pin
; i
++)
344 pin
[i
-1].next
= &pin
[i
];
346 irq_2_pin_ptr
= pin
->next
;
354 unsigned int unused
[3];
358 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
360 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
361 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
364 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
366 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
367 writel(reg
, &io_apic
->index
);
368 return readl(&io_apic
->data
);
371 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
373 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
374 writel(reg
, &io_apic
->index
);
375 writel(value
, &io_apic
->data
);
379 * Re-write a value: to be used for read-modify-write
380 * cycles where the read already set up the index register.
382 * Older SiS APIC requires we rewrite the index register
384 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
386 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
388 writel(reg
, &io_apic
->index
);
389 writel(value
, &io_apic
->data
);
393 static bool io_apic_level_ack_pending(unsigned int irq
)
395 struct irq_pin_list
*entry
;
397 struct irq_cfg
*cfg
= irq_cfg(irq
);
399 spin_lock_irqsave(&ioapic_lock
, flags
);
400 entry
= cfg
->irq_2_pin
;
408 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
409 /* Is the remote IRR bit set? */
410 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
411 spin_unlock_irqrestore(&ioapic_lock
, flags
);
418 spin_unlock_irqrestore(&ioapic_lock
, flags
);
425 struct { u32 w1
, w2
; };
426 struct IO_APIC_route_entry entry
;
429 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
431 union entry_union eu
;
433 spin_lock_irqsave(&ioapic_lock
, flags
);
434 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
435 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
436 spin_unlock_irqrestore(&ioapic_lock
, flags
);
441 * When we write a new IO APIC routing entry, we need to write the high
442 * word first! If the mask bit in the low word is clear, we will enable
443 * the interrupt, and we need to make sure the entry is fully populated
444 * before that happens.
447 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
449 union entry_union eu
;
451 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
452 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
455 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
458 spin_lock_irqsave(&ioapic_lock
, flags
);
459 __ioapic_write_entry(apic
, pin
, e
);
460 spin_unlock_irqrestore(&ioapic_lock
, flags
);
464 * When we mask an IO APIC routing entry, we need to write the low
465 * word first, in order to set the mask bit before we change the
468 static void ioapic_mask_entry(int apic
, int pin
)
471 union entry_union eu
= { .entry
.mask
= 1 };
473 spin_lock_irqsave(&ioapic_lock
, flags
);
474 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
475 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
476 spin_unlock_irqrestore(&ioapic_lock
, flags
);
480 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
484 struct irq_pin_list
*entry
;
487 entry
= cfg
->irq_2_pin
;
496 #ifdef CONFIG_INTR_REMAP
498 * With interrupt-remapping, destination information comes
499 * from interrupt-remapping table entry.
501 if (!irq_remapped(irq
))
502 io_apic_write(apic
, 0x11 + pin
*2, dest
);
504 io_apic_write(apic
, 0x11 + pin
*2, dest
);
506 reg
= io_apic_read(apic
, 0x10 + pin
*2);
507 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
509 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
516 static int assign_irq_vector(int irq
, cpumask_t mask
);
518 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
524 struct irq_desc
*desc
;
526 cpus_and(tmp
, mask
, cpu_online_map
);
531 if (assign_irq_vector(irq
, mask
))
534 cpus_and(tmp
, cfg
->domain
, mask
);
535 dest
= cpu_mask_to_apicid(tmp
);
537 * Only the high 8 bits are valid.
539 dest
= SET_APIC_LOGICAL_ID(dest
);
541 desc
= irq_to_desc(irq
);
542 spin_lock_irqsave(&ioapic_lock
, flags
);
543 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
544 desc
->affinity
= mask
;
545 spin_unlock_irqrestore(&ioapic_lock
, flags
);
547 #endif /* CONFIG_SMP */
550 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
551 * shared ISA-space IRQs, so we have to support them. We are super
552 * fast in the common case, and fast for shared ISA-space IRQs.
554 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
557 struct irq_pin_list
*entry
;
559 /* first time to refer irq_cfg, so with new */
560 cfg
= irq_cfg_alloc(irq
);
561 entry
= cfg
->irq_2_pin
;
563 entry
= get_one_free_irq_2_pin();
564 cfg
->irq_2_pin
= entry
;
567 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
571 while (entry
->next
) {
572 /* not again, please */
573 if (entry
->apic
== apic
&& entry
->pin
== pin
)
579 entry
->next
= get_one_free_irq_2_pin();
583 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
587 * Reroute an IRQ to a different pin.
589 static void __init
replace_pin_at_irq(unsigned int irq
,
590 int oldapic
, int oldpin
,
591 int newapic
, int newpin
)
593 struct irq_cfg
*cfg
= irq_cfg(irq
);
594 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
598 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
599 entry
->apic
= newapic
;
602 /* every one is different, right? */
608 /* why? call replace before add? */
610 add_pin_to_irq(irq
, newapic
, newpin
);
613 #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
617 struct irq_cfg *cfg; \
618 struct irq_pin_list *entry; \
620 cfg = irq_cfg(irq); \
621 entry = cfg->irq_2_pin; \
627 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
628 reg ACTION_DISABLE; \
630 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
634 entry = entry->next; \
638 #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
640 static void name##_IO_APIC_irq (unsigned int irq) \
641 __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
644 DO_ACTION(__unmask
, 0, |= 0, &= ~IO_APIC_REDIR_MASKED
, )
648 * Synchronize the IO-APIC and the CPU by doing
649 * a dummy read from the IO-APIC
651 static inline void io_apic_sync(unsigned int apic
)
653 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
654 readl(&io_apic
->data
);
658 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, &= ~0, io_apic_sync(entry
->apic
))
663 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, &= ~0, )
665 /* mask = 1, trigger = 0 */
666 DO_ACTION(__mask_and_edge
, 0, |= IO_APIC_REDIR_MASKED
, &= ~IO_APIC_REDIR_LEVEL_TRIGGER
, )
668 /* mask = 0, trigger = 1 */
669 DO_ACTION(__unmask_and_level
, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER
, &= ~IO_APIC_REDIR_MASKED
, )
673 static void mask_IO_APIC_irq (unsigned int irq
)
677 spin_lock_irqsave(&ioapic_lock
, flags
);
678 __mask_IO_APIC_irq(irq
);
679 spin_unlock_irqrestore(&ioapic_lock
, flags
);
682 static void unmask_IO_APIC_irq (unsigned int irq
)
686 spin_lock_irqsave(&ioapic_lock
, flags
);
687 __unmask_IO_APIC_irq(irq
);
688 spin_unlock_irqrestore(&ioapic_lock
, flags
);
691 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
693 struct IO_APIC_route_entry entry
;
695 /* Check delivery_mode to be sure we're not clearing an SMI pin */
696 entry
= ioapic_read_entry(apic
, pin
);
697 if (entry
.delivery_mode
== dest_SMI
)
700 * Disable it in the IO-APIC irq-routing table:
702 ioapic_mask_entry(apic
, pin
);
705 static void clear_IO_APIC (void)
709 for (apic
= 0; apic
< nr_ioapics
; apic
++)
710 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
711 clear_IO_APIC_pin(apic
, pin
);
714 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
715 void send_IPI_self(int vector
)
722 apic_wait_icr_idle();
723 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
725 * Send the IPI. The write to APIC_ICR fires this off.
727 apic_write(APIC_ICR
, cfg
);
729 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
733 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
734 * specific CPU-side IRQs.
738 static int pirq_entries
[MAX_PIRQS
];
739 static int pirqs_enabled
;
741 static int __init
ioapic_pirq_setup(char *str
)
744 int ints
[MAX_PIRQS
+1];
746 get_options(str
, ARRAY_SIZE(ints
), ints
);
748 for (i
= 0; i
< MAX_PIRQS
; i
++)
749 pirq_entries
[i
] = -1;
752 apic_printk(APIC_VERBOSE
, KERN_INFO
753 "PIRQ redirection, working around broken MP-BIOS.\n");
755 if (ints
[0] < MAX_PIRQS
)
758 for (i
= 0; i
< max
; i
++) {
759 apic_printk(APIC_VERBOSE
, KERN_DEBUG
760 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
762 * PIRQs are mapped upside down, usually.
764 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
769 __setup("pirq=", ioapic_pirq_setup
);
770 #endif /* CONFIG_X86_32 */
772 #ifdef CONFIG_INTR_REMAP
773 /* I/O APIC RTE contents at the OS boot up */
774 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
777 * Saves and masks all the unmasked IO-APIC RTE's
779 int save_mask_IO_APIC_setup(void)
781 union IO_APIC_reg_01 reg_01
;
786 * The number of IO-APIC IRQ registers (== #pins):
788 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
789 spin_lock_irqsave(&ioapic_lock
, flags
);
790 reg_01
.raw
= io_apic_read(apic
, 1);
791 spin_unlock_irqrestore(&ioapic_lock
, flags
);
792 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
795 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
796 early_ioapic_entries
[apic
] =
797 kzalloc(sizeof(struct IO_APIC_route_entry
) *
798 nr_ioapic_registers
[apic
], GFP_KERNEL
);
799 if (!early_ioapic_entries
[apic
])
803 for (apic
= 0; apic
< nr_ioapics
; apic
++)
804 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
805 struct IO_APIC_route_entry entry
;
807 entry
= early_ioapic_entries
[apic
][pin
] =
808 ioapic_read_entry(apic
, pin
);
811 ioapic_write_entry(apic
, pin
, entry
);
817 void restore_IO_APIC_setup(void)
821 for (apic
= 0; apic
< nr_ioapics
; apic
++)
822 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
823 ioapic_write_entry(apic
, pin
,
824 early_ioapic_entries
[apic
][pin
]);
827 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
830 * for now plain restore of previous settings.
831 * TBD: In the case of OS enabling interrupt-remapping,
832 * IO-APIC RTE's need to be setup to point to interrupt-remapping
833 * table entries. for now, do a plain restore, and wait for
834 * the setup_IO_APIC_irqs() to do proper initialization.
836 restore_IO_APIC_setup();
841 * Find the IRQ entry number of a certain pin.
843 static int find_irq_entry(int apic
, int pin
, int type
)
847 for (i
= 0; i
< mp_irq_entries
; i
++)
848 if (mp_irqs
[i
].mp_irqtype
== type
&&
849 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
850 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
851 mp_irqs
[i
].mp_dstirq
== pin
)
858 * Find the pin to which IRQ[irq] (ISA) is connected
860 static int __init
find_isa_irq_pin(int irq
, int type
)
864 for (i
= 0; i
< mp_irq_entries
; i
++) {
865 int lbus
= mp_irqs
[i
].mp_srcbus
;
867 if (test_bit(lbus
, mp_bus_not_pci
) &&
868 (mp_irqs
[i
].mp_irqtype
== type
) &&
869 (mp_irqs
[i
].mp_srcbusirq
== irq
))
871 return mp_irqs
[i
].mp_dstirq
;
876 static int __init
find_isa_irq_apic(int irq
, int type
)
880 for (i
= 0; i
< mp_irq_entries
; i
++) {
881 int lbus
= mp_irqs
[i
].mp_srcbus
;
883 if (test_bit(lbus
, mp_bus_not_pci
) &&
884 (mp_irqs
[i
].mp_irqtype
== type
) &&
885 (mp_irqs
[i
].mp_srcbusirq
== irq
))
888 if (i
< mp_irq_entries
) {
890 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
891 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
900 * Find a specific PCI IRQ entry.
901 * Not an __init, possibly needed by modules
903 static int pin_2_irq(int idx
, int apic
, int pin
);
905 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
907 int apic
, i
, best_guess
= -1;
909 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
911 if (test_bit(bus
, mp_bus_not_pci
)) {
912 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
915 for (i
= 0; i
< mp_irq_entries
; i
++) {
916 int lbus
= mp_irqs
[i
].mp_srcbus
;
918 for (apic
= 0; apic
< nr_ioapics
; apic
++)
919 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
920 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
923 if (!test_bit(lbus
, mp_bus_not_pci
) &&
924 !mp_irqs
[i
].mp_irqtype
&&
926 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
927 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
929 if (!(apic
|| IO_APIC_IRQ(irq
)))
932 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
935 * Use the first all-but-pin matching entry as a
936 * best-guess fuzzy result for broken mptables.
945 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
947 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
949 * EISA Edge/Level control register, ELCR
951 static int EISA_ELCR(unsigned int irq
)
954 unsigned int port
= 0x4d0 + (irq
>> 3);
955 return (inb(port
) >> (irq
& 7)) & 1;
957 apic_printk(APIC_VERBOSE
, KERN_INFO
958 "Broken MPtable reports ISA irq %d\n", irq
);
964 /* ISA interrupts are always polarity zero edge triggered,
965 * when listed as conforming in the MP table. */
967 #define default_ISA_trigger(idx) (0)
968 #define default_ISA_polarity(idx) (0)
970 /* EISA interrupts are always polarity zero and can be edge or level
971 * trigger depending on the ELCR value. If an interrupt is listed as
972 * EISA conforming in the MP table, that means its trigger type must
973 * be read in from the ELCR */
975 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
976 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
978 /* PCI interrupts are always polarity one level triggered,
979 * when listed as conforming in the MP table. */
981 #define default_PCI_trigger(idx) (1)
982 #define default_PCI_polarity(idx) (1)
984 /* MCA interrupts are always polarity zero level triggered,
985 * when listed as conforming in the MP table. */
987 #define default_MCA_trigger(idx) (1)
988 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
990 static int MPBIOS_polarity(int idx
)
992 int bus
= mp_irqs
[idx
].mp_srcbus
;
996 * Determine IRQ line polarity (high active or low active):
998 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1000 case 0: /* conforms, ie. bus-type dependent polarity */
1001 if (test_bit(bus
, mp_bus_not_pci
))
1002 polarity
= default_ISA_polarity(idx
);
1004 polarity
= default_PCI_polarity(idx
);
1006 case 1: /* high active */
1011 case 2: /* reserved */
1013 printk(KERN_WARNING
"broken BIOS!!\n");
1017 case 3: /* low active */
1022 default: /* invalid */
1024 printk(KERN_WARNING
"broken BIOS!!\n");
1032 static int MPBIOS_trigger(int idx
)
1034 int bus
= mp_irqs
[idx
].mp_srcbus
;
1038 * Determine IRQ trigger mode (edge or level sensitive):
1040 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1042 case 0: /* conforms, ie. bus-type dependent */
1043 if (test_bit(bus
, mp_bus_not_pci
))
1044 trigger
= default_ISA_trigger(idx
);
1046 trigger
= default_PCI_trigger(idx
);
1047 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1048 switch (mp_bus_id_to_type
[bus
]) {
1049 case MP_BUS_ISA
: /* ISA pin */
1051 /* set before the switch */
1054 case MP_BUS_EISA
: /* EISA pin */
1056 trigger
= default_EISA_trigger(idx
);
1059 case MP_BUS_PCI
: /* PCI pin */
1061 /* set before the switch */
1064 case MP_BUS_MCA
: /* MCA pin */
1066 trigger
= default_MCA_trigger(idx
);
1071 printk(KERN_WARNING
"broken BIOS!!\n");
1083 case 2: /* reserved */
1085 printk(KERN_WARNING
"broken BIOS!!\n");
1094 default: /* invalid */
1096 printk(KERN_WARNING
"broken BIOS!!\n");
1104 static inline int irq_polarity(int idx
)
1106 return MPBIOS_polarity(idx
);
1109 static inline int irq_trigger(int idx
)
1111 return MPBIOS_trigger(idx
);
1114 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1115 static int pin_2_irq(int idx
, int apic
, int pin
)
1118 int bus
= mp_irqs
[idx
].mp_srcbus
;
1121 * Debugging check, we are in big trouble if this message pops up!
1123 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1124 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1126 if (test_bit(bus
, mp_bus_not_pci
)) {
1127 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1130 * PCI IRQs are mapped in order
1134 irq
+= nr_ioapic_registers
[i
++];
1137 * For MPS mode, so far only needed by ES7000 platform
1139 if (ioapic_renumber_irq
)
1140 irq
= ioapic_renumber_irq(apic
, irq
);
1143 #ifdef CONFIG_X86_32
1145 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1147 if ((pin
>= 16) && (pin
<= 23)) {
1148 if (pirq_entries
[pin
-16] != -1) {
1149 if (!pirq_entries
[pin
-16]) {
1150 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1151 "disabling PIRQ%d\n", pin
-16);
1153 irq
= pirq_entries
[pin
-16];
1154 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1155 "using PIRQ%d -> IRQ %d\n",
1165 void lock_vector_lock(void)
1167 /* Used to the online set of cpus does not change
1168 * during assign_irq_vector.
1170 spin_lock(&vector_lock
);
1173 void unlock_vector_lock(void)
1175 spin_unlock(&vector_lock
);
1178 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1181 * NOTE! The local APIC isn't very good at handling
1182 * multiple interrupts at the same interrupt level.
1183 * As the interrupt level is determined by taking the
1184 * vector number and shifting that right by 4, we
1185 * want to spread these out a bit so that they don't
1186 * all fall in the same interrupt level.
1188 * Also, we've got to be careful not to trash gate
1189 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1191 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1192 unsigned int old_vector
;
1194 struct irq_cfg
*cfg
;
1198 /* Only try and allocate irqs on cpus that are present */
1199 cpus_and(mask
, mask
, cpu_online_map
);
1201 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1204 old_vector
= cfg
->vector
;
1207 cpus_and(tmp
, cfg
->domain
, mask
);
1208 if (!cpus_empty(tmp
))
1212 for_each_cpu_mask_nr(cpu
, mask
) {
1213 cpumask_t domain
, new_mask
;
1217 domain
= vector_allocation_domain(cpu
);
1218 cpus_and(new_mask
, domain
, cpu_online_map
);
1220 vector
= current_vector
;
1221 offset
= current_offset
;
1224 if (vector
>= first_system_vector
) {
1225 /* If we run out of vectors on large boxen, must share them. */
1226 offset
= (offset
+ 1) % 8;
1227 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1229 if (unlikely(current_vector
== vector
))
1231 #ifdef CONFIG_X86_64
1232 if (vector
== IA32_SYSCALL_VECTOR
)
1235 if (vector
== SYSCALL_VECTOR
)
1238 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1239 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1242 current_vector
= vector
;
1243 current_offset
= offset
;
1245 cfg
->move_in_progress
= 1;
1246 cfg
->old_domain
= cfg
->domain
;
1248 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1249 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1250 cfg
->vector
= vector
;
1251 cfg
->domain
= domain
;
1257 static int assign_irq_vector(int irq
, cpumask_t mask
)
1260 unsigned long flags
;
1262 spin_lock_irqsave(&vector_lock
, flags
);
1263 err
= __assign_irq_vector(irq
, mask
);
1264 spin_unlock_irqrestore(&vector_lock
, flags
);
1268 static void __clear_irq_vector(int irq
)
1270 struct irq_cfg
*cfg
;
1275 BUG_ON(!cfg
->vector
);
1277 vector
= cfg
->vector
;
1278 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1279 for_each_cpu_mask_nr(cpu
, mask
)
1280 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1283 cpus_clear(cfg
->domain
);
1286 void __setup_vector_irq(int cpu
)
1288 /* Initialize vector_irq on a new cpu */
1289 /* This function must be called with vector_lock held */
1291 struct irq_cfg
*cfg
;
1293 /* Mark the inuse vectors */
1294 for_each_irq_cfg(cfg
) {
1295 if (!cpu_isset(cpu
, cfg
->domain
))
1297 vector
= cfg
->vector
;
1299 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1301 /* Mark the free vectors */
1302 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1303 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1308 if (!cpu_isset(cpu
, cfg
->domain
))
1309 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1313 static struct irq_chip ioapic_chip
;
1314 #ifdef CONFIG_INTR_REMAP
1315 static struct irq_chip ir_ioapic_chip
;
1318 #define IOAPIC_AUTO -1
1319 #define IOAPIC_EDGE 0
1320 #define IOAPIC_LEVEL 1
1322 #ifdef CONFIG_X86_32
1323 static inline int IO_APIC_irq_trigger(int irq
)
1327 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1328 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1329 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1330 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1331 return irq_trigger(idx
);
1335 * nonexistent IRQs are edge default
1340 static inline int IO_APIC_irq_trigger(int irq
)
1346 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1348 struct irq_desc
*desc
;
1350 /* first time to use this irq_desc */
1352 desc
= irq_to_desc(irq
);
1354 desc
= irq_to_desc_alloc(irq
);
1356 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1357 trigger
== IOAPIC_LEVEL
)
1358 desc
->status
|= IRQ_LEVEL
;
1360 desc
->status
&= ~IRQ_LEVEL
;
1362 #ifdef CONFIG_INTR_REMAP
1363 if (irq_remapped(irq
)) {
1364 desc
->status
|= IRQ_MOVE_PCNTXT
;
1366 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1370 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1371 handle_edge_irq
, "edge");
1375 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1376 trigger
== IOAPIC_LEVEL
)
1377 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1381 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1382 handle_edge_irq
, "edge");
1385 static int setup_ioapic_entry(int apic
, int irq
,
1386 struct IO_APIC_route_entry
*entry
,
1387 unsigned int destination
, int trigger
,
1388 int polarity
, int vector
)
1391 * add it to the IO-APIC irq-routing table:
1393 memset(entry
,0,sizeof(*entry
));
1395 #ifdef CONFIG_INTR_REMAP
1396 if (intr_remapping_enabled
) {
1397 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1399 struct IR_IO_APIC_route_entry
*ir_entry
=
1400 (struct IR_IO_APIC_route_entry
*) entry
;
1404 panic("No mapping iommu for ioapic %d\n", apic
);
1406 index
= alloc_irte(iommu
, irq
, 1);
1408 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1410 memset(&irte
, 0, sizeof(irte
));
1413 irte
.dst_mode
= INT_DEST_MODE
;
1414 irte
.trigger_mode
= trigger
;
1415 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1416 irte
.vector
= vector
;
1417 irte
.dest_id
= IRTE_DEST(destination
);
1419 modify_irte(irq
, &irte
);
1421 ir_entry
->index2
= (index
>> 15) & 0x1;
1423 ir_entry
->format
= 1;
1424 ir_entry
->index
= (index
& 0x7fff);
1428 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1429 entry
->dest_mode
= INT_DEST_MODE
;
1430 entry
->dest
= destination
;
1433 entry
->mask
= 0; /* enable IRQ */
1434 entry
->trigger
= trigger
;
1435 entry
->polarity
= polarity
;
1436 entry
->vector
= vector
;
1438 /* Mask level triggered irqs.
1439 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1446 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1447 int trigger
, int polarity
)
1449 struct irq_cfg
*cfg
;
1450 struct IO_APIC_route_entry entry
;
1453 if (!IO_APIC_IRQ(irq
))
1459 if (assign_irq_vector(irq
, mask
))
1462 cpus_and(mask
, cfg
->domain
, mask
);
1464 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1465 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1466 "IRQ %d Mode:%i Active:%i)\n",
1467 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1468 irq
, trigger
, polarity
);
1471 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1472 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1474 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1475 mp_ioapics
[apic
].mp_apicid
, pin
);
1476 __clear_irq_vector(irq
);
1480 ioapic_register_intr(irq
, trigger
);
1482 disable_8259A_irq(irq
);
1484 ioapic_write_entry(apic
, pin
, entry
);
1487 static void __init
setup_IO_APIC_irqs(void)
1489 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1491 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1493 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1494 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1496 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1499 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1502 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1505 if (!first_notcon
) {
1506 apic_printk(APIC_VERBOSE
, " not connected.\n");
1510 irq
= pin_2_irq(idx
, apic
, pin
);
1511 #ifdef CONFIG_X86_32
1512 if (multi_timer_check(apic
, irq
))
1515 add_pin_to_irq(irq
, apic
, pin
);
1517 setup_IO_APIC_irq(apic
, pin
, irq
,
1518 irq_trigger(idx
), irq_polarity(idx
));
1523 apic_printk(APIC_VERBOSE
, " not connected.\n");
1527 * Set up the timer pin, possibly with the 8259A-master behind.
1529 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1532 struct IO_APIC_route_entry entry
;
1534 #ifdef CONFIG_INTR_REMAP
1535 if (intr_remapping_enabled
)
1539 memset(&entry
, 0, sizeof(entry
));
1542 * We use logical delivery to get the timer IRQ
1545 entry
.dest_mode
= INT_DEST_MODE
;
1546 entry
.mask
= 1; /* mask IRQ now */
1547 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1548 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1551 entry
.vector
= vector
;
1554 * The timer IRQ doesn't have to know that behind the
1555 * scene we may have a 8259A-master in AEOI mode ...
1557 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1560 * Add it to the IO-APIC irq-routing table:
1562 ioapic_write_entry(apic
, pin
, entry
);
1566 __apicdebuginit(void) print_IO_APIC(void)
1569 union IO_APIC_reg_00 reg_00
;
1570 union IO_APIC_reg_01 reg_01
;
1571 union IO_APIC_reg_02 reg_02
;
1572 union IO_APIC_reg_03 reg_03
;
1573 unsigned long flags
;
1574 struct irq_cfg
*cfg
;
1576 if (apic_verbosity
== APIC_QUIET
)
1579 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1580 for (i
= 0; i
< nr_ioapics
; i
++)
1581 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1582 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1585 * We are a bit conservative about what we expect. We have to
1586 * know about every hardware change ASAP.
1588 printk(KERN_INFO
"testing the IO APIC.......................\n");
1590 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1592 spin_lock_irqsave(&ioapic_lock
, flags
);
1593 reg_00
.raw
= io_apic_read(apic
, 0);
1594 reg_01
.raw
= io_apic_read(apic
, 1);
1595 if (reg_01
.bits
.version
>= 0x10)
1596 reg_02
.raw
= io_apic_read(apic
, 2);
1597 if (reg_01
.bits
.version
>= 0x20)
1598 reg_03
.raw
= io_apic_read(apic
, 3);
1599 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1602 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1603 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1604 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1605 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1606 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1608 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1609 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1611 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1612 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1615 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1616 * but the value of reg_02 is read as the previous read register
1617 * value, so ignore it if reg_02 == reg_01.
1619 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1620 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1621 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1625 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1626 * or reg_03, but the value of reg_0[23] is read as the previous read
1627 * register value, so ignore it if reg_03 == reg_0[12].
1629 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1630 reg_03
.raw
!= reg_01
.raw
) {
1631 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1632 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1635 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1637 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1638 " Stat Dmod Deli Vect: \n");
1640 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1641 struct IO_APIC_route_entry entry
;
1643 entry
= ioapic_read_entry(apic
, i
);
1645 printk(KERN_DEBUG
" %02x %03X ",
1650 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1655 entry
.delivery_status
,
1657 entry
.delivery_mode
,
1662 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1663 for_each_irq_cfg(cfg
) {
1664 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1667 printk(KERN_DEBUG
"IRQ%d ", cfg
->irq
);
1669 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1672 entry
= entry
->next
;
1677 printk(KERN_INFO
".................................... done.\n");
1682 __apicdebuginit(void) print_APIC_bitfield(int base
)
1687 if (apic_verbosity
== APIC_QUIET
)
1690 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1691 for (i
= 0; i
< 8; i
++) {
1692 v
= apic_read(base
+ i
*0x10);
1693 for (j
= 0; j
< 32; j
++) {
1703 __apicdebuginit(void) print_local_APIC(void *dummy
)
1705 unsigned int v
, ver
, maxlvt
;
1708 if (apic_verbosity
== APIC_QUIET
)
1711 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1712 smp_processor_id(), hard_smp_processor_id());
1713 v
= apic_read(APIC_ID
);
1714 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1715 v
= apic_read(APIC_LVR
);
1716 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1717 ver
= GET_APIC_VERSION(v
);
1718 maxlvt
= lapic_get_maxlvt();
1720 v
= apic_read(APIC_TASKPRI
);
1721 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1723 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1724 v
= apic_read(APIC_ARBPRI
);
1725 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1726 v
& APIC_ARBPRI_MASK
);
1727 v
= apic_read(APIC_PROCPRI
);
1728 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1731 v
= apic_read(APIC_EOI
);
1732 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1733 v
= apic_read(APIC_RRR
);
1734 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1735 v
= apic_read(APIC_LDR
);
1736 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1737 v
= apic_read(APIC_DFR
);
1738 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1739 v
= apic_read(APIC_SPIV
);
1740 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1742 printk(KERN_DEBUG
"... APIC ISR field:\n");
1743 print_APIC_bitfield(APIC_ISR
);
1744 printk(KERN_DEBUG
"... APIC TMR field:\n");
1745 print_APIC_bitfield(APIC_TMR
);
1746 printk(KERN_DEBUG
"... APIC IRR field:\n");
1747 print_APIC_bitfield(APIC_IRR
);
1749 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1750 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1751 apic_write(APIC_ESR
, 0);
1753 v
= apic_read(APIC_ESR
);
1754 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1757 icr
= apic_icr_read();
1758 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1759 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1761 v
= apic_read(APIC_LVTT
);
1762 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1764 if (maxlvt
> 3) { /* PC is LVT#4. */
1765 v
= apic_read(APIC_LVTPC
);
1766 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1768 v
= apic_read(APIC_LVT0
);
1769 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1770 v
= apic_read(APIC_LVT1
);
1771 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1773 if (maxlvt
> 2) { /* ERR is LVT#3. */
1774 v
= apic_read(APIC_LVTERR
);
1775 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1778 v
= apic_read(APIC_TMICT
);
1779 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1780 v
= apic_read(APIC_TMCCT
);
1781 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1782 v
= apic_read(APIC_TDCR
);
1783 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1787 __apicdebuginit(void) print_all_local_APICs(void)
1789 on_each_cpu(print_local_APIC
, NULL
, 1);
1792 __apicdebuginit(void) print_PIC(void)
1795 unsigned long flags
;
1797 if (apic_verbosity
== APIC_QUIET
)
1800 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1802 spin_lock_irqsave(&i8259A_lock
, flags
);
1804 v
= inb(0xa1) << 8 | inb(0x21);
1805 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1807 v
= inb(0xa0) << 8 | inb(0x20);
1808 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1812 v
= inb(0xa0) << 8 | inb(0x20);
1816 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1818 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1820 v
= inb(0x4d1) << 8 | inb(0x4d0);
1821 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1824 __apicdebuginit(int) print_all_ICs(void)
1827 print_all_local_APICs();
1833 fs_initcall(print_all_ICs
);
1836 /* Where if anywhere is the i8259 connect in external int mode */
1837 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1839 void __init
enable_IO_APIC(void)
1841 union IO_APIC_reg_01 reg_01
;
1842 int i8259_apic
, i8259_pin
;
1844 unsigned long flags
;
1846 #ifdef CONFIG_X86_32
1849 for (i
= 0; i
< MAX_PIRQS
; i
++)
1850 pirq_entries
[i
] = -1;
1854 * The number of IO-APIC IRQ registers (== #pins):
1856 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1857 spin_lock_irqsave(&ioapic_lock
, flags
);
1858 reg_01
.raw
= io_apic_read(apic
, 1);
1859 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1860 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1862 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1864 /* See if any of the pins is in ExtINT mode */
1865 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1866 struct IO_APIC_route_entry entry
;
1867 entry
= ioapic_read_entry(apic
, pin
);
1869 /* If the interrupt line is enabled and in ExtInt mode
1870 * I have found the pin where the i8259 is connected.
1872 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1873 ioapic_i8259
.apic
= apic
;
1874 ioapic_i8259
.pin
= pin
;
1880 /* Look to see what if the MP table has reported the ExtINT */
1881 /* If we could not find the appropriate pin by looking at the ioapic
1882 * the i8259 probably is not connected the ioapic but give the
1883 * mptable a chance anyway.
1885 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1886 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1887 /* Trust the MP table if nothing is setup in the hardware */
1888 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1889 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1890 ioapic_i8259
.pin
= i8259_pin
;
1891 ioapic_i8259
.apic
= i8259_apic
;
1893 /* Complain if the MP table and the hardware disagree */
1894 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1895 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1897 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1901 * Do not trust the IO-APIC being empty at bootup
1907 * Not an __init, needed by the reboot code
1909 void disable_IO_APIC(void)
1912 * Clear the IO-APIC before rebooting:
1917 * If the i8259 is routed through an IOAPIC
1918 * Put that IOAPIC in virtual wire mode
1919 * so legacy interrupts can be delivered.
1921 if (ioapic_i8259
.pin
!= -1) {
1922 struct IO_APIC_route_entry entry
;
1924 memset(&entry
, 0, sizeof(entry
));
1925 entry
.mask
= 0; /* Enabled */
1926 entry
.trigger
= 0; /* Edge */
1928 entry
.polarity
= 0; /* High */
1929 entry
.delivery_status
= 0;
1930 entry
.dest_mode
= 0; /* Physical */
1931 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1933 entry
.dest
= read_apic_id();
1936 * Add it to the IO-APIC irq-routing table:
1938 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1941 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1944 #ifdef CONFIG_X86_32
1946 * function to set the IO-APIC physical IDs based on the
1947 * values stored in the MPC table.
1949 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1952 static void __init
setup_ioapic_ids_from_mpc(void)
1954 union IO_APIC_reg_00 reg_00
;
1955 physid_mask_t phys_id_present_map
;
1958 unsigned char old_id
;
1959 unsigned long flags
;
1961 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1965 * Don't check I/O APIC IDs for xAPIC systems. They have
1966 * no meaning without the serial APIC bus.
1968 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1969 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1972 * This is broken; anything with a real cpu count has to
1973 * circumvent this idiocy regardless.
1975 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1978 * Set the IOAPIC ID to the value stored in the MPC table.
1980 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1982 /* Read the register 0 value */
1983 spin_lock_irqsave(&ioapic_lock
, flags
);
1984 reg_00
.raw
= io_apic_read(apic
, 0);
1985 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1987 old_id
= mp_ioapics
[apic
].mp_apicid
;
1989 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1990 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1991 apic
, mp_ioapics
[apic
].mp_apicid
);
1992 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1994 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1998 * Sanity check, is the ID really free? Every APIC in a
1999 * system must have a unique ID or we get lots of nice
2000 * 'stuck on smp_invalidate_needed IPI wait' messages.
2002 if (check_apicid_used(phys_id_present_map
,
2003 mp_ioapics
[apic
].mp_apicid
)) {
2004 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2005 apic
, mp_ioapics
[apic
].mp_apicid
);
2006 for (i
= 0; i
< get_physical_broadcast(); i
++)
2007 if (!physid_isset(i
, phys_id_present_map
))
2009 if (i
>= get_physical_broadcast())
2010 panic("Max APIC ID exceeded!\n");
2011 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2013 physid_set(i
, phys_id_present_map
);
2014 mp_ioapics
[apic
].mp_apicid
= i
;
2017 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2018 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2019 "phys_id_present_map\n",
2020 mp_ioapics
[apic
].mp_apicid
);
2021 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2026 * We need to adjust the IRQ routing table
2027 * if the ID changed.
2029 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2030 for (i
= 0; i
< mp_irq_entries
; i
++)
2031 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2032 mp_irqs
[i
].mp_dstapic
2033 = mp_ioapics
[apic
].mp_apicid
;
2036 * Read the right value from the MPC table and
2037 * write it into the ID register.
2039 apic_printk(APIC_VERBOSE
, KERN_INFO
2040 "...changing IO-APIC physical APIC ID to %d ...",
2041 mp_ioapics
[apic
].mp_apicid
);
2043 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2044 spin_lock_irqsave(&ioapic_lock
, flags
);
2049 spin_lock_irqsave(&ioapic_lock
, flags
);
2050 reg_00
.raw
= io_apic_read(apic
, 0);
2051 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2052 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2053 printk("could not set ID!\n");
2055 apic_printk(APIC_VERBOSE
, " ok.\n");
2060 int no_timer_check __initdata
;
2062 static int __init
notimercheck(char *s
)
2067 __setup("no_timer_check", notimercheck
);
2070 * There is a nasty bug in some older SMP boards, their mptable lies
2071 * about the timer IRQ. We do the following to work around the situation:
2073 * - timer IRQ defaults to IO-APIC IRQ
2074 * - if this function detects that timer IRQs are defunct, then we fall
2075 * back to ISA timer IRQs
2077 static int __init
timer_irq_works(void)
2079 unsigned long t1
= jiffies
;
2080 unsigned long flags
;
2085 local_save_flags(flags
);
2087 /* Let ten ticks pass... */
2088 mdelay((10 * 1000) / HZ
);
2089 local_irq_restore(flags
);
2092 * Expect a few ticks at least, to be sure some possible
2093 * glue logic does not lock up after one or two first
2094 * ticks in a non-ExtINT mode. Also the local APIC
2095 * might have cached one ExtINT interrupt. Finally, at
2096 * least one tick may be lost due to delays.
2100 if (time_after(jiffies
, t1
+ 4))
2106 * In the SMP+IOAPIC case it might happen that there are an unspecified
2107 * number of pending IRQ events unhandled. These cases are very rare,
2108 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2109 * better to do it this way as thus we do not have to be aware of
2110 * 'pending' interrupts in the IRQ path, except at this point.
2113 * Edge triggered needs to resend any interrupt
2114 * that was delayed but this is now handled in the device
2119 * Starting up a edge-triggered IO-APIC interrupt is
2120 * nasty - we need to make sure that we get the edge.
2121 * If it is already asserted for some reason, we need
2122 * return 1 to indicate that is was pending.
2124 * This is not complete - we should be able to fake
2125 * an edge even if it isn't on the 8259A...
2128 static unsigned int startup_ioapic_irq(unsigned int irq
)
2130 int was_pending
= 0;
2131 unsigned long flags
;
2133 spin_lock_irqsave(&ioapic_lock
, flags
);
2135 disable_8259A_irq(irq
);
2136 if (i8259A_irq_pending(irq
))
2139 __unmask_IO_APIC_irq(irq
);
2140 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2145 #ifdef CONFIG_X86_64
2146 static int ioapic_retrigger_irq(unsigned int irq
)
2149 struct irq_cfg
*cfg
= irq_cfg(irq
);
2150 unsigned long flags
;
2152 spin_lock_irqsave(&vector_lock
, flags
);
2153 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
2154 spin_unlock_irqrestore(&vector_lock
, flags
);
2159 static int ioapic_retrigger_irq(unsigned int irq
)
2161 send_IPI_self(irq_cfg(irq
)->vector
);
2168 * Level and edge triggered IO-APIC interrupts need different handling,
2169 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2170 * handled with the level-triggered descriptor, but that one has slightly
2171 * more overhead. Level-triggered interrupts cannot be handled with the
2172 * edge-triggered handler, without risking IRQ storms and other ugly
2178 #ifdef CONFIG_INTR_REMAP
2179 static void ir_irq_migration(struct work_struct
*work
);
2181 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2184 * Migrate the IO-APIC irq in the presence of intr-remapping.
2186 * For edge triggered, irq migration is a simple atomic update(of vector
2187 * and cpu destination) of IRTE and flush the hardware cache.
2189 * For level triggered, we need to modify the io-apic RTE aswell with the update
2190 * vector information, along with modifying IRTE with vector and destination.
2191 * So irq migration for level triggered is little bit more complex compared to
2192 * edge triggered migration. But the good news is, we use the same algorithm
2193 * for level triggered migration as we have today, only difference being,
2194 * we now initiate the irq migration from process context instead of the
2195 * interrupt context.
2197 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2198 * suppression) to the IO-APIC, level triggered irq migration will also be
2199 * as simple as edge triggered migration and we can do the irq migration
2200 * with a simple atomic update to IO-APIC RTE.
2202 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
2204 struct irq_cfg
*cfg
;
2205 struct irq_desc
*desc
;
2206 cpumask_t tmp
, cleanup_mask
;
2208 int modify_ioapic_rte
;
2210 unsigned long flags
;
2212 cpus_and(tmp
, mask
, cpu_online_map
);
2213 if (cpus_empty(tmp
))
2216 if (get_irte(irq
, &irte
))
2219 if (assign_irq_vector(irq
, mask
))
2223 cpus_and(tmp
, cfg
->domain
, mask
);
2224 dest
= cpu_mask_to_apicid(tmp
);
2226 desc
= irq_to_desc(irq
);
2227 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2228 if (modify_ioapic_rte
) {
2229 spin_lock_irqsave(&ioapic_lock
, flags
);
2230 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
2231 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2234 irte
.vector
= cfg
->vector
;
2235 irte
.dest_id
= IRTE_DEST(dest
);
2238 * Modified the IRTE and flushes the Interrupt entry cache.
2240 modify_irte(irq
, &irte
);
2242 if (cfg
->move_in_progress
) {
2243 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2244 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2245 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2246 cfg
->move_in_progress
= 0;
2249 desc
->affinity
= mask
;
2252 static int migrate_irq_remapped_level(int irq
)
2255 struct irq_desc
*desc
= irq_to_desc(irq
);
2257 mask_IO_APIC_irq(irq
);
2259 if (io_apic_level_ack_pending(irq
)) {
2261 * Interrupt in progress. Migrating irq now will change the
2262 * vector information in the IO-APIC RTE and that will confuse
2263 * the EOI broadcast performed by cpu.
2264 * So, delay the irq migration to the next instance.
2266 schedule_delayed_work(&ir_migration_work
, 1);
2270 /* everthing is clear. we have right of way */
2271 migrate_ioapic_irq(irq
, desc
->pending_mask
);
2274 desc
->status
&= ~IRQ_MOVE_PENDING
;
2275 cpus_clear(desc
->pending_mask
);
2278 unmask_IO_APIC_irq(irq
);
2282 static void ir_irq_migration(struct work_struct
*work
)
2285 struct irq_desc
*desc
;
2287 for_each_irq_desc(irq
, desc
) {
2288 if (desc
->status
& IRQ_MOVE_PENDING
) {
2289 unsigned long flags
;
2291 spin_lock_irqsave(&desc
->lock
, flags
);
2292 if (!desc
->chip
->set_affinity
||
2293 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2294 desc
->status
&= ~IRQ_MOVE_PENDING
;
2295 spin_unlock_irqrestore(&desc
->lock
, flags
);
2299 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
2300 spin_unlock_irqrestore(&desc
->lock
, flags
);
2306 * Migrates the IRQ destination in the process context.
2308 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
2310 struct irq_desc
*desc
= irq_to_desc(irq
);
2312 if (desc
->status
& IRQ_LEVEL
) {
2313 desc
->status
|= IRQ_MOVE_PENDING
;
2314 desc
->pending_mask
= mask
;
2315 migrate_irq_remapped_level(irq
);
2319 migrate_ioapic_irq(irq
, mask
);
2323 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2325 unsigned vector
, me
;
2327 #ifdef CONFIG_X86_64
2332 me
= smp_processor_id();
2333 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2335 struct irq_desc
*desc
;
2336 struct irq_cfg
*cfg
;
2337 irq
= __get_cpu_var(vector_irq
)[vector
];
2339 desc
= irq_to_desc(irq
);
2344 spin_lock(&desc
->lock
);
2345 if (!cfg
->move_cleanup_count
)
2348 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
2351 __get_cpu_var(vector_irq
)[vector
] = -1;
2352 cfg
->move_cleanup_count
--;
2354 spin_unlock(&desc
->lock
);
2360 static void irq_complete_move(unsigned int irq
)
2362 struct irq_cfg
*cfg
= irq_cfg(irq
);
2363 unsigned vector
, me
;
2365 if (likely(!cfg
->move_in_progress
))
2368 vector
= ~get_irq_regs()->orig_ax
;
2369 me
= smp_processor_id();
2370 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
2371 cpumask_t cleanup_mask
;
2373 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2374 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2375 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2376 cfg
->move_in_progress
= 0;
2380 static inline void irq_complete_move(unsigned int irq
) {}
2382 #ifdef CONFIG_INTR_REMAP
2383 static void ack_x2apic_level(unsigned int irq
)
2388 static void ack_x2apic_edge(unsigned int irq
)
2394 static void ack_apic_edge(unsigned int irq
)
2396 irq_complete_move(irq
);
2397 move_native_irq(irq
);
2401 #ifdef CONFIG_X86_64
2402 static void ack_apic_level(unsigned int irq
)
2404 int do_unmask_irq
= 0;
2406 irq_complete_move(irq
);
2407 #ifdef CONFIG_GENERIC_PENDING_IRQ
2408 /* If we are moving the irq we need to mask it */
2409 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2411 mask_IO_APIC_irq(irq
);
2416 * We must acknowledge the irq before we move it or the acknowledge will
2417 * not propagate properly.
2421 /* Now we can move and renable the irq */
2422 if (unlikely(do_unmask_irq
)) {
2423 /* Only migrate the irq if the ack has been received.
2425 * On rare occasions the broadcast level triggered ack gets
2426 * delayed going to ioapics, and if we reprogram the
2427 * vector while Remote IRR is still set the irq will never
2430 * To prevent this scenario we read the Remote IRR bit
2431 * of the ioapic. This has two effects.
2432 * - On any sane system the read of the ioapic will
2433 * flush writes (and acks) going to the ioapic from
2435 * - We get to see if the ACK has actually been delivered.
2437 * Based on failed experiments of reprogramming the
2438 * ioapic entry from outside of irq context starting
2439 * with masking the ioapic entry and then polling until
2440 * Remote IRR was clear before reprogramming the
2441 * ioapic I don't trust the Remote IRR bit to be
2442 * completey accurate.
2444 * However there appears to be no other way to plug
2445 * this race, so if the Remote IRR bit is not
2446 * accurate and is causing problems then it is a hardware bug
2447 * and you can go talk to the chipset vendor about it.
2449 if (!io_apic_level_ack_pending(irq
))
2450 move_masked_irq(irq
);
2451 unmask_IO_APIC_irq(irq
);
2455 atomic_t irq_mis_count
;
2456 static void ack_apic_level(unsigned int irq
)
2461 irq_complete_move(irq
);
2462 move_native_irq(irq
);
2464 * It appears there is an erratum which affects at least version 0x11
2465 * of I/O APIC (that's the 82093AA and cores integrated into various
2466 * chipsets). Under certain conditions a level-triggered interrupt is
2467 * erroneously delivered as edge-triggered one but the respective IRR
2468 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2469 * message but it will never arrive and further interrupts are blocked
2470 * from the source. The exact reason is so far unknown, but the
2471 * phenomenon was observed when two consecutive interrupt requests
2472 * from a given source get delivered to the same CPU and the source is
2473 * temporarily disabled in between.
2475 * A workaround is to simulate an EOI message manually. We achieve it
2476 * by setting the trigger mode to edge and then to level when the edge
2477 * trigger mode gets detected in the TMR of a local APIC for a
2478 * level-triggered interrupt. We mask the source for the time of the
2479 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2480 * The idea is from Manfred Spraul. --macro
2482 i
= irq_cfg(irq
)->vector
;
2484 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2488 if (!(v
& (1 << (i
& 0x1f)))) {
2489 atomic_inc(&irq_mis_count
);
2490 spin_lock(&ioapic_lock
);
2491 __mask_and_edge_IO_APIC_irq(irq
);
2492 __unmask_and_level_IO_APIC_irq(irq
);
2493 spin_unlock(&ioapic_lock
);
2498 static struct irq_chip ioapic_chip __read_mostly
= {
2500 .startup
= startup_ioapic_irq
,
2501 .mask
= mask_IO_APIC_irq
,
2502 .unmask
= unmask_IO_APIC_irq
,
2503 .ack
= ack_apic_edge
,
2504 .eoi
= ack_apic_level
,
2506 .set_affinity
= set_ioapic_affinity_irq
,
2508 .retrigger
= ioapic_retrigger_irq
,
2511 #ifdef CONFIG_INTR_REMAP
2512 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2513 .name
= "IR-IO-APIC",
2514 .startup
= startup_ioapic_irq
,
2515 .mask
= mask_IO_APIC_irq
,
2516 .unmask
= unmask_IO_APIC_irq
,
2517 .ack
= ack_x2apic_edge
,
2518 .eoi
= ack_x2apic_level
,
2520 .set_affinity
= set_ir_ioapic_affinity_irq
,
2522 .retrigger
= ioapic_retrigger_irq
,
2526 static inline void init_IO_APIC_traps(void)
2529 struct irq_desc
*desc
;
2530 struct irq_cfg
*cfg
;
2533 * NOTE! The local APIC isn't very good at handling
2534 * multiple interrupts at the same interrupt level.
2535 * As the interrupt level is determined by taking the
2536 * vector number and shifting that right by 4, we
2537 * want to spread these out a bit so that they don't
2538 * all fall in the same interrupt level.
2540 * Also, we've got to be careful not to trash gate
2541 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2543 for_each_irq_cfg(cfg
) {
2545 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2547 * Hmm.. We don't have an entry for this,
2548 * so default to an old-fashioned 8259
2549 * interrupt if we can..
2552 make_8259A_irq(irq
);
2554 desc
= irq_to_desc(irq
);
2555 /* Strange. Oh, well.. */
2556 desc
->chip
= &no_irq_chip
;
2563 * The local APIC irq-chip implementation:
2566 static void mask_lapic_irq(unsigned int irq
)
2570 v
= apic_read(APIC_LVT0
);
2571 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2574 static void unmask_lapic_irq(unsigned int irq
)
2578 v
= apic_read(APIC_LVT0
);
2579 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2582 static void ack_lapic_irq (unsigned int irq
)
2587 static struct irq_chip lapic_chip __read_mostly
= {
2588 .name
= "local-APIC",
2589 .mask
= mask_lapic_irq
,
2590 .unmask
= unmask_lapic_irq
,
2591 .ack
= ack_lapic_irq
,
2594 static void lapic_register_intr(int irq
)
2596 struct irq_desc
*desc
;
2598 desc
= irq_to_desc(irq
);
2599 desc
->status
&= ~IRQ_LEVEL
;
2600 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2604 static void __init
setup_nmi(void)
2607 * Dirty trick to enable the NMI watchdog ...
2608 * We put the 8259A master into AEOI mode and
2609 * unmask on all local APICs LVT0 as NMI.
2611 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2612 * is from Maciej W. Rozycki - so we do not have to EOI from
2613 * the NMI handler or the timer interrupt.
2615 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2617 enable_NMI_through_LVT0();
2619 apic_printk(APIC_VERBOSE
, " done.\n");
2623 * This looks a bit hackish but it's about the only one way of sending
2624 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2625 * not support the ExtINT mode, unfortunately. We need to send these
2626 * cycles as some i82489DX-based boards have glue logic that keeps the
2627 * 8259A interrupt line asserted until INTA. --macro
2629 static inline void __init
unlock_ExtINT_logic(void)
2632 struct IO_APIC_route_entry entry0
, entry1
;
2633 unsigned char save_control
, save_freq_select
;
2635 pin
= find_isa_irq_pin(8, mp_INT
);
2640 apic
= find_isa_irq_apic(8, mp_INT
);
2646 entry0
= ioapic_read_entry(apic
, pin
);
2647 clear_IO_APIC_pin(apic
, pin
);
2649 memset(&entry1
, 0, sizeof(entry1
));
2651 entry1
.dest_mode
= 0; /* physical delivery */
2652 entry1
.mask
= 0; /* unmask IRQ now */
2653 entry1
.dest
= hard_smp_processor_id();
2654 entry1
.delivery_mode
= dest_ExtINT
;
2655 entry1
.polarity
= entry0
.polarity
;
2659 ioapic_write_entry(apic
, pin
, entry1
);
2661 save_control
= CMOS_READ(RTC_CONTROL
);
2662 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2663 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2665 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2670 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2674 CMOS_WRITE(save_control
, RTC_CONTROL
);
2675 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2676 clear_IO_APIC_pin(apic
, pin
);
2678 ioapic_write_entry(apic
, pin
, entry0
);
2681 static int disable_timer_pin_1 __initdata
;
2682 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2683 static int __init
disable_timer_pin_setup(char *arg
)
2685 disable_timer_pin_1
= 1;
2688 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2690 int timer_through_8259 __initdata
;
2693 * This code may look a bit paranoid, but it's supposed to cooperate with
2694 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2695 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2696 * fanatically on his truly buggy board.
2698 * FIXME: really need to revamp this for all platforms.
2700 static inline void __init
check_timer(void)
2702 struct irq_cfg
*cfg
= irq_cfg(0);
2703 int apic1
, pin1
, apic2
, pin2
;
2704 unsigned long flags
;
2708 local_irq_save(flags
);
2710 ver
= apic_read(APIC_LVR
);
2711 ver
= GET_APIC_VERSION(ver
);
2714 * get/set the timer IRQ vector:
2716 disable_8259A_irq(0);
2717 assign_irq_vector(0, TARGET_CPUS
);
2720 * As IRQ0 is to be enabled in the 8259A, the virtual
2721 * wire has to be disabled in the local APIC. Also
2722 * timer interrupts need to be acknowledged manually in
2723 * the 8259A for the i82489DX when using the NMI
2724 * watchdog as that APIC treats NMIs as level-triggered.
2725 * The AEOI mode will finish them in the 8259A
2728 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2730 #ifdef CONFIG_X86_32
2731 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2734 pin1
= find_isa_irq_pin(0, mp_INT
);
2735 apic1
= find_isa_irq_apic(0, mp_INT
);
2736 pin2
= ioapic_i8259
.pin
;
2737 apic2
= ioapic_i8259
.apic
;
2739 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2740 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2741 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2744 * Some BIOS writers are clueless and report the ExtINTA
2745 * I/O APIC input from the cascaded 8259A as the timer
2746 * interrupt input. So just in case, if only one pin
2747 * was found above, try it both directly and through the
2751 #ifdef CONFIG_INTR_REMAP
2752 if (intr_remapping_enabled
)
2753 panic("BIOS bug: timer not connected to IO-APIC");
2758 } else if (pin2
== -1) {
2765 * Ok, does IRQ0 through the IOAPIC work?
2768 add_pin_to_irq(0, apic1
, pin1
);
2769 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2771 unmask_IO_APIC_irq(0);
2772 if (timer_irq_works()) {
2773 if (nmi_watchdog
== NMI_IO_APIC
) {
2775 enable_8259A_irq(0);
2777 if (disable_timer_pin_1
> 0)
2778 clear_IO_APIC_pin(0, pin1
);
2781 #ifdef CONFIG_INTR_REMAP
2782 if (intr_remapping_enabled
)
2783 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2785 clear_IO_APIC_pin(apic1
, pin1
);
2787 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2788 "8254 timer not connected to IO-APIC\n");
2790 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2791 "(IRQ0) through the 8259A ...\n");
2792 apic_printk(APIC_QUIET
, KERN_INFO
2793 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2795 * legacy devices should be connected to IO APIC #0
2797 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2798 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2799 unmask_IO_APIC_irq(0);
2800 enable_8259A_irq(0);
2801 if (timer_irq_works()) {
2802 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2803 timer_through_8259
= 1;
2804 if (nmi_watchdog
== NMI_IO_APIC
) {
2805 disable_8259A_irq(0);
2807 enable_8259A_irq(0);
2812 * Cleanup, just in case ...
2814 disable_8259A_irq(0);
2815 clear_IO_APIC_pin(apic2
, pin2
);
2816 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2819 if (nmi_watchdog
== NMI_IO_APIC
) {
2820 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2821 "through the IO-APIC - disabling NMI Watchdog!\n");
2822 nmi_watchdog
= NMI_NONE
;
2824 #ifdef CONFIG_X86_32
2828 apic_printk(APIC_QUIET
, KERN_INFO
2829 "...trying to set up timer as Virtual Wire IRQ...\n");
2831 lapic_register_intr(0);
2832 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2833 enable_8259A_irq(0);
2835 if (timer_irq_works()) {
2836 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2839 disable_8259A_irq(0);
2840 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2841 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2843 apic_printk(APIC_QUIET
, KERN_INFO
2844 "...trying to set up timer as ExtINT IRQ...\n");
2848 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2850 unlock_ExtINT_logic();
2852 if (timer_irq_works()) {
2853 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2856 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2857 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2858 "report. Then try booting with the 'noapic' option.\n");
2860 local_irq_restore(flags
);
2864 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2865 * to devices. However there may be an I/O APIC pin available for
2866 * this interrupt regardless. The pin may be left unconnected, but
2867 * typically it will be reused as an ExtINT cascade interrupt for
2868 * the master 8259A. In the MPS case such a pin will normally be
2869 * reported as an ExtINT interrupt in the MP table. With ACPI
2870 * there is no provision for ExtINT interrupts, and in the absence
2871 * of an override it would be treated as an ordinary ISA I/O APIC
2872 * interrupt, that is edge-triggered and unmasked by default. We
2873 * used to do this, but it caused problems on some systems because
2874 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2875 * the same ExtINT cascade interrupt to drive the local APIC of the
2876 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2877 * the I/O APIC in all cases now. No actual device should request
2878 * it anyway. --macro
2880 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2882 void __init
setup_IO_APIC(void)
2885 #ifdef CONFIG_X86_32
2889 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2893 io_apic_irqs
= ~PIC_IRQS
;
2895 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2897 * Set up IO-APIC IRQ routing.
2899 #ifdef CONFIG_X86_32
2901 setup_ioapic_ids_from_mpc();
2904 setup_IO_APIC_irqs();
2905 init_IO_APIC_traps();
2910 * Called after all the initialization is done. If we didnt find any
2911 * APIC bugs then we can allow the modify fast path
2914 static int __init
io_apic_bug_finalize(void)
2916 if (sis_apic_bug
== -1)
2921 late_initcall(io_apic_bug_finalize
);
2923 struct sysfs_ioapic_data
{
2924 struct sys_device dev
;
2925 struct IO_APIC_route_entry entry
[0];
2927 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2929 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2931 struct IO_APIC_route_entry
*entry
;
2932 struct sysfs_ioapic_data
*data
;
2935 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2936 entry
= data
->entry
;
2937 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2938 *entry
= ioapic_read_entry(dev
->id
, i
);
2943 static int ioapic_resume(struct sys_device
*dev
)
2945 struct IO_APIC_route_entry
*entry
;
2946 struct sysfs_ioapic_data
*data
;
2947 unsigned long flags
;
2948 union IO_APIC_reg_00 reg_00
;
2951 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2952 entry
= data
->entry
;
2954 spin_lock_irqsave(&ioapic_lock
, flags
);
2955 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2956 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2957 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2958 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2960 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2961 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2962 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2967 static struct sysdev_class ioapic_sysdev_class
= {
2969 .suspend
= ioapic_suspend
,
2970 .resume
= ioapic_resume
,
2973 static int __init
ioapic_init_sysfs(void)
2975 struct sys_device
* dev
;
2978 error
= sysdev_class_register(&ioapic_sysdev_class
);
2982 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2983 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2984 * sizeof(struct IO_APIC_route_entry
);
2985 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2986 if (!mp_ioapic_data
[i
]) {
2987 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2990 dev
= &mp_ioapic_data
[i
]->dev
;
2992 dev
->cls
= &ioapic_sysdev_class
;
2993 error
= sysdev_register(dev
);
2995 kfree(mp_ioapic_data
[i
]);
2996 mp_ioapic_data
[i
] = NULL
;
2997 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3005 device_initcall(ioapic_init_sysfs
);
3008 * Dynamic irq allocate and deallocation
3010 unsigned int create_irq_nr(unsigned int irq_want
)
3012 /* Allocate an unused irq */
3015 unsigned long flags
;
3016 struct irq_cfg
*cfg_new
;
3018 #ifndef CONFIG_HAVE_SPARSE_IRQ
3019 irq_want
= nr_irqs
- 1;
3023 spin_lock_irqsave(&vector_lock
, flags
);
3024 for (new = irq_want
; new > 0; new--) {
3025 if (platform_legacy_irq(new))
3027 cfg_new
= irq_cfg(new);
3028 if (cfg_new
&& cfg_new
->vector
!= 0)
3030 /* check if need to create one */
3032 cfg_new
= irq_cfg_alloc(new);
3033 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
3037 spin_unlock_irqrestore(&vector_lock
, flags
);
3040 dynamic_irq_init(irq
);
3045 int create_irq(void)
3049 irq
= create_irq_nr(nr_irqs
- 1);
3057 void destroy_irq(unsigned int irq
)
3059 unsigned long flags
;
3061 dynamic_irq_cleanup(irq
);
3063 #ifdef CONFIG_INTR_REMAP
3066 spin_lock_irqsave(&vector_lock
, flags
);
3067 __clear_irq_vector(irq
);
3068 spin_unlock_irqrestore(&vector_lock
, flags
);
3072 * MSI message composition
3074 #ifdef CONFIG_PCI_MSI
3075 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3077 struct irq_cfg
*cfg
;
3083 err
= assign_irq_vector(irq
, tmp
);
3088 cpus_and(tmp
, cfg
->domain
, tmp
);
3089 dest
= cpu_mask_to_apicid(tmp
);
3091 #ifdef CONFIG_INTR_REMAP
3092 if (irq_remapped(irq
)) {
3097 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3098 BUG_ON(ir_index
== -1);
3100 memset (&irte
, 0, sizeof(irte
));
3103 irte
.dst_mode
= INT_DEST_MODE
;
3104 irte
.trigger_mode
= 0; /* edge */
3105 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3106 irte
.vector
= cfg
->vector
;
3107 irte
.dest_id
= IRTE_DEST(dest
);
3109 modify_irte(irq
, &irte
);
3111 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3112 msg
->data
= sub_handle
;
3113 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3115 MSI_ADDR_IR_INDEX1(ir_index
) |
3116 MSI_ADDR_IR_INDEX2(ir_index
);
3120 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3123 ((INT_DEST_MODE
== 0) ?
3124 MSI_ADDR_DEST_MODE_PHYSICAL
:
3125 MSI_ADDR_DEST_MODE_LOGICAL
) |
3126 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3127 MSI_ADDR_REDIRECTION_CPU
:
3128 MSI_ADDR_REDIRECTION_LOWPRI
) |
3129 MSI_ADDR_DEST_ID(dest
);
3132 MSI_DATA_TRIGGER_EDGE
|
3133 MSI_DATA_LEVEL_ASSERT
|
3134 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3135 MSI_DATA_DELIVERY_FIXED
:
3136 MSI_DATA_DELIVERY_LOWPRI
) |
3137 MSI_DATA_VECTOR(cfg
->vector
);
3143 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3145 struct irq_cfg
*cfg
;
3149 struct irq_desc
*desc
;
3151 cpus_and(tmp
, mask
, cpu_online_map
);
3152 if (cpus_empty(tmp
))
3155 if (assign_irq_vector(irq
, mask
))
3159 cpus_and(tmp
, cfg
->domain
, mask
);
3160 dest
= cpu_mask_to_apicid(tmp
);
3162 read_msi_msg(irq
, &msg
);
3164 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3165 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3166 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3167 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3169 write_msi_msg(irq
, &msg
);
3170 desc
= irq_to_desc(irq
);
3171 desc
->affinity
= mask
;
3174 #ifdef CONFIG_INTR_REMAP
3176 * Migrate the MSI irq to another cpumask. This migration is
3177 * done in the process context using interrupt-remapping hardware.
3179 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3181 struct irq_cfg
*cfg
;
3183 cpumask_t tmp
, cleanup_mask
;
3185 struct irq_desc
*desc
;
3187 cpus_and(tmp
, mask
, cpu_online_map
);
3188 if (cpus_empty(tmp
))
3191 if (get_irte(irq
, &irte
))
3194 if (assign_irq_vector(irq
, mask
))
3198 cpus_and(tmp
, cfg
->domain
, mask
);
3199 dest
= cpu_mask_to_apicid(tmp
);
3201 irte
.vector
= cfg
->vector
;
3202 irte
.dest_id
= IRTE_DEST(dest
);
3205 * atomically update the IRTE with the new destination and vector.
3207 modify_irte(irq
, &irte
);
3210 * After this point, all the interrupts will start arriving
3211 * at the new destination. So, time to cleanup the previous
3212 * vector allocation.
3214 if (cfg
->move_in_progress
) {
3215 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
3216 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
3217 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
3218 cfg
->move_in_progress
= 0;
3221 desc
= irq_to_desc(irq
);
3222 desc
->affinity
= mask
;
3225 #endif /* CONFIG_SMP */
3228 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3229 * which implement the MSI or MSI-X Capability Structure.
3231 static struct irq_chip msi_chip
= {
3233 .unmask
= unmask_msi_irq
,
3234 .mask
= mask_msi_irq
,
3235 .ack
= ack_apic_edge
,
3237 .set_affinity
= set_msi_irq_affinity
,
3239 .retrigger
= ioapic_retrigger_irq
,
3242 #ifdef CONFIG_INTR_REMAP
3243 static struct irq_chip msi_ir_chip
= {
3244 .name
= "IR-PCI-MSI",
3245 .unmask
= unmask_msi_irq
,
3246 .mask
= mask_msi_irq
,
3247 .ack
= ack_x2apic_edge
,
3249 .set_affinity
= ir_set_msi_irq_affinity
,
3251 .retrigger
= ioapic_retrigger_irq
,
3255 * Map the PCI dev to the corresponding remapping hardware unit
3256 * and allocate 'nvec' consecutive interrupt-remapping table entries
3259 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3261 struct intel_iommu
*iommu
;
3264 iommu
= map_dev_to_ir(dev
);
3267 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3271 index
= alloc_irte(iommu
, irq
, nvec
);
3274 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3282 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
3287 ret
= msi_compose_msg(dev
, irq
, &msg
);
3291 set_irq_msi(irq
, desc
);
3292 write_msi_msg(irq
, &msg
);
3294 #ifdef CONFIG_INTR_REMAP
3295 if (irq_remapped(irq
)) {
3296 struct irq_desc
*desc
= irq_to_desc(irq
);
3298 * irq migration in process context
3300 desc
->status
|= IRQ_MOVE_PCNTXT
;
3301 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3304 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3309 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
3313 irq
= dev
->bus
->number
;
3321 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
3325 unsigned int irq_want
;
3327 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3329 irq
= create_irq_nr(irq_want
);
3333 #ifdef CONFIG_INTR_REMAP
3334 if (!intr_remapping_enabled
)
3337 ret
= msi_alloc_irte(dev
, irq
, 1);
3342 ret
= setup_msi_irq(dev
, desc
, irq
);
3349 #ifdef CONFIG_INTR_REMAP
3356 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3359 int ret
, sub_handle
;
3360 struct msi_desc
*desc
;
3361 unsigned int irq_want
;
3363 #ifdef CONFIG_INTR_REMAP
3364 struct intel_iommu
*iommu
= 0;
3368 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3370 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
3371 irq
= create_irq_nr(irq_want
--);
3374 #ifdef CONFIG_INTR_REMAP
3375 if (!intr_remapping_enabled
)
3380 * allocate the consecutive block of IRTE's
3383 index
= msi_alloc_irte(dev
, irq
, nvec
);
3389 iommu
= map_dev_to_ir(dev
);
3395 * setup the mapping between the irq and the IRTE
3396 * base index, the sub_handle pointing to the
3397 * appropriate interrupt remap table entry.
3399 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3403 ret
= setup_msi_irq(dev
, desc
, irq
);
3415 void arch_teardown_msi_irq(unsigned int irq
)
3422 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
3424 struct irq_cfg
*cfg
;
3428 struct irq_desc
*desc
;
3430 cpus_and(tmp
, mask
, cpu_online_map
);
3431 if (cpus_empty(tmp
))
3434 if (assign_irq_vector(irq
, mask
))
3438 cpus_and(tmp
, cfg
->domain
, mask
);
3439 dest
= cpu_mask_to_apicid(tmp
);
3441 dmar_msi_read(irq
, &msg
);
3443 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3444 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3445 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3446 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3448 dmar_msi_write(irq
, &msg
);
3449 desc
= irq_to_desc(irq
);
3450 desc
->affinity
= mask
;
3452 #endif /* CONFIG_SMP */
3454 struct irq_chip dmar_msi_type
= {
3456 .unmask
= dmar_msi_unmask
,
3457 .mask
= dmar_msi_mask
,
3458 .ack
= ack_apic_edge
,
3460 .set_affinity
= dmar_msi_set_affinity
,
3462 .retrigger
= ioapic_retrigger_irq
,
3465 int arch_setup_dmar_msi(unsigned int irq
)
3470 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3473 dmar_msi_write(irq
, &msg
);
3474 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3480 #endif /* CONFIG_PCI_MSI */
3482 * Hypertransport interrupt support
3484 #ifdef CONFIG_HT_IRQ
3488 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3490 struct ht_irq_msg msg
;
3491 fetch_ht_irq_msg(irq
, &msg
);
3493 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3494 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3496 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3497 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3499 write_ht_irq_msg(irq
, &msg
);
3502 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
3504 struct irq_cfg
*cfg
;
3507 struct irq_desc
*desc
;
3509 cpus_and(tmp
, mask
, cpu_online_map
);
3510 if (cpus_empty(tmp
))
3513 if (assign_irq_vector(irq
, mask
))
3517 cpus_and(tmp
, cfg
->domain
, mask
);
3518 dest
= cpu_mask_to_apicid(tmp
);
3520 target_ht_irq(irq
, dest
, cfg
->vector
);
3521 desc
= irq_to_desc(irq
);
3522 desc
->affinity
= mask
;
3526 static struct irq_chip ht_irq_chip
= {
3528 .mask
= mask_ht_irq
,
3529 .unmask
= unmask_ht_irq
,
3530 .ack
= ack_apic_edge
,
3532 .set_affinity
= set_ht_irq_affinity
,
3534 .retrigger
= ioapic_retrigger_irq
,
3537 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3539 struct irq_cfg
*cfg
;
3544 err
= assign_irq_vector(irq
, tmp
);
3546 struct ht_irq_msg msg
;
3550 cpus_and(tmp
, cfg
->domain
, tmp
);
3551 dest
= cpu_mask_to_apicid(tmp
);
3553 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3557 HT_IRQ_LOW_DEST_ID(dest
) |
3558 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3559 ((INT_DEST_MODE
== 0) ?
3560 HT_IRQ_LOW_DM_PHYSICAL
:
3561 HT_IRQ_LOW_DM_LOGICAL
) |
3562 HT_IRQ_LOW_RQEOI_EDGE
|
3563 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3564 HT_IRQ_LOW_MT_FIXED
:
3565 HT_IRQ_LOW_MT_ARBITRATED
) |
3566 HT_IRQ_LOW_IRQ_MASKED
;
3568 write_ht_irq_msg(irq
, &msg
);
3570 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3571 handle_edge_irq
, "edge");
3575 #endif /* CONFIG_HT_IRQ */
3577 /* --------------------------------------------------------------------------
3578 ACPI-based IOAPIC Configuration
3579 -------------------------------------------------------------------------- */
3583 #ifdef CONFIG_X86_32
3584 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3586 union IO_APIC_reg_00 reg_00
;
3587 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3589 unsigned long flags
;
3593 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3594 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3595 * supports up to 16 on one shared APIC bus.
3597 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3598 * advantage of new APIC bus architecture.
3601 if (physids_empty(apic_id_map
))
3602 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3604 spin_lock_irqsave(&ioapic_lock
, flags
);
3605 reg_00
.raw
= io_apic_read(ioapic
, 0);
3606 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3608 if (apic_id
>= get_physical_broadcast()) {
3609 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3610 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3611 apic_id
= reg_00
.bits
.ID
;
3615 * Every APIC in a system must have a unique ID or we get lots of nice
3616 * 'stuck on smp_invalidate_needed IPI wait' messages.
3618 if (check_apicid_used(apic_id_map
, apic_id
)) {
3620 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3621 if (!check_apicid_used(apic_id_map
, i
))
3625 if (i
== get_physical_broadcast())
3626 panic("Max apic_id exceeded!\n");
3628 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3629 "trying %d\n", ioapic
, apic_id
, i
);
3634 tmp
= apicid_to_cpu_present(apic_id
);
3635 physids_or(apic_id_map
, apic_id_map
, tmp
);
3637 if (reg_00
.bits
.ID
!= apic_id
) {
3638 reg_00
.bits
.ID
= apic_id
;
3640 spin_lock_irqsave(&ioapic_lock
, flags
);
3641 io_apic_write(ioapic
, 0, reg_00
.raw
);
3642 reg_00
.raw
= io_apic_read(ioapic
, 0);
3643 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3646 if (reg_00
.bits
.ID
!= apic_id
) {
3647 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3652 apic_printk(APIC_VERBOSE
, KERN_INFO
3653 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3658 int __init
io_apic_get_version(int ioapic
)
3660 union IO_APIC_reg_01 reg_01
;
3661 unsigned long flags
;
3663 spin_lock_irqsave(&ioapic_lock
, flags
);
3664 reg_01
.raw
= io_apic_read(ioapic
, 1);
3665 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3667 return reg_01
.bits
.version
;
3671 int __init
io_apic_get_redir_entries (int ioapic
)
3673 union IO_APIC_reg_01 reg_01
;
3674 unsigned long flags
;
3676 spin_lock_irqsave(&ioapic_lock
, flags
);
3677 reg_01
.raw
= io_apic_read(ioapic
, 1);
3678 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3680 return reg_01
.bits
.entries
;
3684 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3686 if (!IO_APIC_IRQ(irq
)) {
3687 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3693 * IRQs < 16 are already in the irq_2_pin[] map
3696 add_pin_to_irq(irq
, ioapic
, pin
);
3698 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
3704 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3708 if (skip_ioapic_setup
)
3711 for (i
= 0; i
< mp_irq_entries
; i
++)
3712 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3713 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3715 if (i
>= mp_irq_entries
)
3718 *trigger
= irq_trigger(i
);
3719 *polarity
= irq_polarity(i
);
3723 #endif /* CONFIG_ACPI */
3726 * This function currently is only a helper for the i386 smp boot process where
3727 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3728 * so mask in all cases should simply be TARGET_CPUS
3731 void __init
setup_ioapic_dest(void)
3733 int pin
, ioapic
, irq
, irq_entry
;
3734 struct irq_cfg
*cfg
;
3736 if (skip_ioapic_setup
== 1)
3739 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3740 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3741 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3742 if (irq_entry
== -1)
3744 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3746 /* setup_IO_APIC_irqs could fail to get vector for some device
3747 * when you have too many devices, because at that time only boot
3752 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3753 irq_trigger(irq_entry
),
3754 irq_polarity(irq_entry
));
3755 #ifdef CONFIG_INTR_REMAP
3756 else if (intr_remapping_enabled
)
3757 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3760 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3767 #define IOAPIC_RESOURCE_NAME_SIZE 11
3769 static struct resource
*ioapic_resources
;
3771 static struct resource
* __init
ioapic_setup_resources(void)
3774 struct resource
*res
;
3778 if (nr_ioapics
<= 0)
3781 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3784 mem
= alloc_bootmem(n
);
3788 mem
+= sizeof(struct resource
) * nr_ioapics
;
3790 for (i
= 0; i
< nr_ioapics
; i
++) {
3792 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3793 sprintf(mem
, "IOAPIC %u", i
);
3794 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3798 ioapic_resources
= res
;
3803 void __init
ioapic_init_mappings(void)
3805 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3807 struct resource
*ioapic_res
;
3809 ioapic_res
= ioapic_setup_resources();
3810 for (i
= 0; i
< nr_ioapics
; i
++) {
3811 if (smp_found_config
) {
3812 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3813 #ifdef CONFIG_X86_32
3816 "WARNING: bogus zero IO-APIC "
3817 "address found in MPTABLE, "
3818 "disabling IO/APIC support!\n");
3819 smp_found_config
= 0;
3820 skip_ioapic_setup
= 1;
3821 goto fake_ioapic_page
;
3825 #ifdef CONFIG_X86_32
3828 ioapic_phys
= (unsigned long)
3829 alloc_bootmem_pages(PAGE_SIZE
);
3830 ioapic_phys
= __pa(ioapic_phys
);
3832 set_fixmap_nocache(idx
, ioapic_phys
);
3833 apic_printk(APIC_VERBOSE
,
3834 "mapped IOAPIC to %08lx (%08lx)\n",
3835 __fix_to_virt(idx
), ioapic_phys
);
3838 if (ioapic_res
!= NULL
) {
3839 ioapic_res
->start
= ioapic_phys
;
3840 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3846 static int __init
ioapic_insert_resources(void)
3849 struct resource
*r
= ioapic_resources
;
3853 "IO APIC resources could be not be allocated.\n");
3857 for (i
= 0; i
< nr_ioapics
; i
++) {
3858 insert_resource(&iomem_resource
, r
);
3865 /* Insert the IO APIC resources after PCI initialization has occured to handle
3866 * IO APICS that are mapped in on a BAR in PCI space. */
3867 late_initcall(ioapic_insert_resources
);