2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
61 #include <mach_apic.h>
62 #include <mach_apicdef.h>
64 #define __apicdebuginit(type) static type __init
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
70 int sis_apic_bug
= -1;
72 static DEFINE_SPINLOCK(ioapic_lock
);
73 static DEFINE_SPINLOCK(vector_lock
);
77 * Rough estimation of how many shared IRQs there are, can
83 * # of IRQ routing registers
85 int nr_ioapic_registers
[MAX_IO_APICS
];
87 /* I/O APIC entries */
88 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
91 /* MP IRQ source entries */
92 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
94 /* # of MP IRQ source entries */
97 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
98 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
101 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
103 int skip_ioapic_setup
;
105 static int __init
parse_noapic(char *str
)
107 /* disable IO-APIC */
108 disable_ioapic_setup();
111 early_param("noapic", parse_noapic
);
117 struct irq_cfg
*next
;
118 struct irq_pin_list
*irq_2_pin
;
120 cpumask_t old_domain
;
121 unsigned move_cleanup_count
;
123 u8 move_in_progress
: 1;
126 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
127 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
128 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
129 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
130 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
131 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
132 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
133 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
134 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
135 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
136 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
137 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
138 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
139 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
140 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
141 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
142 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
143 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
146 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
147 /* need to be biger than size of irq_cfg_legacy */
148 static int nr_irq_cfg
= 32;
150 static int __init
parse_nr_irq_cfg(char *arg
)
153 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
160 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
162 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
164 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
167 static struct irq_cfg
*irq_cfgx
;
168 static struct irq_cfg
*irq_cfgx_free
;
169 static void __init
init_work(void *data
)
171 struct dyn_array
*da
= data
;
178 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
180 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
181 for (i
= legacy_count
; i
< *da
->nr
; i
++)
182 init_one_irq_cfg(&cfg
[i
]);
184 for (i
= 1; i
< *da
->nr
; i
++)
185 cfg
[i
-1].next
= &cfg
[i
];
187 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
188 irq_cfgx
[legacy_count
- 1].next
= NULL
;
191 #define for_each_irq_cfg(cfg) \
192 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
194 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
196 static struct irq_cfg
*irq_cfg(unsigned int irq
)
211 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
213 struct irq_cfg
*cfg
, *cfg_pri
;
217 cfg_pri
= cfg
= irq_cfgx
;
227 if (!irq_cfgx_free
) {
229 unsigned long total_bytes
;
231 * we run out of pre-allocate ones, allocate more
233 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
235 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
237 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
239 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
242 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
245 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
247 for (i
= 0; i
< nr_irq_cfg
; i
++)
248 init_one_irq_cfg(&cfg
[i
]);
250 for (i
= 1; i
< nr_irq_cfg
; i
++)
251 cfg
[i
-1].next
= &cfg
[i
];
257 irq_cfgx_free
= irq_cfgx_free
->next
;
264 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
265 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
267 /* dump the results */
270 unsigned long bytes
= sizeof(struct irq_cfg
);
272 printk(KERN_DEBUG
"=========================== %d\n", irq
);
273 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
274 for_each_irq_cfg(cfg
) {
276 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
278 printk(KERN_DEBUG
"===========================\n");
285 * This is performance-critical, we want to do it O(1)
287 * the indexing order of this array favors 1:1 mappings
288 * between pins and IRQs.
291 struct irq_pin_list
{
293 struct irq_pin_list
*next
;
296 static struct irq_pin_list
*irq_2_pin_head
;
297 /* fill one page ? */
298 static int nr_irq_2_pin
= 0x100;
299 static struct irq_pin_list
*irq_2_pin_ptr
;
300 static void __init
irq_2_pin_init_work(void *data
)
302 struct dyn_array
*da
= data
;
303 struct irq_pin_list
*pin
;
308 for (i
= 1; i
< *da
->nr
; i
++)
309 pin
[i
-1].next
= &pin
[i
];
311 irq_2_pin_ptr
= &pin
[0];
313 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
315 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
317 struct irq_pin_list
*pin
;
323 irq_2_pin_ptr
= pin
->next
;
329 * we run out of pre-allocate ones, allocate more
331 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
334 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
337 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
338 nr_irq_2_pin
, PAGE_SIZE
, 0);
341 panic("can not get more irq_2_pin\n");
343 for (i
= 1; i
< nr_irq_2_pin
; i
++)
344 pin
[i
-1].next
= &pin
[i
];
346 irq_2_pin_ptr
= pin
->next
;
354 unsigned int unused
[3];
358 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
360 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
361 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
364 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
366 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
367 writel(reg
, &io_apic
->index
);
368 return readl(&io_apic
->data
);
371 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
373 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
374 writel(reg
, &io_apic
->index
);
375 writel(value
, &io_apic
->data
);
379 * Re-write a value: to be used for read-modify-write
380 * cycles where the read already set up the index register.
382 * Older SiS APIC requires we rewrite the index register
384 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
386 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
388 writel(reg
, &io_apic
->index
);
389 writel(value
, &io_apic
->data
);
392 static bool io_apic_level_ack_pending(unsigned int irq
)
394 struct irq_pin_list
*entry
;
396 struct irq_cfg
*cfg
= irq_cfg(irq
);
398 spin_lock_irqsave(&ioapic_lock
, flags
);
399 entry
= cfg
->irq_2_pin
;
407 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
408 /* Is the remote IRR bit set? */
409 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
410 spin_unlock_irqrestore(&ioapic_lock
, flags
);
417 spin_unlock_irqrestore(&ioapic_lock
, flags
);
423 struct { u32 w1
, w2
; };
424 struct IO_APIC_route_entry entry
;
427 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
429 union entry_union eu
;
431 spin_lock_irqsave(&ioapic_lock
, flags
);
432 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
433 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
434 spin_unlock_irqrestore(&ioapic_lock
, flags
);
439 * When we write a new IO APIC routing entry, we need to write the high
440 * word first! If the mask bit in the low word is clear, we will enable
441 * the interrupt, and we need to make sure the entry is fully populated
442 * before that happens.
445 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
447 union entry_union eu
;
449 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
450 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
453 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
456 spin_lock_irqsave(&ioapic_lock
, flags
);
457 __ioapic_write_entry(apic
, pin
, e
);
458 spin_unlock_irqrestore(&ioapic_lock
, flags
);
462 * When we mask an IO APIC routing entry, we need to write the low
463 * word first, in order to set the mask bit before we change the
466 static void ioapic_mask_entry(int apic
, int pin
)
469 union entry_union eu
= { .entry
.mask
= 1 };
471 spin_lock_irqsave(&ioapic_lock
, flags
);
472 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
473 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
474 spin_unlock_irqrestore(&ioapic_lock
, flags
);
478 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
482 struct irq_pin_list
*entry
;
485 entry
= cfg
->irq_2_pin
;
494 #ifdef CONFIG_INTR_REMAP
496 * With interrupt-remapping, destination information comes
497 * from interrupt-remapping table entry.
499 if (!irq_remapped(irq
))
500 io_apic_write(apic
, 0x11 + pin
*2, dest
);
502 io_apic_write(apic
, 0x11 + pin
*2, dest
);
504 reg
= io_apic_read(apic
, 0x10 + pin
*2);
505 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
507 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
514 static int assign_irq_vector(int irq
, cpumask_t mask
);
516 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
522 struct irq_desc
*desc
;
524 cpus_and(tmp
, mask
, cpu_online_map
);
529 if (assign_irq_vector(irq
, mask
))
532 cpus_and(tmp
, cfg
->domain
, mask
);
533 dest
= cpu_mask_to_apicid(tmp
);
535 * Only the high 8 bits are valid.
537 dest
= SET_APIC_LOGICAL_ID(dest
);
539 desc
= irq_to_desc(irq
);
540 spin_lock_irqsave(&ioapic_lock
, flags
);
541 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
542 desc
->affinity
= mask
;
543 spin_unlock_irqrestore(&ioapic_lock
, flags
);
545 #endif /* CONFIG_SMP */
548 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
549 * shared ISA-space IRQs, so we have to support them. We are super
550 * fast in the common case, and fast for shared ISA-space IRQs.
552 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
555 struct irq_pin_list
*entry
;
557 /* first time to refer irq_cfg, so with new */
558 cfg
= irq_cfg_alloc(irq
);
559 entry
= cfg
->irq_2_pin
;
561 entry
= get_one_free_irq_2_pin();
562 cfg
->irq_2_pin
= entry
;
565 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
569 while (entry
->next
) {
570 /* not again, please */
571 if (entry
->apic
== apic
&& entry
->pin
== pin
)
577 entry
->next
= get_one_free_irq_2_pin();
581 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
585 * Reroute an IRQ to a different pin.
587 static void __init
replace_pin_at_irq(unsigned int irq
,
588 int oldapic
, int oldpin
,
589 int newapic
, int newpin
)
591 struct irq_cfg
*cfg
= irq_cfg(irq
);
592 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
596 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
597 entry
->apic
= newapic
;
600 /* every one is different, right? */
606 /* why? call replace before add? */
608 add_pin_to_irq(irq
, newapic
, newpin
);
611 #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
615 struct irq_cfg *cfg; \
616 struct irq_pin_list *entry; \
618 cfg = irq_cfg(irq); \
619 entry = cfg->irq_2_pin; \
625 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
626 reg ACTION_DISABLE; \
628 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
632 entry = entry->next; \
636 #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
638 static void name##_IO_APIC_irq (unsigned int irq) \
639 __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
642 DO_ACTION(__unmask
, 0, |= 0, &= ~IO_APIC_REDIR_MASKED
, )
646 * Synchronize the IO-APIC and the CPU by doing
647 * a dummy read from the IO-APIC
649 static inline void io_apic_sync(unsigned int apic
)
651 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
652 readl(&io_apic
->data
);
656 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, &= ~0, io_apic_sync(entry
->apic
))
661 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, &= ~0, )
663 /* mask = 1, trigger = 0 */
664 DO_ACTION(__mask_and_edge
, 0, |= IO_APIC_REDIR_MASKED
, &= ~IO_APIC_REDIR_LEVEL_TRIGGER
, )
666 /* mask = 0, trigger = 1 */
667 DO_ACTION(__unmask_and_level
, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER
, &= ~IO_APIC_REDIR_MASKED
, )
671 static void mask_IO_APIC_irq (unsigned int irq
)
675 spin_lock_irqsave(&ioapic_lock
, flags
);
676 __mask_IO_APIC_irq(irq
);
677 spin_unlock_irqrestore(&ioapic_lock
, flags
);
680 static void unmask_IO_APIC_irq (unsigned int irq
)
684 spin_lock_irqsave(&ioapic_lock
, flags
);
685 __unmask_IO_APIC_irq(irq
);
686 spin_unlock_irqrestore(&ioapic_lock
, flags
);
689 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
691 struct IO_APIC_route_entry entry
;
693 /* Check delivery_mode to be sure we're not clearing an SMI pin */
694 entry
= ioapic_read_entry(apic
, pin
);
695 if (entry
.delivery_mode
== dest_SMI
)
698 * Disable it in the IO-APIC irq-routing table:
700 ioapic_mask_entry(apic
, pin
);
703 static void clear_IO_APIC (void)
707 for (apic
= 0; apic
< nr_ioapics
; apic
++)
708 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
709 clear_IO_APIC_pin(apic
, pin
);
712 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
713 void send_IPI_self(int vector
)
720 apic_wait_icr_idle();
721 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
723 * Send the IPI. The write to APIC_ICR fires this off.
725 apic_write(APIC_ICR
, cfg
);
727 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
731 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
732 * specific CPU-side IRQs.
736 static int pirq_entries
[MAX_PIRQS
];
737 static int pirqs_enabled
;
739 static int __init
ioapic_pirq_setup(char *str
)
742 int ints
[MAX_PIRQS
+1];
744 get_options(str
, ARRAY_SIZE(ints
), ints
);
746 for (i
= 0; i
< MAX_PIRQS
; i
++)
747 pirq_entries
[i
] = -1;
750 apic_printk(APIC_VERBOSE
, KERN_INFO
751 "PIRQ redirection, working around broken MP-BIOS.\n");
753 if (ints
[0] < MAX_PIRQS
)
756 for (i
= 0; i
< max
; i
++) {
757 apic_printk(APIC_VERBOSE
, KERN_DEBUG
758 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
760 * PIRQs are mapped upside down, usually.
762 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
767 __setup("pirq=", ioapic_pirq_setup
);
768 #endif /* CONFIG_X86_32 */
770 #ifdef CONFIG_INTR_REMAP
771 /* I/O APIC RTE contents at the OS boot up */
772 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
775 * Saves and masks all the unmasked IO-APIC RTE's
777 int save_mask_IO_APIC_setup(void)
779 union IO_APIC_reg_01 reg_01
;
784 * The number of IO-APIC IRQ registers (== #pins):
786 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
787 spin_lock_irqsave(&ioapic_lock
, flags
);
788 reg_01
.raw
= io_apic_read(apic
, 1);
789 spin_unlock_irqrestore(&ioapic_lock
, flags
);
790 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
793 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
794 early_ioapic_entries
[apic
] =
795 kzalloc(sizeof(struct IO_APIC_route_entry
) *
796 nr_ioapic_registers
[apic
], GFP_KERNEL
);
797 if (!early_ioapic_entries
[apic
])
801 for (apic
= 0; apic
< nr_ioapics
; apic
++)
802 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
803 struct IO_APIC_route_entry entry
;
805 entry
= early_ioapic_entries
[apic
][pin
] =
806 ioapic_read_entry(apic
, pin
);
809 ioapic_write_entry(apic
, pin
, entry
);
815 void restore_IO_APIC_setup(void)
819 for (apic
= 0; apic
< nr_ioapics
; apic
++)
820 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
821 ioapic_write_entry(apic
, pin
,
822 early_ioapic_entries
[apic
][pin
]);
825 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
828 * for now plain restore of previous settings.
829 * TBD: In the case of OS enabling interrupt-remapping,
830 * IO-APIC RTE's need to be setup to point to interrupt-remapping
831 * table entries. for now, do a plain restore, and wait for
832 * the setup_IO_APIC_irqs() to do proper initialization.
834 restore_IO_APIC_setup();
839 * Find the IRQ entry number of a certain pin.
841 static int find_irq_entry(int apic
, int pin
, int type
)
845 for (i
= 0; i
< mp_irq_entries
; i
++)
846 if (mp_irqs
[i
].mp_irqtype
== type
&&
847 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
848 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
849 mp_irqs
[i
].mp_dstirq
== pin
)
856 * Find the pin to which IRQ[irq] (ISA) is connected
858 static int __init
find_isa_irq_pin(int irq
, int type
)
862 for (i
= 0; i
< mp_irq_entries
; i
++) {
863 int lbus
= mp_irqs
[i
].mp_srcbus
;
865 if (test_bit(lbus
, mp_bus_not_pci
) &&
866 (mp_irqs
[i
].mp_irqtype
== type
) &&
867 (mp_irqs
[i
].mp_srcbusirq
== irq
))
869 return mp_irqs
[i
].mp_dstirq
;
874 static int __init
find_isa_irq_apic(int irq
, int type
)
878 for (i
= 0; i
< mp_irq_entries
; i
++) {
879 int lbus
= mp_irqs
[i
].mp_srcbus
;
881 if (test_bit(lbus
, mp_bus_not_pci
) &&
882 (mp_irqs
[i
].mp_irqtype
== type
) &&
883 (mp_irqs
[i
].mp_srcbusirq
== irq
))
886 if (i
< mp_irq_entries
) {
888 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
889 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
898 * Find a specific PCI IRQ entry.
899 * Not an __init, possibly needed by modules
901 static int pin_2_irq(int idx
, int apic
, int pin
);
903 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
905 int apic
, i
, best_guess
= -1;
907 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
909 if (test_bit(bus
, mp_bus_not_pci
)) {
910 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
913 for (i
= 0; i
< mp_irq_entries
; i
++) {
914 int lbus
= mp_irqs
[i
].mp_srcbus
;
916 for (apic
= 0; apic
< nr_ioapics
; apic
++)
917 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
918 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
921 if (!test_bit(lbus
, mp_bus_not_pci
) &&
922 !mp_irqs
[i
].mp_irqtype
&&
924 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
925 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
927 if (!(apic
|| IO_APIC_IRQ(irq
)))
930 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
933 * Use the first all-but-pin matching entry as a
934 * best-guess fuzzy result for broken mptables.
943 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
945 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
947 * EISA Edge/Level control register, ELCR
949 static int EISA_ELCR(unsigned int irq
)
952 unsigned int port
= 0x4d0 + (irq
>> 3);
953 return (inb(port
) >> (irq
& 7)) & 1;
955 apic_printk(APIC_VERBOSE
, KERN_INFO
956 "Broken MPtable reports ISA irq %d\n", irq
);
962 /* ISA interrupts are always polarity zero edge triggered,
963 * when listed as conforming in the MP table. */
965 #define default_ISA_trigger(idx) (0)
966 #define default_ISA_polarity(idx) (0)
968 /* EISA interrupts are always polarity zero and can be edge or level
969 * trigger depending on the ELCR value. If an interrupt is listed as
970 * EISA conforming in the MP table, that means its trigger type must
971 * be read in from the ELCR */
973 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
974 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
976 /* PCI interrupts are always polarity one level triggered,
977 * when listed as conforming in the MP table. */
979 #define default_PCI_trigger(idx) (1)
980 #define default_PCI_polarity(idx) (1)
982 /* MCA interrupts are always polarity zero level triggered,
983 * when listed as conforming in the MP table. */
985 #define default_MCA_trigger(idx) (1)
986 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
988 static int MPBIOS_polarity(int idx
)
990 int bus
= mp_irqs
[idx
].mp_srcbus
;
994 * Determine IRQ line polarity (high active or low active):
996 switch (mp_irqs
[idx
].mp_irqflag
& 3)
998 case 0: /* conforms, ie. bus-type dependent polarity */
999 if (test_bit(bus
, mp_bus_not_pci
))
1000 polarity
= default_ISA_polarity(idx
);
1002 polarity
= default_PCI_polarity(idx
);
1004 case 1: /* high active */
1009 case 2: /* reserved */
1011 printk(KERN_WARNING
"broken BIOS!!\n");
1015 case 3: /* low active */
1020 default: /* invalid */
1022 printk(KERN_WARNING
"broken BIOS!!\n");
1030 static int MPBIOS_trigger(int idx
)
1032 int bus
= mp_irqs
[idx
].mp_srcbus
;
1036 * Determine IRQ trigger mode (edge or level sensitive):
1038 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1040 case 0: /* conforms, ie. bus-type dependent */
1041 if (test_bit(bus
, mp_bus_not_pci
))
1042 trigger
= default_ISA_trigger(idx
);
1044 trigger
= default_PCI_trigger(idx
);
1045 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1046 switch (mp_bus_id_to_type
[bus
]) {
1047 case MP_BUS_ISA
: /* ISA pin */
1049 /* set before the switch */
1052 case MP_BUS_EISA
: /* EISA pin */
1054 trigger
= default_EISA_trigger(idx
);
1057 case MP_BUS_PCI
: /* PCI pin */
1059 /* set before the switch */
1062 case MP_BUS_MCA
: /* MCA pin */
1064 trigger
= default_MCA_trigger(idx
);
1069 printk(KERN_WARNING
"broken BIOS!!\n");
1081 case 2: /* reserved */
1083 printk(KERN_WARNING
"broken BIOS!!\n");
1092 default: /* invalid */
1094 printk(KERN_WARNING
"broken BIOS!!\n");
1102 static inline int irq_polarity(int idx
)
1104 return MPBIOS_polarity(idx
);
1107 static inline int irq_trigger(int idx
)
1109 return MPBIOS_trigger(idx
);
1112 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1113 static int pin_2_irq(int idx
, int apic
, int pin
)
1116 int bus
= mp_irqs
[idx
].mp_srcbus
;
1119 * Debugging check, we are in big trouble if this message pops up!
1121 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1122 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1124 if (test_bit(bus
, mp_bus_not_pci
)) {
1125 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1128 * PCI IRQs are mapped in order
1132 irq
+= nr_ioapic_registers
[i
++];
1135 * For MPS mode, so far only needed by ES7000 platform
1137 if (ioapic_renumber_irq
)
1138 irq
= ioapic_renumber_irq(apic
, irq
);
1141 #ifdef CONFIG_X86_32
1143 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1145 if ((pin
>= 16) && (pin
<= 23)) {
1146 if (pirq_entries
[pin
-16] != -1) {
1147 if (!pirq_entries
[pin
-16]) {
1148 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1149 "disabling PIRQ%d\n", pin
-16);
1151 irq
= pirq_entries
[pin
-16];
1152 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1153 "using PIRQ%d -> IRQ %d\n",
1163 void lock_vector_lock(void)
1165 /* Used to the online set of cpus does not change
1166 * during assign_irq_vector.
1168 spin_lock(&vector_lock
);
1171 void unlock_vector_lock(void)
1173 spin_unlock(&vector_lock
);
1176 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1179 * NOTE! The local APIC isn't very good at handling
1180 * multiple interrupts at the same interrupt level.
1181 * As the interrupt level is determined by taking the
1182 * vector number and shifting that right by 4, we
1183 * want to spread these out a bit so that they don't
1184 * all fall in the same interrupt level.
1186 * Also, we've got to be careful not to trash gate
1187 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1189 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1190 unsigned int old_vector
;
1192 struct irq_cfg
*cfg
;
1196 /* Only try and allocate irqs on cpus that are present */
1197 cpus_and(mask
, mask
, cpu_online_map
);
1199 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1202 old_vector
= cfg
->vector
;
1205 cpus_and(tmp
, cfg
->domain
, mask
);
1206 if (!cpus_empty(tmp
))
1210 for_each_cpu_mask_nr(cpu
, mask
) {
1211 cpumask_t domain
, new_mask
;
1215 domain
= vector_allocation_domain(cpu
);
1216 cpus_and(new_mask
, domain
, cpu_online_map
);
1218 vector
= current_vector
;
1219 offset
= current_offset
;
1222 if (vector
>= first_system_vector
) {
1223 /* If we run out of vectors on large boxen, must share them. */
1224 offset
= (offset
+ 1) % 8;
1225 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1227 if (unlikely(current_vector
== vector
))
1229 #ifdef CONFIG_X86_64
1230 if (vector
== IA32_SYSCALL_VECTOR
)
1233 if (vector
== SYSCALL_VECTOR
)
1236 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1237 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1240 current_vector
= vector
;
1241 current_offset
= offset
;
1243 cfg
->move_in_progress
= 1;
1244 cfg
->old_domain
= cfg
->domain
;
1246 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1247 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1248 cfg
->vector
= vector
;
1249 cfg
->domain
= domain
;
1255 static int assign_irq_vector(int irq
, cpumask_t mask
)
1258 unsigned long flags
;
1260 spin_lock_irqsave(&vector_lock
, flags
);
1261 err
= __assign_irq_vector(irq
, mask
);
1262 spin_unlock_irqrestore(&vector_lock
, flags
);
1266 static void __clear_irq_vector(int irq
)
1268 struct irq_cfg
*cfg
;
1273 BUG_ON(!cfg
->vector
);
1275 vector
= cfg
->vector
;
1276 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1277 for_each_cpu_mask_nr(cpu
, mask
)
1278 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1281 cpus_clear(cfg
->domain
);
1284 void __setup_vector_irq(int cpu
)
1286 /* Initialize vector_irq on a new cpu */
1287 /* This function must be called with vector_lock held */
1289 struct irq_cfg
*cfg
;
1291 /* Mark the inuse vectors */
1292 for_each_irq_cfg(cfg
) {
1293 if (!cpu_isset(cpu
, cfg
->domain
))
1295 vector
= cfg
->vector
;
1297 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1299 /* Mark the free vectors */
1300 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1301 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1306 if (!cpu_isset(cpu
, cfg
->domain
))
1307 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1311 static struct irq_chip ioapic_chip
;
1312 #ifdef CONFIG_INTR_REMAP
1313 static struct irq_chip ir_ioapic_chip
;
1316 #define IOAPIC_AUTO -1
1317 #define IOAPIC_EDGE 0
1318 #define IOAPIC_LEVEL 1
1320 #ifdef CONFIG_X86_32
1321 static inline int IO_APIC_irq_trigger(int irq
)
1325 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1326 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1327 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1328 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1329 return irq_trigger(idx
);
1333 * nonexistent IRQs are edge default
1338 static inline int IO_APIC_irq_trigger(int irq
)
1344 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1346 struct irq_desc
*desc
;
1348 /* first time to use this irq_desc */
1350 desc
= irq_to_desc(irq
);
1352 desc
= irq_to_desc_alloc(irq
);
1354 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1355 trigger
== IOAPIC_LEVEL
)
1356 desc
->status
|= IRQ_LEVEL
;
1358 desc
->status
&= ~IRQ_LEVEL
;
1360 #ifdef CONFIG_INTR_REMAP
1361 if (irq_remapped(irq
)) {
1362 desc
->status
|= IRQ_MOVE_PCNTXT
;
1364 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1368 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1369 handle_edge_irq
, "edge");
1373 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1374 trigger
== IOAPIC_LEVEL
)
1375 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1379 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1380 handle_edge_irq
, "edge");
1383 static int setup_ioapic_entry(int apic
, int irq
,
1384 struct IO_APIC_route_entry
*entry
,
1385 unsigned int destination
, int trigger
,
1386 int polarity
, int vector
)
1389 * add it to the IO-APIC irq-routing table:
1391 memset(entry
,0,sizeof(*entry
));
1393 #ifdef CONFIG_INTR_REMAP
1394 if (intr_remapping_enabled
) {
1395 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1397 struct IR_IO_APIC_route_entry
*ir_entry
=
1398 (struct IR_IO_APIC_route_entry
*) entry
;
1402 panic("No mapping iommu for ioapic %d\n", apic
);
1404 index
= alloc_irte(iommu
, irq
, 1);
1406 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1408 memset(&irte
, 0, sizeof(irte
));
1411 irte
.dst_mode
= INT_DEST_MODE
;
1412 irte
.trigger_mode
= trigger
;
1413 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1414 irte
.vector
= vector
;
1415 irte
.dest_id
= IRTE_DEST(destination
);
1417 modify_irte(irq
, &irte
);
1419 ir_entry
->index2
= (index
>> 15) & 0x1;
1421 ir_entry
->format
= 1;
1422 ir_entry
->index
= (index
& 0x7fff);
1426 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1427 entry
->dest_mode
= INT_DEST_MODE
;
1428 entry
->dest
= destination
;
1431 entry
->mask
= 0; /* enable IRQ */
1432 entry
->trigger
= trigger
;
1433 entry
->polarity
= polarity
;
1434 entry
->vector
= vector
;
1436 /* Mask level triggered irqs.
1437 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1444 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1445 int trigger
, int polarity
)
1447 struct irq_cfg
*cfg
;
1448 struct IO_APIC_route_entry entry
;
1451 if (!IO_APIC_IRQ(irq
))
1457 if (assign_irq_vector(irq
, mask
))
1460 cpus_and(mask
, cfg
->domain
, mask
);
1462 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1463 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1464 "IRQ %d Mode:%i Active:%i)\n",
1465 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1466 irq
, trigger
, polarity
);
1469 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1470 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1472 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1473 mp_ioapics
[apic
].mp_apicid
, pin
);
1474 __clear_irq_vector(irq
);
1478 ioapic_register_intr(irq
, trigger
);
1480 disable_8259A_irq(irq
);
1482 ioapic_write_entry(apic
, pin
, entry
);
1485 static void __init
setup_IO_APIC_irqs(void)
1487 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1489 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1491 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1492 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1494 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1497 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1500 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1503 if (!first_notcon
) {
1504 apic_printk(APIC_VERBOSE
, " not connected.\n");
1508 irq
= pin_2_irq(idx
, apic
, pin
);
1509 #ifdef CONFIG_X86_32
1510 if (multi_timer_check(apic
, irq
))
1513 add_pin_to_irq(irq
, apic
, pin
);
1515 setup_IO_APIC_irq(apic
, pin
, irq
,
1516 irq_trigger(idx
), irq_polarity(idx
));
1521 apic_printk(APIC_VERBOSE
, " not connected.\n");
1525 * Set up the timer pin, possibly with the 8259A-master behind.
1527 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1530 struct IO_APIC_route_entry entry
;
1532 #ifdef CONFIG_INTR_REMAP
1533 if (intr_remapping_enabled
)
1537 memset(&entry
, 0, sizeof(entry
));
1540 * We use logical delivery to get the timer IRQ
1543 entry
.dest_mode
= INT_DEST_MODE
;
1544 entry
.mask
= 1; /* mask IRQ now */
1545 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1546 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1549 entry
.vector
= vector
;
1552 * The timer IRQ doesn't have to know that behind the
1553 * scene we may have a 8259A-master in AEOI mode ...
1555 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1558 * Add it to the IO-APIC irq-routing table:
1560 ioapic_write_entry(apic
, pin
, entry
);
1564 __apicdebuginit(void) print_IO_APIC(void)
1567 union IO_APIC_reg_00 reg_00
;
1568 union IO_APIC_reg_01 reg_01
;
1569 union IO_APIC_reg_02 reg_02
;
1570 union IO_APIC_reg_03 reg_03
;
1571 unsigned long flags
;
1572 struct irq_cfg
*cfg
;
1574 if (apic_verbosity
== APIC_QUIET
)
1577 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1578 for (i
= 0; i
< nr_ioapics
; i
++)
1579 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1580 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1583 * We are a bit conservative about what we expect. We have to
1584 * know about every hardware change ASAP.
1586 printk(KERN_INFO
"testing the IO APIC.......................\n");
1588 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1590 spin_lock_irqsave(&ioapic_lock
, flags
);
1591 reg_00
.raw
= io_apic_read(apic
, 0);
1592 reg_01
.raw
= io_apic_read(apic
, 1);
1593 if (reg_01
.bits
.version
>= 0x10)
1594 reg_02
.raw
= io_apic_read(apic
, 2);
1595 if (reg_01
.bits
.version
>= 0x20)
1596 reg_03
.raw
= io_apic_read(apic
, 3);
1597 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1600 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1601 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1602 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1603 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1604 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1606 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1607 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1609 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1610 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1613 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1614 * but the value of reg_02 is read as the previous read register
1615 * value, so ignore it if reg_02 == reg_01.
1617 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1618 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1619 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1623 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1624 * or reg_03, but the value of reg_0[23] is read as the previous read
1625 * register value, so ignore it if reg_03 == reg_0[12].
1627 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1628 reg_03
.raw
!= reg_01
.raw
) {
1629 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1630 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1633 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1635 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1636 " Stat Dmod Deli Vect: \n");
1638 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1639 struct IO_APIC_route_entry entry
;
1641 entry
= ioapic_read_entry(apic
, i
);
1643 printk(KERN_DEBUG
" %02x %03X ",
1648 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1653 entry
.delivery_status
,
1655 entry
.delivery_mode
,
1660 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1661 for_each_irq_cfg(cfg
) {
1662 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1665 printk(KERN_DEBUG
"IRQ%d ", cfg
->irq
);
1667 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1670 entry
= entry
->next
;
1675 printk(KERN_INFO
".................................... done.\n");
1680 __apicdebuginit(void) print_APIC_bitfield(int base
)
1685 if (apic_verbosity
== APIC_QUIET
)
1688 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1689 for (i
= 0; i
< 8; i
++) {
1690 v
= apic_read(base
+ i
*0x10);
1691 for (j
= 0; j
< 32; j
++) {
1701 __apicdebuginit(void) print_local_APIC(void *dummy
)
1703 unsigned int v
, ver
, maxlvt
;
1706 if (apic_verbosity
== APIC_QUIET
)
1709 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1710 smp_processor_id(), hard_smp_processor_id());
1711 v
= apic_read(APIC_ID
);
1712 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1713 v
= apic_read(APIC_LVR
);
1714 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1715 ver
= GET_APIC_VERSION(v
);
1716 maxlvt
= lapic_get_maxlvt();
1718 v
= apic_read(APIC_TASKPRI
);
1719 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1721 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1722 v
= apic_read(APIC_ARBPRI
);
1723 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1724 v
& APIC_ARBPRI_MASK
);
1725 v
= apic_read(APIC_PROCPRI
);
1726 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1729 v
= apic_read(APIC_EOI
);
1730 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1731 v
= apic_read(APIC_RRR
);
1732 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1733 v
= apic_read(APIC_LDR
);
1734 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1735 v
= apic_read(APIC_DFR
);
1736 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1737 v
= apic_read(APIC_SPIV
);
1738 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1740 printk(KERN_DEBUG
"... APIC ISR field:\n");
1741 print_APIC_bitfield(APIC_ISR
);
1742 printk(KERN_DEBUG
"... APIC TMR field:\n");
1743 print_APIC_bitfield(APIC_TMR
);
1744 printk(KERN_DEBUG
"... APIC IRR field:\n");
1745 print_APIC_bitfield(APIC_IRR
);
1747 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1748 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1749 apic_write(APIC_ESR
, 0);
1751 v
= apic_read(APIC_ESR
);
1752 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1755 icr
= apic_icr_read();
1756 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1757 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1759 v
= apic_read(APIC_LVTT
);
1760 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1762 if (maxlvt
> 3) { /* PC is LVT#4. */
1763 v
= apic_read(APIC_LVTPC
);
1764 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1766 v
= apic_read(APIC_LVT0
);
1767 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1768 v
= apic_read(APIC_LVT1
);
1769 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1771 if (maxlvt
> 2) { /* ERR is LVT#3. */
1772 v
= apic_read(APIC_LVTERR
);
1773 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1776 v
= apic_read(APIC_TMICT
);
1777 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1778 v
= apic_read(APIC_TMCCT
);
1779 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1780 v
= apic_read(APIC_TDCR
);
1781 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1785 __apicdebuginit(void) print_all_local_APICs(void)
1787 on_each_cpu(print_local_APIC
, NULL
, 1);
1790 __apicdebuginit(void) print_PIC(void)
1793 unsigned long flags
;
1795 if (apic_verbosity
== APIC_QUIET
)
1798 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1800 spin_lock_irqsave(&i8259A_lock
, flags
);
1802 v
= inb(0xa1) << 8 | inb(0x21);
1803 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1805 v
= inb(0xa0) << 8 | inb(0x20);
1806 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1810 v
= inb(0xa0) << 8 | inb(0x20);
1814 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1816 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1818 v
= inb(0x4d1) << 8 | inb(0x4d0);
1819 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1822 __apicdebuginit(int) print_all_ICs(void)
1825 print_all_local_APICs();
1831 fs_initcall(print_all_ICs
);
1834 /* Where if anywhere is the i8259 connect in external int mode */
1835 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1837 void __init
enable_IO_APIC(void)
1839 union IO_APIC_reg_01 reg_01
;
1840 int i8259_apic
, i8259_pin
;
1842 unsigned long flags
;
1844 #ifdef CONFIG_X86_32
1847 for (i
= 0; i
< MAX_PIRQS
; i
++)
1848 pirq_entries
[i
] = -1;
1852 * The number of IO-APIC IRQ registers (== #pins):
1854 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1855 spin_lock_irqsave(&ioapic_lock
, flags
);
1856 reg_01
.raw
= io_apic_read(apic
, 1);
1857 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1858 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1860 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1862 /* See if any of the pins is in ExtINT mode */
1863 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1864 struct IO_APIC_route_entry entry
;
1865 entry
= ioapic_read_entry(apic
, pin
);
1867 /* If the interrupt line is enabled and in ExtInt mode
1868 * I have found the pin where the i8259 is connected.
1870 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1871 ioapic_i8259
.apic
= apic
;
1872 ioapic_i8259
.pin
= pin
;
1878 /* Look to see what if the MP table has reported the ExtINT */
1879 /* If we could not find the appropriate pin by looking at the ioapic
1880 * the i8259 probably is not connected the ioapic but give the
1881 * mptable a chance anyway.
1883 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1884 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1885 /* Trust the MP table if nothing is setup in the hardware */
1886 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1887 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1888 ioapic_i8259
.pin
= i8259_pin
;
1889 ioapic_i8259
.apic
= i8259_apic
;
1891 /* Complain if the MP table and the hardware disagree */
1892 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1893 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1895 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1899 * Do not trust the IO-APIC being empty at bootup
1905 * Not an __init, needed by the reboot code
1907 void disable_IO_APIC(void)
1910 * Clear the IO-APIC before rebooting:
1915 * If the i8259 is routed through an IOAPIC
1916 * Put that IOAPIC in virtual wire mode
1917 * so legacy interrupts can be delivered.
1919 if (ioapic_i8259
.pin
!= -1) {
1920 struct IO_APIC_route_entry entry
;
1922 memset(&entry
, 0, sizeof(entry
));
1923 entry
.mask
= 0; /* Enabled */
1924 entry
.trigger
= 0; /* Edge */
1926 entry
.polarity
= 0; /* High */
1927 entry
.delivery_status
= 0;
1928 entry
.dest_mode
= 0; /* Physical */
1929 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1931 entry
.dest
= read_apic_id();
1934 * Add it to the IO-APIC irq-routing table:
1936 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1939 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1942 #ifdef CONFIG_X86_32
1944 * function to set the IO-APIC physical IDs based on the
1945 * values stored in the MPC table.
1947 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1950 static void __init
setup_ioapic_ids_from_mpc(void)
1952 union IO_APIC_reg_00 reg_00
;
1953 physid_mask_t phys_id_present_map
;
1956 unsigned char old_id
;
1957 unsigned long flags
;
1959 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1963 * Don't check I/O APIC IDs for xAPIC systems. They have
1964 * no meaning without the serial APIC bus.
1966 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1967 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1970 * This is broken; anything with a real cpu count has to
1971 * circumvent this idiocy regardless.
1973 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1976 * Set the IOAPIC ID to the value stored in the MPC table.
1978 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1980 /* Read the register 0 value */
1981 spin_lock_irqsave(&ioapic_lock
, flags
);
1982 reg_00
.raw
= io_apic_read(apic
, 0);
1983 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1985 old_id
= mp_ioapics
[apic
].mp_apicid
;
1987 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1988 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1989 apic
, mp_ioapics
[apic
].mp_apicid
);
1990 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1992 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1996 * Sanity check, is the ID really free? Every APIC in a
1997 * system must have a unique ID or we get lots of nice
1998 * 'stuck on smp_invalidate_needed IPI wait' messages.
2000 if (check_apicid_used(phys_id_present_map
,
2001 mp_ioapics
[apic
].mp_apicid
)) {
2002 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2003 apic
, mp_ioapics
[apic
].mp_apicid
);
2004 for (i
= 0; i
< get_physical_broadcast(); i
++)
2005 if (!physid_isset(i
, phys_id_present_map
))
2007 if (i
>= get_physical_broadcast())
2008 panic("Max APIC ID exceeded!\n");
2009 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2011 physid_set(i
, phys_id_present_map
);
2012 mp_ioapics
[apic
].mp_apicid
= i
;
2015 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2016 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2017 "phys_id_present_map\n",
2018 mp_ioapics
[apic
].mp_apicid
);
2019 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2024 * We need to adjust the IRQ routing table
2025 * if the ID changed.
2027 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2028 for (i
= 0; i
< mp_irq_entries
; i
++)
2029 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2030 mp_irqs
[i
].mp_dstapic
2031 = mp_ioapics
[apic
].mp_apicid
;
2034 * Read the right value from the MPC table and
2035 * write it into the ID register.
2037 apic_printk(APIC_VERBOSE
, KERN_INFO
2038 "...changing IO-APIC physical APIC ID to %d ...",
2039 mp_ioapics
[apic
].mp_apicid
);
2041 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2042 spin_lock_irqsave(&ioapic_lock
, flags
);
2047 spin_lock_irqsave(&ioapic_lock
, flags
);
2048 reg_00
.raw
= io_apic_read(apic
, 0);
2049 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2050 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2051 printk("could not set ID!\n");
2053 apic_printk(APIC_VERBOSE
, " ok.\n");
2058 int no_timer_check __initdata
;
2060 static int __init
notimercheck(char *s
)
2065 __setup("no_timer_check", notimercheck
);
2068 * There is a nasty bug in some older SMP boards, their mptable lies
2069 * about the timer IRQ. We do the following to work around the situation:
2071 * - timer IRQ defaults to IO-APIC IRQ
2072 * - if this function detects that timer IRQs are defunct, then we fall
2073 * back to ISA timer IRQs
2075 static int __init
timer_irq_works(void)
2077 unsigned long t1
= jiffies
;
2078 unsigned long flags
;
2083 local_save_flags(flags
);
2085 /* Let ten ticks pass... */
2086 mdelay((10 * 1000) / HZ
);
2087 local_irq_restore(flags
);
2090 * Expect a few ticks at least, to be sure some possible
2091 * glue logic does not lock up after one or two first
2092 * ticks in a non-ExtINT mode. Also the local APIC
2093 * might have cached one ExtINT interrupt. Finally, at
2094 * least one tick may be lost due to delays.
2098 if (time_after(jiffies
, t1
+ 4))
2104 * In the SMP+IOAPIC case it might happen that there are an unspecified
2105 * number of pending IRQ events unhandled. These cases are very rare,
2106 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2107 * better to do it this way as thus we do not have to be aware of
2108 * 'pending' interrupts in the IRQ path, except at this point.
2111 * Edge triggered needs to resend any interrupt
2112 * that was delayed but this is now handled in the device
2117 * Starting up a edge-triggered IO-APIC interrupt is
2118 * nasty - we need to make sure that we get the edge.
2119 * If it is already asserted for some reason, we need
2120 * return 1 to indicate that is was pending.
2122 * This is not complete - we should be able to fake
2123 * an edge even if it isn't on the 8259A...
2126 static unsigned int startup_ioapic_irq(unsigned int irq
)
2128 int was_pending
= 0;
2129 unsigned long flags
;
2131 spin_lock_irqsave(&ioapic_lock
, flags
);
2133 disable_8259A_irq(irq
);
2134 if (i8259A_irq_pending(irq
))
2137 __unmask_IO_APIC_irq(irq
);
2138 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2143 #ifdef CONFIG_X86_64
2144 static int ioapic_retrigger_irq(unsigned int irq
)
2147 struct irq_cfg
*cfg
= irq_cfg(irq
);
2148 unsigned long flags
;
2150 spin_lock_irqsave(&vector_lock
, flags
);
2151 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
2152 spin_unlock_irqrestore(&vector_lock
, flags
);
2157 static int ioapic_retrigger_irq(unsigned int irq
)
2159 send_IPI_self(irq_cfg(irq
)->vector
);
2166 * Level and edge triggered IO-APIC interrupts need different handling,
2167 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2168 * handled with the level-triggered descriptor, but that one has slightly
2169 * more overhead. Level-triggered interrupts cannot be handled with the
2170 * edge-triggered handler, without risking IRQ storms and other ugly
2176 #ifdef CONFIG_INTR_REMAP
2177 static void ir_irq_migration(struct work_struct
*work
);
2179 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2182 * Migrate the IO-APIC irq in the presence of intr-remapping.
2184 * For edge triggered, irq migration is a simple atomic update(of vector
2185 * and cpu destination) of IRTE and flush the hardware cache.
2187 * For level triggered, we need to modify the io-apic RTE aswell with the update
2188 * vector information, along with modifying IRTE with vector and destination.
2189 * So irq migration for level triggered is little bit more complex compared to
2190 * edge triggered migration. But the good news is, we use the same algorithm
2191 * for level triggered migration as we have today, only difference being,
2192 * we now initiate the irq migration from process context instead of the
2193 * interrupt context.
2195 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2196 * suppression) to the IO-APIC, level triggered irq migration will also be
2197 * as simple as edge triggered migration and we can do the irq migration
2198 * with a simple atomic update to IO-APIC RTE.
2200 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
2202 struct irq_cfg
*cfg
;
2203 struct irq_desc
*desc
;
2204 cpumask_t tmp
, cleanup_mask
;
2206 int modify_ioapic_rte
;
2208 unsigned long flags
;
2210 cpus_and(tmp
, mask
, cpu_online_map
);
2211 if (cpus_empty(tmp
))
2214 if (get_irte(irq
, &irte
))
2217 if (assign_irq_vector(irq
, mask
))
2221 cpus_and(tmp
, cfg
->domain
, mask
);
2222 dest
= cpu_mask_to_apicid(tmp
);
2224 desc
= irq_to_desc(irq
);
2225 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2226 if (modify_ioapic_rte
) {
2227 spin_lock_irqsave(&ioapic_lock
, flags
);
2228 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
2229 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2232 irte
.vector
= cfg
->vector
;
2233 irte
.dest_id
= IRTE_DEST(dest
);
2236 * Modified the IRTE and flushes the Interrupt entry cache.
2238 modify_irte(irq
, &irte
);
2240 if (cfg
->move_in_progress
) {
2241 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2242 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2243 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2244 cfg
->move_in_progress
= 0;
2247 desc
->affinity
= mask
;
2250 static int migrate_irq_remapped_level(int irq
)
2253 struct irq_desc
*desc
= irq_to_desc(irq
);
2255 mask_IO_APIC_irq(irq
);
2257 if (io_apic_level_ack_pending(irq
)) {
2259 * Interrupt in progress. Migrating irq now will change the
2260 * vector information in the IO-APIC RTE and that will confuse
2261 * the EOI broadcast performed by cpu.
2262 * So, delay the irq migration to the next instance.
2264 schedule_delayed_work(&ir_migration_work
, 1);
2268 /* everthing is clear. we have right of way */
2269 migrate_ioapic_irq(irq
, desc
->pending_mask
);
2272 desc
->status
&= ~IRQ_MOVE_PENDING
;
2273 cpus_clear(desc
->pending_mask
);
2276 unmask_IO_APIC_irq(irq
);
2280 static void ir_irq_migration(struct work_struct
*work
)
2283 struct irq_desc
*desc
;
2285 for_each_irq_desc(irq
, desc
) {
2286 if (desc
->status
& IRQ_MOVE_PENDING
) {
2287 unsigned long flags
;
2289 spin_lock_irqsave(&desc
->lock
, flags
);
2290 if (!desc
->chip
->set_affinity
||
2291 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2292 desc
->status
&= ~IRQ_MOVE_PENDING
;
2293 spin_unlock_irqrestore(&desc
->lock
, flags
);
2297 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
2298 spin_unlock_irqrestore(&desc
->lock
, flags
);
2304 * Migrates the IRQ destination in the process context.
2306 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
2308 struct irq_desc
*desc
= irq_to_desc(irq
);
2310 if (desc
->status
& IRQ_LEVEL
) {
2311 desc
->status
|= IRQ_MOVE_PENDING
;
2312 desc
->pending_mask
= mask
;
2313 migrate_irq_remapped_level(irq
);
2317 migrate_ioapic_irq(irq
, mask
);
2321 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2323 unsigned vector
, me
;
2325 #ifdef CONFIG_X86_64
2330 me
= smp_processor_id();
2331 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2333 struct irq_desc
*desc
;
2334 struct irq_cfg
*cfg
;
2335 irq
= __get_cpu_var(vector_irq
)[vector
];
2337 desc
= irq_to_desc(irq
);
2342 spin_lock(&desc
->lock
);
2343 if (!cfg
->move_cleanup_count
)
2346 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
2349 __get_cpu_var(vector_irq
)[vector
] = -1;
2350 cfg
->move_cleanup_count
--;
2352 spin_unlock(&desc
->lock
);
2358 static void irq_complete_move(unsigned int irq
)
2360 struct irq_cfg
*cfg
= irq_cfg(irq
);
2361 unsigned vector
, me
;
2363 if (likely(!cfg
->move_in_progress
))
2366 vector
= ~get_irq_regs()->orig_ax
;
2367 me
= smp_processor_id();
2368 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
2369 cpumask_t cleanup_mask
;
2371 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2372 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2373 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2374 cfg
->move_in_progress
= 0;
2378 static inline void irq_complete_move(unsigned int irq
) {}
2380 #ifdef CONFIG_INTR_REMAP
2381 static void ack_x2apic_level(unsigned int irq
)
2386 static void ack_x2apic_edge(unsigned int irq
)
2392 static void ack_apic_edge(unsigned int irq
)
2394 irq_complete_move(irq
);
2395 move_native_irq(irq
);
2399 #ifdef CONFIG_X86_32
2400 atomic_t irq_mis_count
;
2403 static void ack_apic_level(unsigned int irq
)
2405 #ifdef CONFIG_X86_32
2409 int do_unmask_irq
= 0;
2411 irq_complete_move(irq
);
2412 #ifdef CONFIG_GENERIC_PENDING_IRQ
2413 /* If we are moving the irq we need to mask it */
2414 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2416 mask_IO_APIC_irq(irq
);
2420 #ifdef CONFIG_X86_32
2422 * It appears there is an erratum which affects at least version 0x11
2423 * of I/O APIC (that's the 82093AA and cores integrated into various
2424 * chipsets). Under certain conditions a level-triggered interrupt is
2425 * erroneously delivered as edge-triggered one but the respective IRR
2426 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2427 * message but it will never arrive and further interrupts are blocked
2428 * from the source. The exact reason is so far unknown, but the
2429 * phenomenon was observed when two consecutive interrupt requests
2430 * from a given source get delivered to the same CPU and the source is
2431 * temporarily disabled in between.
2433 * A workaround is to simulate an EOI message manually. We achieve it
2434 * by setting the trigger mode to edge and then to level when the edge
2435 * trigger mode gets detected in the TMR of a local APIC for a
2436 * level-triggered interrupt. We mask the source for the time of the
2437 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2438 * The idea is from Manfred Spraul. --macro
2440 i
= irq_cfg(irq
)->vector
;
2442 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2446 * We must acknowledge the irq before we move it or the acknowledge will
2447 * not propagate properly.
2451 /* Now we can move and renable the irq */
2452 if (unlikely(do_unmask_irq
)) {
2453 /* Only migrate the irq if the ack has been received.
2455 * On rare occasions the broadcast level triggered ack gets
2456 * delayed going to ioapics, and if we reprogram the
2457 * vector while Remote IRR is still set the irq will never
2460 * To prevent this scenario we read the Remote IRR bit
2461 * of the ioapic. This has two effects.
2462 * - On any sane system the read of the ioapic will
2463 * flush writes (and acks) going to the ioapic from
2465 * - We get to see if the ACK has actually been delivered.
2467 * Based on failed experiments of reprogramming the
2468 * ioapic entry from outside of irq context starting
2469 * with masking the ioapic entry and then polling until
2470 * Remote IRR was clear before reprogramming the
2471 * ioapic I don't trust the Remote IRR bit to be
2472 * completey accurate.
2474 * However there appears to be no other way to plug
2475 * this race, so if the Remote IRR bit is not
2476 * accurate and is causing problems then it is a hardware bug
2477 * and you can go talk to the chipset vendor about it.
2479 if (!io_apic_level_ack_pending(irq
))
2480 move_masked_irq(irq
);
2481 unmask_IO_APIC_irq(irq
);
2484 #ifdef CONFIG_X86_32
2485 if (!(v
& (1 << (i
& 0x1f)))) {
2486 atomic_inc(&irq_mis_count
);
2487 spin_lock(&ioapic_lock
);
2488 __mask_and_edge_IO_APIC_irq(irq
);
2489 __unmask_and_level_IO_APIC_irq(irq
);
2490 spin_unlock(&ioapic_lock
);
2495 static struct irq_chip ioapic_chip __read_mostly
= {
2497 .startup
= startup_ioapic_irq
,
2498 .mask
= mask_IO_APIC_irq
,
2499 .unmask
= unmask_IO_APIC_irq
,
2500 .ack
= ack_apic_edge
,
2501 .eoi
= ack_apic_level
,
2503 .set_affinity
= set_ioapic_affinity_irq
,
2505 .retrigger
= ioapic_retrigger_irq
,
2508 #ifdef CONFIG_INTR_REMAP
2509 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2510 .name
= "IR-IO-APIC",
2511 .startup
= startup_ioapic_irq
,
2512 .mask
= mask_IO_APIC_irq
,
2513 .unmask
= unmask_IO_APIC_irq
,
2514 .ack
= ack_x2apic_edge
,
2515 .eoi
= ack_x2apic_level
,
2517 .set_affinity
= set_ir_ioapic_affinity_irq
,
2519 .retrigger
= ioapic_retrigger_irq
,
2523 static inline void init_IO_APIC_traps(void)
2526 struct irq_desc
*desc
;
2527 struct irq_cfg
*cfg
;
2530 * NOTE! The local APIC isn't very good at handling
2531 * multiple interrupts at the same interrupt level.
2532 * As the interrupt level is determined by taking the
2533 * vector number and shifting that right by 4, we
2534 * want to spread these out a bit so that they don't
2535 * all fall in the same interrupt level.
2537 * Also, we've got to be careful not to trash gate
2538 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2540 for_each_irq_cfg(cfg
) {
2542 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2544 * Hmm.. We don't have an entry for this,
2545 * so default to an old-fashioned 8259
2546 * interrupt if we can..
2549 make_8259A_irq(irq
);
2551 desc
= irq_to_desc(irq
);
2552 /* Strange. Oh, well.. */
2553 desc
->chip
= &no_irq_chip
;
2560 * The local APIC irq-chip implementation:
2563 static void mask_lapic_irq(unsigned int irq
)
2567 v
= apic_read(APIC_LVT0
);
2568 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2571 static void unmask_lapic_irq(unsigned int irq
)
2575 v
= apic_read(APIC_LVT0
);
2576 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2579 static void ack_lapic_irq (unsigned int irq
)
2584 static struct irq_chip lapic_chip __read_mostly
= {
2585 .name
= "local-APIC",
2586 .mask
= mask_lapic_irq
,
2587 .unmask
= unmask_lapic_irq
,
2588 .ack
= ack_lapic_irq
,
2591 static void lapic_register_intr(int irq
)
2593 struct irq_desc
*desc
;
2595 desc
= irq_to_desc(irq
);
2596 desc
->status
&= ~IRQ_LEVEL
;
2597 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2601 static void __init
setup_nmi(void)
2604 * Dirty trick to enable the NMI watchdog ...
2605 * We put the 8259A master into AEOI mode and
2606 * unmask on all local APICs LVT0 as NMI.
2608 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2609 * is from Maciej W. Rozycki - so we do not have to EOI from
2610 * the NMI handler or the timer interrupt.
2612 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2614 enable_NMI_through_LVT0();
2616 apic_printk(APIC_VERBOSE
, " done.\n");
2620 * This looks a bit hackish but it's about the only one way of sending
2621 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2622 * not support the ExtINT mode, unfortunately. We need to send these
2623 * cycles as some i82489DX-based boards have glue logic that keeps the
2624 * 8259A interrupt line asserted until INTA. --macro
2626 static inline void __init
unlock_ExtINT_logic(void)
2629 struct IO_APIC_route_entry entry0
, entry1
;
2630 unsigned char save_control
, save_freq_select
;
2632 pin
= find_isa_irq_pin(8, mp_INT
);
2637 apic
= find_isa_irq_apic(8, mp_INT
);
2643 entry0
= ioapic_read_entry(apic
, pin
);
2644 clear_IO_APIC_pin(apic
, pin
);
2646 memset(&entry1
, 0, sizeof(entry1
));
2648 entry1
.dest_mode
= 0; /* physical delivery */
2649 entry1
.mask
= 0; /* unmask IRQ now */
2650 entry1
.dest
= hard_smp_processor_id();
2651 entry1
.delivery_mode
= dest_ExtINT
;
2652 entry1
.polarity
= entry0
.polarity
;
2656 ioapic_write_entry(apic
, pin
, entry1
);
2658 save_control
= CMOS_READ(RTC_CONTROL
);
2659 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2660 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2662 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2667 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2671 CMOS_WRITE(save_control
, RTC_CONTROL
);
2672 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2673 clear_IO_APIC_pin(apic
, pin
);
2675 ioapic_write_entry(apic
, pin
, entry0
);
2678 static int disable_timer_pin_1 __initdata
;
2679 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2680 static int __init
disable_timer_pin_setup(char *arg
)
2682 disable_timer_pin_1
= 1;
2685 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2687 int timer_through_8259 __initdata
;
2690 * This code may look a bit paranoid, but it's supposed to cooperate with
2691 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2692 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2693 * fanatically on his truly buggy board.
2695 * FIXME: really need to revamp this for all platforms.
2697 static inline void __init
check_timer(void)
2699 struct irq_cfg
*cfg
= irq_cfg(0);
2700 int apic1
, pin1
, apic2
, pin2
;
2701 unsigned long flags
;
2705 local_irq_save(flags
);
2707 ver
= apic_read(APIC_LVR
);
2708 ver
= GET_APIC_VERSION(ver
);
2711 * get/set the timer IRQ vector:
2713 disable_8259A_irq(0);
2714 assign_irq_vector(0, TARGET_CPUS
);
2717 * As IRQ0 is to be enabled in the 8259A, the virtual
2718 * wire has to be disabled in the local APIC. Also
2719 * timer interrupts need to be acknowledged manually in
2720 * the 8259A for the i82489DX when using the NMI
2721 * watchdog as that APIC treats NMIs as level-triggered.
2722 * The AEOI mode will finish them in the 8259A
2725 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2727 #ifdef CONFIG_X86_32
2728 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2731 pin1
= find_isa_irq_pin(0, mp_INT
);
2732 apic1
= find_isa_irq_apic(0, mp_INT
);
2733 pin2
= ioapic_i8259
.pin
;
2734 apic2
= ioapic_i8259
.apic
;
2736 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2737 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2738 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2741 * Some BIOS writers are clueless and report the ExtINTA
2742 * I/O APIC input from the cascaded 8259A as the timer
2743 * interrupt input. So just in case, if only one pin
2744 * was found above, try it both directly and through the
2748 #ifdef CONFIG_INTR_REMAP
2749 if (intr_remapping_enabled
)
2750 panic("BIOS bug: timer not connected to IO-APIC");
2755 } else if (pin2
== -1) {
2762 * Ok, does IRQ0 through the IOAPIC work?
2765 add_pin_to_irq(0, apic1
, pin1
);
2766 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2768 unmask_IO_APIC_irq(0);
2769 if (timer_irq_works()) {
2770 if (nmi_watchdog
== NMI_IO_APIC
) {
2772 enable_8259A_irq(0);
2774 if (disable_timer_pin_1
> 0)
2775 clear_IO_APIC_pin(0, pin1
);
2778 #ifdef CONFIG_INTR_REMAP
2779 if (intr_remapping_enabled
)
2780 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2782 clear_IO_APIC_pin(apic1
, pin1
);
2784 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2785 "8254 timer not connected to IO-APIC\n");
2787 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2788 "(IRQ0) through the 8259A ...\n");
2789 apic_printk(APIC_QUIET
, KERN_INFO
2790 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2792 * legacy devices should be connected to IO APIC #0
2794 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2795 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2796 unmask_IO_APIC_irq(0);
2797 enable_8259A_irq(0);
2798 if (timer_irq_works()) {
2799 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2800 timer_through_8259
= 1;
2801 if (nmi_watchdog
== NMI_IO_APIC
) {
2802 disable_8259A_irq(0);
2804 enable_8259A_irq(0);
2809 * Cleanup, just in case ...
2811 disable_8259A_irq(0);
2812 clear_IO_APIC_pin(apic2
, pin2
);
2813 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2816 if (nmi_watchdog
== NMI_IO_APIC
) {
2817 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2818 "through the IO-APIC - disabling NMI Watchdog!\n");
2819 nmi_watchdog
= NMI_NONE
;
2821 #ifdef CONFIG_X86_32
2825 apic_printk(APIC_QUIET
, KERN_INFO
2826 "...trying to set up timer as Virtual Wire IRQ...\n");
2828 lapic_register_intr(0);
2829 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2830 enable_8259A_irq(0);
2832 if (timer_irq_works()) {
2833 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2836 disable_8259A_irq(0);
2837 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2838 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2840 apic_printk(APIC_QUIET
, KERN_INFO
2841 "...trying to set up timer as ExtINT IRQ...\n");
2845 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2847 unlock_ExtINT_logic();
2849 if (timer_irq_works()) {
2850 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2853 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2854 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2855 "report. Then try booting with the 'noapic' option.\n");
2857 local_irq_restore(flags
);
2861 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2862 * to devices. However there may be an I/O APIC pin available for
2863 * this interrupt regardless. The pin may be left unconnected, but
2864 * typically it will be reused as an ExtINT cascade interrupt for
2865 * the master 8259A. In the MPS case such a pin will normally be
2866 * reported as an ExtINT interrupt in the MP table. With ACPI
2867 * there is no provision for ExtINT interrupts, and in the absence
2868 * of an override it would be treated as an ordinary ISA I/O APIC
2869 * interrupt, that is edge-triggered and unmasked by default. We
2870 * used to do this, but it caused problems on some systems because
2871 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2872 * the same ExtINT cascade interrupt to drive the local APIC of the
2873 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2874 * the I/O APIC in all cases now. No actual device should request
2875 * it anyway. --macro
2877 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2879 void __init
setup_IO_APIC(void)
2882 #ifdef CONFIG_X86_32
2886 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2890 io_apic_irqs
= ~PIC_IRQS
;
2892 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2894 * Set up IO-APIC IRQ routing.
2896 #ifdef CONFIG_X86_32
2898 setup_ioapic_ids_from_mpc();
2901 setup_IO_APIC_irqs();
2902 init_IO_APIC_traps();
2907 * Called after all the initialization is done. If we didnt find any
2908 * APIC bugs then we can allow the modify fast path
2911 static int __init
io_apic_bug_finalize(void)
2913 if (sis_apic_bug
== -1)
2918 late_initcall(io_apic_bug_finalize
);
2920 struct sysfs_ioapic_data
{
2921 struct sys_device dev
;
2922 struct IO_APIC_route_entry entry
[0];
2924 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2926 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2928 struct IO_APIC_route_entry
*entry
;
2929 struct sysfs_ioapic_data
*data
;
2932 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2933 entry
= data
->entry
;
2934 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2935 *entry
= ioapic_read_entry(dev
->id
, i
);
2940 static int ioapic_resume(struct sys_device
*dev
)
2942 struct IO_APIC_route_entry
*entry
;
2943 struct sysfs_ioapic_data
*data
;
2944 unsigned long flags
;
2945 union IO_APIC_reg_00 reg_00
;
2948 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2949 entry
= data
->entry
;
2951 spin_lock_irqsave(&ioapic_lock
, flags
);
2952 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2953 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2954 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2955 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2957 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2958 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2959 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2964 static struct sysdev_class ioapic_sysdev_class
= {
2966 .suspend
= ioapic_suspend
,
2967 .resume
= ioapic_resume
,
2970 static int __init
ioapic_init_sysfs(void)
2972 struct sys_device
* dev
;
2975 error
= sysdev_class_register(&ioapic_sysdev_class
);
2979 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2980 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2981 * sizeof(struct IO_APIC_route_entry
);
2982 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2983 if (!mp_ioapic_data
[i
]) {
2984 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2987 dev
= &mp_ioapic_data
[i
]->dev
;
2989 dev
->cls
= &ioapic_sysdev_class
;
2990 error
= sysdev_register(dev
);
2992 kfree(mp_ioapic_data
[i
]);
2993 mp_ioapic_data
[i
] = NULL
;
2994 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3002 device_initcall(ioapic_init_sysfs
);
3005 * Dynamic irq allocate and deallocation
3007 unsigned int create_irq_nr(unsigned int irq_want
)
3009 /* Allocate an unused irq */
3012 unsigned long flags
;
3013 struct irq_cfg
*cfg_new
;
3015 #ifndef CONFIG_HAVE_SPARSE_IRQ
3016 irq_want
= nr_irqs
- 1;
3020 spin_lock_irqsave(&vector_lock
, flags
);
3021 for (new = irq_want
; new > 0; new--) {
3022 if (platform_legacy_irq(new))
3024 cfg_new
= irq_cfg(new);
3025 if (cfg_new
&& cfg_new
->vector
!= 0)
3027 /* check if need to create one */
3029 cfg_new
= irq_cfg_alloc(new);
3030 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
3034 spin_unlock_irqrestore(&vector_lock
, flags
);
3037 dynamic_irq_init(irq
);
3042 int create_irq(void)
3046 irq
= create_irq_nr(nr_irqs
- 1);
3054 void destroy_irq(unsigned int irq
)
3056 unsigned long flags
;
3058 dynamic_irq_cleanup(irq
);
3060 #ifdef CONFIG_INTR_REMAP
3063 spin_lock_irqsave(&vector_lock
, flags
);
3064 __clear_irq_vector(irq
);
3065 spin_unlock_irqrestore(&vector_lock
, flags
);
3069 * MSI message composition
3071 #ifdef CONFIG_PCI_MSI
3072 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3074 struct irq_cfg
*cfg
;
3080 err
= assign_irq_vector(irq
, tmp
);
3085 cpus_and(tmp
, cfg
->domain
, tmp
);
3086 dest
= cpu_mask_to_apicid(tmp
);
3088 #ifdef CONFIG_INTR_REMAP
3089 if (irq_remapped(irq
)) {
3094 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3095 BUG_ON(ir_index
== -1);
3097 memset (&irte
, 0, sizeof(irte
));
3100 irte
.dst_mode
= INT_DEST_MODE
;
3101 irte
.trigger_mode
= 0; /* edge */
3102 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3103 irte
.vector
= cfg
->vector
;
3104 irte
.dest_id
= IRTE_DEST(dest
);
3106 modify_irte(irq
, &irte
);
3108 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3109 msg
->data
= sub_handle
;
3110 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3112 MSI_ADDR_IR_INDEX1(ir_index
) |
3113 MSI_ADDR_IR_INDEX2(ir_index
);
3117 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3120 ((INT_DEST_MODE
== 0) ?
3121 MSI_ADDR_DEST_MODE_PHYSICAL
:
3122 MSI_ADDR_DEST_MODE_LOGICAL
) |
3123 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3124 MSI_ADDR_REDIRECTION_CPU
:
3125 MSI_ADDR_REDIRECTION_LOWPRI
) |
3126 MSI_ADDR_DEST_ID(dest
);
3129 MSI_DATA_TRIGGER_EDGE
|
3130 MSI_DATA_LEVEL_ASSERT
|
3131 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3132 MSI_DATA_DELIVERY_FIXED
:
3133 MSI_DATA_DELIVERY_LOWPRI
) |
3134 MSI_DATA_VECTOR(cfg
->vector
);
3140 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3142 struct irq_cfg
*cfg
;
3146 struct irq_desc
*desc
;
3148 cpus_and(tmp
, mask
, cpu_online_map
);
3149 if (cpus_empty(tmp
))
3152 if (assign_irq_vector(irq
, mask
))
3156 cpus_and(tmp
, cfg
->domain
, mask
);
3157 dest
= cpu_mask_to_apicid(tmp
);
3159 read_msi_msg(irq
, &msg
);
3161 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3162 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3163 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3164 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3166 write_msi_msg(irq
, &msg
);
3167 desc
= irq_to_desc(irq
);
3168 desc
->affinity
= mask
;
3171 #ifdef CONFIG_INTR_REMAP
3173 * Migrate the MSI irq to another cpumask. This migration is
3174 * done in the process context using interrupt-remapping hardware.
3176 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3178 struct irq_cfg
*cfg
;
3180 cpumask_t tmp
, cleanup_mask
;
3182 struct irq_desc
*desc
;
3184 cpus_and(tmp
, mask
, cpu_online_map
);
3185 if (cpus_empty(tmp
))
3188 if (get_irte(irq
, &irte
))
3191 if (assign_irq_vector(irq
, mask
))
3195 cpus_and(tmp
, cfg
->domain
, mask
);
3196 dest
= cpu_mask_to_apicid(tmp
);
3198 irte
.vector
= cfg
->vector
;
3199 irte
.dest_id
= IRTE_DEST(dest
);
3202 * atomically update the IRTE with the new destination and vector.
3204 modify_irte(irq
, &irte
);
3207 * After this point, all the interrupts will start arriving
3208 * at the new destination. So, time to cleanup the previous
3209 * vector allocation.
3211 if (cfg
->move_in_progress
) {
3212 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
3213 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
3214 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
3215 cfg
->move_in_progress
= 0;
3218 desc
= irq_to_desc(irq
);
3219 desc
->affinity
= mask
;
3222 #endif /* CONFIG_SMP */
3225 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3226 * which implement the MSI or MSI-X Capability Structure.
3228 static struct irq_chip msi_chip
= {
3230 .unmask
= unmask_msi_irq
,
3231 .mask
= mask_msi_irq
,
3232 .ack
= ack_apic_edge
,
3234 .set_affinity
= set_msi_irq_affinity
,
3236 .retrigger
= ioapic_retrigger_irq
,
3239 #ifdef CONFIG_INTR_REMAP
3240 static struct irq_chip msi_ir_chip
= {
3241 .name
= "IR-PCI-MSI",
3242 .unmask
= unmask_msi_irq
,
3243 .mask
= mask_msi_irq
,
3244 .ack
= ack_x2apic_edge
,
3246 .set_affinity
= ir_set_msi_irq_affinity
,
3248 .retrigger
= ioapic_retrigger_irq
,
3252 * Map the PCI dev to the corresponding remapping hardware unit
3253 * and allocate 'nvec' consecutive interrupt-remapping table entries
3256 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3258 struct intel_iommu
*iommu
;
3261 iommu
= map_dev_to_ir(dev
);
3264 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3268 index
= alloc_irte(iommu
, irq
, nvec
);
3271 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3279 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
3284 ret
= msi_compose_msg(dev
, irq
, &msg
);
3288 set_irq_msi(irq
, desc
);
3289 write_msi_msg(irq
, &msg
);
3291 #ifdef CONFIG_INTR_REMAP
3292 if (irq_remapped(irq
)) {
3293 struct irq_desc
*desc
= irq_to_desc(irq
);
3295 * irq migration in process context
3297 desc
->status
|= IRQ_MOVE_PCNTXT
;
3298 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3301 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3306 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
3310 irq
= dev
->bus
->number
;
3318 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
3322 unsigned int irq_want
;
3324 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3326 irq
= create_irq_nr(irq_want
);
3330 #ifdef CONFIG_INTR_REMAP
3331 if (!intr_remapping_enabled
)
3334 ret
= msi_alloc_irte(dev
, irq
, 1);
3339 ret
= setup_msi_irq(dev
, desc
, irq
);
3346 #ifdef CONFIG_INTR_REMAP
3353 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3356 int ret
, sub_handle
;
3357 struct msi_desc
*desc
;
3358 unsigned int irq_want
;
3360 #ifdef CONFIG_INTR_REMAP
3361 struct intel_iommu
*iommu
= 0;
3365 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3367 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
3368 irq
= create_irq_nr(irq_want
--);
3371 #ifdef CONFIG_INTR_REMAP
3372 if (!intr_remapping_enabled
)
3377 * allocate the consecutive block of IRTE's
3380 index
= msi_alloc_irte(dev
, irq
, nvec
);
3386 iommu
= map_dev_to_ir(dev
);
3392 * setup the mapping between the irq and the IRTE
3393 * base index, the sub_handle pointing to the
3394 * appropriate interrupt remap table entry.
3396 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3400 ret
= setup_msi_irq(dev
, desc
, irq
);
3412 void arch_teardown_msi_irq(unsigned int irq
)
3419 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
3421 struct irq_cfg
*cfg
;
3425 struct irq_desc
*desc
;
3427 cpus_and(tmp
, mask
, cpu_online_map
);
3428 if (cpus_empty(tmp
))
3431 if (assign_irq_vector(irq
, mask
))
3435 cpus_and(tmp
, cfg
->domain
, mask
);
3436 dest
= cpu_mask_to_apicid(tmp
);
3438 dmar_msi_read(irq
, &msg
);
3440 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3441 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3442 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3443 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3445 dmar_msi_write(irq
, &msg
);
3446 desc
= irq_to_desc(irq
);
3447 desc
->affinity
= mask
;
3449 #endif /* CONFIG_SMP */
3451 struct irq_chip dmar_msi_type
= {
3453 .unmask
= dmar_msi_unmask
,
3454 .mask
= dmar_msi_mask
,
3455 .ack
= ack_apic_edge
,
3457 .set_affinity
= dmar_msi_set_affinity
,
3459 .retrigger
= ioapic_retrigger_irq
,
3462 int arch_setup_dmar_msi(unsigned int irq
)
3467 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3470 dmar_msi_write(irq
, &msg
);
3471 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3477 #endif /* CONFIG_PCI_MSI */
3479 * Hypertransport interrupt support
3481 #ifdef CONFIG_HT_IRQ
3485 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3487 struct ht_irq_msg msg
;
3488 fetch_ht_irq_msg(irq
, &msg
);
3490 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3491 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3493 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3494 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3496 write_ht_irq_msg(irq
, &msg
);
3499 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
3501 struct irq_cfg
*cfg
;
3504 struct irq_desc
*desc
;
3506 cpus_and(tmp
, mask
, cpu_online_map
);
3507 if (cpus_empty(tmp
))
3510 if (assign_irq_vector(irq
, mask
))
3514 cpus_and(tmp
, cfg
->domain
, mask
);
3515 dest
= cpu_mask_to_apicid(tmp
);
3517 target_ht_irq(irq
, dest
, cfg
->vector
);
3518 desc
= irq_to_desc(irq
);
3519 desc
->affinity
= mask
;
3523 static struct irq_chip ht_irq_chip
= {
3525 .mask
= mask_ht_irq
,
3526 .unmask
= unmask_ht_irq
,
3527 .ack
= ack_apic_edge
,
3529 .set_affinity
= set_ht_irq_affinity
,
3531 .retrigger
= ioapic_retrigger_irq
,
3534 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3536 struct irq_cfg
*cfg
;
3541 err
= assign_irq_vector(irq
, tmp
);
3543 struct ht_irq_msg msg
;
3547 cpus_and(tmp
, cfg
->domain
, tmp
);
3548 dest
= cpu_mask_to_apicid(tmp
);
3550 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3554 HT_IRQ_LOW_DEST_ID(dest
) |
3555 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3556 ((INT_DEST_MODE
== 0) ?
3557 HT_IRQ_LOW_DM_PHYSICAL
:
3558 HT_IRQ_LOW_DM_LOGICAL
) |
3559 HT_IRQ_LOW_RQEOI_EDGE
|
3560 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3561 HT_IRQ_LOW_MT_FIXED
:
3562 HT_IRQ_LOW_MT_ARBITRATED
) |
3563 HT_IRQ_LOW_IRQ_MASKED
;
3565 write_ht_irq_msg(irq
, &msg
);
3567 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3568 handle_edge_irq
, "edge");
3572 #endif /* CONFIG_HT_IRQ */
3574 /* --------------------------------------------------------------------------
3575 ACPI-based IOAPIC Configuration
3576 -------------------------------------------------------------------------- */
3580 #ifdef CONFIG_X86_32
3581 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3583 union IO_APIC_reg_00 reg_00
;
3584 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3586 unsigned long flags
;
3590 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3591 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3592 * supports up to 16 on one shared APIC bus.
3594 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3595 * advantage of new APIC bus architecture.
3598 if (physids_empty(apic_id_map
))
3599 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3601 spin_lock_irqsave(&ioapic_lock
, flags
);
3602 reg_00
.raw
= io_apic_read(ioapic
, 0);
3603 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3605 if (apic_id
>= get_physical_broadcast()) {
3606 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3607 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3608 apic_id
= reg_00
.bits
.ID
;
3612 * Every APIC in a system must have a unique ID or we get lots of nice
3613 * 'stuck on smp_invalidate_needed IPI wait' messages.
3615 if (check_apicid_used(apic_id_map
, apic_id
)) {
3617 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3618 if (!check_apicid_used(apic_id_map
, i
))
3622 if (i
== get_physical_broadcast())
3623 panic("Max apic_id exceeded!\n");
3625 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3626 "trying %d\n", ioapic
, apic_id
, i
);
3631 tmp
= apicid_to_cpu_present(apic_id
);
3632 physids_or(apic_id_map
, apic_id_map
, tmp
);
3634 if (reg_00
.bits
.ID
!= apic_id
) {
3635 reg_00
.bits
.ID
= apic_id
;
3637 spin_lock_irqsave(&ioapic_lock
, flags
);
3638 io_apic_write(ioapic
, 0, reg_00
.raw
);
3639 reg_00
.raw
= io_apic_read(ioapic
, 0);
3640 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3643 if (reg_00
.bits
.ID
!= apic_id
) {
3644 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3649 apic_printk(APIC_VERBOSE
, KERN_INFO
3650 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3655 int __init
io_apic_get_version(int ioapic
)
3657 union IO_APIC_reg_01 reg_01
;
3658 unsigned long flags
;
3660 spin_lock_irqsave(&ioapic_lock
, flags
);
3661 reg_01
.raw
= io_apic_read(ioapic
, 1);
3662 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3664 return reg_01
.bits
.version
;
3668 int __init
io_apic_get_redir_entries (int ioapic
)
3670 union IO_APIC_reg_01 reg_01
;
3671 unsigned long flags
;
3673 spin_lock_irqsave(&ioapic_lock
, flags
);
3674 reg_01
.raw
= io_apic_read(ioapic
, 1);
3675 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3677 return reg_01
.bits
.entries
;
3681 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3683 if (!IO_APIC_IRQ(irq
)) {
3684 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3690 * IRQs < 16 are already in the irq_2_pin[] map
3693 add_pin_to_irq(irq
, ioapic
, pin
);
3695 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
3701 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3705 if (skip_ioapic_setup
)
3708 for (i
= 0; i
< mp_irq_entries
; i
++)
3709 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3710 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3712 if (i
>= mp_irq_entries
)
3715 *trigger
= irq_trigger(i
);
3716 *polarity
= irq_polarity(i
);
3720 #endif /* CONFIG_ACPI */
3723 * This function currently is only a helper for the i386 smp boot process where
3724 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3725 * so mask in all cases should simply be TARGET_CPUS
3728 void __init
setup_ioapic_dest(void)
3730 int pin
, ioapic
, irq
, irq_entry
;
3731 struct irq_cfg
*cfg
;
3733 if (skip_ioapic_setup
== 1)
3736 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3737 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3738 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3739 if (irq_entry
== -1)
3741 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3743 /* setup_IO_APIC_irqs could fail to get vector for some device
3744 * when you have too many devices, because at that time only boot
3749 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3750 irq_trigger(irq_entry
),
3751 irq_polarity(irq_entry
));
3752 #ifdef CONFIG_INTR_REMAP
3753 else if (intr_remapping_enabled
)
3754 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3757 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3764 #define IOAPIC_RESOURCE_NAME_SIZE 11
3766 static struct resource
*ioapic_resources
;
3768 static struct resource
* __init
ioapic_setup_resources(void)
3771 struct resource
*res
;
3775 if (nr_ioapics
<= 0)
3778 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3781 mem
= alloc_bootmem(n
);
3785 mem
+= sizeof(struct resource
) * nr_ioapics
;
3787 for (i
= 0; i
< nr_ioapics
; i
++) {
3789 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3790 sprintf(mem
, "IOAPIC %u", i
);
3791 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3795 ioapic_resources
= res
;
3800 void __init
ioapic_init_mappings(void)
3802 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3804 struct resource
*ioapic_res
;
3806 ioapic_res
= ioapic_setup_resources();
3807 for (i
= 0; i
< nr_ioapics
; i
++) {
3808 if (smp_found_config
) {
3809 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3810 #ifdef CONFIG_X86_32
3813 "WARNING: bogus zero IO-APIC "
3814 "address found in MPTABLE, "
3815 "disabling IO/APIC support!\n");
3816 smp_found_config
= 0;
3817 skip_ioapic_setup
= 1;
3818 goto fake_ioapic_page
;
3822 #ifdef CONFIG_X86_32
3825 ioapic_phys
= (unsigned long)
3826 alloc_bootmem_pages(PAGE_SIZE
);
3827 ioapic_phys
= __pa(ioapic_phys
);
3829 set_fixmap_nocache(idx
, ioapic_phys
);
3830 apic_printk(APIC_VERBOSE
,
3831 "mapped IOAPIC to %08lx (%08lx)\n",
3832 __fix_to_virt(idx
), ioapic_phys
);
3835 if (ioapic_res
!= NULL
) {
3836 ioapic_res
->start
= ioapic_phys
;
3837 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3843 static int __init
ioapic_insert_resources(void)
3846 struct resource
*r
= ioapic_resources
;
3850 "IO APIC resources could be not be allocated.\n");
3854 for (i
= 0; i
< nr_ioapics
; i
++) {
3855 insert_resource(&iomem_resource
, r
);
3862 /* Insert the IO APIC resources after PCI initialization has occured to handle
3863 * IO APICS that are mapped in on a BAR in PCI space. */
3864 late_initcall(ioapic_insert_resources
);