2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
61 #include <mach_apic.h>
62 #include <mach_apicdef.h>
64 #define __apicdebuginit(type) static type __init
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
70 int sis_apic_bug
= -1;
72 static DEFINE_SPINLOCK(ioapic_lock
);
73 static DEFINE_SPINLOCK(vector_lock
);
76 * # of IRQ routing registers
78 int nr_ioapic_registers
[MAX_IO_APICS
];
80 /* I/O APIC entries */
81 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
84 /* MP IRQ source entries */
85 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
87 /* # of MP IRQ source entries */
90 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
91 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
94 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
96 int skip_ioapic_setup
;
98 static int __init
parse_noapic(char *str
)
100 /* disable IO-APIC */
101 disable_ioapic_setup();
104 early_param("noapic", parse_noapic
);
110 #ifdef CONFIG_HAVE_SPARSE_IRQ
111 struct irq_cfg
*next
;
113 struct irq_pin_list
*irq_2_pin
;
115 cpumask_t old_domain
;
116 unsigned move_cleanup_count
;
118 u8 move_in_progress
: 1;
121 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
122 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
123 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
124 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
125 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
126 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
127 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
128 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
129 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
130 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
131 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
132 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
133 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
134 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
135 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
136 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
137 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
138 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
141 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
143 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
145 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
148 static struct irq_cfg
*irq_cfgx
;
151 * Protect the irq_cfgx_free freelist:
153 static DEFINE_SPINLOCK(irq_cfg_lock
);
155 #ifdef CONFIG_HAVE_SPARSE_IRQ
156 static struct irq_cfg
*irq_cfgx_free
;
158 static void __init
init_work(void *data
)
160 struct dyn_array
*da
= data
;
167 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
169 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
170 for (i
= legacy_count
; i
< *da
->nr
; i
++)
171 init_one_irq_cfg(&cfg
[i
]);
173 #ifdef CONFIG_HAVE_SPARSE_IRQ
174 for (i
= 1; i
< *da
->nr
; i
++)
175 cfg
[i
-1].next
= &cfg
[i
];
177 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
178 irq_cfgx
[legacy_count
- 1].next
= NULL
;
182 #ifdef CONFIG_HAVE_SPARSE_IRQ
183 /* need to be biger than size of irq_cfg_legacy */
184 static int nr_irq_cfg
= 32;
186 static int __init
parse_nr_irq_cfg(char *arg
)
189 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
196 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
198 #define for_each_irq_cfg(irqX, cfg) \
199 for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U)
202 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
204 static struct irq_cfg
*irq_cfg(unsigned int irq
)
219 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
221 struct irq_cfg
*cfg
, *cfg_pri
;
226 cfg_pri
= cfg
= irq_cfgx
;
236 spin_lock_irqsave(&irq_cfg_lock
, flags
);
237 if (!irq_cfgx_free
) {
239 unsigned long total_bytes
;
241 * we run out of pre-allocate ones, allocate more
243 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
245 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
247 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
249 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
252 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
255 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
257 for (i
= 0; i
< nr_irq_cfg
; i
++)
258 init_one_irq_cfg(&cfg
[i
]);
260 for (i
= 1; i
< nr_irq_cfg
; i
++)
261 cfg
[i
-1].next
= &cfg
[i
];
267 irq_cfgx_free
= irq_cfgx_free
->next
;
275 spin_unlock_irqrestore(&irq_cfg_lock
, flags
);
277 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
278 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
280 /* dump the results */
283 unsigned long bytes
= sizeof(struct irq_cfg
);
285 printk(KERN_DEBUG
"=========================== %d\n", irq
);
286 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
287 for_each_irq_cfg(cfg
) {
289 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
291 printk(KERN_DEBUG
"===========================\n");
298 #define for_each_irq_cfg(irq, cfg) \
299 for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
301 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irqs
, PAGE_SIZE
, init_work
);
303 struct irq_cfg
*irq_cfg(unsigned int irq
)
306 return &irq_cfgx
[irq
];
310 struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
317 * This is performance-critical, we want to do it O(1)
319 * the indexing order of this array favors 1:1 mappings
320 * between pins and IRQs.
323 struct irq_pin_list
{
325 struct irq_pin_list
*next
;
328 static struct irq_pin_list
*irq_2_pin_head
;
329 /* fill one page ? */
330 static int nr_irq_2_pin
= 0x100;
331 static struct irq_pin_list
*irq_2_pin_ptr
;
332 static void __init
irq_2_pin_init_work(void *data
)
334 struct dyn_array
*da
= data
;
335 struct irq_pin_list
*pin
;
340 for (i
= 1; i
< *da
->nr
; i
++)
341 pin
[i
-1].next
= &pin
[i
];
343 irq_2_pin_ptr
= &pin
[0];
345 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
347 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
349 struct irq_pin_list
*pin
;
355 irq_2_pin_ptr
= pin
->next
;
361 * we run out of pre-allocate ones, allocate more
363 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
366 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
369 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
370 nr_irq_2_pin
, PAGE_SIZE
, 0);
373 panic("can not get more irq_2_pin\n");
375 for (i
= 1; i
< nr_irq_2_pin
; i
++)
376 pin
[i
-1].next
= &pin
[i
];
378 irq_2_pin_ptr
= pin
->next
;
386 unsigned int unused
[3];
390 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
392 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
393 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
396 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
398 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
399 writel(reg
, &io_apic
->index
);
400 return readl(&io_apic
->data
);
403 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
405 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
406 writel(reg
, &io_apic
->index
);
407 writel(value
, &io_apic
->data
);
411 * Re-write a value: to be used for read-modify-write
412 * cycles where the read already set up the index register.
414 * Older SiS APIC requires we rewrite the index register
416 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
418 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
420 writel(reg
, &io_apic
->index
);
421 writel(value
, &io_apic
->data
);
424 static bool io_apic_level_ack_pending(unsigned int irq
)
426 struct irq_pin_list
*entry
;
428 struct irq_cfg
*cfg
= irq_cfg(irq
);
430 spin_lock_irqsave(&ioapic_lock
, flags
);
431 entry
= cfg
->irq_2_pin
;
439 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
440 /* Is the remote IRR bit set? */
441 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
442 spin_unlock_irqrestore(&ioapic_lock
, flags
);
449 spin_unlock_irqrestore(&ioapic_lock
, flags
);
455 struct { u32 w1
, w2
; };
456 struct IO_APIC_route_entry entry
;
459 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
461 union entry_union eu
;
463 spin_lock_irqsave(&ioapic_lock
, flags
);
464 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
465 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
466 spin_unlock_irqrestore(&ioapic_lock
, flags
);
471 * When we write a new IO APIC routing entry, we need to write the high
472 * word first! If the mask bit in the low word is clear, we will enable
473 * the interrupt, and we need to make sure the entry is fully populated
474 * before that happens.
477 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
479 union entry_union eu
;
481 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
482 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
485 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
488 spin_lock_irqsave(&ioapic_lock
, flags
);
489 __ioapic_write_entry(apic
, pin
, e
);
490 spin_unlock_irqrestore(&ioapic_lock
, flags
);
494 * When we mask an IO APIC routing entry, we need to write the low
495 * word first, in order to set the mask bit before we change the
498 static void ioapic_mask_entry(int apic
, int pin
)
501 union entry_union eu
= { .entry
.mask
= 1 };
503 spin_lock_irqsave(&ioapic_lock
, flags
);
504 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
505 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
506 spin_unlock_irqrestore(&ioapic_lock
, flags
);
510 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
514 struct irq_pin_list
*entry
;
517 entry
= cfg
->irq_2_pin
;
526 #ifdef CONFIG_INTR_REMAP
528 * With interrupt-remapping, destination information comes
529 * from interrupt-remapping table entry.
531 if (!irq_remapped(irq
))
532 io_apic_write(apic
, 0x11 + pin
*2, dest
);
534 io_apic_write(apic
, 0x11 + pin
*2, dest
);
536 reg
= io_apic_read(apic
, 0x10 + pin
*2);
537 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
539 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
546 static int assign_irq_vector(int irq
, cpumask_t mask
);
548 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
554 struct irq_desc
*desc
;
556 cpus_and(tmp
, mask
, cpu_online_map
);
561 if (assign_irq_vector(irq
, mask
))
564 cpus_and(tmp
, cfg
->domain
, mask
);
565 dest
= cpu_mask_to_apicid(tmp
);
567 * Only the high 8 bits are valid.
569 dest
= SET_APIC_LOGICAL_ID(dest
);
571 desc
= irq_to_desc(irq
);
572 spin_lock_irqsave(&ioapic_lock
, flags
);
573 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
574 desc
->affinity
= mask
;
575 spin_unlock_irqrestore(&ioapic_lock
, flags
);
577 #endif /* CONFIG_SMP */
580 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
581 * shared ISA-space IRQs, so we have to support them. We are super
582 * fast in the common case, and fast for shared ISA-space IRQs.
584 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
587 struct irq_pin_list
*entry
;
589 /* first time to refer irq_cfg, so with new */
590 cfg
= irq_cfg_alloc(irq
);
591 entry
= cfg
->irq_2_pin
;
593 entry
= get_one_free_irq_2_pin();
594 cfg
->irq_2_pin
= entry
;
597 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
601 while (entry
->next
) {
602 /* not again, please */
603 if (entry
->apic
== apic
&& entry
->pin
== pin
)
609 entry
->next
= get_one_free_irq_2_pin();
613 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
617 * Reroute an IRQ to a different pin.
619 static void __init
replace_pin_at_irq(unsigned int irq
,
620 int oldapic
, int oldpin
,
621 int newapic
, int newpin
)
623 struct irq_cfg
*cfg
= irq_cfg(irq
);
624 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
628 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
629 entry
->apic
= newapic
;
632 /* every one is different, right? */
638 /* why? call replace before add? */
640 add_pin_to_irq(irq
, newapic
, newpin
);
643 #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
647 struct irq_cfg *cfg; \
648 struct irq_pin_list *entry; \
650 cfg = irq_cfg(irq); \
651 entry = cfg->irq_2_pin; \
657 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
658 reg ACTION_DISABLE; \
660 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
664 entry = entry->next; \
668 #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
670 static void name##_IO_APIC_irq (unsigned int irq) \
671 __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
674 DO_ACTION(__unmask
, 0, |= 0, &= ~IO_APIC_REDIR_MASKED
, )
678 * Synchronize the IO-APIC and the CPU by doing
679 * a dummy read from the IO-APIC
681 static inline void io_apic_sync(unsigned int apic
)
683 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
684 readl(&io_apic
->data
);
688 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, &= ~0, io_apic_sync(entry
->apic
))
693 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, &= ~0, )
695 /* mask = 1, trigger = 0 */
696 DO_ACTION(__mask_and_edge
, 0, |= IO_APIC_REDIR_MASKED
, &= ~IO_APIC_REDIR_LEVEL_TRIGGER
, )
698 /* mask = 0, trigger = 1 */
699 DO_ACTION(__unmask_and_level
, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER
, &= ~IO_APIC_REDIR_MASKED
, )
703 static void mask_IO_APIC_irq (unsigned int irq
)
707 spin_lock_irqsave(&ioapic_lock
, flags
);
708 __mask_IO_APIC_irq(irq
);
709 spin_unlock_irqrestore(&ioapic_lock
, flags
);
712 static void unmask_IO_APIC_irq (unsigned int irq
)
716 spin_lock_irqsave(&ioapic_lock
, flags
);
717 __unmask_IO_APIC_irq(irq
);
718 spin_unlock_irqrestore(&ioapic_lock
, flags
);
721 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
723 struct IO_APIC_route_entry entry
;
725 /* Check delivery_mode to be sure we're not clearing an SMI pin */
726 entry
= ioapic_read_entry(apic
, pin
);
727 if (entry
.delivery_mode
== dest_SMI
)
730 * Disable it in the IO-APIC irq-routing table:
732 ioapic_mask_entry(apic
, pin
);
735 static void clear_IO_APIC (void)
739 for (apic
= 0; apic
< nr_ioapics
; apic
++)
740 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
741 clear_IO_APIC_pin(apic
, pin
);
744 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
745 void send_IPI_self(int vector
)
752 apic_wait_icr_idle();
753 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
755 * Send the IPI. The write to APIC_ICR fires this off.
757 apic_write(APIC_ICR
, cfg
);
759 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
763 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
764 * specific CPU-side IRQs.
768 static int pirq_entries
[MAX_PIRQS
];
769 static int pirqs_enabled
;
771 static int __init
ioapic_pirq_setup(char *str
)
774 int ints
[MAX_PIRQS
+1];
776 get_options(str
, ARRAY_SIZE(ints
), ints
);
778 for (i
= 0; i
< MAX_PIRQS
; i
++)
779 pirq_entries
[i
] = -1;
782 apic_printk(APIC_VERBOSE
, KERN_INFO
783 "PIRQ redirection, working around broken MP-BIOS.\n");
785 if (ints
[0] < MAX_PIRQS
)
788 for (i
= 0; i
< max
; i
++) {
789 apic_printk(APIC_VERBOSE
, KERN_DEBUG
790 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
792 * PIRQs are mapped upside down, usually.
794 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
799 __setup("pirq=", ioapic_pirq_setup
);
800 #endif /* CONFIG_X86_32 */
802 #ifdef CONFIG_INTR_REMAP
803 /* I/O APIC RTE contents at the OS boot up */
804 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
807 * Saves and masks all the unmasked IO-APIC RTE's
809 int save_mask_IO_APIC_setup(void)
811 union IO_APIC_reg_01 reg_01
;
816 * The number of IO-APIC IRQ registers (== #pins):
818 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
819 spin_lock_irqsave(&ioapic_lock
, flags
);
820 reg_01
.raw
= io_apic_read(apic
, 1);
821 spin_unlock_irqrestore(&ioapic_lock
, flags
);
822 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
825 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
826 early_ioapic_entries
[apic
] =
827 kzalloc(sizeof(struct IO_APIC_route_entry
) *
828 nr_ioapic_registers
[apic
], GFP_KERNEL
);
829 if (!early_ioapic_entries
[apic
])
833 for (apic
= 0; apic
< nr_ioapics
; apic
++)
834 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
835 struct IO_APIC_route_entry entry
;
837 entry
= early_ioapic_entries
[apic
][pin
] =
838 ioapic_read_entry(apic
, pin
);
841 ioapic_write_entry(apic
, pin
, entry
);
847 void restore_IO_APIC_setup(void)
851 for (apic
= 0; apic
< nr_ioapics
; apic
++)
852 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
853 ioapic_write_entry(apic
, pin
,
854 early_ioapic_entries
[apic
][pin
]);
857 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
860 * for now plain restore of previous settings.
861 * TBD: In the case of OS enabling interrupt-remapping,
862 * IO-APIC RTE's need to be setup to point to interrupt-remapping
863 * table entries. for now, do a plain restore, and wait for
864 * the setup_IO_APIC_irqs() to do proper initialization.
866 restore_IO_APIC_setup();
871 * Find the IRQ entry number of a certain pin.
873 static int find_irq_entry(int apic
, int pin
, int type
)
877 for (i
= 0; i
< mp_irq_entries
; i
++)
878 if (mp_irqs
[i
].mp_irqtype
== type
&&
879 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
880 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
881 mp_irqs
[i
].mp_dstirq
== pin
)
888 * Find the pin to which IRQ[irq] (ISA) is connected
890 static int __init
find_isa_irq_pin(int irq
, int type
)
894 for (i
= 0; i
< mp_irq_entries
; i
++) {
895 int lbus
= mp_irqs
[i
].mp_srcbus
;
897 if (test_bit(lbus
, mp_bus_not_pci
) &&
898 (mp_irqs
[i
].mp_irqtype
== type
) &&
899 (mp_irqs
[i
].mp_srcbusirq
== irq
))
901 return mp_irqs
[i
].mp_dstirq
;
906 static int __init
find_isa_irq_apic(int irq
, int type
)
910 for (i
= 0; i
< mp_irq_entries
; i
++) {
911 int lbus
= mp_irqs
[i
].mp_srcbus
;
913 if (test_bit(lbus
, mp_bus_not_pci
) &&
914 (mp_irqs
[i
].mp_irqtype
== type
) &&
915 (mp_irqs
[i
].mp_srcbusirq
== irq
))
918 if (i
< mp_irq_entries
) {
920 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
921 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
930 * Find a specific PCI IRQ entry.
931 * Not an __init, possibly needed by modules
933 static int pin_2_irq(int idx
, int apic
, int pin
);
935 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
937 int apic
, i
, best_guess
= -1;
939 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
941 if (test_bit(bus
, mp_bus_not_pci
)) {
942 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
945 for (i
= 0; i
< mp_irq_entries
; i
++) {
946 int lbus
= mp_irqs
[i
].mp_srcbus
;
948 for (apic
= 0; apic
< nr_ioapics
; apic
++)
949 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
950 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
953 if (!test_bit(lbus
, mp_bus_not_pci
) &&
954 !mp_irqs
[i
].mp_irqtype
&&
956 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
957 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
959 if (!(apic
|| IO_APIC_IRQ(irq
)))
962 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
965 * Use the first all-but-pin matching entry as a
966 * best-guess fuzzy result for broken mptables.
975 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
977 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
979 * EISA Edge/Level control register, ELCR
981 static int EISA_ELCR(unsigned int irq
)
984 unsigned int port
= 0x4d0 + (irq
>> 3);
985 return (inb(port
) >> (irq
& 7)) & 1;
987 apic_printk(APIC_VERBOSE
, KERN_INFO
988 "Broken MPtable reports ISA irq %d\n", irq
);
994 /* ISA interrupts are always polarity zero edge triggered,
995 * when listed as conforming in the MP table. */
997 #define default_ISA_trigger(idx) (0)
998 #define default_ISA_polarity(idx) (0)
1000 /* EISA interrupts are always polarity zero and can be edge or level
1001 * trigger depending on the ELCR value. If an interrupt is listed as
1002 * EISA conforming in the MP table, that means its trigger type must
1003 * be read in from the ELCR */
1005 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1006 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1008 /* PCI interrupts are always polarity one level triggered,
1009 * when listed as conforming in the MP table. */
1011 #define default_PCI_trigger(idx) (1)
1012 #define default_PCI_polarity(idx) (1)
1014 /* MCA interrupts are always polarity zero level triggered,
1015 * when listed as conforming in the MP table. */
1017 #define default_MCA_trigger(idx) (1)
1018 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1020 static int MPBIOS_polarity(int idx
)
1022 int bus
= mp_irqs
[idx
].mp_srcbus
;
1026 * Determine IRQ line polarity (high active or low active):
1028 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1030 case 0: /* conforms, ie. bus-type dependent polarity */
1031 if (test_bit(bus
, mp_bus_not_pci
))
1032 polarity
= default_ISA_polarity(idx
);
1034 polarity
= default_PCI_polarity(idx
);
1036 case 1: /* high active */
1041 case 2: /* reserved */
1043 printk(KERN_WARNING
"broken BIOS!!\n");
1047 case 3: /* low active */
1052 default: /* invalid */
1054 printk(KERN_WARNING
"broken BIOS!!\n");
1062 static int MPBIOS_trigger(int idx
)
1064 int bus
= mp_irqs
[idx
].mp_srcbus
;
1068 * Determine IRQ trigger mode (edge or level sensitive):
1070 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1072 case 0: /* conforms, ie. bus-type dependent */
1073 if (test_bit(bus
, mp_bus_not_pci
))
1074 trigger
= default_ISA_trigger(idx
);
1076 trigger
= default_PCI_trigger(idx
);
1077 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1078 switch (mp_bus_id_to_type
[bus
]) {
1079 case MP_BUS_ISA
: /* ISA pin */
1081 /* set before the switch */
1084 case MP_BUS_EISA
: /* EISA pin */
1086 trigger
= default_EISA_trigger(idx
);
1089 case MP_BUS_PCI
: /* PCI pin */
1091 /* set before the switch */
1094 case MP_BUS_MCA
: /* MCA pin */
1096 trigger
= default_MCA_trigger(idx
);
1101 printk(KERN_WARNING
"broken BIOS!!\n");
1113 case 2: /* reserved */
1115 printk(KERN_WARNING
"broken BIOS!!\n");
1124 default: /* invalid */
1126 printk(KERN_WARNING
"broken BIOS!!\n");
1134 static inline int irq_polarity(int idx
)
1136 return MPBIOS_polarity(idx
);
1139 static inline int irq_trigger(int idx
)
1141 return MPBIOS_trigger(idx
);
1144 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1145 static int pin_2_irq(int idx
, int apic
, int pin
)
1148 int bus
= mp_irqs
[idx
].mp_srcbus
;
1151 * Debugging check, we are in big trouble if this message pops up!
1153 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1154 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1156 if (test_bit(bus
, mp_bus_not_pci
)) {
1157 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1160 * PCI IRQs are mapped in order
1164 irq
+= nr_ioapic_registers
[i
++];
1167 * For MPS mode, so far only needed by ES7000 platform
1169 if (ioapic_renumber_irq
)
1170 irq
= ioapic_renumber_irq(apic
, irq
);
1173 #ifdef CONFIG_X86_32
1175 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1177 if ((pin
>= 16) && (pin
<= 23)) {
1178 if (pirq_entries
[pin
-16] != -1) {
1179 if (!pirq_entries
[pin
-16]) {
1180 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1181 "disabling PIRQ%d\n", pin
-16);
1183 irq
= pirq_entries
[pin
-16];
1184 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1185 "using PIRQ%d -> IRQ %d\n",
1195 void lock_vector_lock(void)
1197 /* Used to the online set of cpus does not change
1198 * during assign_irq_vector.
1200 spin_lock(&vector_lock
);
1203 void unlock_vector_lock(void)
1205 spin_unlock(&vector_lock
);
1208 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1211 * NOTE! The local APIC isn't very good at handling
1212 * multiple interrupts at the same interrupt level.
1213 * As the interrupt level is determined by taking the
1214 * vector number and shifting that right by 4, we
1215 * want to spread these out a bit so that they don't
1216 * all fall in the same interrupt level.
1218 * Also, we've got to be careful not to trash gate
1219 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1221 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1222 unsigned int old_vector
;
1224 struct irq_cfg
*cfg
;
1228 /* Only try and allocate irqs on cpus that are present */
1229 cpus_and(mask
, mask
, cpu_online_map
);
1231 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1234 old_vector
= cfg
->vector
;
1237 cpus_and(tmp
, cfg
->domain
, mask
);
1238 if (!cpus_empty(tmp
))
1242 for_each_cpu_mask_nr(cpu
, mask
) {
1243 cpumask_t domain
, new_mask
;
1247 domain
= vector_allocation_domain(cpu
);
1248 cpus_and(new_mask
, domain
, cpu_online_map
);
1250 vector
= current_vector
;
1251 offset
= current_offset
;
1254 if (vector
>= first_system_vector
) {
1255 /* If we run out of vectors on large boxen, must share them. */
1256 offset
= (offset
+ 1) % 8;
1257 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1259 if (unlikely(current_vector
== vector
))
1261 #ifdef CONFIG_X86_64
1262 if (vector
== IA32_SYSCALL_VECTOR
)
1265 if (vector
== SYSCALL_VECTOR
)
1268 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1269 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1272 current_vector
= vector
;
1273 current_offset
= offset
;
1275 cfg
->move_in_progress
= 1;
1276 cfg
->old_domain
= cfg
->domain
;
1278 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1279 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1280 cfg
->vector
= vector
;
1281 cfg
->domain
= domain
;
1287 static int assign_irq_vector(int irq
, cpumask_t mask
)
1290 unsigned long flags
;
1292 spin_lock_irqsave(&vector_lock
, flags
);
1293 err
= __assign_irq_vector(irq
, mask
);
1294 spin_unlock_irqrestore(&vector_lock
, flags
);
1298 static void __clear_irq_vector(int irq
)
1300 struct irq_cfg
*cfg
;
1305 BUG_ON(!cfg
->vector
);
1307 vector
= cfg
->vector
;
1308 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1309 for_each_cpu_mask_nr(cpu
, mask
)
1310 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1313 cpus_clear(cfg
->domain
);
1316 void __setup_vector_irq(int cpu
)
1318 /* Initialize vector_irq on a new cpu */
1319 /* This function must be called with vector_lock held */
1321 struct irq_cfg
*cfg
;
1323 /* Mark the inuse vectors */
1324 for_each_irq_cfg(irq
, cfg
) {
1325 if (!cpu_isset(cpu
, cfg
->domain
))
1327 vector
= cfg
->vector
;
1328 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1330 /* Mark the free vectors */
1331 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1332 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1337 if (!cpu_isset(cpu
, cfg
->domain
))
1338 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1342 static struct irq_chip ioapic_chip
;
1343 #ifdef CONFIG_INTR_REMAP
1344 static struct irq_chip ir_ioapic_chip
;
1347 #define IOAPIC_AUTO -1
1348 #define IOAPIC_EDGE 0
1349 #define IOAPIC_LEVEL 1
1351 #ifdef CONFIG_X86_32
1352 static inline int IO_APIC_irq_trigger(int irq
)
1356 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1357 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1358 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1359 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1360 return irq_trigger(idx
);
1364 * nonexistent IRQs are edge default
1369 static inline int IO_APIC_irq_trigger(int irq
)
1375 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1377 struct irq_desc
*desc
;
1379 /* first time to use this irq_desc */
1381 desc
= irq_to_desc(irq
);
1383 desc
= irq_to_desc_alloc(irq
);
1385 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1386 trigger
== IOAPIC_LEVEL
)
1387 desc
->status
|= IRQ_LEVEL
;
1389 desc
->status
&= ~IRQ_LEVEL
;
1391 #ifdef CONFIG_INTR_REMAP
1392 if (irq_remapped(irq
)) {
1393 desc
->status
|= IRQ_MOVE_PCNTXT
;
1395 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1399 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1400 handle_edge_irq
, "edge");
1404 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1405 trigger
== IOAPIC_LEVEL
)
1406 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1410 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1411 handle_edge_irq
, "edge");
1414 static int setup_ioapic_entry(int apic
, int irq
,
1415 struct IO_APIC_route_entry
*entry
,
1416 unsigned int destination
, int trigger
,
1417 int polarity
, int vector
)
1420 * add it to the IO-APIC irq-routing table:
1422 memset(entry
,0,sizeof(*entry
));
1424 #ifdef CONFIG_INTR_REMAP
1425 if (intr_remapping_enabled
) {
1426 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1428 struct IR_IO_APIC_route_entry
*ir_entry
=
1429 (struct IR_IO_APIC_route_entry
*) entry
;
1433 panic("No mapping iommu for ioapic %d\n", apic
);
1435 index
= alloc_irte(iommu
, irq
, 1);
1437 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1439 memset(&irte
, 0, sizeof(irte
));
1442 irte
.dst_mode
= INT_DEST_MODE
;
1443 irte
.trigger_mode
= trigger
;
1444 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1445 irte
.vector
= vector
;
1446 irte
.dest_id
= IRTE_DEST(destination
);
1448 modify_irte(irq
, &irte
);
1450 ir_entry
->index2
= (index
>> 15) & 0x1;
1452 ir_entry
->format
= 1;
1453 ir_entry
->index
= (index
& 0x7fff);
1457 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1458 entry
->dest_mode
= INT_DEST_MODE
;
1459 entry
->dest
= destination
;
1462 entry
->mask
= 0; /* enable IRQ */
1463 entry
->trigger
= trigger
;
1464 entry
->polarity
= polarity
;
1465 entry
->vector
= vector
;
1467 /* Mask level triggered irqs.
1468 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1475 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1476 int trigger
, int polarity
)
1478 struct irq_cfg
*cfg
;
1479 struct IO_APIC_route_entry entry
;
1482 if (!IO_APIC_IRQ(irq
))
1488 if (assign_irq_vector(irq
, mask
))
1491 cpus_and(mask
, cfg
->domain
, mask
);
1493 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1494 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1495 "IRQ %d Mode:%i Active:%i)\n",
1496 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1497 irq
, trigger
, polarity
);
1500 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1501 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1503 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1504 mp_ioapics
[apic
].mp_apicid
, pin
);
1505 __clear_irq_vector(irq
);
1509 ioapic_register_intr(irq
, trigger
);
1511 disable_8259A_irq(irq
);
1513 ioapic_write_entry(apic
, pin
, entry
);
1516 static void __init
setup_IO_APIC_irqs(void)
1518 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1520 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1522 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1523 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1525 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1528 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1531 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1534 if (!first_notcon
) {
1535 apic_printk(APIC_VERBOSE
, " not connected.\n");
1539 irq
= pin_2_irq(idx
, apic
, pin
);
1540 #ifdef CONFIG_X86_32
1541 if (multi_timer_check(apic
, irq
))
1544 add_pin_to_irq(irq
, apic
, pin
);
1546 setup_IO_APIC_irq(apic
, pin
, irq
,
1547 irq_trigger(idx
), irq_polarity(idx
));
1552 apic_printk(APIC_VERBOSE
, " not connected.\n");
1556 * Set up the timer pin, possibly with the 8259A-master behind.
1558 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1561 struct IO_APIC_route_entry entry
;
1563 #ifdef CONFIG_INTR_REMAP
1564 if (intr_remapping_enabled
)
1568 memset(&entry
, 0, sizeof(entry
));
1571 * We use logical delivery to get the timer IRQ
1574 entry
.dest_mode
= INT_DEST_MODE
;
1575 entry
.mask
= 1; /* mask IRQ now */
1576 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1577 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1580 entry
.vector
= vector
;
1583 * The timer IRQ doesn't have to know that behind the
1584 * scene we may have a 8259A-master in AEOI mode ...
1586 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1589 * Add it to the IO-APIC irq-routing table:
1591 ioapic_write_entry(apic
, pin
, entry
);
1595 __apicdebuginit(void) print_IO_APIC(void)
1598 union IO_APIC_reg_00 reg_00
;
1599 union IO_APIC_reg_01 reg_01
;
1600 union IO_APIC_reg_02 reg_02
;
1601 union IO_APIC_reg_03 reg_03
;
1602 unsigned long flags
;
1603 struct irq_cfg
*cfg
;
1606 if (apic_verbosity
== APIC_QUIET
)
1609 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1610 for (i
= 0; i
< nr_ioapics
; i
++)
1611 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1612 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1615 * We are a bit conservative about what we expect. We have to
1616 * know about every hardware change ASAP.
1618 printk(KERN_INFO
"testing the IO APIC.......................\n");
1620 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1622 spin_lock_irqsave(&ioapic_lock
, flags
);
1623 reg_00
.raw
= io_apic_read(apic
, 0);
1624 reg_01
.raw
= io_apic_read(apic
, 1);
1625 if (reg_01
.bits
.version
>= 0x10)
1626 reg_02
.raw
= io_apic_read(apic
, 2);
1627 if (reg_01
.bits
.version
>= 0x20)
1628 reg_03
.raw
= io_apic_read(apic
, 3);
1629 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1632 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1633 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1634 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1635 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1636 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1638 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1639 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1641 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1642 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1645 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1646 * but the value of reg_02 is read as the previous read register
1647 * value, so ignore it if reg_02 == reg_01.
1649 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1650 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1651 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1655 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1656 * or reg_03, but the value of reg_0[23] is read as the previous read
1657 * register value, so ignore it if reg_03 == reg_0[12].
1659 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1660 reg_03
.raw
!= reg_01
.raw
) {
1661 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1662 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1665 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1667 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1668 " Stat Dmod Deli Vect: \n");
1670 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1671 struct IO_APIC_route_entry entry
;
1673 entry
= ioapic_read_entry(apic
, i
);
1675 printk(KERN_DEBUG
" %02x %03X ",
1680 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1685 entry
.delivery_status
,
1687 entry
.delivery_mode
,
1692 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1693 for_each_irq_cfg(irq
, cfg
) {
1694 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1697 printk(KERN_DEBUG
"IRQ%d ", irq
);
1699 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1702 entry
= entry
->next
;
1707 printk(KERN_INFO
".................................... done.\n");
1712 __apicdebuginit(void) print_APIC_bitfield(int base
)
1717 if (apic_verbosity
== APIC_QUIET
)
1720 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1721 for (i
= 0; i
< 8; i
++) {
1722 v
= apic_read(base
+ i
*0x10);
1723 for (j
= 0; j
< 32; j
++) {
1733 __apicdebuginit(void) print_local_APIC(void *dummy
)
1735 unsigned int v
, ver
, maxlvt
;
1738 if (apic_verbosity
== APIC_QUIET
)
1741 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1742 smp_processor_id(), hard_smp_processor_id());
1743 v
= apic_read(APIC_ID
);
1744 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1745 v
= apic_read(APIC_LVR
);
1746 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1747 ver
= GET_APIC_VERSION(v
);
1748 maxlvt
= lapic_get_maxlvt();
1750 v
= apic_read(APIC_TASKPRI
);
1751 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1753 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1754 v
= apic_read(APIC_ARBPRI
);
1755 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1756 v
& APIC_ARBPRI_MASK
);
1757 v
= apic_read(APIC_PROCPRI
);
1758 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1761 v
= apic_read(APIC_EOI
);
1762 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1763 v
= apic_read(APIC_RRR
);
1764 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1765 v
= apic_read(APIC_LDR
);
1766 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1767 v
= apic_read(APIC_DFR
);
1768 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1769 v
= apic_read(APIC_SPIV
);
1770 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1772 printk(KERN_DEBUG
"... APIC ISR field:\n");
1773 print_APIC_bitfield(APIC_ISR
);
1774 printk(KERN_DEBUG
"... APIC TMR field:\n");
1775 print_APIC_bitfield(APIC_TMR
);
1776 printk(KERN_DEBUG
"... APIC IRR field:\n");
1777 print_APIC_bitfield(APIC_IRR
);
1779 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1780 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1781 apic_write(APIC_ESR
, 0);
1783 v
= apic_read(APIC_ESR
);
1784 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1787 icr
= apic_icr_read();
1788 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1789 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1791 v
= apic_read(APIC_LVTT
);
1792 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1794 if (maxlvt
> 3) { /* PC is LVT#4. */
1795 v
= apic_read(APIC_LVTPC
);
1796 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1798 v
= apic_read(APIC_LVT0
);
1799 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1800 v
= apic_read(APIC_LVT1
);
1801 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1803 if (maxlvt
> 2) { /* ERR is LVT#3. */
1804 v
= apic_read(APIC_LVTERR
);
1805 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1808 v
= apic_read(APIC_TMICT
);
1809 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1810 v
= apic_read(APIC_TMCCT
);
1811 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1812 v
= apic_read(APIC_TDCR
);
1813 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1817 __apicdebuginit(void) print_all_local_APICs(void)
1822 for_each_online_cpu(cpu
)
1823 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1827 __apicdebuginit(void) print_PIC(void)
1830 unsigned long flags
;
1832 if (apic_verbosity
== APIC_QUIET
)
1835 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1837 spin_lock_irqsave(&i8259A_lock
, flags
);
1839 v
= inb(0xa1) << 8 | inb(0x21);
1840 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1842 v
= inb(0xa0) << 8 | inb(0x20);
1843 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1847 v
= inb(0xa0) << 8 | inb(0x20);
1851 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1853 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1855 v
= inb(0x4d1) << 8 | inb(0x4d0);
1856 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1859 __apicdebuginit(int) print_all_ICs(void)
1862 print_all_local_APICs();
1868 fs_initcall(print_all_ICs
);
1871 /* Where if anywhere is the i8259 connect in external int mode */
1872 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1874 void __init
enable_IO_APIC(void)
1876 union IO_APIC_reg_01 reg_01
;
1877 int i8259_apic
, i8259_pin
;
1879 unsigned long flags
;
1881 #ifdef CONFIG_X86_32
1884 for (i
= 0; i
< MAX_PIRQS
; i
++)
1885 pirq_entries
[i
] = -1;
1889 * The number of IO-APIC IRQ registers (== #pins):
1891 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1892 spin_lock_irqsave(&ioapic_lock
, flags
);
1893 reg_01
.raw
= io_apic_read(apic
, 1);
1894 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1895 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1897 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1899 /* See if any of the pins is in ExtINT mode */
1900 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1901 struct IO_APIC_route_entry entry
;
1902 entry
= ioapic_read_entry(apic
, pin
);
1904 /* If the interrupt line is enabled and in ExtInt mode
1905 * I have found the pin where the i8259 is connected.
1907 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1908 ioapic_i8259
.apic
= apic
;
1909 ioapic_i8259
.pin
= pin
;
1915 /* Look to see what if the MP table has reported the ExtINT */
1916 /* If we could not find the appropriate pin by looking at the ioapic
1917 * the i8259 probably is not connected the ioapic but give the
1918 * mptable a chance anyway.
1920 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1921 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1922 /* Trust the MP table if nothing is setup in the hardware */
1923 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1924 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1925 ioapic_i8259
.pin
= i8259_pin
;
1926 ioapic_i8259
.apic
= i8259_apic
;
1928 /* Complain if the MP table and the hardware disagree */
1929 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1930 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1932 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1936 * Do not trust the IO-APIC being empty at bootup
1942 * Not an __init, needed by the reboot code
1944 void disable_IO_APIC(void)
1947 * Clear the IO-APIC before rebooting:
1952 * If the i8259 is routed through an IOAPIC
1953 * Put that IOAPIC in virtual wire mode
1954 * so legacy interrupts can be delivered.
1956 if (ioapic_i8259
.pin
!= -1) {
1957 struct IO_APIC_route_entry entry
;
1959 memset(&entry
, 0, sizeof(entry
));
1960 entry
.mask
= 0; /* Enabled */
1961 entry
.trigger
= 0; /* Edge */
1963 entry
.polarity
= 0; /* High */
1964 entry
.delivery_status
= 0;
1965 entry
.dest_mode
= 0; /* Physical */
1966 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1968 entry
.dest
= read_apic_id();
1971 * Add it to the IO-APIC irq-routing table:
1973 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1976 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1979 #ifdef CONFIG_X86_32
1981 * function to set the IO-APIC physical IDs based on the
1982 * values stored in the MPC table.
1984 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1987 static void __init
setup_ioapic_ids_from_mpc(void)
1989 union IO_APIC_reg_00 reg_00
;
1990 physid_mask_t phys_id_present_map
;
1993 unsigned char old_id
;
1994 unsigned long flags
;
1996 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2000 * Don't check I/O APIC IDs for xAPIC systems. They have
2001 * no meaning without the serial APIC bus.
2003 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2004 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2007 * This is broken; anything with a real cpu count has to
2008 * circumvent this idiocy regardless.
2010 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2013 * Set the IOAPIC ID to the value stored in the MPC table.
2015 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2017 /* Read the register 0 value */
2018 spin_lock_irqsave(&ioapic_lock
, flags
);
2019 reg_00
.raw
= io_apic_read(apic
, 0);
2020 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2022 old_id
= mp_ioapics
[apic
].mp_apicid
;
2024 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
2025 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2026 apic
, mp_ioapics
[apic
].mp_apicid
);
2027 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2029 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
2033 * Sanity check, is the ID really free? Every APIC in a
2034 * system must have a unique ID or we get lots of nice
2035 * 'stuck on smp_invalidate_needed IPI wait' messages.
2037 if (check_apicid_used(phys_id_present_map
,
2038 mp_ioapics
[apic
].mp_apicid
)) {
2039 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2040 apic
, mp_ioapics
[apic
].mp_apicid
);
2041 for (i
= 0; i
< get_physical_broadcast(); i
++)
2042 if (!physid_isset(i
, phys_id_present_map
))
2044 if (i
>= get_physical_broadcast())
2045 panic("Max APIC ID exceeded!\n");
2046 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2048 physid_set(i
, phys_id_present_map
);
2049 mp_ioapics
[apic
].mp_apicid
= i
;
2052 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2053 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2054 "phys_id_present_map\n",
2055 mp_ioapics
[apic
].mp_apicid
);
2056 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2061 * We need to adjust the IRQ routing table
2062 * if the ID changed.
2064 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2065 for (i
= 0; i
< mp_irq_entries
; i
++)
2066 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2067 mp_irqs
[i
].mp_dstapic
2068 = mp_ioapics
[apic
].mp_apicid
;
2071 * Read the right value from the MPC table and
2072 * write it into the ID register.
2074 apic_printk(APIC_VERBOSE
, KERN_INFO
2075 "...changing IO-APIC physical APIC ID to %d ...",
2076 mp_ioapics
[apic
].mp_apicid
);
2078 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2079 spin_lock_irqsave(&ioapic_lock
, flags
);
2080 io_apic_write(apic
, 0, reg_00
.raw
);
2081 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2086 spin_lock_irqsave(&ioapic_lock
, flags
);
2087 reg_00
.raw
= io_apic_read(apic
, 0);
2088 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2089 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2090 printk("could not set ID!\n");
2092 apic_printk(APIC_VERBOSE
, " ok.\n");
2097 int no_timer_check __initdata
;
2099 static int __init
notimercheck(char *s
)
2104 __setup("no_timer_check", notimercheck
);
2107 * There is a nasty bug in some older SMP boards, their mptable lies
2108 * about the timer IRQ. We do the following to work around the situation:
2110 * - timer IRQ defaults to IO-APIC IRQ
2111 * - if this function detects that timer IRQs are defunct, then we fall
2112 * back to ISA timer IRQs
2114 static int __init
timer_irq_works(void)
2116 unsigned long t1
= jiffies
;
2117 unsigned long flags
;
2122 local_save_flags(flags
);
2124 /* Let ten ticks pass... */
2125 mdelay((10 * 1000) / HZ
);
2126 local_irq_restore(flags
);
2129 * Expect a few ticks at least, to be sure some possible
2130 * glue logic does not lock up after one or two first
2131 * ticks in a non-ExtINT mode. Also the local APIC
2132 * might have cached one ExtINT interrupt. Finally, at
2133 * least one tick may be lost due to delays.
2137 if (time_after(jiffies
, t1
+ 4))
2143 * In the SMP+IOAPIC case it might happen that there are an unspecified
2144 * number of pending IRQ events unhandled. These cases are very rare,
2145 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2146 * better to do it this way as thus we do not have to be aware of
2147 * 'pending' interrupts in the IRQ path, except at this point.
2150 * Edge triggered needs to resend any interrupt
2151 * that was delayed but this is now handled in the device
2156 * Starting up a edge-triggered IO-APIC interrupt is
2157 * nasty - we need to make sure that we get the edge.
2158 * If it is already asserted for some reason, we need
2159 * return 1 to indicate that is was pending.
2161 * This is not complete - we should be able to fake
2162 * an edge even if it isn't on the 8259A...
2165 static unsigned int startup_ioapic_irq(unsigned int irq
)
2167 int was_pending
= 0;
2168 unsigned long flags
;
2170 spin_lock_irqsave(&ioapic_lock
, flags
);
2172 disable_8259A_irq(irq
);
2173 if (i8259A_irq_pending(irq
))
2176 __unmask_IO_APIC_irq(irq
);
2177 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2182 #ifdef CONFIG_X86_64
2183 static int ioapic_retrigger_irq(unsigned int irq
)
2186 struct irq_cfg
*cfg
= irq_cfg(irq
);
2187 unsigned long flags
;
2189 spin_lock_irqsave(&vector_lock
, flags
);
2190 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
2191 spin_unlock_irqrestore(&vector_lock
, flags
);
2196 static int ioapic_retrigger_irq(unsigned int irq
)
2198 send_IPI_self(irq_cfg(irq
)->vector
);
2205 * Level and edge triggered IO-APIC interrupts need different handling,
2206 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2207 * handled with the level-triggered descriptor, but that one has slightly
2208 * more overhead. Level-triggered interrupts cannot be handled with the
2209 * edge-triggered handler, without risking IRQ storms and other ugly
2215 #ifdef CONFIG_INTR_REMAP
2216 static void ir_irq_migration(struct work_struct
*work
);
2218 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2221 * Migrate the IO-APIC irq in the presence of intr-remapping.
2223 * For edge triggered, irq migration is a simple atomic update(of vector
2224 * and cpu destination) of IRTE and flush the hardware cache.
2226 * For level triggered, we need to modify the io-apic RTE aswell with the update
2227 * vector information, along with modifying IRTE with vector and destination.
2228 * So irq migration for level triggered is little bit more complex compared to
2229 * edge triggered migration. But the good news is, we use the same algorithm
2230 * for level triggered migration as we have today, only difference being,
2231 * we now initiate the irq migration from process context instead of the
2232 * interrupt context.
2234 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2235 * suppression) to the IO-APIC, level triggered irq migration will also be
2236 * as simple as edge triggered migration and we can do the irq migration
2237 * with a simple atomic update to IO-APIC RTE.
2239 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
2241 struct irq_cfg
*cfg
;
2242 struct irq_desc
*desc
;
2243 cpumask_t tmp
, cleanup_mask
;
2245 int modify_ioapic_rte
;
2247 unsigned long flags
;
2249 cpus_and(tmp
, mask
, cpu_online_map
);
2250 if (cpus_empty(tmp
))
2253 if (get_irte(irq
, &irte
))
2256 if (assign_irq_vector(irq
, mask
))
2260 cpus_and(tmp
, cfg
->domain
, mask
);
2261 dest
= cpu_mask_to_apicid(tmp
);
2263 desc
= irq_to_desc(irq
);
2264 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2265 if (modify_ioapic_rte
) {
2266 spin_lock_irqsave(&ioapic_lock
, flags
);
2267 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
2268 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2271 irte
.vector
= cfg
->vector
;
2272 irte
.dest_id
= IRTE_DEST(dest
);
2275 * Modified the IRTE and flushes the Interrupt entry cache.
2277 modify_irte(irq
, &irte
);
2279 if (cfg
->move_in_progress
) {
2280 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2281 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2282 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2283 cfg
->move_in_progress
= 0;
2286 desc
->affinity
= mask
;
2289 static int migrate_irq_remapped_level(int irq
)
2292 struct irq_desc
*desc
= irq_to_desc(irq
);
2294 mask_IO_APIC_irq(irq
);
2296 if (io_apic_level_ack_pending(irq
)) {
2298 * Interrupt in progress. Migrating irq now will change the
2299 * vector information in the IO-APIC RTE and that will confuse
2300 * the EOI broadcast performed by cpu.
2301 * So, delay the irq migration to the next instance.
2303 schedule_delayed_work(&ir_migration_work
, 1);
2307 /* everthing is clear. we have right of way */
2308 migrate_ioapic_irq(irq
, desc
->pending_mask
);
2311 desc
->status
&= ~IRQ_MOVE_PENDING
;
2312 cpus_clear(desc
->pending_mask
);
2315 unmask_IO_APIC_irq(irq
);
2319 static void ir_irq_migration(struct work_struct
*work
)
2322 struct irq_desc
*desc
;
2324 for_each_irq_desc(irq
, desc
) {
2325 if (desc
->status
& IRQ_MOVE_PENDING
) {
2326 unsigned long flags
;
2328 spin_lock_irqsave(&desc
->lock
, flags
);
2329 if (!desc
->chip
->set_affinity
||
2330 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2331 desc
->status
&= ~IRQ_MOVE_PENDING
;
2332 spin_unlock_irqrestore(&desc
->lock
, flags
);
2336 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
2337 spin_unlock_irqrestore(&desc
->lock
, flags
);
2343 * Migrates the IRQ destination in the process context.
2345 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
2347 struct irq_desc
*desc
= irq_to_desc(irq
);
2349 if (desc
->status
& IRQ_LEVEL
) {
2350 desc
->status
|= IRQ_MOVE_PENDING
;
2351 desc
->pending_mask
= mask
;
2352 migrate_irq_remapped_level(irq
);
2356 migrate_ioapic_irq(irq
, mask
);
2360 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2362 unsigned vector
, me
;
2364 #ifdef CONFIG_X86_64
2369 me
= smp_processor_id();
2370 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2372 struct irq_desc
*desc
;
2373 struct irq_cfg
*cfg
;
2374 irq
= __get_cpu_var(vector_irq
)[vector
];
2376 desc
= irq_to_desc(irq
);
2381 spin_lock(&desc
->lock
);
2382 if (!cfg
->move_cleanup_count
)
2385 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
2388 __get_cpu_var(vector_irq
)[vector
] = -1;
2389 cfg
->move_cleanup_count
--;
2391 spin_unlock(&desc
->lock
);
2397 static void irq_complete_move(unsigned int irq
)
2399 struct irq_cfg
*cfg
= irq_cfg(irq
);
2400 unsigned vector
, me
;
2402 if (likely(!cfg
->move_in_progress
))
2405 vector
= ~get_irq_regs()->orig_ax
;
2406 me
= smp_processor_id();
2407 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
2408 cpumask_t cleanup_mask
;
2410 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2411 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2412 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2413 cfg
->move_in_progress
= 0;
2417 static inline void irq_complete_move(unsigned int irq
) {}
2419 #ifdef CONFIG_INTR_REMAP
2420 static void ack_x2apic_level(unsigned int irq
)
2425 static void ack_x2apic_edge(unsigned int irq
)
2431 static void ack_apic_edge(unsigned int irq
)
2433 irq_complete_move(irq
);
2434 move_native_irq(irq
);
2438 #ifdef CONFIG_X86_32
2439 atomic_t irq_mis_count
;
2442 static void ack_apic_level(unsigned int irq
)
2444 #ifdef CONFIG_X86_32
2448 int do_unmask_irq
= 0;
2450 irq_complete_move(irq
);
2451 #ifdef CONFIG_GENERIC_PENDING_IRQ
2452 /* If we are moving the irq we need to mask it */
2453 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2455 mask_IO_APIC_irq(irq
);
2459 #ifdef CONFIG_X86_32
2461 * It appears there is an erratum which affects at least version 0x11
2462 * of I/O APIC (that's the 82093AA and cores integrated into various
2463 * chipsets). Under certain conditions a level-triggered interrupt is
2464 * erroneously delivered as edge-triggered one but the respective IRR
2465 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2466 * message but it will never arrive and further interrupts are blocked
2467 * from the source. The exact reason is so far unknown, but the
2468 * phenomenon was observed when two consecutive interrupt requests
2469 * from a given source get delivered to the same CPU and the source is
2470 * temporarily disabled in between.
2472 * A workaround is to simulate an EOI message manually. We achieve it
2473 * by setting the trigger mode to edge and then to level when the edge
2474 * trigger mode gets detected in the TMR of a local APIC for a
2475 * level-triggered interrupt. We mask the source for the time of the
2476 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2477 * The idea is from Manfred Spraul. --macro
2479 i
= irq_cfg(irq
)->vector
;
2481 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2485 * We must acknowledge the irq before we move it or the acknowledge will
2486 * not propagate properly.
2490 /* Now we can move and renable the irq */
2491 if (unlikely(do_unmask_irq
)) {
2492 /* Only migrate the irq if the ack has been received.
2494 * On rare occasions the broadcast level triggered ack gets
2495 * delayed going to ioapics, and if we reprogram the
2496 * vector while Remote IRR is still set the irq will never
2499 * To prevent this scenario we read the Remote IRR bit
2500 * of the ioapic. This has two effects.
2501 * - On any sane system the read of the ioapic will
2502 * flush writes (and acks) going to the ioapic from
2504 * - We get to see if the ACK has actually been delivered.
2506 * Based on failed experiments of reprogramming the
2507 * ioapic entry from outside of irq context starting
2508 * with masking the ioapic entry and then polling until
2509 * Remote IRR was clear before reprogramming the
2510 * ioapic I don't trust the Remote IRR bit to be
2511 * completey accurate.
2513 * However there appears to be no other way to plug
2514 * this race, so if the Remote IRR bit is not
2515 * accurate and is causing problems then it is a hardware bug
2516 * and you can go talk to the chipset vendor about it.
2518 if (!io_apic_level_ack_pending(irq
))
2519 move_masked_irq(irq
);
2520 unmask_IO_APIC_irq(irq
);
2523 #ifdef CONFIG_X86_32
2524 if (!(v
& (1 << (i
& 0x1f)))) {
2525 atomic_inc(&irq_mis_count
);
2526 spin_lock(&ioapic_lock
);
2527 __mask_and_edge_IO_APIC_irq(irq
);
2528 __unmask_and_level_IO_APIC_irq(irq
);
2529 spin_unlock(&ioapic_lock
);
2534 static struct irq_chip ioapic_chip __read_mostly
= {
2536 .startup
= startup_ioapic_irq
,
2537 .mask
= mask_IO_APIC_irq
,
2538 .unmask
= unmask_IO_APIC_irq
,
2539 .ack
= ack_apic_edge
,
2540 .eoi
= ack_apic_level
,
2542 .set_affinity
= set_ioapic_affinity_irq
,
2544 .retrigger
= ioapic_retrigger_irq
,
2547 #ifdef CONFIG_INTR_REMAP
2548 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2549 .name
= "IR-IO-APIC",
2550 .startup
= startup_ioapic_irq
,
2551 .mask
= mask_IO_APIC_irq
,
2552 .unmask
= unmask_IO_APIC_irq
,
2553 .ack
= ack_x2apic_edge
,
2554 .eoi
= ack_x2apic_level
,
2556 .set_affinity
= set_ir_ioapic_affinity_irq
,
2558 .retrigger
= ioapic_retrigger_irq
,
2562 static inline void init_IO_APIC_traps(void)
2565 struct irq_desc
*desc
;
2566 struct irq_cfg
*cfg
;
2569 * NOTE! The local APIC isn't very good at handling
2570 * multiple interrupts at the same interrupt level.
2571 * As the interrupt level is determined by taking the
2572 * vector number and shifting that right by 4, we
2573 * want to spread these out a bit so that they don't
2574 * all fall in the same interrupt level.
2576 * Also, we've got to be careful not to trash gate
2577 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2579 for_each_irq_cfg(irq
, cfg
) {
2580 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2582 * Hmm.. We don't have an entry for this,
2583 * so default to an old-fashioned 8259
2584 * interrupt if we can..
2587 make_8259A_irq(irq
);
2589 desc
= irq_to_desc(irq
);
2590 /* Strange. Oh, well.. */
2591 desc
->chip
= &no_irq_chip
;
2598 * The local APIC irq-chip implementation:
2601 static void mask_lapic_irq(unsigned int irq
)
2605 v
= apic_read(APIC_LVT0
);
2606 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2609 static void unmask_lapic_irq(unsigned int irq
)
2613 v
= apic_read(APIC_LVT0
);
2614 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2617 static void ack_lapic_irq (unsigned int irq
)
2622 static struct irq_chip lapic_chip __read_mostly
= {
2623 .name
= "local-APIC",
2624 .mask
= mask_lapic_irq
,
2625 .unmask
= unmask_lapic_irq
,
2626 .ack
= ack_lapic_irq
,
2629 static void lapic_register_intr(int irq
)
2631 struct irq_desc
*desc
;
2633 desc
= irq_to_desc(irq
);
2634 desc
->status
&= ~IRQ_LEVEL
;
2635 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2639 static void __init
setup_nmi(void)
2642 * Dirty trick to enable the NMI watchdog ...
2643 * We put the 8259A master into AEOI mode and
2644 * unmask on all local APICs LVT0 as NMI.
2646 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2647 * is from Maciej W. Rozycki - so we do not have to EOI from
2648 * the NMI handler or the timer interrupt.
2650 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2652 enable_NMI_through_LVT0();
2654 apic_printk(APIC_VERBOSE
, " done.\n");
2658 * This looks a bit hackish but it's about the only one way of sending
2659 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2660 * not support the ExtINT mode, unfortunately. We need to send these
2661 * cycles as some i82489DX-based boards have glue logic that keeps the
2662 * 8259A interrupt line asserted until INTA. --macro
2664 static inline void __init
unlock_ExtINT_logic(void)
2667 struct IO_APIC_route_entry entry0
, entry1
;
2668 unsigned char save_control
, save_freq_select
;
2670 pin
= find_isa_irq_pin(8, mp_INT
);
2675 apic
= find_isa_irq_apic(8, mp_INT
);
2681 entry0
= ioapic_read_entry(apic
, pin
);
2682 clear_IO_APIC_pin(apic
, pin
);
2684 memset(&entry1
, 0, sizeof(entry1
));
2686 entry1
.dest_mode
= 0; /* physical delivery */
2687 entry1
.mask
= 0; /* unmask IRQ now */
2688 entry1
.dest
= hard_smp_processor_id();
2689 entry1
.delivery_mode
= dest_ExtINT
;
2690 entry1
.polarity
= entry0
.polarity
;
2694 ioapic_write_entry(apic
, pin
, entry1
);
2696 save_control
= CMOS_READ(RTC_CONTROL
);
2697 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2698 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2700 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2705 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2709 CMOS_WRITE(save_control
, RTC_CONTROL
);
2710 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2711 clear_IO_APIC_pin(apic
, pin
);
2713 ioapic_write_entry(apic
, pin
, entry0
);
2716 static int disable_timer_pin_1 __initdata
;
2717 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2718 static int __init
disable_timer_pin_setup(char *arg
)
2720 disable_timer_pin_1
= 1;
2723 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2725 int timer_through_8259 __initdata
;
2728 * This code may look a bit paranoid, but it's supposed to cooperate with
2729 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2730 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2731 * fanatically on his truly buggy board.
2733 * FIXME: really need to revamp this for all platforms.
2735 static inline void __init
check_timer(void)
2737 struct irq_cfg
*cfg
= irq_cfg(0);
2738 int apic1
, pin1
, apic2
, pin2
;
2739 unsigned long flags
;
2743 local_irq_save(flags
);
2745 ver
= apic_read(APIC_LVR
);
2746 ver
= GET_APIC_VERSION(ver
);
2749 * get/set the timer IRQ vector:
2751 disable_8259A_irq(0);
2752 assign_irq_vector(0, TARGET_CPUS
);
2755 * As IRQ0 is to be enabled in the 8259A, the virtual
2756 * wire has to be disabled in the local APIC. Also
2757 * timer interrupts need to be acknowledged manually in
2758 * the 8259A for the i82489DX when using the NMI
2759 * watchdog as that APIC treats NMIs as level-triggered.
2760 * The AEOI mode will finish them in the 8259A
2763 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2765 #ifdef CONFIG_X86_32
2766 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2769 pin1
= find_isa_irq_pin(0, mp_INT
);
2770 apic1
= find_isa_irq_apic(0, mp_INT
);
2771 pin2
= ioapic_i8259
.pin
;
2772 apic2
= ioapic_i8259
.apic
;
2774 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2775 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2776 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2779 * Some BIOS writers are clueless and report the ExtINTA
2780 * I/O APIC input from the cascaded 8259A as the timer
2781 * interrupt input. So just in case, if only one pin
2782 * was found above, try it both directly and through the
2786 #ifdef CONFIG_INTR_REMAP
2787 if (intr_remapping_enabled
)
2788 panic("BIOS bug: timer not connected to IO-APIC");
2793 } else if (pin2
== -1) {
2800 * Ok, does IRQ0 through the IOAPIC work?
2803 add_pin_to_irq(0, apic1
, pin1
);
2804 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2806 unmask_IO_APIC_irq(0);
2807 if (timer_irq_works()) {
2808 if (nmi_watchdog
== NMI_IO_APIC
) {
2810 enable_8259A_irq(0);
2812 if (disable_timer_pin_1
> 0)
2813 clear_IO_APIC_pin(0, pin1
);
2816 #ifdef CONFIG_INTR_REMAP
2817 if (intr_remapping_enabled
)
2818 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2820 clear_IO_APIC_pin(apic1
, pin1
);
2822 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2823 "8254 timer not connected to IO-APIC\n");
2825 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2826 "(IRQ0) through the 8259A ...\n");
2827 apic_printk(APIC_QUIET
, KERN_INFO
2828 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2830 * legacy devices should be connected to IO APIC #0
2832 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2833 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2834 unmask_IO_APIC_irq(0);
2835 enable_8259A_irq(0);
2836 if (timer_irq_works()) {
2837 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2838 timer_through_8259
= 1;
2839 if (nmi_watchdog
== NMI_IO_APIC
) {
2840 disable_8259A_irq(0);
2842 enable_8259A_irq(0);
2847 * Cleanup, just in case ...
2849 disable_8259A_irq(0);
2850 clear_IO_APIC_pin(apic2
, pin2
);
2851 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2854 if (nmi_watchdog
== NMI_IO_APIC
) {
2855 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2856 "through the IO-APIC - disabling NMI Watchdog!\n");
2857 nmi_watchdog
= NMI_NONE
;
2859 #ifdef CONFIG_X86_32
2863 apic_printk(APIC_QUIET
, KERN_INFO
2864 "...trying to set up timer as Virtual Wire IRQ...\n");
2866 lapic_register_intr(0);
2867 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2868 enable_8259A_irq(0);
2870 if (timer_irq_works()) {
2871 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2874 disable_8259A_irq(0);
2875 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2876 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2878 apic_printk(APIC_QUIET
, KERN_INFO
2879 "...trying to set up timer as ExtINT IRQ...\n");
2883 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2885 unlock_ExtINT_logic();
2887 if (timer_irq_works()) {
2888 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2891 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2892 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2893 "report. Then try booting with the 'noapic' option.\n");
2895 local_irq_restore(flags
);
2899 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2900 * to devices. However there may be an I/O APIC pin available for
2901 * this interrupt regardless. The pin may be left unconnected, but
2902 * typically it will be reused as an ExtINT cascade interrupt for
2903 * the master 8259A. In the MPS case such a pin will normally be
2904 * reported as an ExtINT interrupt in the MP table. With ACPI
2905 * there is no provision for ExtINT interrupts, and in the absence
2906 * of an override it would be treated as an ordinary ISA I/O APIC
2907 * interrupt, that is edge-triggered and unmasked by default. We
2908 * used to do this, but it caused problems on some systems because
2909 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2910 * the same ExtINT cascade interrupt to drive the local APIC of the
2911 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2912 * the I/O APIC in all cases now. No actual device should request
2913 * it anyway. --macro
2915 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2917 void __init
setup_IO_APIC(void)
2920 #ifdef CONFIG_X86_32
2924 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2928 io_apic_irqs
= ~PIC_IRQS
;
2930 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2932 * Set up IO-APIC IRQ routing.
2934 #ifdef CONFIG_X86_32
2936 setup_ioapic_ids_from_mpc();
2939 setup_IO_APIC_irqs();
2940 init_IO_APIC_traps();
2945 * Called after all the initialization is done. If we didnt find any
2946 * APIC bugs then we can allow the modify fast path
2949 static int __init
io_apic_bug_finalize(void)
2951 if (sis_apic_bug
== -1)
2956 late_initcall(io_apic_bug_finalize
);
2958 struct sysfs_ioapic_data
{
2959 struct sys_device dev
;
2960 struct IO_APIC_route_entry entry
[0];
2962 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2964 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2966 struct IO_APIC_route_entry
*entry
;
2967 struct sysfs_ioapic_data
*data
;
2970 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2971 entry
= data
->entry
;
2972 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2973 *entry
= ioapic_read_entry(dev
->id
, i
);
2978 static int ioapic_resume(struct sys_device
*dev
)
2980 struct IO_APIC_route_entry
*entry
;
2981 struct sysfs_ioapic_data
*data
;
2982 unsigned long flags
;
2983 union IO_APIC_reg_00 reg_00
;
2986 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2987 entry
= data
->entry
;
2989 spin_lock_irqsave(&ioapic_lock
, flags
);
2990 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2991 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2992 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2993 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2995 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2996 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2997 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3002 static struct sysdev_class ioapic_sysdev_class
= {
3004 .suspend
= ioapic_suspend
,
3005 .resume
= ioapic_resume
,
3008 static int __init
ioapic_init_sysfs(void)
3010 struct sys_device
* dev
;
3013 error
= sysdev_class_register(&ioapic_sysdev_class
);
3017 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3018 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3019 * sizeof(struct IO_APIC_route_entry
);
3020 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3021 if (!mp_ioapic_data
[i
]) {
3022 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3025 dev
= &mp_ioapic_data
[i
]->dev
;
3027 dev
->cls
= &ioapic_sysdev_class
;
3028 error
= sysdev_register(dev
);
3030 kfree(mp_ioapic_data
[i
]);
3031 mp_ioapic_data
[i
] = NULL
;
3032 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3040 device_initcall(ioapic_init_sysfs
);
3043 * Dynamic irq allocate and deallocation
3045 unsigned int create_irq_nr(unsigned int irq_want
)
3047 /* Allocate an unused irq */
3050 unsigned long flags
;
3051 struct irq_cfg
*cfg_new
;
3053 #ifndef CONFIG_HAVE_SPARSE_IRQ
3054 irq_want
= nr_irqs
- 1;
3058 spin_lock_irqsave(&vector_lock
, flags
);
3059 for (new = irq_want
; new > 0; new--) {
3060 if (platform_legacy_irq(new))
3062 cfg_new
= irq_cfg(new);
3063 if (cfg_new
&& cfg_new
->vector
!= 0)
3065 /* check if need to create one */
3067 cfg_new
= irq_cfg_alloc(new);
3068 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
3072 spin_unlock_irqrestore(&vector_lock
, flags
);
3075 dynamic_irq_init(irq
);
3080 int create_irq(void)
3084 irq
= create_irq_nr(nr_irqs
- 1);
3092 void destroy_irq(unsigned int irq
)
3094 unsigned long flags
;
3096 dynamic_irq_cleanup(irq
);
3098 #ifdef CONFIG_INTR_REMAP
3101 spin_lock_irqsave(&vector_lock
, flags
);
3102 __clear_irq_vector(irq
);
3103 spin_unlock_irqrestore(&vector_lock
, flags
);
3107 * MSI message composition
3109 #ifdef CONFIG_PCI_MSI
3110 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3112 struct irq_cfg
*cfg
;
3118 err
= assign_irq_vector(irq
, tmp
);
3123 cpus_and(tmp
, cfg
->domain
, tmp
);
3124 dest
= cpu_mask_to_apicid(tmp
);
3126 #ifdef CONFIG_INTR_REMAP
3127 if (irq_remapped(irq
)) {
3132 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3133 BUG_ON(ir_index
== -1);
3135 memset (&irte
, 0, sizeof(irte
));
3138 irte
.dst_mode
= INT_DEST_MODE
;
3139 irte
.trigger_mode
= 0; /* edge */
3140 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3141 irte
.vector
= cfg
->vector
;
3142 irte
.dest_id
= IRTE_DEST(dest
);
3144 modify_irte(irq
, &irte
);
3146 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3147 msg
->data
= sub_handle
;
3148 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3150 MSI_ADDR_IR_INDEX1(ir_index
) |
3151 MSI_ADDR_IR_INDEX2(ir_index
);
3155 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3158 ((INT_DEST_MODE
== 0) ?
3159 MSI_ADDR_DEST_MODE_PHYSICAL
:
3160 MSI_ADDR_DEST_MODE_LOGICAL
) |
3161 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3162 MSI_ADDR_REDIRECTION_CPU
:
3163 MSI_ADDR_REDIRECTION_LOWPRI
) |
3164 MSI_ADDR_DEST_ID(dest
);
3167 MSI_DATA_TRIGGER_EDGE
|
3168 MSI_DATA_LEVEL_ASSERT
|
3169 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3170 MSI_DATA_DELIVERY_FIXED
:
3171 MSI_DATA_DELIVERY_LOWPRI
) |
3172 MSI_DATA_VECTOR(cfg
->vector
);
3178 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3180 struct irq_cfg
*cfg
;
3184 struct irq_desc
*desc
;
3186 cpus_and(tmp
, mask
, cpu_online_map
);
3187 if (cpus_empty(tmp
))
3190 if (assign_irq_vector(irq
, mask
))
3194 cpus_and(tmp
, cfg
->domain
, mask
);
3195 dest
= cpu_mask_to_apicid(tmp
);
3197 read_msi_msg(irq
, &msg
);
3199 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3200 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3201 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3202 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3204 write_msi_msg(irq
, &msg
);
3205 desc
= irq_to_desc(irq
);
3206 desc
->affinity
= mask
;
3209 #ifdef CONFIG_INTR_REMAP
3211 * Migrate the MSI irq to another cpumask. This migration is
3212 * done in the process context using interrupt-remapping hardware.
3214 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3216 struct irq_cfg
*cfg
;
3218 cpumask_t tmp
, cleanup_mask
;
3220 struct irq_desc
*desc
;
3222 cpus_and(tmp
, mask
, cpu_online_map
);
3223 if (cpus_empty(tmp
))
3226 if (get_irte(irq
, &irte
))
3229 if (assign_irq_vector(irq
, mask
))
3233 cpus_and(tmp
, cfg
->domain
, mask
);
3234 dest
= cpu_mask_to_apicid(tmp
);
3236 irte
.vector
= cfg
->vector
;
3237 irte
.dest_id
= IRTE_DEST(dest
);
3240 * atomically update the IRTE with the new destination and vector.
3242 modify_irte(irq
, &irte
);
3245 * After this point, all the interrupts will start arriving
3246 * at the new destination. So, time to cleanup the previous
3247 * vector allocation.
3249 if (cfg
->move_in_progress
) {
3250 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
3251 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
3252 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
3253 cfg
->move_in_progress
= 0;
3256 desc
= irq_to_desc(irq
);
3257 desc
->affinity
= mask
;
3260 #endif /* CONFIG_SMP */
3263 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3264 * which implement the MSI or MSI-X Capability Structure.
3266 static struct irq_chip msi_chip
= {
3268 .unmask
= unmask_msi_irq
,
3269 .mask
= mask_msi_irq
,
3270 .ack
= ack_apic_edge
,
3272 .set_affinity
= set_msi_irq_affinity
,
3274 .retrigger
= ioapic_retrigger_irq
,
3277 #ifdef CONFIG_INTR_REMAP
3278 static struct irq_chip msi_ir_chip
= {
3279 .name
= "IR-PCI-MSI",
3280 .unmask
= unmask_msi_irq
,
3281 .mask
= mask_msi_irq
,
3282 .ack
= ack_x2apic_edge
,
3284 .set_affinity
= ir_set_msi_irq_affinity
,
3286 .retrigger
= ioapic_retrigger_irq
,
3290 * Map the PCI dev to the corresponding remapping hardware unit
3291 * and allocate 'nvec' consecutive interrupt-remapping table entries
3294 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3296 struct intel_iommu
*iommu
;
3299 iommu
= map_dev_to_ir(dev
);
3302 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3306 index
= alloc_irte(iommu
, irq
, nvec
);
3309 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3317 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
3322 ret
= msi_compose_msg(dev
, irq
, &msg
);
3326 set_irq_msi(irq
, desc
);
3327 write_msi_msg(irq
, &msg
);
3329 #ifdef CONFIG_INTR_REMAP
3330 if (irq_remapped(irq
)) {
3331 struct irq_desc
*desc
= irq_to_desc(irq
);
3333 * irq migration in process context
3335 desc
->status
|= IRQ_MOVE_PCNTXT
;
3336 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3339 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3344 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
3348 irq
= dev
->bus
->number
;
3356 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
3360 unsigned int irq_want
;
3362 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3364 irq
= create_irq_nr(irq_want
);
3368 #ifdef CONFIG_INTR_REMAP
3369 if (!intr_remapping_enabled
)
3372 ret
= msi_alloc_irte(dev
, irq
, 1);
3377 ret
= setup_msi_irq(dev
, desc
, irq
);
3384 #ifdef CONFIG_INTR_REMAP
3391 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3394 int ret
, sub_handle
;
3395 struct msi_desc
*desc
;
3396 unsigned int irq_want
;
3398 #ifdef CONFIG_INTR_REMAP
3399 struct intel_iommu
*iommu
= 0;
3403 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3405 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
3406 irq
= create_irq_nr(irq_want
--);
3409 #ifdef CONFIG_INTR_REMAP
3410 if (!intr_remapping_enabled
)
3415 * allocate the consecutive block of IRTE's
3418 index
= msi_alloc_irte(dev
, irq
, nvec
);
3424 iommu
= map_dev_to_ir(dev
);
3430 * setup the mapping between the irq and the IRTE
3431 * base index, the sub_handle pointing to the
3432 * appropriate interrupt remap table entry.
3434 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3438 ret
= setup_msi_irq(dev
, desc
, irq
);
3450 void arch_teardown_msi_irq(unsigned int irq
)
3457 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
3459 struct irq_cfg
*cfg
;
3463 struct irq_desc
*desc
;
3465 cpus_and(tmp
, mask
, cpu_online_map
);
3466 if (cpus_empty(tmp
))
3469 if (assign_irq_vector(irq
, mask
))
3473 cpus_and(tmp
, cfg
->domain
, mask
);
3474 dest
= cpu_mask_to_apicid(tmp
);
3476 dmar_msi_read(irq
, &msg
);
3478 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3479 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3480 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3481 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3483 dmar_msi_write(irq
, &msg
);
3484 desc
= irq_to_desc(irq
);
3485 desc
->affinity
= mask
;
3487 #endif /* CONFIG_SMP */
3489 struct irq_chip dmar_msi_type
= {
3491 .unmask
= dmar_msi_unmask
,
3492 .mask
= dmar_msi_mask
,
3493 .ack
= ack_apic_edge
,
3495 .set_affinity
= dmar_msi_set_affinity
,
3497 .retrigger
= ioapic_retrigger_irq
,
3500 int arch_setup_dmar_msi(unsigned int irq
)
3505 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3508 dmar_msi_write(irq
, &msg
);
3509 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3515 #endif /* CONFIG_PCI_MSI */
3517 * Hypertransport interrupt support
3519 #ifdef CONFIG_HT_IRQ
3523 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3525 struct ht_irq_msg msg
;
3526 fetch_ht_irq_msg(irq
, &msg
);
3528 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3529 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3531 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3532 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3534 write_ht_irq_msg(irq
, &msg
);
3537 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
3539 struct irq_cfg
*cfg
;
3542 struct irq_desc
*desc
;
3544 cpus_and(tmp
, mask
, cpu_online_map
);
3545 if (cpus_empty(tmp
))
3548 if (assign_irq_vector(irq
, mask
))
3552 cpus_and(tmp
, cfg
->domain
, mask
);
3553 dest
= cpu_mask_to_apicid(tmp
);
3555 target_ht_irq(irq
, dest
, cfg
->vector
);
3556 desc
= irq_to_desc(irq
);
3557 desc
->affinity
= mask
;
3561 static struct irq_chip ht_irq_chip
= {
3563 .mask
= mask_ht_irq
,
3564 .unmask
= unmask_ht_irq
,
3565 .ack
= ack_apic_edge
,
3567 .set_affinity
= set_ht_irq_affinity
,
3569 .retrigger
= ioapic_retrigger_irq
,
3572 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3574 struct irq_cfg
*cfg
;
3579 err
= assign_irq_vector(irq
, tmp
);
3581 struct ht_irq_msg msg
;
3585 cpus_and(tmp
, cfg
->domain
, tmp
);
3586 dest
= cpu_mask_to_apicid(tmp
);
3588 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3592 HT_IRQ_LOW_DEST_ID(dest
) |
3593 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3594 ((INT_DEST_MODE
== 0) ?
3595 HT_IRQ_LOW_DM_PHYSICAL
:
3596 HT_IRQ_LOW_DM_LOGICAL
) |
3597 HT_IRQ_LOW_RQEOI_EDGE
|
3598 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3599 HT_IRQ_LOW_MT_FIXED
:
3600 HT_IRQ_LOW_MT_ARBITRATED
) |
3601 HT_IRQ_LOW_IRQ_MASKED
;
3603 write_ht_irq_msg(irq
, &msg
);
3605 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3606 handle_edge_irq
, "edge");
3610 #endif /* CONFIG_HT_IRQ */
3612 int __init
io_apic_get_redir_entries (int ioapic
)
3614 union IO_APIC_reg_01 reg_01
;
3615 unsigned long flags
;
3617 spin_lock_irqsave(&ioapic_lock
, flags
);
3618 reg_01
.raw
= io_apic_read(ioapic
, 1);
3619 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3621 return reg_01
.bits
.entries
;
3624 int __init
probe_nr_irqs(void)
3631 int nr_min
= NR_IRQS
;
3634 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3635 nr
+= io_apic_get_redir_entries(idx
) + 1;
3637 /* double it for hotplug and msi and nmi */
3640 /* something wrong ? */
3647 /* --------------------------------------------------------------------------
3648 ACPI-based IOAPIC Configuration
3649 -------------------------------------------------------------------------- */
3653 #ifdef CONFIG_X86_32
3654 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3656 union IO_APIC_reg_00 reg_00
;
3657 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3659 unsigned long flags
;
3663 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3664 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3665 * supports up to 16 on one shared APIC bus.
3667 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3668 * advantage of new APIC bus architecture.
3671 if (physids_empty(apic_id_map
))
3672 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3674 spin_lock_irqsave(&ioapic_lock
, flags
);
3675 reg_00
.raw
= io_apic_read(ioapic
, 0);
3676 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3678 if (apic_id
>= get_physical_broadcast()) {
3679 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3680 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3681 apic_id
= reg_00
.bits
.ID
;
3685 * Every APIC in a system must have a unique ID or we get lots of nice
3686 * 'stuck on smp_invalidate_needed IPI wait' messages.
3688 if (check_apicid_used(apic_id_map
, apic_id
)) {
3690 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3691 if (!check_apicid_used(apic_id_map
, i
))
3695 if (i
== get_physical_broadcast())
3696 panic("Max apic_id exceeded!\n");
3698 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3699 "trying %d\n", ioapic
, apic_id
, i
);
3704 tmp
= apicid_to_cpu_present(apic_id
);
3705 physids_or(apic_id_map
, apic_id_map
, tmp
);
3707 if (reg_00
.bits
.ID
!= apic_id
) {
3708 reg_00
.bits
.ID
= apic_id
;
3710 spin_lock_irqsave(&ioapic_lock
, flags
);
3711 io_apic_write(ioapic
, 0, reg_00
.raw
);
3712 reg_00
.raw
= io_apic_read(ioapic
, 0);
3713 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3716 if (reg_00
.bits
.ID
!= apic_id
) {
3717 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3722 apic_printk(APIC_VERBOSE
, KERN_INFO
3723 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3728 int __init
io_apic_get_version(int ioapic
)
3730 union IO_APIC_reg_01 reg_01
;
3731 unsigned long flags
;
3733 spin_lock_irqsave(&ioapic_lock
, flags
);
3734 reg_01
.raw
= io_apic_read(ioapic
, 1);
3735 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3737 return reg_01
.bits
.version
;
3741 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3743 if (!IO_APIC_IRQ(irq
)) {
3744 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3750 * IRQs < 16 are already in the irq_2_pin[] map
3753 add_pin_to_irq(irq
, ioapic
, pin
);
3755 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
3761 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3765 if (skip_ioapic_setup
)
3768 for (i
= 0; i
< mp_irq_entries
; i
++)
3769 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3770 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3772 if (i
>= mp_irq_entries
)
3775 *trigger
= irq_trigger(i
);
3776 *polarity
= irq_polarity(i
);
3780 #endif /* CONFIG_ACPI */
3783 * This function currently is only a helper for the i386 smp boot process where
3784 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3785 * so mask in all cases should simply be TARGET_CPUS
3788 void __init
setup_ioapic_dest(void)
3790 int pin
, ioapic
, irq
, irq_entry
;
3791 struct irq_cfg
*cfg
;
3793 if (skip_ioapic_setup
== 1)
3796 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3797 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3798 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3799 if (irq_entry
== -1)
3801 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3803 /* setup_IO_APIC_irqs could fail to get vector for some device
3804 * when you have too many devices, because at that time only boot
3809 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3810 irq_trigger(irq_entry
),
3811 irq_polarity(irq_entry
));
3812 #ifdef CONFIG_INTR_REMAP
3813 else if (intr_remapping_enabled
)
3814 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3817 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3824 #define IOAPIC_RESOURCE_NAME_SIZE 11
3826 static struct resource
*ioapic_resources
;
3828 static struct resource
* __init
ioapic_setup_resources(void)
3831 struct resource
*res
;
3835 if (nr_ioapics
<= 0)
3838 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3841 mem
= alloc_bootmem(n
);
3845 mem
+= sizeof(struct resource
) * nr_ioapics
;
3847 for (i
= 0; i
< nr_ioapics
; i
++) {
3849 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3850 sprintf(mem
, "IOAPIC %u", i
);
3851 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3855 ioapic_resources
= res
;
3860 void __init
ioapic_init_mappings(void)
3862 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3864 struct resource
*ioapic_res
;
3866 ioapic_res
= ioapic_setup_resources();
3867 for (i
= 0; i
< nr_ioapics
; i
++) {
3868 if (smp_found_config
) {
3869 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3870 #ifdef CONFIG_X86_32
3873 "WARNING: bogus zero IO-APIC "
3874 "address found in MPTABLE, "
3875 "disabling IO/APIC support!\n");
3876 smp_found_config
= 0;
3877 skip_ioapic_setup
= 1;
3878 goto fake_ioapic_page
;
3882 #ifdef CONFIG_X86_32
3885 ioapic_phys
= (unsigned long)
3886 alloc_bootmem_pages(PAGE_SIZE
);
3887 ioapic_phys
= __pa(ioapic_phys
);
3889 set_fixmap_nocache(idx
, ioapic_phys
);
3890 apic_printk(APIC_VERBOSE
,
3891 "mapped IOAPIC to %08lx (%08lx)\n",
3892 __fix_to_virt(idx
), ioapic_phys
);
3895 if (ioapic_res
!= NULL
) {
3896 ioapic_res
->start
= ioapic_phys
;
3897 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3903 static int __init
ioapic_insert_resources(void)
3906 struct resource
*r
= ioapic_resources
;
3910 "IO APIC resources could be not be allocated.\n");
3914 for (i
= 0; i
< nr_ioapics
; i
++) {
3915 insert_resource(&iomem_resource
, r
);
3922 /* Insert the IO APIC resources after PCI initialization has occured to handle
3923 * IO APICS that are mapped in on a BAR in PCI space. */
3924 late_initcall(ioapic_insert_resources
);