2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
63 #include <mach_apic.h>
64 #include <mach_apicdef.h>
66 #define __apicdebuginit(type) static type __init
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
72 int sis_apic_bug
= -1;
74 static DEFINE_SPINLOCK(ioapic_lock
);
75 static DEFINE_SPINLOCK(vector_lock
);
78 * # of IRQ routing registers
80 int nr_ioapic_registers
[MAX_IO_APICS
];
82 /* I/O APIC entries */
83 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
86 /* MP IRQ source entries */
87 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
89 /* # of MP IRQ source entries */
92 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
93 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
96 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
98 int skip_ioapic_setup
;
100 static int __init
parse_noapic(char *str
)
102 /* disable IO-APIC */
103 disable_ioapic_setup();
106 early_param("noapic", parse_noapic
);
112 #ifdef CONFIG_HAVE_SPARSE_IRQ
113 struct irq_cfg
*next
;
115 struct irq_pin_list
*irq_2_pin
;
117 cpumask_t old_domain
;
118 unsigned move_cleanup_count
;
120 u8 move_in_progress
: 1;
123 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
124 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
125 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
126 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
127 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
128 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
129 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
130 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
131 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
132 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
133 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
134 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
135 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
136 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
137 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
138 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
139 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
140 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
143 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
145 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
147 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
150 static struct irq_cfg
*irq_cfgx
;
152 #ifdef CONFIG_HAVE_SPARSE_IRQ
154 * Protect the irq_cfgx_free freelist:
156 static DEFINE_SPINLOCK(irq_cfg_lock
);
158 static struct irq_cfg
*irq_cfgx_free
;
161 static void __init
init_work(void *data
)
163 struct dyn_array
*da
= data
;
170 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
172 legacy_count
= ARRAY_SIZE(irq_cfg_legacy
);
173 for (i
= legacy_count
; i
< *da
->nr
; i
++)
174 init_one_irq_cfg(&cfg
[i
]);
176 #ifdef CONFIG_HAVE_SPARSE_IRQ
177 for (i
= 1; i
< *da
->nr
; i
++)
178 cfg
[i
-1].next
= &cfg
[i
];
180 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
181 irq_cfgx
[legacy_count
- 1].next
= NULL
;
185 #ifdef CONFIG_HAVE_SPARSE_IRQ
186 /* need to be biger than size of irq_cfg_legacy */
187 static int nr_irq_cfg
= 32;
189 static int __init
parse_nr_irq_cfg(char *arg
)
192 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
199 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
201 #define for_each_irq_cfg(irqX, cfg) \
202 for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U)
205 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
207 static struct irq_cfg
*irq_cfg(unsigned int irq
)
222 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
224 struct irq_cfg
*cfg
, *cfg_pri
;
229 cfg_pri
= cfg
= irq_cfgx
;
239 spin_lock_irqsave(&irq_cfg_lock
, flags
);
240 if (!irq_cfgx_free
) {
242 unsigned long total_bytes
;
244 * we run out of pre-allocate ones, allocate more
246 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
248 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
250 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
252 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
255 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
258 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
260 for (i
= 0; i
< nr_irq_cfg
; i
++)
261 init_one_irq_cfg(&cfg
[i
]);
263 for (i
= 1; i
< nr_irq_cfg
; i
++)
264 cfg
[i
-1].next
= &cfg
[i
];
270 irq_cfgx_free
= irq_cfgx_free
->next
;
278 spin_unlock_irqrestore(&irq_cfg_lock
, flags
);
284 #define for_each_irq_cfg(irq, cfg) \
285 for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
287 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irqs
, PAGE_SIZE
, init_work
);
289 struct irq_cfg
*irq_cfg(unsigned int irq
)
292 return &irq_cfgx
[irq
];
296 struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
303 * This is performance-critical, we want to do it O(1)
305 * the indexing order of this array favors 1:1 mappings
306 * between pins and IRQs.
309 struct irq_pin_list
{
311 struct irq_pin_list
*next
;
314 static struct irq_pin_list
*irq_2_pin_head
;
315 /* fill one page ? */
316 static int nr_irq_2_pin
= 0x100;
317 static struct irq_pin_list
*irq_2_pin_ptr
;
318 static void __init
irq_2_pin_init_work(void *data
)
320 struct dyn_array
*da
= data
;
321 struct irq_pin_list
*pin
;
326 for (i
= 1; i
< *da
->nr
; i
++)
327 pin
[i
-1].next
= &pin
[i
];
329 irq_2_pin_ptr
= &pin
[0];
331 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
333 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
335 struct irq_pin_list
*pin
;
341 irq_2_pin_ptr
= pin
->next
;
347 * we run out of pre-allocate ones, allocate more
349 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
352 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
355 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
356 nr_irq_2_pin
, PAGE_SIZE
, 0);
359 panic("can not get more irq_2_pin\n");
361 for (i
= 1; i
< nr_irq_2_pin
; i
++)
362 pin
[i
-1].next
= &pin
[i
];
364 irq_2_pin_ptr
= pin
->next
;
372 unsigned int unused
[3];
376 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
378 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
379 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
382 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
384 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
385 writel(reg
, &io_apic
->index
);
386 return readl(&io_apic
->data
);
389 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
391 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
392 writel(reg
, &io_apic
->index
);
393 writel(value
, &io_apic
->data
);
397 * Re-write a value: to be used for read-modify-write
398 * cycles where the read already set up the index register.
400 * Older SiS APIC requires we rewrite the index register
402 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
404 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
406 writel(reg
, &io_apic
->index
);
407 writel(value
, &io_apic
->data
);
410 static bool io_apic_level_ack_pending(unsigned int irq
)
412 struct irq_pin_list
*entry
;
414 struct irq_cfg
*cfg
= irq_cfg(irq
);
416 spin_lock_irqsave(&ioapic_lock
, flags
);
417 entry
= cfg
->irq_2_pin
;
425 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
426 /* Is the remote IRR bit set? */
427 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
428 spin_unlock_irqrestore(&ioapic_lock
, flags
);
435 spin_unlock_irqrestore(&ioapic_lock
, flags
);
441 struct { u32 w1
, w2
; };
442 struct IO_APIC_route_entry entry
;
445 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
447 union entry_union eu
;
449 spin_lock_irqsave(&ioapic_lock
, flags
);
450 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
451 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
452 spin_unlock_irqrestore(&ioapic_lock
, flags
);
457 * When we write a new IO APIC routing entry, we need to write the high
458 * word first! If the mask bit in the low word is clear, we will enable
459 * the interrupt, and we need to make sure the entry is fully populated
460 * before that happens.
463 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
465 union entry_union eu
;
467 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
468 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
471 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
474 spin_lock_irqsave(&ioapic_lock
, flags
);
475 __ioapic_write_entry(apic
, pin
, e
);
476 spin_unlock_irqrestore(&ioapic_lock
, flags
);
480 * When we mask an IO APIC routing entry, we need to write the low
481 * word first, in order to set the mask bit before we change the
484 static void ioapic_mask_entry(int apic
, int pin
)
487 union entry_union eu
= { .entry
.mask
= 1 };
489 spin_lock_irqsave(&ioapic_lock
, flags
);
490 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
491 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
492 spin_unlock_irqrestore(&ioapic_lock
, flags
);
496 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
500 struct irq_pin_list
*entry
;
503 entry
= cfg
->irq_2_pin
;
512 #ifdef CONFIG_INTR_REMAP
514 * With interrupt-remapping, destination information comes
515 * from interrupt-remapping table entry.
517 if (!irq_remapped(irq
))
518 io_apic_write(apic
, 0x11 + pin
*2, dest
);
520 io_apic_write(apic
, 0x11 + pin
*2, dest
);
522 reg
= io_apic_read(apic
, 0x10 + pin
*2);
523 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
525 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
532 static int assign_irq_vector(int irq
, cpumask_t mask
);
534 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
540 struct irq_desc
*desc
;
542 cpus_and(tmp
, mask
, cpu_online_map
);
547 if (assign_irq_vector(irq
, mask
))
550 cpus_and(tmp
, cfg
->domain
, mask
);
551 dest
= cpu_mask_to_apicid(tmp
);
553 * Only the high 8 bits are valid.
555 dest
= SET_APIC_LOGICAL_ID(dest
);
557 desc
= irq_to_desc(irq
);
558 spin_lock_irqsave(&ioapic_lock
, flags
);
559 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
560 desc
->affinity
= mask
;
561 spin_unlock_irqrestore(&ioapic_lock
, flags
);
563 #endif /* CONFIG_SMP */
566 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
567 * shared ISA-space IRQs, so we have to support them. We are super
568 * fast in the common case, and fast for shared ISA-space IRQs.
570 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
573 struct irq_pin_list
*entry
;
575 /* first time to refer irq_cfg, so with new */
576 cfg
= irq_cfg_alloc(irq
);
577 entry
= cfg
->irq_2_pin
;
579 entry
= get_one_free_irq_2_pin();
580 cfg
->irq_2_pin
= entry
;
586 while (entry
->next
) {
587 /* not again, please */
588 if (entry
->apic
== apic
&& entry
->pin
== pin
)
594 entry
->next
= get_one_free_irq_2_pin();
601 * Reroute an IRQ to a different pin.
603 static void __init
replace_pin_at_irq(unsigned int irq
,
604 int oldapic
, int oldpin
,
605 int newapic
, int newpin
)
607 struct irq_cfg
*cfg
= irq_cfg(irq
);
608 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
612 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
613 entry
->apic
= newapic
;
616 /* every one is different, right? */
622 /* why? call replace before add? */
624 add_pin_to_irq(irq
, newapic
, newpin
);
627 static inline void io_apic_modify_irq(unsigned int irq
,
628 int mask_and
, int mask_or
,
629 void (*final
)(struct irq_pin_list
*entry
))
633 struct irq_pin_list
*entry
;
636 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
639 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
642 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
648 static void __unmask_IO_APIC_irq(unsigned int irq
)
650 io_apic_modify_irq(irq
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
654 void io_apic_sync(struct irq_pin_list
*entry
)
657 * Synchronize the IO-APIC and the CPU by doing
658 * a dummy read from the IO-APIC
660 struct io_apic __iomem
*io_apic
;
661 io_apic
= io_apic_base(entry
->apic
);
662 readl(&io_apic
->data
);
665 static void __mask_IO_APIC_irq(unsigned int irq
)
667 io_apic_modify_irq(irq
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
669 #else /* CONFIG_X86_32 */
670 static void __mask_IO_APIC_irq(unsigned int irq
)
672 io_apic_modify_irq(irq
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
675 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
677 io_apic_modify_irq(irq
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
678 IO_APIC_REDIR_MASKED
, NULL
);
681 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
683 io_apic_modify_irq(irq
, ~IO_APIC_REDIR_MASKED
,
684 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
686 #endif /* CONFIG_X86_32 */
688 static void mask_IO_APIC_irq (unsigned int irq
)
692 spin_lock_irqsave(&ioapic_lock
, flags
);
693 __mask_IO_APIC_irq(irq
);
694 spin_unlock_irqrestore(&ioapic_lock
, flags
);
697 static void unmask_IO_APIC_irq (unsigned int irq
)
701 spin_lock_irqsave(&ioapic_lock
, flags
);
702 __unmask_IO_APIC_irq(irq
);
703 spin_unlock_irqrestore(&ioapic_lock
, flags
);
706 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
708 struct IO_APIC_route_entry entry
;
710 /* Check delivery_mode to be sure we're not clearing an SMI pin */
711 entry
= ioapic_read_entry(apic
, pin
);
712 if (entry
.delivery_mode
== dest_SMI
)
715 * Disable it in the IO-APIC irq-routing table:
717 ioapic_mask_entry(apic
, pin
);
720 static void clear_IO_APIC (void)
724 for (apic
= 0; apic
< nr_ioapics
; apic
++)
725 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
726 clear_IO_APIC_pin(apic
, pin
);
729 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
730 void send_IPI_self(int vector
)
737 apic_wait_icr_idle();
738 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
740 * Send the IPI. The write to APIC_ICR fires this off.
742 apic_write(APIC_ICR
, cfg
);
744 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
748 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
749 * specific CPU-side IRQs.
753 static int pirq_entries
[MAX_PIRQS
];
754 static int pirqs_enabled
;
756 static int __init
ioapic_pirq_setup(char *str
)
759 int ints
[MAX_PIRQS
+1];
761 get_options(str
, ARRAY_SIZE(ints
), ints
);
763 for (i
= 0; i
< MAX_PIRQS
; i
++)
764 pirq_entries
[i
] = -1;
767 apic_printk(APIC_VERBOSE
, KERN_INFO
768 "PIRQ redirection, working around broken MP-BIOS.\n");
770 if (ints
[0] < MAX_PIRQS
)
773 for (i
= 0; i
< max
; i
++) {
774 apic_printk(APIC_VERBOSE
, KERN_DEBUG
775 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
777 * PIRQs are mapped upside down, usually.
779 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
784 __setup("pirq=", ioapic_pirq_setup
);
785 #endif /* CONFIG_X86_32 */
787 #ifdef CONFIG_INTR_REMAP
788 /* I/O APIC RTE contents at the OS boot up */
789 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
792 * Saves and masks all the unmasked IO-APIC RTE's
794 int save_mask_IO_APIC_setup(void)
796 union IO_APIC_reg_01 reg_01
;
801 * The number of IO-APIC IRQ registers (== #pins):
803 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
804 spin_lock_irqsave(&ioapic_lock
, flags
);
805 reg_01
.raw
= io_apic_read(apic
, 1);
806 spin_unlock_irqrestore(&ioapic_lock
, flags
);
807 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
810 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
811 early_ioapic_entries
[apic
] =
812 kzalloc(sizeof(struct IO_APIC_route_entry
) *
813 nr_ioapic_registers
[apic
], GFP_KERNEL
);
814 if (!early_ioapic_entries
[apic
])
818 for (apic
= 0; apic
< nr_ioapics
; apic
++)
819 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
820 struct IO_APIC_route_entry entry
;
822 entry
= early_ioapic_entries
[apic
][pin
] =
823 ioapic_read_entry(apic
, pin
);
826 ioapic_write_entry(apic
, pin
, entry
);
833 for (; apic
> 0; apic
--)
834 kfree(early_ioapic_entries
[apic
]);
835 kfree(early_ioapic_entries
[apic
]);
836 memset(early_ioapic_entries
, 0,
837 ARRAY_SIZE(early_ioapic_entries
));
842 void restore_IO_APIC_setup(void)
846 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
847 if (!early_ioapic_entries
[apic
])
849 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
850 ioapic_write_entry(apic
, pin
,
851 early_ioapic_entries
[apic
][pin
]);
852 kfree(early_ioapic_entries
[apic
]);
853 early_ioapic_entries
[apic
] = NULL
;
857 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
860 * for now plain restore of previous settings.
861 * TBD: In the case of OS enabling interrupt-remapping,
862 * IO-APIC RTE's need to be setup to point to interrupt-remapping
863 * table entries. for now, do a plain restore, and wait for
864 * the setup_IO_APIC_irqs() to do proper initialization.
866 restore_IO_APIC_setup();
871 * Find the IRQ entry number of a certain pin.
873 static int find_irq_entry(int apic
, int pin
, int type
)
877 for (i
= 0; i
< mp_irq_entries
; i
++)
878 if (mp_irqs
[i
].mp_irqtype
== type
&&
879 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
880 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
881 mp_irqs
[i
].mp_dstirq
== pin
)
888 * Find the pin to which IRQ[irq] (ISA) is connected
890 static int __init
find_isa_irq_pin(int irq
, int type
)
894 for (i
= 0; i
< mp_irq_entries
; i
++) {
895 int lbus
= mp_irqs
[i
].mp_srcbus
;
897 if (test_bit(lbus
, mp_bus_not_pci
) &&
898 (mp_irqs
[i
].mp_irqtype
== type
) &&
899 (mp_irqs
[i
].mp_srcbusirq
== irq
))
901 return mp_irqs
[i
].mp_dstirq
;
906 static int __init
find_isa_irq_apic(int irq
, int type
)
910 for (i
= 0; i
< mp_irq_entries
; i
++) {
911 int lbus
= mp_irqs
[i
].mp_srcbus
;
913 if (test_bit(lbus
, mp_bus_not_pci
) &&
914 (mp_irqs
[i
].mp_irqtype
== type
) &&
915 (mp_irqs
[i
].mp_srcbusirq
== irq
))
918 if (i
< mp_irq_entries
) {
920 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
921 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
930 * Find a specific PCI IRQ entry.
931 * Not an __init, possibly needed by modules
933 static int pin_2_irq(int idx
, int apic
, int pin
);
935 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
937 int apic
, i
, best_guess
= -1;
939 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
941 if (test_bit(bus
, mp_bus_not_pci
)) {
942 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
945 for (i
= 0; i
< mp_irq_entries
; i
++) {
946 int lbus
= mp_irqs
[i
].mp_srcbus
;
948 for (apic
= 0; apic
< nr_ioapics
; apic
++)
949 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
950 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
953 if (!test_bit(lbus
, mp_bus_not_pci
) &&
954 !mp_irqs
[i
].mp_irqtype
&&
956 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
957 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
959 if (!(apic
|| IO_APIC_IRQ(irq
)))
962 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
965 * Use the first all-but-pin matching entry as a
966 * best-guess fuzzy result for broken mptables.
975 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
977 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
979 * EISA Edge/Level control register, ELCR
981 static int EISA_ELCR(unsigned int irq
)
984 unsigned int port
= 0x4d0 + (irq
>> 3);
985 return (inb(port
) >> (irq
& 7)) & 1;
987 apic_printk(APIC_VERBOSE
, KERN_INFO
988 "Broken MPtable reports ISA irq %d\n", irq
);
994 /* ISA interrupts are always polarity zero edge triggered,
995 * when listed as conforming in the MP table. */
997 #define default_ISA_trigger(idx) (0)
998 #define default_ISA_polarity(idx) (0)
1000 /* EISA interrupts are always polarity zero and can be edge or level
1001 * trigger depending on the ELCR value. If an interrupt is listed as
1002 * EISA conforming in the MP table, that means its trigger type must
1003 * be read in from the ELCR */
1005 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1006 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1008 /* PCI interrupts are always polarity one level triggered,
1009 * when listed as conforming in the MP table. */
1011 #define default_PCI_trigger(idx) (1)
1012 #define default_PCI_polarity(idx) (1)
1014 /* MCA interrupts are always polarity zero level triggered,
1015 * when listed as conforming in the MP table. */
1017 #define default_MCA_trigger(idx) (1)
1018 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1020 static int MPBIOS_polarity(int idx
)
1022 int bus
= mp_irqs
[idx
].mp_srcbus
;
1026 * Determine IRQ line polarity (high active or low active):
1028 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1030 case 0: /* conforms, ie. bus-type dependent polarity */
1031 if (test_bit(bus
, mp_bus_not_pci
))
1032 polarity
= default_ISA_polarity(idx
);
1034 polarity
= default_PCI_polarity(idx
);
1036 case 1: /* high active */
1041 case 2: /* reserved */
1043 printk(KERN_WARNING
"broken BIOS!!\n");
1047 case 3: /* low active */
1052 default: /* invalid */
1054 printk(KERN_WARNING
"broken BIOS!!\n");
1062 static int MPBIOS_trigger(int idx
)
1064 int bus
= mp_irqs
[idx
].mp_srcbus
;
1068 * Determine IRQ trigger mode (edge or level sensitive):
1070 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1072 case 0: /* conforms, ie. bus-type dependent */
1073 if (test_bit(bus
, mp_bus_not_pci
))
1074 trigger
= default_ISA_trigger(idx
);
1076 trigger
= default_PCI_trigger(idx
);
1077 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1078 switch (mp_bus_id_to_type
[bus
]) {
1079 case MP_BUS_ISA
: /* ISA pin */
1081 /* set before the switch */
1084 case MP_BUS_EISA
: /* EISA pin */
1086 trigger
= default_EISA_trigger(idx
);
1089 case MP_BUS_PCI
: /* PCI pin */
1091 /* set before the switch */
1094 case MP_BUS_MCA
: /* MCA pin */
1096 trigger
= default_MCA_trigger(idx
);
1101 printk(KERN_WARNING
"broken BIOS!!\n");
1113 case 2: /* reserved */
1115 printk(KERN_WARNING
"broken BIOS!!\n");
1124 default: /* invalid */
1126 printk(KERN_WARNING
"broken BIOS!!\n");
1134 static inline int irq_polarity(int idx
)
1136 return MPBIOS_polarity(idx
);
1139 static inline int irq_trigger(int idx
)
1141 return MPBIOS_trigger(idx
);
1144 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1145 static int pin_2_irq(int idx
, int apic
, int pin
)
1148 int bus
= mp_irqs
[idx
].mp_srcbus
;
1151 * Debugging check, we are in big trouble if this message pops up!
1153 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1154 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1156 if (test_bit(bus
, mp_bus_not_pci
)) {
1157 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1160 * PCI IRQs are mapped in order
1164 irq
+= nr_ioapic_registers
[i
++];
1167 * For MPS mode, so far only needed by ES7000 platform
1169 if (ioapic_renumber_irq
)
1170 irq
= ioapic_renumber_irq(apic
, irq
);
1173 #ifdef CONFIG_X86_32
1175 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1177 if ((pin
>= 16) && (pin
<= 23)) {
1178 if (pirq_entries
[pin
-16] != -1) {
1179 if (!pirq_entries
[pin
-16]) {
1180 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1181 "disabling PIRQ%d\n", pin
-16);
1183 irq
= pirq_entries
[pin
-16];
1184 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1185 "using PIRQ%d -> IRQ %d\n",
1195 void lock_vector_lock(void)
1197 /* Used to the online set of cpus does not change
1198 * during assign_irq_vector.
1200 spin_lock(&vector_lock
);
1203 void unlock_vector_lock(void)
1205 spin_unlock(&vector_lock
);
1208 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1211 * NOTE! The local APIC isn't very good at handling
1212 * multiple interrupts at the same interrupt level.
1213 * As the interrupt level is determined by taking the
1214 * vector number and shifting that right by 4, we
1215 * want to spread these out a bit so that they don't
1216 * all fall in the same interrupt level.
1218 * Also, we've got to be careful not to trash gate
1219 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1221 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1222 unsigned int old_vector
;
1224 struct irq_cfg
*cfg
;
1228 /* Only try and allocate irqs on cpus that are present */
1229 cpus_and(mask
, mask
, cpu_online_map
);
1231 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1234 old_vector
= cfg
->vector
;
1237 cpus_and(tmp
, cfg
->domain
, mask
);
1238 if (!cpus_empty(tmp
))
1242 for_each_cpu_mask_nr(cpu
, mask
) {
1243 cpumask_t domain
, new_mask
;
1247 domain
= vector_allocation_domain(cpu
);
1248 cpus_and(new_mask
, domain
, cpu_online_map
);
1250 vector
= current_vector
;
1251 offset
= current_offset
;
1254 if (vector
>= first_system_vector
) {
1255 /* If we run out of vectors on large boxen, must share them. */
1256 offset
= (offset
+ 1) % 8;
1257 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1259 if (unlikely(current_vector
== vector
))
1261 #ifdef CONFIG_X86_64
1262 if (vector
== IA32_SYSCALL_VECTOR
)
1265 if (vector
== SYSCALL_VECTOR
)
1268 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1269 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1272 current_vector
= vector
;
1273 current_offset
= offset
;
1275 cfg
->move_in_progress
= 1;
1276 cfg
->old_domain
= cfg
->domain
;
1278 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1279 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1280 cfg
->vector
= vector
;
1281 cfg
->domain
= domain
;
1287 static int assign_irq_vector(int irq
, cpumask_t mask
)
1290 unsigned long flags
;
1292 spin_lock_irqsave(&vector_lock
, flags
);
1293 err
= __assign_irq_vector(irq
, mask
);
1294 spin_unlock_irqrestore(&vector_lock
, flags
);
1298 static void __clear_irq_vector(int irq
)
1300 struct irq_cfg
*cfg
;
1305 BUG_ON(!cfg
->vector
);
1307 vector
= cfg
->vector
;
1308 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1309 for_each_cpu_mask_nr(cpu
, mask
)
1310 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1313 cpus_clear(cfg
->domain
);
1316 void __setup_vector_irq(int cpu
)
1318 /* Initialize vector_irq on a new cpu */
1319 /* This function must be called with vector_lock held */
1321 struct irq_cfg
*cfg
;
1323 /* Mark the inuse vectors */
1324 for_each_irq_cfg(irq
, cfg
) {
1325 if (!cpu_isset(cpu
, cfg
->domain
))
1327 vector
= cfg
->vector
;
1328 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1330 /* Mark the free vectors */
1331 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1332 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1337 if (!cpu_isset(cpu
, cfg
->domain
))
1338 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1342 static struct irq_chip ioapic_chip
;
1343 #ifdef CONFIG_INTR_REMAP
1344 static struct irq_chip ir_ioapic_chip
;
1347 #define IOAPIC_AUTO -1
1348 #define IOAPIC_EDGE 0
1349 #define IOAPIC_LEVEL 1
1351 #ifdef CONFIG_X86_32
1352 static inline int IO_APIC_irq_trigger(int irq
)
1356 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1357 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1358 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1359 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1360 return irq_trigger(idx
);
1364 * nonexistent IRQs are edge default
1369 static inline int IO_APIC_irq_trigger(int irq
)
1375 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1377 struct irq_desc
*desc
;
1379 /* first time to use this irq_desc */
1381 desc
= irq_to_desc(irq
);
1383 desc
= irq_to_desc_alloc(irq
);
1385 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1386 trigger
== IOAPIC_LEVEL
)
1387 desc
->status
|= IRQ_LEVEL
;
1389 desc
->status
&= ~IRQ_LEVEL
;
1391 #ifdef CONFIG_INTR_REMAP
1392 if (irq_remapped(irq
)) {
1393 desc
->status
|= IRQ_MOVE_PCNTXT
;
1395 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1399 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1400 handle_edge_irq
, "edge");
1404 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1405 trigger
== IOAPIC_LEVEL
)
1406 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1410 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1411 handle_edge_irq
, "edge");
1414 static int setup_ioapic_entry(int apic
, int irq
,
1415 struct IO_APIC_route_entry
*entry
,
1416 unsigned int destination
, int trigger
,
1417 int polarity
, int vector
)
1420 * add it to the IO-APIC irq-routing table:
1422 memset(entry
,0,sizeof(*entry
));
1424 #ifdef CONFIG_INTR_REMAP
1425 if (intr_remapping_enabled
) {
1426 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1428 struct IR_IO_APIC_route_entry
*ir_entry
=
1429 (struct IR_IO_APIC_route_entry
*) entry
;
1433 panic("No mapping iommu for ioapic %d\n", apic
);
1435 index
= alloc_irte(iommu
, irq
, 1);
1437 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1439 memset(&irte
, 0, sizeof(irte
));
1442 irte
.dst_mode
= INT_DEST_MODE
;
1443 irte
.trigger_mode
= trigger
;
1444 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1445 irte
.vector
= vector
;
1446 irte
.dest_id
= IRTE_DEST(destination
);
1448 modify_irte(irq
, &irte
);
1450 ir_entry
->index2
= (index
>> 15) & 0x1;
1452 ir_entry
->format
= 1;
1453 ir_entry
->index
= (index
& 0x7fff);
1457 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1458 entry
->dest_mode
= INT_DEST_MODE
;
1459 entry
->dest
= destination
;
1462 entry
->mask
= 0; /* enable IRQ */
1463 entry
->trigger
= trigger
;
1464 entry
->polarity
= polarity
;
1465 entry
->vector
= vector
;
1467 /* Mask level triggered irqs.
1468 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1475 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1476 int trigger
, int polarity
)
1478 struct irq_cfg
*cfg
;
1479 struct IO_APIC_route_entry entry
;
1482 if (!IO_APIC_IRQ(irq
))
1488 if (assign_irq_vector(irq
, mask
))
1491 cpus_and(mask
, cfg
->domain
, mask
);
1493 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1494 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1495 "IRQ %d Mode:%i Active:%i)\n",
1496 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1497 irq
, trigger
, polarity
);
1500 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1501 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1503 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1504 mp_ioapics
[apic
].mp_apicid
, pin
);
1505 __clear_irq_vector(irq
);
1509 ioapic_register_intr(irq
, trigger
);
1511 disable_8259A_irq(irq
);
1513 ioapic_write_entry(apic
, pin
, entry
);
1516 static void __init
setup_IO_APIC_irqs(void)
1518 int apic
, pin
, idx
, irq
;
1521 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1523 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1524 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1526 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1530 apic_printk(APIC_VERBOSE
,
1531 KERN_DEBUG
" %d-%d",
1532 mp_ioapics
[apic
].mp_apicid
,
1535 apic_printk(APIC_VERBOSE
, " %d-%d",
1536 mp_ioapics
[apic
].mp_apicid
,
1541 apic_printk(APIC_VERBOSE
,
1542 " (apicid-pin) not connected\n");
1546 irq
= pin_2_irq(idx
, apic
, pin
);
1547 #ifdef CONFIG_X86_32
1548 if (multi_timer_check(apic
, irq
))
1551 add_pin_to_irq(irq
, apic
, pin
);
1553 setup_IO_APIC_irq(apic
, pin
, irq
,
1554 irq_trigger(idx
), irq_polarity(idx
));
1559 apic_printk(APIC_VERBOSE
,
1560 " (apicid-pin) not connected\n");
1564 * Set up the timer pin, possibly with the 8259A-master behind.
1566 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1569 struct IO_APIC_route_entry entry
;
1571 #ifdef CONFIG_INTR_REMAP
1572 if (intr_remapping_enabled
)
1576 memset(&entry
, 0, sizeof(entry
));
1579 * We use logical delivery to get the timer IRQ
1582 entry
.dest_mode
= INT_DEST_MODE
;
1583 entry
.mask
= 1; /* mask IRQ now */
1584 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1585 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1588 entry
.vector
= vector
;
1591 * The timer IRQ doesn't have to know that behind the
1592 * scene we may have a 8259A-master in AEOI mode ...
1594 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1597 * Add it to the IO-APIC irq-routing table:
1599 ioapic_write_entry(apic
, pin
, entry
);
1603 __apicdebuginit(void) print_IO_APIC(void)
1606 union IO_APIC_reg_00 reg_00
;
1607 union IO_APIC_reg_01 reg_01
;
1608 union IO_APIC_reg_02 reg_02
;
1609 union IO_APIC_reg_03 reg_03
;
1610 unsigned long flags
;
1611 struct irq_cfg
*cfg
;
1614 if (apic_verbosity
== APIC_QUIET
)
1617 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1618 for (i
= 0; i
< nr_ioapics
; i
++)
1619 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1620 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1623 * We are a bit conservative about what we expect. We have to
1624 * know about every hardware change ASAP.
1626 printk(KERN_INFO
"testing the IO APIC.......................\n");
1628 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1630 spin_lock_irqsave(&ioapic_lock
, flags
);
1631 reg_00
.raw
= io_apic_read(apic
, 0);
1632 reg_01
.raw
= io_apic_read(apic
, 1);
1633 if (reg_01
.bits
.version
>= 0x10)
1634 reg_02
.raw
= io_apic_read(apic
, 2);
1635 if (reg_01
.bits
.version
>= 0x20)
1636 reg_03
.raw
= io_apic_read(apic
, 3);
1637 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1640 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1641 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1642 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1643 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1644 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1646 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1647 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1649 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1650 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1653 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1654 * but the value of reg_02 is read as the previous read register
1655 * value, so ignore it if reg_02 == reg_01.
1657 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1658 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1659 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1663 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1664 * or reg_03, but the value of reg_0[23] is read as the previous read
1665 * register value, so ignore it if reg_03 == reg_0[12].
1667 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1668 reg_03
.raw
!= reg_01
.raw
) {
1669 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1670 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1673 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1675 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1676 " Stat Dmod Deli Vect: \n");
1678 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1679 struct IO_APIC_route_entry entry
;
1681 entry
= ioapic_read_entry(apic
, i
);
1683 printk(KERN_DEBUG
" %02x %03X ",
1688 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1693 entry
.delivery_status
,
1695 entry
.delivery_mode
,
1700 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1701 for_each_irq_cfg(irq
, cfg
) {
1702 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1705 printk(KERN_DEBUG
"IRQ%d ", irq
);
1707 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1710 entry
= entry
->next
;
1715 printk(KERN_INFO
".................................... done.\n");
1720 __apicdebuginit(void) print_APIC_bitfield(int base
)
1725 if (apic_verbosity
== APIC_QUIET
)
1728 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1729 for (i
= 0; i
< 8; i
++) {
1730 v
= apic_read(base
+ i
*0x10);
1731 for (j
= 0; j
< 32; j
++) {
1741 __apicdebuginit(void) print_local_APIC(void *dummy
)
1743 unsigned int v
, ver
, maxlvt
;
1746 if (apic_verbosity
== APIC_QUIET
)
1749 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1750 smp_processor_id(), hard_smp_processor_id());
1751 v
= apic_read(APIC_ID
);
1752 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1753 v
= apic_read(APIC_LVR
);
1754 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1755 ver
= GET_APIC_VERSION(v
);
1756 maxlvt
= lapic_get_maxlvt();
1758 v
= apic_read(APIC_TASKPRI
);
1759 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1761 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1762 if (!APIC_XAPIC(ver
)) {
1763 v
= apic_read(APIC_ARBPRI
);
1764 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1765 v
& APIC_ARBPRI_MASK
);
1767 v
= apic_read(APIC_PROCPRI
);
1768 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1772 * Remote read supported only in the 82489DX and local APIC for
1773 * Pentium processors.
1775 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1776 v
= apic_read(APIC_RRR
);
1777 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1780 v
= apic_read(APIC_LDR
);
1781 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1782 if (!x2apic_enabled()) {
1783 v
= apic_read(APIC_DFR
);
1784 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1786 v
= apic_read(APIC_SPIV
);
1787 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1789 printk(KERN_DEBUG
"... APIC ISR field:\n");
1790 print_APIC_bitfield(APIC_ISR
);
1791 printk(KERN_DEBUG
"... APIC TMR field:\n");
1792 print_APIC_bitfield(APIC_TMR
);
1793 printk(KERN_DEBUG
"... APIC IRR field:\n");
1794 print_APIC_bitfield(APIC_IRR
);
1796 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1797 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1798 apic_write(APIC_ESR
, 0);
1800 v
= apic_read(APIC_ESR
);
1801 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1804 icr
= apic_icr_read();
1805 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1806 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1808 v
= apic_read(APIC_LVTT
);
1809 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1811 if (maxlvt
> 3) { /* PC is LVT#4. */
1812 v
= apic_read(APIC_LVTPC
);
1813 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1815 v
= apic_read(APIC_LVT0
);
1816 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1817 v
= apic_read(APIC_LVT1
);
1818 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1820 if (maxlvt
> 2) { /* ERR is LVT#3. */
1821 v
= apic_read(APIC_LVTERR
);
1822 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1825 v
= apic_read(APIC_TMICT
);
1826 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1827 v
= apic_read(APIC_TMCCT
);
1828 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1829 v
= apic_read(APIC_TDCR
);
1830 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1834 __apicdebuginit(void) print_all_local_APICs(void)
1839 for_each_online_cpu(cpu
)
1840 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1844 __apicdebuginit(void) print_PIC(void)
1847 unsigned long flags
;
1849 if (apic_verbosity
== APIC_QUIET
)
1852 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1854 spin_lock_irqsave(&i8259A_lock
, flags
);
1856 v
= inb(0xa1) << 8 | inb(0x21);
1857 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1859 v
= inb(0xa0) << 8 | inb(0x20);
1860 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1864 v
= inb(0xa0) << 8 | inb(0x20);
1868 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1870 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1872 v
= inb(0x4d1) << 8 | inb(0x4d0);
1873 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1876 __apicdebuginit(int) print_all_ICs(void)
1879 print_all_local_APICs();
1885 fs_initcall(print_all_ICs
);
1888 /* Where if anywhere is the i8259 connect in external int mode */
1889 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1891 void __init
enable_IO_APIC(void)
1893 union IO_APIC_reg_01 reg_01
;
1894 int i8259_apic
, i8259_pin
;
1896 unsigned long flags
;
1898 #ifdef CONFIG_X86_32
1901 for (i
= 0; i
< MAX_PIRQS
; i
++)
1902 pirq_entries
[i
] = -1;
1906 * The number of IO-APIC IRQ registers (== #pins):
1908 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1909 spin_lock_irqsave(&ioapic_lock
, flags
);
1910 reg_01
.raw
= io_apic_read(apic
, 1);
1911 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1912 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1914 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1916 /* See if any of the pins is in ExtINT mode */
1917 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1918 struct IO_APIC_route_entry entry
;
1919 entry
= ioapic_read_entry(apic
, pin
);
1921 /* If the interrupt line is enabled and in ExtInt mode
1922 * I have found the pin where the i8259 is connected.
1924 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1925 ioapic_i8259
.apic
= apic
;
1926 ioapic_i8259
.pin
= pin
;
1932 /* Look to see what if the MP table has reported the ExtINT */
1933 /* If we could not find the appropriate pin by looking at the ioapic
1934 * the i8259 probably is not connected the ioapic but give the
1935 * mptable a chance anyway.
1937 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1938 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1939 /* Trust the MP table if nothing is setup in the hardware */
1940 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1941 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1942 ioapic_i8259
.pin
= i8259_pin
;
1943 ioapic_i8259
.apic
= i8259_apic
;
1945 /* Complain if the MP table and the hardware disagree */
1946 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1947 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1949 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1953 * Do not trust the IO-APIC being empty at bootup
1959 * Not an __init, needed by the reboot code
1961 void disable_IO_APIC(void)
1964 * Clear the IO-APIC before rebooting:
1969 * If the i8259 is routed through an IOAPIC
1970 * Put that IOAPIC in virtual wire mode
1971 * so legacy interrupts can be delivered.
1973 if (ioapic_i8259
.pin
!= -1) {
1974 struct IO_APIC_route_entry entry
;
1976 memset(&entry
, 0, sizeof(entry
));
1977 entry
.mask
= 0; /* Enabled */
1978 entry
.trigger
= 0; /* Edge */
1980 entry
.polarity
= 0; /* High */
1981 entry
.delivery_status
= 0;
1982 entry
.dest_mode
= 0; /* Physical */
1983 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1985 entry
.dest
= read_apic_id();
1988 * Add it to the IO-APIC irq-routing table:
1990 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1993 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1996 #ifdef CONFIG_X86_32
1998 * function to set the IO-APIC physical IDs based on the
1999 * values stored in the MPC table.
2001 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2004 static void __init
setup_ioapic_ids_from_mpc(void)
2006 union IO_APIC_reg_00 reg_00
;
2007 physid_mask_t phys_id_present_map
;
2010 unsigned char old_id
;
2011 unsigned long flags
;
2013 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2017 * Don't check I/O APIC IDs for xAPIC systems. They have
2018 * no meaning without the serial APIC bus.
2020 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2021 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2024 * This is broken; anything with a real cpu count has to
2025 * circumvent this idiocy regardless.
2027 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2030 * Set the IOAPIC ID to the value stored in the MPC table.
2032 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2034 /* Read the register 0 value */
2035 spin_lock_irqsave(&ioapic_lock
, flags
);
2036 reg_00
.raw
= io_apic_read(apic
, 0);
2037 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2039 old_id
= mp_ioapics
[apic
].mp_apicid
;
2041 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
2042 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2043 apic
, mp_ioapics
[apic
].mp_apicid
);
2044 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2046 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
2050 * Sanity check, is the ID really free? Every APIC in a
2051 * system must have a unique ID or we get lots of nice
2052 * 'stuck on smp_invalidate_needed IPI wait' messages.
2054 if (check_apicid_used(phys_id_present_map
,
2055 mp_ioapics
[apic
].mp_apicid
)) {
2056 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2057 apic
, mp_ioapics
[apic
].mp_apicid
);
2058 for (i
= 0; i
< get_physical_broadcast(); i
++)
2059 if (!physid_isset(i
, phys_id_present_map
))
2061 if (i
>= get_physical_broadcast())
2062 panic("Max APIC ID exceeded!\n");
2063 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2065 physid_set(i
, phys_id_present_map
);
2066 mp_ioapics
[apic
].mp_apicid
= i
;
2069 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2070 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2071 "phys_id_present_map\n",
2072 mp_ioapics
[apic
].mp_apicid
);
2073 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2078 * We need to adjust the IRQ routing table
2079 * if the ID changed.
2081 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2082 for (i
= 0; i
< mp_irq_entries
; i
++)
2083 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2084 mp_irqs
[i
].mp_dstapic
2085 = mp_ioapics
[apic
].mp_apicid
;
2088 * Read the right value from the MPC table and
2089 * write it into the ID register.
2091 apic_printk(APIC_VERBOSE
, KERN_INFO
2092 "...changing IO-APIC physical APIC ID to %d ...",
2093 mp_ioapics
[apic
].mp_apicid
);
2095 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2096 spin_lock_irqsave(&ioapic_lock
, flags
);
2097 io_apic_write(apic
, 0, reg_00
.raw
);
2098 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2103 spin_lock_irqsave(&ioapic_lock
, flags
);
2104 reg_00
.raw
= io_apic_read(apic
, 0);
2105 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2106 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2107 printk("could not set ID!\n");
2109 apic_printk(APIC_VERBOSE
, " ok.\n");
2114 int no_timer_check __initdata
;
2116 static int __init
notimercheck(char *s
)
2121 __setup("no_timer_check", notimercheck
);
2124 * There is a nasty bug in some older SMP boards, their mptable lies
2125 * about the timer IRQ. We do the following to work around the situation:
2127 * - timer IRQ defaults to IO-APIC IRQ
2128 * - if this function detects that timer IRQs are defunct, then we fall
2129 * back to ISA timer IRQs
2131 static int __init
timer_irq_works(void)
2133 unsigned long t1
= jiffies
;
2134 unsigned long flags
;
2139 local_save_flags(flags
);
2141 /* Let ten ticks pass... */
2142 mdelay((10 * 1000) / HZ
);
2143 local_irq_restore(flags
);
2146 * Expect a few ticks at least, to be sure some possible
2147 * glue logic does not lock up after one or two first
2148 * ticks in a non-ExtINT mode. Also the local APIC
2149 * might have cached one ExtINT interrupt. Finally, at
2150 * least one tick may be lost due to delays.
2154 if (time_after(jiffies
, t1
+ 4))
2160 * In the SMP+IOAPIC case it might happen that there are an unspecified
2161 * number of pending IRQ events unhandled. These cases are very rare,
2162 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2163 * better to do it this way as thus we do not have to be aware of
2164 * 'pending' interrupts in the IRQ path, except at this point.
2167 * Edge triggered needs to resend any interrupt
2168 * that was delayed but this is now handled in the device
2173 * Starting up a edge-triggered IO-APIC interrupt is
2174 * nasty - we need to make sure that we get the edge.
2175 * If it is already asserted for some reason, we need
2176 * return 1 to indicate that is was pending.
2178 * This is not complete - we should be able to fake
2179 * an edge even if it isn't on the 8259A...
2182 static unsigned int startup_ioapic_irq(unsigned int irq
)
2184 int was_pending
= 0;
2185 unsigned long flags
;
2187 spin_lock_irqsave(&ioapic_lock
, flags
);
2189 disable_8259A_irq(irq
);
2190 if (i8259A_irq_pending(irq
))
2193 __unmask_IO_APIC_irq(irq
);
2194 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2199 #ifdef CONFIG_X86_64
2200 static int ioapic_retrigger_irq(unsigned int irq
)
2203 struct irq_cfg
*cfg
= irq_cfg(irq
);
2204 unsigned long flags
;
2206 spin_lock_irqsave(&vector_lock
, flags
);
2207 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
2208 spin_unlock_irqrestore(&vector_lock
, flags
);
2213 static int ioapic_retrigger_irq(unsigned int irq
)
2215 send_IPI_self(irq_cfg(irq
)->vector
);
2222 * Level and edge triggered IO-APIC interrupts need different handling,
2223 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2224 * handled with the level-triggered descriptor, but that one has slightly
2225 * more overhead. Level-triggered interrupts cannot be handled with the
2226 * edge-triggered handler, without risking IRQ storms and other ugly
2232 #ifdef CONFIG_INTR_REMAP
2233 static void ir_irq_migration(struct work_struct
*work
);
2235 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2238 * Migrate the IO-APIC irq in the presence of intr-remapping.
2240 * For edge triggered, irq migration is a simple atomic update(of vector
2241 * and cpu destination) of IRTE and flush the hardware cache.
2243 * For level triggered, we need to modify the io-apic RTE aswell with the update
2244 * vector information, along with modifying IRTE with vector and destination.
2245 * So irq migration for level triggered is little bit more complex compared to
2246 * edge triggered migration. But the good news is, we use the same algorithm
2247 * for level triggered migration as we have today, only difference being,
2248 * we now initiate the irq migration from process context instead of the
2249 * interrupt context.
2251 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2252 * suppression) to the IO-APIC, level triggered irq migration will also be
2253 * as simple as edge triggered migration and we can do the irq migration
2254 * with a simple atomic update to IO-APIC RTE.
2256 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
2258 struct irq_cfg
*cfg
;
2259 struct irq_desc
*desc
;
2260 cpumask_t tmp
, cleanup_mask
;
2262 int modify_ioapic_rte
;
2264 unsigned long flags
;
2266 cpus_and(tmp
, mask
, cpu_online_map
);
2267 if (cpus_empty(tmp
))
2270 if (get_irte(irq
, &irte
))
2273 if (assign_irq_vector(irq
, mask
))
2277 cpus_and(tmp
, cfg
->domain
, mask
);
2278 dest
= cpu_mask_to_apicid(tmp
);
2280 desc
= irq_to_desc(irq
);
2281 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2282 if (modify_ioapic_rte
) {
2283 spin_lock_irqsave(&ioapic_lock
, flags
);
2284 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
2285 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2288 irte
.vector
= cfg
->vector
;
2289 irte
.dest_id
= IRTE_DEST(dest
);
2292 * Modified the IRTE and flushes the Interrupt entry cache.
2294 modify_irte(irq
, &irte
);
2296 if (cfg
->move_in_progress
) {
2297 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2298 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2299 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2300 cfg
->move_in_progress
= 0;
2303 desc
->affinity
= mask
;
2306 static int migrate_irq_remapped_level(int irq
)
2309 struct irq_desc
*desc
= irq_to_desc(irq
);
2311 mask_IO_APIC_irq(irq
);
2313 if (io_apic_level_ack_pending(irq
)) {
2315 * Interrupt in progress. Migrating irq now will change the
2316 * vector information in the IO-APIC RTE and that will confuse
2317 * the EOI broadcast performed by cpu.
2318 * So, delay the irq migration to the next instance.
2320 schedule_delayed_work(&ir_migration_work
, 1);
2324 /* everthing is clear. we have right of way */
2325 migrate_ioapic_irq(irq
, desc
->pending_mask
);
2328 desc
->status
&= ~IRQ_MOVE_PENDING
;
2329 cpus_clear(desc
->pending_mask
);
2332 unmask_IO_APIC_irq(irq
);
2336 static void ir_irq_migration(struct work_struct
*work
)
2339 struct irq_desc
*desc
;
2341 for_each_irq_desc(irq
, desc
) {
2342 if (desc
->status
& IRQ_MOVE_PENDING
) {
2343 unsigned long flags
;
2345 spin_lock_irqsave(&desc
->lock
, flags
);
2346 if (!desc
->chip
->set_affinity
||
2347 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2348 desc
->status
&= ~IRQ_MOVE_PENDING
;
2349 spin_unlock_irqrestore(&desc
->lock
, flags
);
2353 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
2354 spin_unlock_irqrestore(&desc
->lock
, flags
);
2360 * Migrates the IRQ destination in the process context.
2362 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
2364 struct irq_desc
*desc
= irq_to_desc(irq
);
2366 if (desc
->status
& IRQ_LEVEL
) {
2367 desc
->status
|= IRQ_MOVE_PENDING
;
2368 desc
->pending_mask
= mask
;
2369 migrate_irq_remapped_level(irq
);
2373 migrate_ioapic_irq(irq
, mask
);
2377 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2379 unsigned vector
, me
;
2381 #ifdef CONFIG_X86_64
2386 me
= smp_processor_id();
2387 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2389 struct irq_desc
*desc
;
2390 struct irq_cfg
*cfg
;
2391 irq
= __get_cpu_var(vector_irq
)[vector
];
2393 desc
= irq_to_desc(irq
);
2398 spin_lock(&desc
->lock
);
2399 if (!cfg
->move_cleanup_count
)
2402 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
2405 __get_cpu_var(vector_irq
)[vector
] = -1;
2406 cfg
->move_cleanup_count
--;
2408 spin_unlock(&desc
->lock
);
2414 static void irq_complete_move(unsigned int irq
)
2416 struct irq_cfg
*cfg
= irq_cfg(irq
);
2417 unsigned vector
, me
;
2419 if (likely(!cfg
->move_in_progress
))
2422 vector
= ~get_irq_regs()->orig_ax
;
2423 me
= smp_processor_id();
2424 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
2425 cpumask_t cleanup_mask
;
2427 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2428 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2429 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2430 cfg
->move_in_progress
= 0;
2434 static inline void irq_complete_move(unsigned int irq
) {}
2436 #ifdef CONFIG_INTR_REMAP
2437 static void ack_x2apic_level(unsigned int irq
)
2442 static void ack_x2apic_edge(unsigned int irq
)
2448 static void ack_apic_edge(unsigned int irq
)
2450 irq_complete_move(irq
);
2451 move_native_irq(irq
);
2455 #ifdef CONFIG_X86_32
2456 atomic_t irq_mis_count
;
2459 static void ack_apic_level(unsigned int irq
)
2461 #ifdef CONFIG_X86_32
2465 int do_unmask_irq
= 0;
2467 irq_complete_move(irq
);
2468 #ifdef CONFIG_GENERIC_PENDING_IRQ
2469 /* If we are moving the irq we need to mask it */
2470 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2472 mask_IO_APIC_irq(irq
);
2476 #ifdef CONFIG_X86_32
2478 * It appears there is an erratum which affects at least version 0x11
2479 * of I/O APIC (that's the 82093AA and cores integrated into various
2480 * chipsets). Under certain conditions a level-triggered interrupt is
2481 * erroneously delivered as edge-triggered one but the respective IRR
2482 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2483 * message but it will never arrive and further interrupts are blocked
2484 * from the source. The exact reason is so far unknown, but the
2485 * phenomenon was observed when two consecutive interrupt requests
2486 * from a given source get delivered to the same CPU and the source is
2487 * temporarily disabled in between.
2489 * A workaround is to simulate an EOI message manually. We achieve it
2490 * by setting the trigger mode to edge and then to level when the edge
2491 * trigger mode gets detected in the TMR of a local APIC for a
2492 * level-triggered interrupt. We mask the source for the time of the
2493 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2494 * The idea is from Manfred Spraul. --macro
2496 i
= irq_cfg(irq
)->vector
;
2498 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2502 * We must acknowledge the irq before we move it or the acknowledge will
2503 * not propagate properly.
2507 /* Now we can move and renable the irq */
2508 if (unlikely(do_unmask_irq
)) {
2509 /* Only migrate the irq if the ack has been received.
2511 * On rare occasions the broadcast level triggered ack gets
2512 * delayed going to ioapics, and if we reprogram the
2513 * vector while Remote IRR is still set the irq will never
2516 * To prevent this scenario we read the Remote IRR bit
2517 * of the ioapic. This has two effects.
2518 * - On any sane system the read of the ioapic will
2519 * flush writes (and acks) going to the ioapic from
2521 * - We get to see if the ACK has actually been delivered.
2523 * Based on failed experiments of reprogramming the
2524 * ioapic entry from outside of irq context starting
2525 * with masking the ioapic entry and then polling until
2526 * Remote IRR was clear before reprogramming the
2527 * ioapic I don't trust the Remote IRR bit to be
2528 * completey accurate.
2530 * However there appears to be no other way to plug
2531 * this race, so if the Remote IRR bit is not
2532 * accurate and is causing problems then it is a hardware bug
2533 * and you can go talk to the chipset vendor about it.
2535 if (!io_apic_level_ack_pending(irq
))
2536 move_masked_irq(irq
);
2537 unmask_IO_APIC_irq(irq
);
2540 #ifdef CONFIG_X86_32
2541 if (!(v
& (1 << (i
& 0x1f)))) {
2542 atomic_inc(&irq_mis_count
);
2543 spin_lock(&ioapic_lock
);
2544 __mask_and_edge_IO_APIC_irq(irq
);
2545 __unmask_and_level_IO_APIC_irq(irq
);
2546 spin_unlock(&ioapic_lock
);
2551 static struct irq_chip ioapic_chip __read_mostly
= {
2553 .startup
= startup_ioapic_irq
,
2554 .mask
= mask_IO_APIC_irq
,
2555 .unmask
= unmask_IO_APIC_irq
,
2556 .ack
= ack_apic_edge
,
2557 .eoi
= ack_apic_level
,
2559 .set_affinity
= set_ioapic_affinity_irq
,
2561 .retrigger
= ioapic_retrigger_irq
,
2564 #ifdef CONFIG_INTR_REMAP
2565 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2566 .name
= "IR-IO-APIC",
2567 .startup
= startup_ioapic_irq
,
2568 .mask
= mask_IO_APIC_irq
,
2569 .unmask
= unmask_IO_APIC_irq
,
2570 .ack
= ack_x2apic_edge
,
2571 .eoi
= ack_x2apic_level
,
2573 .set_affinity
= set_ir_ioapic_affinity_irq
,
2575 .retrigger
= ioapic_retrigger_irq
,
2579 static inline void init_IO_APIC_traps(void)
2582 struct irq_desc
*desc
;
2583 struct irq_cfg
*cfg
;
2586 * NOTE! The local APIC isn't very good at handling
2587 * multiple interrupts at the same interrupt level.
2588 * As the interrupt level is determined by taking the
2589 * vector number and shifting that right by 4, we
2590 * want to spread these out a bit so that they don't
2591 * all fall in the same interrupt level.
2593 * Also, we've got to be careful not to trash gate
2594 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2596 for_each_irq_cfg(irq
, cfg
) {
2597 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2599 * Hmm.. We don't have an entry for this,
2600 * so default to an old-fashioned 8259
2601 * interrupt if we can..
2604 make_8259A_irq(irq
);
2606 desc
= irq_to_desc(irq
);
2607 /* Strange. Oh, well.. */
2608 desc
->chip
= &no_irq_chip
;
2615 * The local APIC irq-chip implementation:
2618 static void mask_lapic_irq(unsigned int irq
)
2622 v
= apic_read(APIC_LVT0
);
2623 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2626 static void unmask_lapic_irq(unsigned int irq
)
2630 v
= apic_read(APIC_LVT0
);
2631 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2634 static void ack_lapic_irq (unsigned int irq
)
2639 static struct irq_chip lapic_chip __read_mostly
= {
2640 .name
= "local-APIC",
2641 .mask
= mask_lapic_irq
,
2642 .unmask
= unmask_lapic_irq
,
2643 .ack
= ack_lapic_irq
,
2646 static void lapic_register_intr(int irq
)
2648 struct irq_desc
*desc
;
2650 desc
= irq_to_desc(irq
);
2651 desc
->status
&= ~IRQ_LEVEL
;
2652 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2656 static void __init
setup_nmi(void)
2659 * Dirty trick to enable the NMI watchdog ...
2660 * We put the 8259A master into AEOI mode and
2661 * unmask on all local APICs LVT0 as NMI.
2663 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2664 * is from Maciej W. Rozycki - so we do not have to EOI from
2665 * the NMI handler or the timer interrupt.
2667 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2669 enable_NMI_through_LVT0();
2671 apic_printk(APIC_VERBOSE
, " done.\n");
2675 * This looks a bit hackish but it's about the only one way of sending
2676 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2677 * not support the ExtINT mode, unfortunately. We need to send these
2678 * cycles as some i82489DX-based boards have glue logic that keeps the
2679 * 8259A interrupt line asserted until INTA. --macro
2681 static inline void __init
unlock_ExtINT_logic(void)
2684 struct IO_APIC_route_entry entry0
, entry1
;
2685 unsigned char save_control
, save_freq_select
;
2687 pin
= find_isa_irq_pin(8, mp_INT
);
2692 apic
= find_isa_irq_apic(8, mp_INT
);
2698 entry0
= ioapic_read_entry(apic
, pin
);
2699 clear_IO_APIC_pin(apic
, pin
);
2701 memset(&entry1
, 0, sizeof(entry1
));
2703 entry1
.dest_mode
= 0; /* physical delivery */
2704 entry1
.mask
= 0; /* unmask IRQ now */
2705 entry1
.dest
= hard_smp_processor_id();
2706 entry1
.delivery_mode
= dest_ExtINT
;
2707 entry1
.polarity
= entry0
.polarity
;
2711 ioapic_write_entry(apic
, pin
, entry1
);
2713 save_control
= CMOS_READ(RTC_CONTROL
);
2714 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2715 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2717 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2722 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2726 CMOS_WRITE(save_control
, RTC_CONTROL
);
2727 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2728 clear_IO_APIC_pin(apic
, pin
);
2730 ioapic_write_entry(apic
, pin
, entry0
);
2733 static int disable_timer_pin_1 __initdata
;
2734 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2735 static int __init
disable_timer_pin_setup(char *arg
)
2737 disable_timer_pin_1
= 1;
2740 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2742 int timer_through_8259 __initdata
;
2745 * This code may look a bit paranoid, but it's supposed to cooperate with
2746 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2747 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2748 * fanatically on his truly buggy board.
2750 * FIXME: really need to revamp this for all platforms.
2752 static inline void __init
check_timer(void)
2754 struct irq_cfg
*cfg
= irq_cfg(0);
2755 int apic1
, pin1
, apic2
, pin2
;
2756 unsigned long flags
;
2760 local_irq_save(flags
);
2762 ver
= apic_read(APIC_LVR
);
2763 ver
= GET_APIC_VERSION(ver
);
2766 * get/set the timer IRQ vector:
2768 disable_8259A_irq(0);
2769 assign_irq_vector(0, TARGET_CPUS
);
2772 * As IRQ0 is to be enabled in the 8259A, the virtual
2773 * wire has to be disabled in the local APIC. Also
2774 * timer interrupts need to be acknowledged manually in
2775 * the 8259A for the i82489DX when using the NMI
2776 * watchdog as that APIC treats NMIs as level-triggered.
2777 * The AEOI mode will finish them in the 8259A
2780 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2782 #ifdef CONFIG_X86_32
2783 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2786 pin1
= find_isa_irq_pin(0, mp_INT
);
2787 apic1
= find_isa_irq_apic(0, mp_INT
);
2788 pin2
= ioapic_i8259
.pin
;
2789 apic2
= ioapic_i8259
.apic
;
2791 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2792 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2793 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2796 * Some BIOS writers are clueless and report the ExtINTA
2797 * I/O APIC input from the cascaded 8259A as the timer
2798 * interrupt input. So just in case, if only one pin
2799 * was found above, try it both directly and through the
2803 #ifdef CONFIG_INTR_REMAP
2804 if (intr_remapping_enabled
)
2805 panic("BIOS bug: timer not connected to IO-APIC");
2810 } else if (pin2
== -1) {
2817 * Ok, does IRQ0 through the IOAPIC work?
2820 add_pin_to_irq(0, apic1
, pin1
);
2821 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2823 unmask_IO_APIC_irq(0);
2824 if (timer_irq_works()) {
2825 if (nmi_watchdog
== NMI_IO_APIC
) {
2827 enable_8259A_irq(0);
2829 if (disable_timer_pin_1
> 0)
2830 clear_IO_APIC_pin(0, pin1
);
2833 #ifdef CONFIG_INTR_REMAP
2834 if (intr_remapping_enabled
)
2835 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2837 clear_IO_APIC_pin(apic1
, pin1
);
2839 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2840 "8254 timer not connected to IO-APIC\n");
2842 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2843 "(IRQ0) through the 8259A ...\n");
2844 apic_printk(APIC_QUIET
, KERN_INFO
2845 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2847 * legacy devices should be connected to IO APIC #0
2849 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2850 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2851 unmask_IO_APIC_irq(0);
2852 enable_8259A_irq(0);
2853 if (timer_irq_works()) {
2854 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2855 timer_through_8259
= 1;
2856 if (nmi_watchdog
== NMI_IO_APIC
) {
2857 disable_8259A_irq(0);
2859 enable_8259A_irq(0);
2864 * Cleanup, just in case ...
2866 disable_8259A_irq(0);
2867 clear_IO_APIC_pin(apic2
, pin2
);
2868 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2871 if (nmi_watchdog
== NMI_IO_APIC
) {
2872 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2873 "through the IO-APIC - disabling NMI Watchdog!\n");
2874 nmi_watchdog
= NMI_NONE
;
2876 #ifdef CONFIG_X86_32
2880 apic_printk(APIC_QUIET
, KERN_INFO
2881 "...trying to set up timer as Virtual Wire IRQ...\n");
2883 lapic_register_intr(0);
2884 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2885 enable_8259A_irq(0);
2887 if (timer_irq_works()) {
2888 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2891 disable_8259A_irq(0);
2892 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2893 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2895 apic_printk(APIC_QUIET
, KERN_INFO
2896 "...trying to set up timer as ExtINT IRQ...\n");
2900 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2902 unlock_ExtINT_logic();
2904 if (timer_irq_works()) {
2905 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2908 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2909 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2910 "report. Then try booting with the 'noapic' option.\n");
2912 local_irq_restore(flags
);
2916 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2917 * to devices. However there may be an I/O APIC pin available for
2918 * this interrupt regardless. The pin may be left unconnected, but
2919 * typically it will be reused as an ExtINT cascade interrupt for
2920 * the master 8259A. In the MPS case such a pin will normally be
2921 * reported as an ExtINT interrupt in the MP table. With ACPI
2922 * there is no provision for ExtINT interrupts, and in the absence
2923 * of an override it would be treated as an ordinary ISA I/O APIC
2924 * interrupt, that is edge-triggered and unmasked by default. We
2925 * used to do this, but it caused problems on some systems because
2926 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2927 * the same ExtINT cascade interrupt to drive the local APIC of the
2928 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2929 * the I/O APIC in all cases now. No actual device should request
2930 * it anyway. --macro
2932 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2934 void __init
setup_IO_APIC(void)
2937 #ifdef CONFIG_X86_32
2941 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2945 io_apic_irqs
= ~PIC_IRQS
;
2947 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2949 * Set up IO-APIC IRQ routing.
2951 #ifdef CONFIG_X86_32
2953 setup_ioapic_ids_from_mpc();
2956 setup_IO_APIC_irqs();
2957 init_IO_APIC_traps();
2962 * Called after all the initialization is done. If we didnt find any
2963 * APIC bugs then we can allow the modify fast path
2966 static int __init
io_apic_bug_finalize(void)
2968 if (sis_apic_bug
== -1)
2973 late_initcall(io_apic_bug_finalize
);
2975 struct sysfs_ioapic_data
{
2976 struct sys_device dev
;
2977 struct IO_APIC_route_entry entry
[0];
2979 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2981 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2983 struct IO_APIC_route_entry
*entry
;
2984 struct sysfs_ioapic_data
*data
;
2987 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2988 entry
= data
->entry
;
2989 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2990 *entry
= ioapic_read_entry(dev
->id
, i
);
2995 static int ioapic_resume(struct sys_device
*dev
)
2997 struct IO_APIC_route_entry
*entry
;
2998 struct sysfs_ioapic_data
*data
;
2999 unsigned long flags
;
3000 union IO_APIC_reg_00 reg_00
;
3003 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3004 entry
= data
->entry
;
3006 spin_lock_irqsave(&ioapic_lock
, flags
);
3007 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3008 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
3009 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
3010 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3012 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3013 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3014 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3019 static struct sysdev_class ioapic_sysdev_class
= {
3021 .suspend
= ioapic_suspend
,
3022 .resume
= ioapic_resume
,
3025 static int __init
ioapic_init_sysfs(void)
3027 struct sys_device
* dev
;
3030 error
= sysdev_class_register(&ioapic_sysdev_class
);
3034 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3035 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3036 * sizeof(struct IO_APIC_route_entry
);
3037 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3038 if (!mp_ioapic_data
[i
]) {
3039 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3042 dev
= &mp_ioapic_data
[i
]->dev
;
3044 dev
->cls
= &ioapic_sysdev_class
;
3045 error
= sysdev_register(dev
);
3047 kfree(mp_ioapic_data
[i
]);
3048 mp_ioapic_data
[i
] = NULL
;
3049 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3057 device_initcall(ioapic_init_sysfs
);
3060 * Dynamic irq allocate and deallocation
3062 unsigned int create_irq_nr(unsigned int irq_want
)
3064 /* Allocate an unused irq */
3067 unsigned long flags
;
3068 struct irq_cfg
*cfg_new
;
3070 #ifndef CONFIG_HAVE_SPARSE_IRQ
3071 irq_want
= nr_irqs
- 1;
3075 spin_lock_irqsave(&vector_lock
, flags
);
3076 for (new = irq_want
; new > 0; new--) {
3077 if (platform_legacy_irq(new))
3079 cfg_new
= irq_cfg(new);
3080 if (cfg_new
&& cfg_new
->vector
!= 0)
3082 /* check if need to create one */
3084 cfg_new
= irq_cfg_alloc(new);
3085 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
3089 spin_unlock_irqrestore(&vector_lock
, flags
);
3092 dynamic_irq_init(irq
);
3097 int create_irq(void)
3101 irq
= create_irq_nr(nr_irqs
- 1);
3109 void destroy_irq(unsigned int irq
)
3111 unsigned long flags
;
3113 dynamic_irq_cleanup(irq
);
3115 #ifdef CONFIG_INTR_REMAP
3118 spin_lock_irqsave(&vector_lock
, flags
);
3119 __clear_irq_vector(irq
);
3120 spin_unlock_irqrestore(&vector_lock
, flags
);
3124 * MSI message composition
3126 #ifdef CONFIG_PCI_MSI
3127 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3129 struct irq_cfg
*cfg
;
3135 err
= assign_irq_vector(irq
, tmp
);
3140 cpus_and(tmp
, cfg
->domain
, tmp
);
3141 dest
= cpu_mask_to_apicid(tmp
);
3143 #ifdef CONFIG_INTR_REMAP
3144 if (irq_remapped(irq
)) {
3149 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3150 BUG_ON(ir_index
== -1);
3152 memset (&irte
, 0, sizeof(irte
));
3155 irte
.dst_mode
= INT_DEST_MODE
;
3156 irte
.trigger_mode
= 0; /* edge */
3157 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3158 irte
.vector
= cfg
->vector
;
3159 irte
.dest_id
= IRTE_DEST(dest
);
3161 modify_irte(irq
, &irte
);
3163 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3164 msg
->data
= sub_handle
;
3165 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3167 MSI_ADDR_IR_INDEX1(ir_index
) |
3168 MSI_ADDR_IR_INDEX2(ir_index
);
3172 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3175 ((INT_DEST_MODE
== 0) ?
3176 MSI_ADDR_DEST_MODE_PHYSICAL
:
3177 MSI_ADDR_DEST_MODE_LOGICAL
) |
3178 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3179 MSI_ADDR_REDIRECTION_CPU
:
3180 MSI_ADDR_REDIRECTION_LOWPRI
) |
3181 MSI_ADDR_DEST_ID(dest
);
3184 MSI_DATA_TRIGGER_EDGE
|
3185 MSI_DATA_LEVEL_ASSERT
|
3186 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3187 MSI_DATA_DELIVERY_FIXED
:
3188 MSI_DATA_DELIVERY_LOWPRI
) |
3189 MSI_DATA_VECTOR(cfg
->vector
);
3195 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3197 struct irq_cfg
*cfg
;
3201 struct irq_desc
*desc
;
3203 cpus_and(tmp
, mask
, cpu_online_map
);
3204 if (cpus_empty(tmp
))
3207 if (assign_irq_vector(irq
, mask
))
3211 cpus_and(tmp
, cfg
->domain
, mask
);
3212 dest
= cpu_mask_to_apicid(tmp
);
3214 read_msi_msg(irq
, &msg
);
3216 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3217 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3218 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3219 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3221 write_msi_msg(irq
, &msg
);
3222 desc
= irq_to_desc(irq
);
3223 desc
->affinity
= mask
;
3226 #ifdef CONFIG_INTR_REMAP
3228 * Migrate the MSI irq to another cpumask. This migration is
3229 * done in the process context using interrupt-remapping hardware.
3231 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3233 struct irq_cfg
*cfg
;
3235 cpumask_t tmp
, cleanup_mask
;
3237 struct irq_desc
*desc
;
3239 cpus_and(tmp
, mask
, cpu_online_map
);
3240 if (cpus_empty(tmp
))
3243 if (get_irte(irq
, &irte
))
3246 if (assign_irq_vector(irq
, mask
))
3250 cpus_and(tmp
, cfg
->domain
, mask
);
3251 dest
= cpu_mask_to_apicid(tmp
);
3253 irte
.vector
= cfg
->vector
;
3254 irte
.dest_id
= IRTE_DEST(dest
);
3257 * atomically update the IRTE with the new destination and vector.
3259 modify_irte(irq
, &irte
);
3262 * After this point, all the interrupts will start arriving
3263 * at the new destination. So, time to cleanup the previous
3264 * vector allocation.
3266 if (cfg
->move_in_progress
) {
3267 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
3268 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
3269 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
3270 cfg
->move_in_progress
= 0;
3273 desc
= irq_to_desc(irq
);
3274 desc
->affinity
= mask
;
3277 #endif /* CONFIG_SMP */
3280 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3281 * which implement the MSI or MSI-X Capability Structure.
3283 static struct irq_chip msi_chip
= {
3285 .unmask
= unmask_msi_irq
,
3286 .mask
= mask_msi_irq
,
3287 .ack
= ack_apic_edge
,
3289 .set_affinity
= set_msi_irq_affinity
,
3291 .retrigger
= ioapic_retrigger_irq
,
3294 #ifdef CONFIG_INTR_REMAP
3295 static struct irq_chip msi_ir_chip
= {
3296 .name
= "IR-PCI-MSI",
3297 .unmask
= unmask_msi_irq
,
3298 .mask
= mask_msi_irq
,
3299 .ack
= ack_x2apic_edge
,
3301 .set_affinity
= ir_set_msi_irq_affinity
,
3303 .retrigger
= ioapic_retrigger_irq
,
3307 * Map the PCI dev to the corresponding remapping hardware unit
3308 * and allocate 'nvec' consecutive interrupt-remapping table entries
3311 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3313 struct intel_iommu
*iommu
;
3316 iommu
= map_dev_to_ir(dev
);
3319 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3323 index
= alloc_irte(iommu
, irq
, nvec
);
3326 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3334 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
3339 ret
= msi_compose_msg(dev
, irq
, &msg
);
3343 set_irq_msi(irq
, desc
);
3344 write_msi_msg(irq
, &msg
);
3346 #ifdef CONFIG_INTR_REMAP
3347 if (irq_remapped(irq
)) {
3348 struct irq_desc
*desc
= irq_to_desc(irq
);
3350 * irq migration in process context
3352 desc
->status
|= IRQ_MOVE_PCNTXT
;
3353 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3356 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3361 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
3365 irq
= dev
->bus
->number
;
3373 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
3377 unsigned int irq_want
;
3379 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3381 irq
= create_irq_nr(irq_want
);
3385 #ifdef CONFIG_INTR_REMAP
3386 if (!intr_remapping_enabled
)
3389 ret
= msi_alloc_irte(dev
, irq
, 1);
3394 ret
= setup_msi_irq(dev
, desc
, irq
);
3401 #ifdef CONFIG_INTR_REMAP
3408 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3411 int ret
, sub_handle
;
3412 struct msi_desc
*desc
;
3413 unsigned int irq_want
;
3415 #ifdef CONFIG_INTR_REMAP
3416 struct intel_iommu
*iommu
= 0;
3420 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3422 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
3423 irq
= create_irq_nr(irq_want
--);
3426 #ifdef CONFIG_INTR_REMAP
3427 if (!intr_remapping_enabled
)
3432 * allocate the consecutive block of IRTE's
3435 index
= msi_alloc_irte(dev
, irq
, nvec
);
3441 iommu
= map_dev_to_ir(dev
);
3447 * setup the mapping between the irq and the IRTE
3448 * base index, the sub_handle pointing to the
3449 * appropriate interrupt remap table entry.
3451 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3455 ret
= setup_msi_irq(dev
, desc
, irq
);
3467 void arch_teardown_msi_irq(unsigned int irq
)
3474 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
3476 struct irq_cfg
*cfg
;
3480 struct irq_desc
*desc
;
3482 cpus_and(tmp
, mask
, cpu_online_map
);
3483 if (cpus_empty(tmp
))
3486 if (assign_irq_vector(irq
, mask
))
3490 cpus_and(tmp
, cfg
->domain
, mask
);
3491 dest
= cpu_mask_to_apicid(tmp
);
3493 dmar_msi_read(irq
, &msg
);
3495 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3496 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3497 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3498 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3500 dmar_msi_write(irq
, &msg
);
3501 desc
= irq_to_desc(irq
);
3502 desc
->affinity
= mask
;
3504 #endif /* CONFIG_SMP */
3506 struct irq_chip dmar_msi_type
= {
3508 .unmask
= dmar_msi_unmask
,
3509 .mask
= dmar_msi_mask
,
3510 .ack
= ack_apic_edge
,
3512 .set_affinity
= dmar_msi_set_affinity
,
3514 .retrigger
= ioapic_retrigger_irq
,
3517 int arch_setup_dmar_msi(unsigned int irq
)
3522 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3525 dmar_msi_write(irq
, &msg
);
3526 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3532 #ifdef CONFIG_HPET_TIMER
3535 static void hpet_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
3537 struct irq_cfg
*cfg
;
3538 struct irq_desc
*desc
;
3543 cpus_and(tmp
, mask
, cpu_online_map
);
3544 if (cpus_empty(tmp
))
3547 if (assign_irq_vector(irq
, mask
))
3551 cpus_and(tmp
, cfg
->domain
, mask
);
3552 dest
= cpu_mask_to_apicid(tmp
);
3554 hpet_msi_read(irq
, &msg
);
3556 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3557 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3558 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3559 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3561 hpet_msi_write(irq
, &msg
);
3562 desc
= irq_to_desc(irq
);
3563 desc
->affinity
= mask
;
3565 #endif /* CONFIG_SMP */
3567 struct irq_chip hpet_msi_type
= {
3569 .unmask
= hpet_msi_unmask
,
3570 .mask
= hpet_msi_mask
,
3571 .ack
= ack_apic_edge
,
3573 .set_affinity
= hpet_msi_set_affinity
,
3575 .retrigger
= ioapic_retrigger_irq
,
3578 int arch_setup_hpet_msi(unsigned int irq
)
3583 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3587 hpet_msi_write(irq
, &msg
);
3588 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3594 #endif /* CONFIG_PCI_MSI */
3596 * Hypertransport interrupt support
3598 #ifdef CONFIG_HT_IRQ
3602 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3604 struct ht_irq_msg msg
;
3605 fetch_ht_irq_msg(irq
, &msg
);
3607 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3608 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3610 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3611 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3613 write_ht_irq_msg(irq
, &msg
);
3616 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
3618 struct irq_cfg
*cfg
;
3621 struct irq_desc
*desc
;
3623 cpus_and(tmp
, mask
, cpu_online_map
);
3624 if (cpus_empty(tmp
))
3627 if (assign_irq_vector(irq
, mask
))
3631 cpus_and(tmp
, cfg
->domain
, mask
);
3632 dest
= cpu_mask_to_apicid(tmp
);
3634 target_ht_irq(irq
, dest
, cfg
->vector
);
3635 desc
= irq_to_desc(irq
);
3636 desc
->affinity
= mask
;
3640 static struct irq_chip ht_irq_chip
= {
3642 .mask
= mask_ht_irq
,
3643 .unmask
= unmask_ht_irq
,
3644 .ack
= ack_apic_edge
,
3646 .set_affinity
= set_ht_irq_affinity
,
3648 .retrigger
= ioapic_retrigger_irq
,
3651 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3653 struct irq_cfg
*cfg
;
3658 err
= assign_irq_vector(irq
, tmp
);
3660 struct ht_irq_msg msg
;
3664 cpus_and(tmp
, cfg
->domain
, tmp
);
3665 dest
= cpu_mask_to_apicid(tmp
);
3667 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3671 HT_IRQ_LOW_DEST_ID(dest
) |
3672 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3673 ((INT_DEST_MODE
== 0) ?
3674 HT_IRQ_LOW_DM_PHYSICAL
:
3675 HT_IRQ_LOW_DM_LOGICAL
) |
3676 HT_IRQ_LOW_RQEOI_EDGE
|
3677 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3678 HT_IRQ_LOW_MT_FIXED
:
3679 HT_IRQ_LOW_MT_ARBITRATED
) |
3680 HT_IRQ_LOW_IRQ_MASKED
;
3682 write_ht_irq_msg(irq
, &msg
);
3684 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3685 handle_edge_irq
, "edge");
3689 #endif /* CONFIG_HT_IRQ */
3691 int __init
io_apic_get_redir_entries (int ioapic
)
3693 union IO_APIC_reg_01 reg_01
;
3694 unsigned long flags
;
3696 spin_lock_irqsave(&ioapic_lock
, flags
);
3697 reg_01
.raw
= io_apic_read(ioapic
, 1);
3698 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3700 return reg_01
.bits
.entries
;
3703 int __init
probe_nr_irqs(void)
3710 int nr_min
= NR_IRQS
;
3713 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3714 nr
+= io_apic_get_redir_entries(idx
) + 1;
3716 /* double it for hotplug and msi and nmi */
3719 /* something wrong ? */
3726 /* --------------------------------------------------------------------------
3727 ACPI-based IOAPIC Configuration
3728 -------------------------------------------------------------------------- */
3732 #ifdef CONFIG_X86_32
3733 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3735 union IO_APIC_reg_00 reg_00
;
3736 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3738 unsigned long flags
;
3742 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3743 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3744 * supports up to 16 on one shared APIC bus.
3746 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3747 * advantage of new APIC bus architecture.
3750 if (physids_empty(apic_id_map
))
3751 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3753 spin_lock_irqsave(&ioapic_lock
, flags
);
3754 reg_00
.raw
= io_apic_read(ioapic
, 0);
3755 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3757 if (apic_id
>= get_physical_broadcast()) {
3758 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3759 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3760 apic_id
= reg_00
.bits
.ID
;
3764 * Every APIC in a system must have a unique ID or we get lots of nice
3765 * 'stuck on smp_invalidate_needed IPI wait' messages.
3767 if (check_apicid_used(apic_id_map
, apic_id
)) {
3769 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3770 if (!check_apicid_used(apic_id_map
, i
))
3774 if (i
== get_physical_broadcast())
3775 panic("Max apic_id exceeded!\n");
3777 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3778 "trying %d\n", ioapic
, apic_id
, i
);
3783 tmp
= apicid_to_cpu_present(apic_id
);
3784 physids_or(apic_id_map
, apic_id_map
, tmp
);
3786 if (reg_00
.bits
.ID
!= apic_id
) {
3787 reg_00
.bits
.ID
= apic_id
;
3789 spin_lock_irqsave(&ioapic_lock
, flags
);
3790 io_apic_write(ioapic
, 0, reg_00
.raw
);
3791 reg_00
.raw
= io_apic_read(ioapic
, 0);
3792 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3795 if (reg_00
.bits
.ID
!= apic_id
) {
3796 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3801 apic_printk(APIC_VERBOSE
, KERN_INFO
3802 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3807 int __init
io_apic_get_version(int ioapic
)
3809 union IO_APIC_reg_01 reg_01
;
3810 unsigned long flags
;
3812 spin_lock_irqsave(&ioapic_lock
, flags
);
3813 reg_01
.raw
= io_apic_read(ioapic
, 1);
3814 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3816 return reg_01
.bits
.version
;
3820 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3822 if (!IO_APIC_IRQ(irq
)) {
3823 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3829 * IRQs < 16 are already in the irq_2_pin[] map
3832 add_pin_to_irq(irq
, ioapic
, pin
);
3834 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
3840 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3844 if (skip_ioapic_setup
)
3847 for (i
= 0; i
< mp_irq_entries
; i
++)
3848 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3849 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3851 if (i
>= mp_irq_entries
)
3854 *trigger
= irq_trigger(i
);
3855 *polarity
= irq_polarity(i
);
3859 #endif /* CONFIG_ACPI */
3862 * This function currently is only a helper for the i386 smp boot process where
3863 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3864 * so mask in all cases should simply be TARGET_CPUS
3867 void __init
setup_ioapic_dest(void)
3869 int pin
, ioapic
, irq
, irq_entry
;
3870 struct irq_cfg
*cfg
;
3872 if (skip_ioapic_setup
== 1)
3875 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3876 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3877 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3878 if (irq_entry
== -1)
3880 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3882 /* setup_IO_APIC_irqs could fail to get vector for some device
3883 * when you have too many devices, because at that time only boot
3888 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3889 irq_trigger(irq_entry
),
3890 irq_polarity(irq_entry
));
3891 #ifdef CONFIG_INTR_REMAP
3892 else if (intr_remapping_enabled
)
3893 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3896 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3903 #define IOAPIC_RESOURCE_NAME_SIZE 11
3905 static struct resource
*ioapic_resources
;
3907 static struct resource
* __init
ioapic_setup_resources(void)
3910 struct resource
*res
;
3914 if (nr_ioapics
<= 0)
3917 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3920 mem
= alloc_bootmem(n
);
3924 mem
+= sizeof(struct resource
) * nr_ioapics
;
3926 for (i
= 0; i
< nr_ioapics
; i
++) {
3928 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3929 sprintf(mem
, "IOAPIC %u", i
);
3930 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3934 ioapic_resources
= res
;
3939 void __init
ioapic_init_mappings(void)
3941 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3943 struct resource
*ioapic_res
;
3945 ioapic_res
= ioapic_setup_resources();
3946 for (i
= 0; i
< nr_ioapics
; i
++) {
3947 if (smp_found_config
) {
3948 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3949 #ifdef CONFIG_X86_32
3952 "WARNING: bogus zero IO-APIC "
3953 "address found in MPTABLE, "
3954 "disabling IO/APIC support!\n");
3955 smp_found_config
= 0;
3956 skip_ioapic_setup
= 1;
3957 goto fake_ioapic_page
;
3961 #ifdef CONFIG_X86_32
3964 ioapic_phys
= (unsigned long)
3965 alloc_bootmem_pages(PAGE_SIZE
);
3966 ioapic_phys
= __pa(ioapic_phys
);
3968 set_fixmap_nocache(idx
, ioapic_phys
);
3969 apic_printk(APIC_VERBOSE
,
3970 "mapped IOAPIC to %08lx (%08lx)\n",
3971 __fix_to_virt(idx
), ioapic_phys
);
3974 if (ioapic_res
!= NULL
) {
3975 ioapic_res
->start
= ioapic_phys
;
3976 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3982 static int __init
ioapic_insert_resources(void)
3985 struct resource
*r
= ioapic_resources
;
3989 "IO APIC resources could be not be allocated.\n");
3993 for (i
= 0; i
< nr_ioapics
; i
++) {
3994 insert_resource(&iomem_resource
, r
);
4001 /* Insert the IO APIC resources after PCI initialization has occured to handle
4002 * IO APICS that are mapped in on a BAR in PCI space. */
4003 late_initcall(ioapic_insert_resources
);