2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
63 #include <mach_apic.h>
64 #include <mach_apicdef.h>
66 #define __apicdebuginit(type) static type __init
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
72 int sis_apic_bug
= -1;
74 static DEFINE_SPINLOCK(ioapic_lock
);
75 static DEFINE_SPINLOCK(vector_lock
);
78 * # of IRQ routing registers
80 int nr_ioapic_registers
[MAX_IO_APICS
];
82 /* I/O APIC entries */
83 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
86 /* MP IRQ source entries */
87 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
89 /* # of MP IRQ source entries */
92 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
93 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
96 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
98 int skip_ioapic_setup
;
100 static int __init
parse_noapic(char *str
)
102 /* disable IO-APIC */
103 disable_ioapic_setup();
106 early_param("noapic", parse_noapic
);
112 #ifdef CONFIG_HAVE_SPARSE_IRQ
113 struct irq_cfg
*next
;
115 struct irq_pin_list
*irq_2_pin
;
117 cpumask_t old_domain
;
118 unsigned move_cleanup_count
;
120 u8 move_in_progress
: 1;
123 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
124 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
125 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
126 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
127 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
128 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
129 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
130 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
131 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
132 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
133 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
134 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
135 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
136 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
137 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
138 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
139 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
140 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
143 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
145 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
147 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
150 static struct irq_cfg
*irq_cfgx
;
152 #ifdef CONFIG_HAVE_SPARSE_IRQ
154 * Protect the irq_cfgx_free freelist:
156 static DEFINE_SPINLOCK(irq_cfg_lock
);
158 static struct irq_cfg
*irq_cfgx_free
;
161 static void __init
init_work(void *data
)
163 struct dyn_array
*da
= data
;
170 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
172 legacy_count
= ARRAY_SIZE(irq_cfg_legacy
);
173 for (i
= legacy_count
; i
< *da
->nr
; i
++)
174 init_one_irq_cfg(&cfg
[i
]);
176 #ifdef CONFIG_HAVE_SPARSE_IRQ
177 for (i
= 1; i
< *da
->nr
; i
++)
178 cfg
[i
-1].next
= &cfg
[i
];
180 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
181 irq_cfgx
[legacy_count
- 1].next
= NULL
;
185 #ifdef CONFIG_HAVE_SPARSE_IRQ
186 /* need to be biger than size of irq_cfg_legacy */
187 static int nr_irq_cfg
= 32;
189 static int __init
parse_nr_irq_cfg(char *arg
)
192 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
199 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
201 #define for_each_irq_cfg(irqX, cfg) \
202 for (cfg = irq_cfgx, irqX = cfg->irq; cfg; cfg = cfg->next, irqX = cfg ? cfg->irq : -1U)
205 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
207 static struct irq_cfg
*irq_cfg(unsigned int irq
)
222 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
224 struct irq_cfg
*cfg
, *cfg_pri
;
229 cfg_pri
= cfg
= irq_cfgx
;
239 spin_lock_irqsave(&irq_cfg_lock
, flags
);
240 if (!irq_cfgx_free
) {
242 unsigned long total_bytes
;
244 * we run out of pre-allocate ones, allocate more
246 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
248 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
250 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
252 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
255 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
258 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
260 for (i
= 0; i
< nr_irq_cfg
; i
++)
261 init_one_irq_cfg(&cfg
[i
]);
263 for (i
= 1; i
< nr_irq_cfg
; i
++)
264 cfg
[i
-1].next
= &cfg
[i
];
270 irq_cfgx_free
= irq_cfgx_free
->next
;
278 spin_unlock_irqrestore(&irq_cfg_lock
, flags
);
280 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
281 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
283 /* dump the results */
286 unsigned long bytes
= sizeof(struct irq_cfg
);
288 printk(KERN_DEBUG
"=========================== %d\n", irq
);
289 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
290 for_each_irq_cfg(cfg
) {
292 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
294 printk(KERN_DEBUG
"===========================\n");
301 #define for_each_irq_cfg(irq, cfg) \
302 for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq])
304 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irqs
, PAGE_SIZE
, init_work
);
306 struct irq_cfg
*irq_cfg(unsigned int irq
)
309 return &irq_cfgx
[irq
];
313 struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
320 * This is performance-critical, we want to do it O(1)
322 * the indexing order of this array favors 1:1 mappings
323 * between pins and IRQs.
326 struct irq_pin_list
{
328 struct irq_pin_list
*next
;
331 static struct irq_pin_list
*irq_2_pin_head
;
332 /* fill one page ? */
333 static int nr_irq_2_pin
= 0x100;
334 static struct irq_pin_list
*irq_2_pin_ptr
;
335 static void __init
irq_2_pin_init_work(void *data
)
337 struct dyn_array
*da
= data
;
338 struct irq_pin_list
*pin
;
343 for (i
= 1; i
< *da
->nr
; i
++)
344 pin
[i
-1].next
= &pin
[i
];
346 irq_2_pin_ptr
= &pin
[0];
348 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
350 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
352 struct irq_pin_list
*pin
;
358 irq_2_pin_ptr
= pin
->next
;
364 * we run out of pre-allocate ones, allocate more
366 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
369 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
372 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
373 nr_irq_2_pin
, PAGE_SIZE
, 0);
376 panic("can not get more irq_2_pin\n");
378 for (i
= 1; i
< nr_irq_2_pin
; i
++)
379 pin
[i
-1].next
= &pin
[i
];
381 irq_2_pin_ptr
= pin
->next
;
389 unsigned int unused
[3];
393 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
395 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
396 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
399 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
401 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
402 writel(reg
, &io_apic
->index
);
403 return readl(&io_apic
->data
);
406 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
408 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
409 writel(reg
, &io_apic
->index
);
410 writel(value
, &io_apic
->data
);
414 * Re-write a value: to be used for read-modify-write
415 * cycles where the read already set up the index register.
417 * Older SiS APIC requires we rewrite the index register
419 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
421 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
423 writel(reg
, &io_apic
->index
);
424 writel(value
, &io_apic
->data
);
427 static bool io_apic_level_ack_pending(unsigned int irq
)
429 struct irq_pin_list
*entry
;
431 struct irq_cfg
*cfg
= irq_cfg(irq
);
433 spin_lock_irqsave(&ioapic_lock
, flags
);
434 entry
= cfg
->irq_2_pin
;
442 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
443 /* Is the remote IRR bit set? */
444 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
445 spin_unlock_irqrestore(&ioapic_lock
, flags
);
452 spin_unlock_irqrestore(&ioapic_lock
, flags
);
458 struct { u32 w1
, w2
; };
459 struct IO_APIC_route_entry entry
;
462 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
464 union entry_union eu
;
466 spin_lock_irqsave(&ioapic_lock
, flags
);
467 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
468 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
469 spin_unlock_irqrestore(&ioapic_lock
, flags
);
474 * When we write a new IO APIC routing entry, we need to write the high
475 * word first! If the mask bit in the low word is clear, we will enable
476 * the interrupt, and we need to make sure the entry is fully populated
477 * before that happens.
480 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
482 union entry_union eu
;
484 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
485 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
488 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
491 spin_lock_irqsave(&ioapic_lock
, flags
);
492 __ioapic_write_entry(apic
, pin
, e
);
493 spin_unlock_irqrestore(&ioapic_lock
, flags
);
497 * When we mask an IO APIC routing entry, we need to write the low
498 * word first, in order to set the mask bit before we change the
501 static void ioapic_mask_entry(int apic
, int pin
)
504 union entry_union eu
= { .entry
.mask
= 1 };
506 spin_lock_irqsave(&ioapic_lock
, flags
);
507 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
508 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
509 spin_unlock_irqrestore(&ioapic_lock
, flags
);
513 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
517 struct irq_pin_list
*entry
;
520 entry
= cfg
->irq_2_pin
;
529 #ifdef CONFIG_INTR_REMAP
531 * With interrupt-remapping, destination information comes
532 * from interrupt-remapping table entry.
534 if (!irq_remapped(irq
))
535 io_apic_write(apic
, 0x11 + pin
*2, dest
);
537 io_apic_write(apic
, 0x11 + pin
*2, dest
);
539 reg
= io_apic_read(apic
, 0x10 + pin
*2);
540 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
542 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
549 static int assign_irq_vector(int irq
, cpumask_t mask
);
551 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
557 struct irq_desc
*desc
;
559 cpus_and(tmp
, mask
, cpu_online_map
);
564 if (assign_irq_vector(irq
, mask
))
567 cpus_and(tmp
, cfg
->domain
, mask
);
568 dest
= cpu_mask_to_apicid(tmp
);
570 * Only the high 8 bits are valid.
572 dest
= SET_APIC_LOGICAL_ID(dest
);
574 desc
= irq_to_desc(irq
);
575 spin_lock_irqsave(&ioapic_lock
, flags
);
576 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
577 desc
->affinity
= mask
;
578 spin_unlock_irqrestore(&ioapic_lock
, flags
);
580 #endif /* CONFIG_SMP */
583 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
584 * shared ISA-space IRQs, so we have to support them. We are super
585 * fast in the common case, and fast for shared ISA-space IRQs.
587 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
590 struct irq_pin_list
*entry
;
592 /* first time to refer irq_cfg, so with new */
593 cfg
= irq_cfg_alloc(irq
);
594 entry
= cfg
->irq_2_pin
;
596 entry
= get_one_free_irq_2_pin();
597 cfg
->irq_2_pin
= entry
;
600 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
604 while (entry
->next
) {
605 /* not again, please */
606 if (entry
->apic
== apic
&& entry
->pin
== pin
)
612 entry
->next
= get_one_free_irq_2_pin();
616 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
620 * Reroute an IRQ to a different pin.
622 static void __init
replace_pin_at_irq(unsigned int irq
,
623 int oldapic
, int oldpin
,
624 int newapic
, int newpin
)
626 struct irq_cfg
*cfg
= irq_cfg(irq
);
627 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
631 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
632 entry
->apic
= newapic
;
635 /* every one is different, right? */
641 /* why? call replace before add? */
643 add_pin_to_irq(irq
, newapic
, newpin
);
646 static inline void io_apic_modify_irq(unsigned int irq
,
647 int mask_and
, int mask_or
,
648 void (*final
)(struct irq_pin_list
*entry
))
652 struct irq_pin_list
*entry
;
655 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
658 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
661 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
667 static void __unmask_IO_APIC_irq(unsigned int irq
)
669 io_apic_modify_irq(irq
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
673 void io_apic_sync(struct irq_pin_list
*entry
)
676 * Synchronize the IO-APIC and the CPU by doing
677 * a dummy read from the IO-APIC
679 struct io_apic __iomem
*io_apic
;
680 io_apic
= io_apic_base(entry
->apic
);
681 readl(&io_apic
->data
);
684 static void __mask_IO_APIC_irq(unsigned int irq
)
686 io_apic_modify_irq(irq
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
688 #else /* CONFIG_X86_32 */
689 static void __mask_IO_APIC_irq(unsigned int irq
)
691 io_apic_modify_irq(irq
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
694 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
696 io_apic_modify_irq(irq
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
697 IO_APIC_REDIR_MASKED
, NULL
);
700 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
702 io_apic_modify_irq(irq
, ~IO_APIC_REDIR_MASKED
,
703 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
705 #endif /* CONFIG_X86_32 */
707 static void mask_IO_APIC_irq (unsigned int irq
)
711 spin_lock_irqsave(&ioapic_lock
, flags
);
712 __mask_IO_APIC_irq(irq
);
713 spin_unlock_irqrestore(&ioapic_lock
, flags
);
716 static void unmask_IO_APIC_irq (unsigned int irq
)
720 spin_lock_irqsave(&ioapic_lock
, flags
);
721 __unmask_IO_APIC_irq(irq
);
722 spin_unlock_irqrestore(&ioapic_lock
, flags
);
725 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
727 struct IO_APIC_route_entry entry
;
729 /* Check delivery_mode to be sure we're not clearing an SMI pin */
730 entry
= ioapic_read_entry(apic
, pin
);
731 if (entry
.delivery_mode
== dest_SMI
)
734 * Disable it in the IO-APIC irq-routing table:
736 ioapic_mask_entry(apic
, pin
);
739 static void clear_IO_APIC (void)
743 for (apic
= 0; apic
< nr_ioapics
; apic
++)
744 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
745 clear_IO_APIC_pin(apic
, pin
);
748 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
749 void send_IPI_self(int vector
)
756 apic_wait_icr_idle();
757 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
759 * Send the IPI. The write to APIC_ICR fires this off.
761 apic_write(APIC_ICR
, cfg
);
763 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
767 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
768 * specific CPU-side IRQs.
772 static int pirq_entries
[MAX_PIRQS
];
773 static int pirqs_enabled
;
775 static int __init
ioapic_pirq_setup(char *str
)
778 int ints
[MAX_PIRQS
+1];
780 get_options(str
, ARRAY_SIZE(ints
), ints
);
782 for (i
= 0; i
< MAX_PIRQS
; i
++)
783 pirq_entries
[i
] = -1;
786 apic_printk(APIC_VERBOSE
, KERN_INFO
787 "PIRQ redirection, working around broken MP-BIOS.\n");
789 if (ints
[0] < MAX_PIRQS
)
792 for (i
= 0; i
< max
; i
++) {
793 apic_printk(APIC_VERBOSE
, KERN_DEBUG
794 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
796 * PIRQs are mapped upside down, usually.
798 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
803 __setup("pirq=", ioapic_pirq_setup
);
804 #endif /* CONFIG_X86_32 */
806 #ifdef CONFIG_INTR_REMAP
807 /* I/O APIC RTE contents at the OS boot up */
808 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
811 * Saves and masks all the unmasked IO-APIC RTE's
813 int save_mask_IO_APIC_setup(void)
815 union IO_APIC_reg_01 reg_01
;
820 * The number of IO-APIC IRQ registers (== #pins):
822 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
823 spin_lock_irqsave(&ioapic_lock
, flags
);
824 reg_01
.raw
= io_apic_read(apic
, 1);
825 spin_unlock_irqrestore(&ioapic_lock
, flags
);
826 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
829 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
830 early_ioapic_entries
[apic
] =
831 kzalloc(sizeof(struct IO_APIC_route_entry
) *
832 nr_ioapic_registers
[apic
], GFP_KERNEL
);
833 if (!early_ioapic_entries
[apic
])
837 for (apic
= 0; apic
< nr_ioapics
; apic
++)
838 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
839 struct IO_APIC_route_entry entry
;
841 entry
= early_ioapic_entries
[apic
][pin
] =
842 ioapic_read_entry(apic
, pin
);
845 ioapic_write_entry(apic
, pin
, entry
);
851 void restore_IO_APIC_setup(void)
855 for (apic
= 0; apic
< nr_ioapics
; apic
++)
856 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
857 ioapic_write_entry(apic
, pin
,
858 early_ioapic_entries
[apic
][pin
]);
861 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
864 * for now plain restore of previous settings.
865 * TBD: In the case of OS enabling interrupt-remapping,
866 * IO-APIC RTE's need to be setup to point to interrupt-remapping
867 * table entries. for now, do a plain restore, and wait for
868 * the setup_IO_APIC_irqs() to do proper initialization.
870 restore_IO_APIC_setup();
875 * Find the IRQ entry number of a certain pin.
877 static int find_irq_entry(int apic
, int pin
, int type
)
881 for (i
= 0; i
< mp_irq_entries
; i
++)
882 if (mp_irqs
[i
].mp_irqtype
== type
&&
883 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
884 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
885 mp_irqs
[i
].mp_dstirq
== pin
)
892 * Find the pin to which IRQ[irq] (ISA) is connected
894 static int __init
find_isa_irq_pin(int irq
, int type
)
898 for (i
= 0; i
< mp_irq_entries
; i
++) {
899 int lbus
= mp_irqs
[i
].mp_srcbus
;
901 if (test_bit(lbus
, mp_bus_not_pci
) &&
902 (mp_irqs
[i
].mp_irqtype
== type
) &&
903 (mp_irqs
[i
].mp_srcbusirq
== irq
))
905 return mp_irqs
[i
].mp_dstirq
;
910 static int __init
find_isa_irq_apic(int irq
, int type
)
914 for (i
= 0; i
< mp_irq_entries
; i
++) {
915 int lbus
= mp_irqs
[i
].mp_srcbus
;
917 if (test_bit(lbus
, mp_bus_not_pci
) &&
918 (mp_irqs
[i
].mp_irqtype
== type
) &&
919 (mp_irqs
[i
].mp_srcbusirq
== irq
))
922 if (i
< mp_irq_entries
) {
924 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
925 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
934 * Find a specific PCI IRQ entry.
935 * Not an __init, possibly needed by modules
937 static int pin_2_irq(int idx
, int apic
, int pin
);
939 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
941 int apic
, i
, best_guess
= -1;
943 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
945 if (test_bit(bus
, mp_bus_not_pci
)) {
946 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
949 for (i
= 0; i
< mp_irq_entries
; i
++) {
950 int lbus
= mp_irqs
[i
].mp_srcbus
;
952 for (apic
= 0; apic
< nr_ioapics
; apic
++)
953 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
954 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
957 if (!test_bit(lbus
, mp_bus_not_pci
) &&
958 !mp_irqs
[i
].mp_irqtype
&&
960 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
961 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
963 if (!(apic
|| IO_APIC_IRQ(irq
)))
966 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
969 * Use the first all-but-pin matching entry as a
970 * best-guess fuzzy result for broken mptables.
979 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
981 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
983 * EISA Edge/Level control register, ELCR
985 static int EISA_ELCR(unsigned int irq
)
988 unsigned int port
= 0x4d0 + (irq
>> 3);
989 return (inb(port
) >> (irq
& 7)) & 1;
991 apic_printk(APIC_VERBOSE
, KERN_INFO
992 "Broken MPtable reports ISA irq %d\n", irq
);
998 /* ISA interrupts are always polarity zero edge triggered,
999 * when listed as conforming in the MP table. */
1001 #define default_ISA_trigger(idx) (0)
1002 #define default_ISA_polarity(idx) (0)
1004 /* EISA interrupts are always polarity zero and can be edge or level
1005 * trigger depending on the ELCR value. If an interrupt is listed as
1006 * EISA conforming in the MP table, that means its trigger type must
1007 * be read in from the ELCR */
1009 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1010 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1012 /* PCI interrupts are always polarity one level triggered,
1013 * when listed as conforming in the MP table. */
1015 #define default_PCI_trigger(idx) (1)
1016 #define default_PCI_polarity(idx) (1)
1018 /* MCA interrupts are always polarity zero level triggered,
1019 * when listed as conforming in the MP table. */
1021 #define default_MCA_trigger(idx) (1)
1022 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1024 static int MPBIOS_polarity(int idx
)
1026 int bus
= mp_irqs
[idx
].mp_srcbus
;
1030 * Determine IRQ line polarity (high active or low active):
1032 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1034 case 0: /* conforms, ie. bus-type dependent polarity */
1035 if (test_bit(bus
, mp_bus_not_pci
))
1036 polarity
= default_ISA_polarity(idx
);
1038 polarity
= default_PCI_polarity(idx
);
1040 case 1: /* high active */
1045 case 2: /* reserved */
1047 printk(KERN_WARNING
"broken BIOS!!\n");
1051 case 3: /* low active */
1056 default: /* invalid */
1058 printk(KERN_WARNING
"broken BIOS!!\n");
1066 static int MPBIOS_trigger(int idx
)
1068 int bus
= mp_irqs
[idx
].mp_srcbus
;
1072 * Determine IRQ trigger mode (edge or level sensitive):
1074 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1076 case 0: /* conforms, ie. bus-type dependent */
1077 if (test_bit(bus
, mp_bus_not_pci
))
1078 trigger
= default_ISA_trigger(idx
);
1080 trigger
= default_PCI_trigger(idx
);
1081 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1082 switch (mp_bus_id_to_type
[bus
]) {
1083 case MP_BUS_ISA
: /* ISA pin */
1085 /* set before the switch */
1088 case MP_BUS_EISA
: /* EISA pin */
1090 trigger
= default_EISA_trigger(idx
);
1093 case MP_BUS_PCI
: /* PCI pin */
1095 /* set before the switch */
1098 case MP_BUS_MCA
: /* MCA pin */
1100 trigger
= default_MCA_trigger(idx
);
1105 printk(KERN_WARNING
"broken BIOS!!\n");
1117 case 2: /* reserved */
1119 printk(KERN_WARNING
"broken BIOS!!\n");
1128 default: /* invalid */
1130 printk(KERN_WARNING
"broken BIOS!!\n");
1138 static inline int irq_polarity(int idx
)
1140 return MPBIOS_polarity(idx
);
1143 static inline int irq_trigger(int idx
)
1145 return MPBIOS_trigger(idx
);
1148 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1149 static int pin_2_irq(int idx
, int apic
, int pin
)
1152 int bus
= mp_irqs
[idx
].mp_srcbus
;
1155 * Debugging check, we are in big trouble if this message pops up!
1157 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1158 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1160 if (test_bit(bus
, mp_bus_not_pci
)) {
1161 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1164 * PCI IRQs are mapped in order
1168 irq
+= nr_ioapic_registers
[i
++];
1171 * For MPS mode, so far only needed by ES7000 platform
1173 if (ioapic_renumber_irq
)
1174 irq
= ioapic_renumber_irq(apic
, irq
);
1177 #ifdef CONFIG_X86_32
1179 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1181 if ((pin
>= 16) && (pin
<= 23)) {
1182 if (pirq_entries
[pin
-16] != -1) {
1183 if (!pirq_entries
[pin
-16]) {
1184 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1185 "disabling PIRQ%d\n", pin
-16);
1187 irq
= pirq_entries
[pin
-16];
1188 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1189 "using PIRQ%d -> IRQ %d\n",
1199 void lock_vector_lock(void)
1201 /* Used to the online set of cpus does not change
1202 * during assign_irq_vector.
1204 spin_lock(&vector_lock
);
1207 void unlock_vector_lock(void)
1209 spin_unlock(&vector_lock
);
1212 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1215 * NOTE! The local APIC isn't very good at handling
1216 * multiple interrupts at the same interrupt level.
1217 * As the interrupt level is determined by taking the
1218 * vector number and shifting that right by 4, we
1219 * want to spread these out a bit so that they don't
1220 * all fall in the same interrupt level.
1222 * Also, we've got to be careful not to trash gate
1223 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1225 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1226 unsigned int old_vector
;
1228 struct irq_cfg
*cfg
;
1232 /* Only try and allocate irqs on cpus that are present */
1233 cpus_and(mask
, mask
, cpu_online_map
);
1235 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1238 old_vector
= cfg
->vector
;
1241 cpus_and(tmp
, cfg
->domain
, mask
);
1242 if (!cpus_empty(tmp
))
1246 for_each_cpu_mask_nr(cpu
, mask
) {
1247 cpumask_t domain
, new_mask
;
1251 domain
= vector_allocation_domain(cpu
);
1252 cpus_and(new_mask
, domain
, cpu_online_map
);
1254 vector
= current_vector
;
1255 offset
= current_offset
;
1258 if (vector
>= first_system_vector
) {
1259 /* If we run out of vectors on large boxen, must share them. */
1260 offset
= (offset
+ 1) % 8;
1261 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1263 if (unlikely(current_vector
== vector
))
1265 #ifdef CONFIG_X86_64
1266 if (vector
== IA32_SYSCALL_VECTOR
)
1269 if (vector
== SYSCALL_VECTOR
)
1272 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1273 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1276 current_vector
= vector
;
1277 current_offset
= offset
;
1279 cfg
->move_in_progress
= 1;
1280 cfg
->old_domain
= cfg
->domain
;
1282 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1283 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1284 cfg
->vector
= vector
;
1285 cfg
->domain
= domain
;
1291 static int assign_irq_vector(int irq
, cpumask_t mask
)
1294 unsigned long flags
;
1296 spin_lock_irqsave(&vector_lock
, flags
);
1297 err
= __assign_irq_vector(irq
, mask
);
1298 spin_unlock_irqrestore(&vector_lock
, flags
);
1302 static void __clear_irq_vector(int irq
)
1304 struct irq_cfg
*cfg
;
1309 BUG_ON(!cfg
->vector
);
1311 vector
= cfg
->vector
;
1312 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1313 for_each_cpu_mask_nr(cpu
, mask
)
1314 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1317 cpus_clear(cfg
->domain
);
1320 void __setup_vector_irq(int cpu
)
1322 /* Initialize vector_irq on a new cpu */
1323 /* This function must be called with vector_lock held */
1325 struct irq_cfg
*cfg
;
1327 /* Mark the inuse vectors */
1328 for_each_irq_cfg(irq
, cfg
) {
1329 if (!cpu_isset(cpu
, cfg
->domain
))
1331 vector
= cfg
->vector
;
1332 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1334 /* Mark the free vectors */
1335 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1336 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1341 if (!cpu_isset(cpu
, cfg
->domain
))
1342 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1346 static struct irq_chip ioapic_chip
;
1347 #ifdef CONFIG_INTR_REMAP
1348 static struct irq_chip ir_ioapic_chip
;
1351 #define IOAPIC_AUTO -1
1352 #define IOAPIC_EDGE 0
1353 #define IOAPIC_LEVEL 1
1355 #ifdef CONFIG_X86_32
1356 static inline int IO_APIC_irq_trigger(int irq
)
1360 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1361 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1362 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1363 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1364 return irq_trigger(idx
);
1368 * nonexistent IRQs are edge default
1373 static inline int IO_APIC_irq_trigger(int irq
)
1379 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1381 struct irq_desc
*desc
;
1383 /* first time to use this irq_desc */
1385 desc
= irq_to_desc(irq
);
1387 desc
= irq_to_desc_alloc(irq
);
1389 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1390 trigger
== IOAPIC_LEVEL
)
1391 desc
->status
|= IRQ_LEVEL
;
1393 desc
->status
&= ~IRQ_LEVEL
;
1395 #ifdef CONFIG_INTR_REMAP
1396 if (irq_remapped(irq
)) {
1397 desc
->status
|= IRQ_MOVE_PCNTXT
;
1399 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1403 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1404 handle_edge_irq
, "edge");
1408 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1409 trigger
== IOAPIC_LEVEL
)
1410 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1414 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1415 handle_edge_irq
, "edge");
1418 static int setup_ioapic_entry(int apic
, int irq
,
1419 struct IO_APIC_route_entry
*entry
,
1420 unsigned int destination
, int trigger
,
1421 int polarity
, int vector
)
1424 * add it to the IO-APIC irq-routing table:
1426 memset(entry
,0,sizeof(*entry
));
1428 #ifdef CONFIG_INTR_REMAP
1429 if (intr_remapping_enabled
) {
1430 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1432 struct IR_IO_APIC_route_entry
*ir_entry
=
1433 (struct IR_IO_APIC_route_entry
*) entry
;
1437 panic("No mapping iommu for ioapic %d\n", apic
);
1439 index
= alloc_irte(iommu
, irq
, 1);
1441 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1443 memset(&irte
, 0, sizeof(irte
));
1446 irte
.dst_mode
= INT_DEST_MODE
;
1447 irte
.trigger_mode
= trigger
;
1448 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1449 irte
.vector
= vector
;
1450 irte
.dest_id
= IRTE_DEST(destination
);
1452 modify_irte(irq
, &irte
);
1454 ir_entry
->index2
= (index
>> 15) & 0x1;
1456 ir_entry
->format
= 1;
1457 ir_entry
->index
= (index
& 0x7fff);
1461 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1462 entry
->dest_mode
= INT_DEST_MODE
;
1463 entry
->dest
= destination
;
1466 entry
->mask
= 0; /* enable IRQ */
1467 entry
->trigger
= trigger
;
1468 entry
->polarity
= polarity
;
1469 entry
->vector
= vector
;
1471 /* Mask level triggered irqs.
1472 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1479 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1480 int trigger
, int polarity
)
1482 struct irq_cfg
*cfg
;
1483 struct IO_APIC_route_entry entry
;
1486 if (!IO_APIC_IRQ(irq
))
1492 if (assign_irq_vector(irq
, mask
))
1495 cpus_and(mask
, cfg
->domain
, mask
);
1497 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1498 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1499 "IRQ %d Mode:%i Active:%i)\n",
1500 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1501 irq
, trigger
, polarity
);
1504 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1505 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1507 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1508 mp_ioapics
[apic
].mp_apicid
, pin
);
1509 __clear_irq_vector(irq
);
1513 ioapic_register_intr(irq
, trigger
);
1515 disable_8259A_irq(irq
);
1517 ioapic_write_entry(apic
, pin
, entry
);
1520 static void __init
setup_IO_APIC_irqs(void)
1522 int apic
, pin
, idx
, irq
;
1525 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1527 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1528 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1530 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1534 apic_printk(APIC_VERBOSE
,
1535 KERN_DEBUG
" %d-%d",
1536 mp_ioapics
[apic
].mp_apicid
,
1539 apic_printk(APIC_VERBOSE
, " %d-%d",
1540 mp_ioapics
[apic
].mp_apicid
,
1545 irq
= pin_2_irq(idx
, apic
, pin
);
1546 #ifdef CONFIG_X86_32
1547 if (multi_timer_check(apic
, irq
))
1550 add_pin_to_irq(irq
, apic
, pin
);
1552 setup_IO_APIC_irq(apic
, pin
, irq
,
1553 irq_trigger(idx
), irq_polarity(idx
));
1556 apic_printk(APIC_VERBOSE
,
1557 " (apicid-pin) not connected\n");
1563 apic_printk(APIC_VERBOSE
,
1564 " (apicid-pin) not connected\n");
1568 * Set up the timer pin, possibly with the 8259A-master behind.
1570 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1573 struct IO_APIC_route_entry entry
;
1575 #ifdef CONFIG_INTR_REMAP
1576 if (intr_remapping_enabled
)
1580 memset(&entry
, 0, sizeof(entry
));
1583 * We use logical delivery to get the timer IRQ
1586 entry
.dest_mode
= INT_DEST_MODE
;
1587 entry
.mask
= 1; /* mask IRQ now */
1588 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1589 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1592 entry
.vector
= vector
;
1595 * The timer IRQ doesn't have to know that behind the
1596 * scene we may have a 8259A-master in AEOI mode ...
1598 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1601 * Add it to the IO-APIC irq-routing table:
1603 ioapic_write_entry(apic
, pin
, entry
);
1607 __apicdebuginit(void) print_IO_APIC(void)
1610 union IO_APIC_reg_00 reg_00
;
1611 union IO_APIC_reg_01 reg_01
;
1612 union IO_APIC_reg_02 reg_02
;
1613 union IO_APIC_reg_03 reg_03
;
1614 unsigned long flags
;
1615 struct irq_cfg
*cfg
;
1618 if (apic_verbosity
== APIC_QUIET
)
1621 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1622 for (i
= 0; i
< nr_ioapics
; i
++)
1623 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1624 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1627 * We are a bit conservative about what we expect. We have to
1628 * know about every hardware change ASAP.
1630 printk(KERN_INFO
"testing the IO APIC.......................\n");
1632 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1634 spin_lock_irqsave(&ioapic_lock
, flags
);
1635 reg_00
.raw
= io_apic_read(apic
, 0);
1636 reg_01
.raw
= io_apic_read(apic
, 1);
1637 if (reg_01
.bits
.version
>= 0x10)
1638 reg_02
.raw
= io_apic_read(apic
, 2);
1639 if (reg_01
.bits
.version
>= 0x20)
1640 reg_03
.raw
= io_apic_read(apic
, 3);
1641 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1644 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1645 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1646 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1647 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1648 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1650 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1651 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1653 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1654 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1657 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1658 * but the value of reg_02 is read as the previous read register
1659 * value, so ignore it if reg_02 == reg_01.
1661 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1662 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1663 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1667 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1668 * or reg_03, but the value of reg_0[23] is read as the previous read
1669 * register value, so ignore it if reg_03 == reg_0[12].
1671 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1672 reg_03
.raw
!= reg_01
.raw
) {
1673 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1674 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1677 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1679 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1680 " Stat Dmod Deli Vect: \n");
1682 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1683 struct IO_APIC_route_entry entry
;
1685 entry
= ioapic_read_entry(apic
, i
);
1687 printk(KERN_DEBUG
" %02x %03X ",
1692 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1697 entry
.delivery_status
,
1699 entry
.delivery_mode
,
1704 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1705 for_each_irq_cfg(irq
, cfg
) {
1706 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1709 printk(KERN_DEBUG
"IRQ%d ", irq
);
1711 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1714 entry
= entry
->next
;
1719 printk(KERN_INFO
".................................... done.\n");
1724 __apicdebuginit(void) print_APIC_bitfield(int base
)
1729 if (apic_verbosity
== APIC_QUIET
)
1732 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1733 for (i
= 0; i
< 8; i
++) {
1734 v
= apic_read(base
+ i
*0x10);
1735 for (j
= 0; j
< 32; j
++) {
1745 __apicdebuginit(void) print_local_APIC(void *dummy
)
1747 unsigned int v
, ver
, maxlvt
;
1750 if (apic_verbosity
== APIC_QUIET
)
1753 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1754 smp_processor_id(), hard_smp_processor_id());
1755 v
= apic_read(APIC_ID
);
1756 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1757 v
= apic_read(APIC_LVR
);
1758 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1759 ver
= GET_APIC_VERSION(v
);
1760 maxlvt
= lapic_get_maxlvt();
1762 v
= apic_read(APIC_TASKPRI
);
1763 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1765 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1766 if (!APIC_XAPIC(ver
)) {
1767 v
= apic_read(APIC_ARBPRI
);
1768 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1769 v
& APIC_ARBPRI_MASK
);
1771 v
= apic_read(APIC_PROCPRI
);
1772 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1776 * Remote read supported only in the 82489DX and local APIC for
1777 * Pentium processors.
1779 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1780 v
= apic_read(APIC_RRR
);
1781 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1784 v
= apic_read(APIC_LDR
);
1785 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1786 if (!x2apic_enabled()) {
1787 v
= apic_read(APIC_DFR
);
1788 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1790 v
= apic_read(APIC_SPIV
);
1791 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1793 printk(KERN_DEBUG
"... APIC ISR field:\n");
1794 print_APIC_bitfield(APIC_ISR
);
1795 printk(KERN_DEBUG
"... APIC TMR field:\n");
1796 print_APIC_bitfield(APIC_TMR
);
1797 printk(KERN_DEBUG
"... APIC IRR field:\n");
1798 print_APIC_bitfield(APIC_IRR
);
1800 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1801 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1802 apic_write(APIC_ESR
, 0);
1804 v
= apic_read(APIC_ESR
);
1805 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1808 icr
= apic_icr_read();
1809 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1810 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1812 v
= apic_read(APIC_LVTT
);
1813 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1815 if (maxlvt
> 3) { /* PC is LVT#4. */
1816 v
= apic_read(APIC_LVTPC
);
1817 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1819 v
= apic_read(APIC_LVT0
);
1820 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1821 v
= apic_read(APIC_LVT1
);
1822 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1824 if (maxlvt
> 2) { /* ERR is LVT#3. */
1825 v
= apic_read(APIC_LVTERR
);
1826 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1829 v
= apic_read(APIC_TMICT
);
1830 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1831 v
= apic_read(APIC_TMCCT
);
1832 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1833 v
= apic_read(APIC_TDCR
);
1834 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1838 __apicdebuginit(void) print_all_local_APICs(void)
1843 for_each_online_cpu(cpu
)
1844 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1848 __apicdebuginit(void) print_PIC(void)
1851 unsigned long flags
;
1853 if (apic_verbosity
== APIC_QUIET
)
1856 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1858 spin_lock_irqsave(&i8259A_lock
, flags
);
1860 v
= inb(0xa1) << 8 | inb(0x21);
1861 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1863 v
= inb(0xa0) << 8 | inb(0x20);
1864 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1868 v
= inb(0xa0) << 8 | inb(0x20);
1872 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1874 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1876 v
= inb(0x4d1) << 8 | inb(0x4d0);
1877 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1880 __apicdebuginit(int) print_all_ICs(void)
1883 print_all_local_APICs();
1889 fs_initcall(print_all_ICs
);
1892 /* Where if anywhere is the i8259 connect in external int mode */
1893 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1895 void __init
enable_IO_APIC(void)
1897 union IO_APIC_reg_01 reg_01
;
1898 int i8259_apic
, i8259_pin
;
1900 unsigned long flags
;
1902 #ifdef CONFIG_X86_32
1905 for (i
= 0; i
< MAX_PIRQS
; i
++)
1906 pirq_entries
[i
] = -1;
1910 * The number of IO-APIC IRQ registers (== #pins):
1912 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1913 spin_lock_irqsave(&ioapic_lock
, flags
);
1914 reg_01
.raw
= io_apic_read(apic
, 1);
1915 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1916 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1918 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1920 /* See if any of the pins is in ExtINT mode */
1921 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1922 struct IO_APIC_route_entry entry
;
1923 entry
= ioapic_read_entry(apic
, pin
);
1925 /* If the interrupt line is enabled and in ExtInt mode
1926 * I have found the pin where the i8259 is connected.
1928 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1929 ioapic_i8259
.apic
= apic
;
1930 ioapic_i8259
.pin
= pin
;
1936 /* Look to see what if the MP table has reported the ExtINT */
1937 /* If we could not find the appropriate pin by looking at the ioapic
1938 * the i8259 probably is not connected the ioapic but give the
1939 * mptable a chance anyway.
1941 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1942 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1943 /* Trust the MP table if nothing is setup in the hardware */
1944 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1945 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1946 ioapic_i8259
.pin
= i8259_pin
;
1947 ioapic_i8259
.apic
= i8259_apic
;
1949 /* Complain if the MP table and the hardware disagree */
1950 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1951 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1953 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1957 * Do not trust the IO-APIC being empty at bootup
1963 * Not an __init, needed by the reboot code
1965 void disable_IO_APIC(void)
1968 * Clear the IO-APIC before rebooting:
1973 * If the i8259 is routed through an IOAPIC
1974 * Put that IOAPIC in virtual wire mode
1975 * so legacy interrupts can be delivered.
1977 if (ioapic_i8259
.pin
!= -1) {
1978 struct IO_APIC_route_entry entry
;
1980 memset(&entry
, 0, sizeof(entry
));
1981 entry
.mask
= 0; /* Enabled */
1982 entry
.trigger
= 0; /* Edge */
1984 entry
.polarity
= 0; /* High */
1985 entry
.delivery_status
= 0;
1986 entry
.dest_mode
= 0; /* Physical */
1987 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1989 entry
.dest
= read_apic_id();
1992 * Add it to the IO-APIC irq-routing table:
1994 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1997 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
2000 #ifdef CONFIG_X86_32
2002 * function to set the IO-APIC physical IDs based on the
2003 * values stored in the MPC table.
2005 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2008 static void __init
setup_ioapic_ids_from_mpc(void)
2010 union IO_APIC_reg_00 reg_00
;
2011 physid_mask_t phys_id_present_map
;
2014 unsigned char old_id
;
2015 unsigned long flags
;
2017 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2021 * Don't check I/O APIC IDs for xAPIC systems. They have
2022 * no meaning without the serial APIC bus.
2024 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2025 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2028 * This is broken; anything with a real cpu count has to
2029 * circumvent this idiocy regardless.
2031 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2034 * Set the IOAPIC ID to the value stored in the MPC table.
2036 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2038 /* Read the register 0 value */
2039 spin_lock_irqsave(&ioapic_lock
, flags
);
2040 reg_00
.raw
= io_apic_read(apic
, 0);
2041 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2043 old_id
= mp_ioapics
[apic
].mp_apicid
;
2045 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
2046 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2047 apic
, mp_ioapics
[apic
].mp_apicid
);
2048 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2050 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
2054 * Sanity check, is the ID really free? Every APIC in a
2055 * system must have a unique ID or we get lots of nice
2056 * 'stuck on smp_invalidate_needed IPI wait' messages.
2058 if (check_apicid_used(phys_id_present_map
,
2059 mp_ioapics
[apic
].mp_apicid
)) {
2060 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2061 apic
, mp_ioapics
[apic
].mp_apicid
);
2062 for (i
= 0; i
< get_physical_broadcast(); i
++)
2063 if (!physid_isset(i
, phys_id_present_map
))
2065 if (i
>= get_physical_broadcast())
2066 panic("Max APIC ID exceeded!\n");
2067 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2069 physid_set(i
, phys_id_present_map
);
2070 mp_ioapics
[apic
].mp_apicid
= i
;
2073 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2074 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2075 "phys_id_present_map\n",
2076 mp_ioapics
[apic
].mp_apicid
);
2077 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2082 * We need to adjust the IRQ routing table
2083 * if the ID changed.
2085 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2086 for (i
= 0; i
< mp_irq_entries
; i
++)
2087 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2088 mp_irqs
[i
].mp_dstapic
2089 = mp_ioapics
[apic
].mp_apicid
;
2092 * Read the right value from the MPC table and
2093 * write it into the ID register.
2095 apic_printk(APIC_VERBOSE
, KERN_INFO
2096 "...changing IO-APIC physical APIC ID to %d ...",
2097 mp_ioapics
[apic
].mp_apicid
);
2099 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2100 spin_lock_irqsave(&ioapic_lock
, flags
);
2101 io_apic_write(apic
, 0, reg_00
.raw
);
2102 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2107 spin_lock_irqsave(&ioapic_lock
, flags
);
2108 reg_00
.raw
= io_apic_read(apic
, 0);
2109 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2110 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2111 printk("could not set ID!\n");
2113 apic_printk(APIC_VERBOSE
, " ok.\n");
2118 int no_timer_check __initdata
;
2120 static int __init
notimercheck(char *s
)
2125 __setup("no_timer_check", notimercheck
);
2128 * There is a nasty bug in some older SMP boards, their mptable lies
2129 * about the timer IRQ. We do the following to work around the situation:
2131 * - timer IRQ defaults to IO-APIC IRQ
2132 * - if this function detects that timer IRQs are defunct, then we fall
2133 * back to ISA timer IRQs
2135 static int __init
timer_irq_works(void)
2137 unsigned long t1
= jiffies
;
2138 unsigned long flags
;
2143 local_save_flags(flags
);
2145 /* Let ten ticks pass... */
2146 mdelay((10 * 1000) / HZ
);
2147 local_irq_restore(flags
);
2150 * Expect a few ticks at least, to be sure some possible
2151 * glue logic does not lock up after one or two first
2152 * ticks in a non-ExtINT mode. Also the local APIC
2153 * might have cached one ExtINT interrupt. Finally, at
2154 * least one tick may be lost due to delays.
2158 if (time_after(jiffies
, t1
+ 4))
2164 * In the SMP+IOAPIC case it might happen that there are an unspecified
2165 * number of pending IRQ events unhandled. These cases are very rare,
2166 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2167 * better to do it this way as thus we do not have to be aware of
2168 * 'pending' interrupts in the IRQ path, except at this point.
2171 * Edge triggered needs to resend any interrupt
2172 * that was delayed but this is now handled in the device
2177 * Starting up a edge-triggered IO-APIC interrupt is
2178 * nasty - we need to make sure that we get the edge.
2179 * If it is already asserted for some reason, we need
2180 * return 1 to indicate that is was pending.
2182 * This is not complete - we should be able to fake
2183 * an edge even if it isn't on the 8259A...
2186 static unsigned int startup_ioapic_irq(unsigned int irq
)
2188 int was_pending
= 0;
2189 unsigned long flags
;
2191 spin_lock_irqsave(&ioapic_lock
, flags
);
2193 disable_8259A_irq(irq
);
2194 if (i8259A_irq_pending(irq
))
2197 __unmask_IO_APIC_irq(irq
);
2198 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2203 #ifdef CONFIG_X86_64
2204 static int ioapic_retrigger_irq(unsigned int irq
)
2207 struct irq_cfg
*cfg
= irq_cfg(irq
);
2208 unsigned long flags
;
2210 spin_lock_irqsave(&vector_lock
, flags
);
2211 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
2212 spin_unlock_irqrestore(&vector_lock
, flags
);
2217 static int ioapic_retrigger_irq(unsigned int irq
)
2219 send_IPI_self(irq_cfg(irq
)->vector
);
2226 * Level and edge triggered IO-APIC interrupts need different handling,
2227 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2228 * handled with the level-triggered descriptor, but that one has slightly
2229 * more overhead. Level-triggered interrupts cannot be handled with the
2230 * edge-triggered handler, without risking IRQ storms and other ugly
2236 #ifdef CONFIG_INTR_REMAP
2237 static void ir_irq_migration(struct work_struct
*work
);
2239 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2242 * Migrate the IO-APIC irq in the presence of intr-remapping.
2244 * For edge triggered, irq migration is a simple atomic update(of vector
2245 * and cpu destination) of IRTE and flush the hardware cache.
2247 * For level triggered, we need to modify the io-apic RTE aswell with the update
2248 * vector information, along with modifying IRTE with vector and destination.
2249 * So irq migration for level triggered is little bit more complex compared to
2250 * edge triggered migration. But the good news is, we use the same algorithm
2251 * for level triggered migration as we have today, only difference being,
2252 * we now initiate the irq migration from process context instead of the
2253 * interrupt context.
2255 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2256 * suppression) to the IO-APIC, level triggered irq migration will also be
2257 * as simple as edge triggered migration and we can do the irq migration
2258 * with a simple atomic update to IO-APIC RTE.
2260 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
2262 struct irq_cfg
*cfg
;
2263 struct irq_desc
*desc
;
2264 cpumask_t tmp
, cleanup_mask
;
2266 int modify_ioapic_rte
;
2268 unsigned long flags
;
2270 cpus_and(tmp
, mask
, cpu_online_map
);
2271 if (cpus_empty(tmp
))
2274 if (get_irte(irq
, &irte
))
2277 if (assign_irq_vector(irq
, mask
))
2281 cpus_and(tmp
, cfg
->domain
, mask
);
2282 dest
= cpu_mask_to_apicid(tmp
);
2284 desc
= irq_to_desc(irq
);
2285 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2286 if (modify_ioapic_rte
) {
2287 spin_lock_irqsave(&ioapic_lock
, flags
);
2288 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
2289 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2292 irte
.vector
= cfg
->vector
;
2293 irte
.dest_id
= IRTE_DEST(dest
);
2296 * Modified the IRTE and flushes the Interrupt entry cache.
2298 modify_irte(irq
, &irte
);
2300 if (cfg
->move_in_progress
) {
2301 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2302 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2303 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2304 cfg
->move_in_progress
= 0;
2307 desc
->affinity
= mask
;
2310 static int migrate_irq_remapped_level(int irq
)
2313 struct irq_desc
*desc
= irq_to_desc(irq
);
2315 mask_IO_APIC_irq(irq
);
2317 if (io_apic_level_ack_pending(irq
)) {
2319 * Interrupt in progress. Migrating irq now will change the
2320 * vector information in the IO-APIC RTE and that will confuse
2321 * the EOI broadcast performed by cpu.
2322 * So, delay the irq migration to the next instance.
2324 schedule_delayed_work(&ir_migration_work
, 1);
2328 /* everthing is clear. we have right of way */
2329 migrate_ioapic_irq(irq
, desc
->pending_mask
);
2332 desc
->status
&= ~IRQ_MOVE_PENDING
;
2333 cpus_clear(desc
->pending_mask
);
2336 unmask_IO_APIC_irq(irq
);
2340 static void ir_irq_migration(struct work_struct
*work
)
2343 struct irq_desc
*desc
;
2345 for_each_irq_desc(irq
, desc
) {
2346 if (desc
->status
& IRQ_MOVE_PENDING
) {
2347 unsigned long flags
;
2349 spin_lock_irqsave(&desc
->lock
, flags
);
2350 if (!desc
->chip
->set_affinity
||
2351 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2352 desc
->status
&= ~IRQ_MOVE_PENDING
;
2353 spin_unlock_irqrestore(&desc
->lock
, flags
);
2357 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
2358 spin_unlock_irqrestore(&desc
->lock
, flags
);
2364 * Migrates the IRQ destination in the process context.
2366 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
2368 struct irq_desc
*desc
= irq_to_desc(irq
);
2370 if (desc
->status
& IRQ_LEVEL
) {
2371 desc
->status
|= IRQ_MOVE_PENDING
;
2372 desc
->pending_mask
= mask
;
2373 migrate_irq_remapped_level(irq
);
2377 migrate_ioapic_irq(irq
, mask
);
2381 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2383 unsigned vector
, me
;
2385 #ifdef CONFIG_X86_64
2390 me
= smp_processor_id();
2391 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2393 struct irq_desc
*desc
;
2394 struct irq_cfg
*cfg
;
2395 irq
= __get_cpu_var(vector_irq
)[vector
];
2397 desc
= irq_to_desc(irq
);
2402 spin_lock(&desc
->lock
);
2403 if (!cfg
->move_cleanup_count
)
2406 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
2409 __get_cpu_var(vector_irq
)[vector
] = -1;
2410 cfg
->move_cleanup_count
--;
2412 spin_unlock(&desc
->lock
);
2418 static void irq_complete_move(unsigned int irq
)
2420 struct irq_cfg
*cfg
= irq_cfg(irq
);
2421 unsigned vector
, me
;
2423 if (likely(!cfg
->move_in_progress
))
2426 vector
= ~get_irq_regs()->orig_ax
;
2427 me
= smp_processor_id();
2428 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
2429 cpumask_t cleanup_mask
;
2431 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2432 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2433 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2434 cfg
->move_in_progress
= 0;
2438 static inline void irq_complete_move(unsigned int irq
) {}
2440 #ifdef CONFIG_INTR_REMAP
2441 static void ack_x2apic_level(unsigned int irq
)
2446 static void ack_x2apic_edge(unsigned int irq
)
2452 static void ack_apic_edge(unsigned int irq
)
2454 irq_complete_move(irq
);
2455 move_native_irq(irq
);
2459 #ifdef CONFIG_X86_32
2460 atomic_t irq_mis_count
;
2463 static void ack_apic_level(unsigned int irq
)
2465 #ifdef CONFIG_X86_32
2469 int do_unmask_irq
= 0;
2471 irq_complete_move(irq
);
2472 #ifdef CONFIG_GENERIC_PENDING_IRQ
2473 /* If we are moving the irq we need to mask it */
2474 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2476 mask_IO_APIC_irq(irq
);
2480 #ifdef CONFIG_X86_32
2482 * It appears there is an erratum which affects at least version 0x11
2483 * of I/O APIC (that's the 82093AA and cores integrated into various
2484 * chipsets). Under certain conditions a level-triggered interrupt is
2485 * erroneously delivered as edge-triggered one but the respective IRR
2486 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2487 * message but it will never arrive and further interrupts are blocked
2488 * from the source. The exact reason is so far unknown, but the
2489 * phenomenon was observed when two consecutive interrupt requests
2490 * from a given source get delivered to the same CPU and the source is
2491 * temporarily disabled in between.
2493 * A workaround is to simulate an EOI message manually. We achieve it
2494 * by setting the trigger mode to edge and then to level when the edge
2495 * trigger mode gets detected in the TMR of a local APIC for a
2496 * level-triggered interrupt. We mask the source for the time of the
2497 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2498 * The idea is from Manfred Spraul. --macro
2500 i
= irq_cfg(irq
)->vector
;
2502 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2506 * We must acknowledge the irq before we move it or the acknowledge will
2507 * not propagate properly.
2511 /* Now we can move and renable the irq */
2512 if (unlikely(do_unmask_irq
)) {
2513 /* Only migrate the irq if the ack has been received.
2515 * On rare occasions the broadcast level triggered ack gets
2516 * delayed going to ioapics, and if we reprogram the
2517 * vector while Remote IRR is still set the irq will never
2520 * To prevent this scenario we read the Remote IRR bit
2521 * of the ioapic. This has two effects.
2522 * - On any sane system the read of the ioapic will
2523 * flush writes (and acks) going to the ioapic from
2525 * - We get to see if the ACK has actually been delivered.
2527 * Based on failed experiments of reprogramming the
2528 * ioapic entry from outside of irq context starting
2529 * with masking the ioapic entry and then polling until
2530 * Remote IRR was clear before reprogramming the
2531 * ioapic I don't trust the Remote IRR bit to be
2532 * completey accurate.
2534 * However there appears to be no other way to plug
2535 * this race, so if the Remote IRR bit is not
2536 * accurate and is causing problems then it is a hardware bug
2537 * and you can go talk to the chipset vendor about it.
2539 if (!io_apic_level_ack_pending(irq
))
2540 move_masked_irq(irq
);
2541 unmask_IO_APIC_irq(irq
);
2544 #ifdef CONFIG_X86_32
2545 if (!(v
& (1 << (i
& 0x1f)))) {
2546 atomic_inc(&irq_mis_count
);
2547 spin_lock(&ioapic_lock
);
2548 __mask_and_edge_IO_APIC_irq(irq
);
2549 __unmask_and_level_IO_APIC_irq(irq
);
2550 spin_unlock(&ioapic_lock
);
2555 static struct irq_chip ioapic_chip __read_mostly
= {
2557 .startup
= startup_ioapic_irq
,
2558 .mask
= mask_IO_APIC_irq
,
2559 .unmask
= unmask_IO_APIC_irq
,
2560 .ack
= ack_apic_edge
,
2561 .eoi
= ack_apic_level
,
2563 .set_affinity
= set_ioapic_affinity_irq
,
2565 .retrigger
= ioapic_retrigger_irq
,
2568 #ifdef CONFIG_INTR_REMAP
2569 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2570 .name
= "IR-IO-APIC",
2571 .startup
= startup_ioapic_irq
,
2572 .mask
= mask_IO_APIC_irq
,
2573 .unmask
= unmask_IO_APIC_irq
,
2574 .ack
= ack_x2apic_edge
,
2575 .eoi
= ack_x2apic_level
,
2577 .set_affinity
= set_ir_ioapic_affinity_irq
,
2579 .retrigger
= ioapic_retrigger_irq
,
2583 static inline void init_IO_APIC_traps(void)
2586 struct irq_desc
*desc
;
2587 struct irq_cfg
*cfg
;
2590 * NOTE! The local APIC isn't very good at handling
2591 * multiple interrupts at the same interrupt level.
2592 * As the interrupt level is determined by taking the
2593 * vector number and shifting that right by 4, we
2594 * want to spread these out a bit so that they don't
2595 * all fall in the same interrupt level.
2597 * Also, we've got to be careful not to trash gate
2598 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2600 for_each_irq_cfg(irq
, cfg
) {
2601 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2603 * Hmm.. We don't have an entry for this,
2604 * so default to an old-fashioned 8259
2605 * interrupt if we can..
2608 make_8259A_irq(irq
);
2610 desc
= irq_to_desc(irq
);
2611 /* Strange. Oh, well.. */
2612 desc
->chip
= &no_irq_chip
;
2619 * The local APIC irq-chip implementation:
2622 static void mask_lapic_irq(unsigned int irq
)
2626 v
= apic_read(APIC_LVT0
);
2627 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2630 static void unmask_lapic_irq(unsigned int irq
)
2634 v
= apic_read(APIC_LVT0
);
2635 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2638 static void ack_lapic_irq (unsigned int irq
)
2643 static struct irq_chip lapic_chip __read_mostly
= {
2644 .name
= "local-APIC",
2645 .mask
= mask_lapic_irq
,
2646 .unmask
= unmask_lapic_irq
,
2647 .ack
= ack_lapic_irq
,
2650 static void lapic_register_intr(int irq
)
2652 struct irq_desc
*desc
;
2654 desc
= irq_to_desc(irq
);
2655 desc
->status
&= ~IRQ_LEVEL
;
2656 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2660 static void __init
setup_nmi(void)
2663 * Dirty trick to enable the NMI watchdog ...
2664 * We put the 8259A master into AEOI mode and
2665 * unmask on all local APICs LVT0 as NMI.
2667 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2668 * is from Maciej W. Rozycki - so we do not have to EOI from
2669 * the NMI handler or the timer interrupt.
2671 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2673 enable_NMI_through_LVT0();
2675 apic_printk(APIC_VERBOSE
, " done.\n");
2679 * This looks a bit hackish but it's about the only one way of sending
2680 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2681 * not support the ExtINT mode, unfortunately. We need to send these
2682 * cycles as some i82489DX-based boards have glue logic that keeps the
2683 * 8259A interrupt line asserted until INTA. --macro
2685 static inline void __init
unlock_ExtINT_logic(void)
2688 struct IO_APIC_route_entry entry0
, entry1
;
2689 unsigned char save_control
, save_freq_select
;
2691 pin
= find_isa_irq_pin(8, mp_INT
);
2696 apic
= find_isa_irq_apic(8, mp_INT
);
2702 entry0
= ioapic_read_entry(apic
, pin
);
2703 clear_IO_APIC_pin(apic
, pin
);
2705 memset(&entry1
, 0, sizeof(entry1
));
2707 entry1
.dest_mode
= 0; /* physical delivery */
2708 entry1
.mask
= 0; /* unmask IRQ now */
2709 entry1
.dest
= hard_smp_processor_id();
2710 entry1
.delivery_mode
= dest_ExtINT
;
2711 entry1
.polarity
= entry0
.polarity
;
2715 ioapic_write_entry(apic
, pin
, entry1
);
2717 save_control
= CMOS_READ(RTC_CONTROL
);
2718 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2719 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2721 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2726 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2730 CMOS_WRITE(save_control
, RTC_CONTROL
);
2731 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2732 clear_IO_APIC_pin(apic
, pin
);
2734 ioapic_write_entry(apic
, pin
, entry0
);
2737 static int disable_timer_pin_1 __initdata
;
2738 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2739 static int __init
disable_timer_pin_setup(char *arg
)
2741 disable_timer_pin_1
= 1;
2744 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2746 int timer_through_8259 __initdata
;
2749 * This code may look a bit paranoid, but it's supposed to cooperate with
2750 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2751 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2752 * fanatically on his truly buggy board.
2754 * FIXME: really need to revamp this for all platforms.
2756 static inline void __init
check_timer(void)
2758 struct irq_cfg
*cfg
= irq_cfg(0);
2759 int apic1
, pin1
, apic2
, pin2
;
2760 unsigned long flags
;
2764 local_irq_save(flags
);
2766 ver
= apic_read(APIC_LVR
);
2767 ver
= GET_APIC_VERSION(ver
);
2770 * get/set the timer IRQ vector:
2772 disable_8259A_irq(0);
2773 assign_irq_vector(0, TARGET_CPUS
);
2776 * As IRQ0 is to be enabled in the 8259A, the virtual
2777 * wire has to be disabled in the local APIC. Also
2778 * timer interrupts need to be acknowledged manually in
2779 * the 8259A for the i82489DX when using the NMI
2780 * watchdog as that APIC treats NMIs as level-triggered.
2781 * The AEOI mode will finish them in the 8259A
2784 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2786 #ifdef CONFIG_X86_32
2787 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2790 pin1
= find_isa_irq_pin(0, mp_INT
);
2791 apic1
= find_isa_irq_apic(0, mp_INT
);
2792 pin2
= ioapic_i8259
.pin
;
2793 apic2
= ioapic_i8259
.apic
;
2795 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2796 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2797 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2800 * Some BIOS writers are clueless and report the ExtINTA
2801 * I/O APIC input from the cascaded 8259A as the timer
2802 * interrupt input. So just in case, if only one pin
2803 * was found above, try it both directly and through the
2807 #ifdef CONFIG_INTR_REMAP
2808 if (intr_remapping_enabled
)
2809 panic("BIOS bug: timer not connected to IO-APIC");
2814 } else if (pin2
== -1) {
2821 * Ok, does IRQ0 through the IOAPIC work?
2824 add_pin_to_irq(0, apic1
, pin1
);
2825 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2827 unmask_IO_APIC_irq(0);
2828 if (timer_irq_works()) {
2829 if (nmi_watchdog
== NMI_IO_APIC
) {
2831 enable_8259A_irq(0);
2833 if (disable_timer_pin_1
> 0)
2834 clear_IO_APIC_pin(0, pin1
);
2837 #ifdef CONFIG_INTR_REMAP
2838 if (intr_remapping_enabled
)
2839 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2841 clear_IO_APIC_pin(apic1
, pin1
);
2843 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2844 "8254 timer not connected to IO-APIC\n");
2846 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2847 "(IRQ0) through the 8259A ...\n");
2848 apic_printk(APIC_QUIET
, KERN_INFO
2849 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2851 * legacy devices should be connected to IO APIC #0
2853 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2854 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2855 unmask_IO_APIC_irq(0);
2856 enable_8259A_irq(0);
2857 if (timer_irq_works()) {
2858 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2859 timer_through_8259
= 1;
2860 if (nmi_watchdog
== NMI_IO_APIC
) {
2861 disable_8259A_irq(0);
2863 enable_8259A_irq(0);
2868 * Cleanup, just in case ...
2870 disable_8259A_irq(0);
2871 clear_IO_APIC_pin(apic2
, pin2
);
2872 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2875 if (nmi_watchdog
== NMI_IO_APIC
) {
2876 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2877 "through the IO-APIC - disabling NMI Watchdog!\n");
2878 nmi_watchdog
= NMI_NONE
;
2880 #ifdef CONFIG_X86_32
2884 apic_printk(APIC_QUIET
, KERN_INFO
2885 "...trying to set up timer as Virtual Wire IRQ...\n");
2887 lapic_register_intr(0);
2888 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2889 enable_8259A_irq(0);
2891 if (timer_irq_works()) {
2892 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2895 disable_8259A_irq(0);
2896 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2897 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2899 apic_printk(APIC_QUIET
, KERN_INFO
2900 "...trying to set up timer as ExtINT IRQ...\n");
2904 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2906 unlock_ExtINT_logic();
2908 if (timer_irq_works()) {
2909 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2912 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2913 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2914 "report. Then try booting with the 'noapic' option.\n");
2916 local_irq_restore(flags
);
2920 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2921 * to devices. However there may be an I/O APIC pin available for
2922 * this interrupt regardless. The pin may be left unconnected, but
2923 * typically it will be reused as an ExtINT cascade interrupt for
2924 * the master 8259A. In the MPS case such a pin will normally be
2925 * reported as an ExtINT interrupt in the MP table. With ACPI
2926 * there is no provision for ExtINT interrupts, and in the absence
2927 * of an override it would be treated as an ordinary ISA I/O APIC
2928 * interrupt, that is edge-triggered and unmasked by default. We
2929 * used to do this, but it caused problems on some systems because
2930 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2931 * the same ExtINT cascade interrupt to drive the local APIC of the
2932 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2933 * the I/O APIC in all cases now. No actual device should request
2934 * it anyway. --macro
2936 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2938 void __init
setup_IO_APIC(void)
2941 #ifdef CONFIG_X86_32
2945 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2949 io_apic_irqs
= ~PIC_IRQS
;
2951 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2953 * Set up IO-APIC IRQ routing.
2955 #ifdef CONFIG_X86_32
2957 setup_ioapic_ids_from_mpc();
2960 setup_IO_APIC_irqs();
2961 init_IO_APIC_traps();
2966 * Called after all the initialization is done. If we didnt find any
2967 * APIC bugs then we can allow the modify fast path
2970 static int __init
io_apic_bug_finalize(void)
2972 if (sis_apic_bug
== -1)
2977 late_initcall(io_apic_bug_finalize
);
2979 struct sysfs_ioapic_data
{
2980 struct sys_device dev
;
2981 struct IO_APIC_route_entry entry
[0];
2983 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2985 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2987 struct IO_APIC_route_entry
*entry
;
2988 struct sysfs_ioapic_data
*data
;
2991 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2992 entry
= data
->entry
;
2993 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2994 *entry
= ioapic_read_entry(dev
->id
, i
);
2999 static int ioapic_resume(struct sys_device
*dev
)
3001 struct IO_APIC_route_entry
*entry
;
3002 struct sysfs_ioapic_data
*data
;
3003 unsigned long flags
;
3004 union IO_APIC_reg_00 reg_00
;
3007 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3008 entry
= data
->entry
;
3010 spin_lock_irqsave(&ioapic_lock
, flags
);
3011 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3012 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
3013 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
3014 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3016 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3017 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3018 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3023 static struct sysdev_class ioapic_sysdev_class
= {
3025 .suspend
= ioapic_suspend
,
3026 .resume
= ioapic_resume
,
3029 static int __init
ioapic_init_sysfs(void)
3031 struct sys_device
* dev
;
3034 error
= sysdev_class_register(&ioapic_sysdev_class
);
3038 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3039 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3040 * sizeof(struct IO_APIC_route_entry
);
3041 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3042 if (!mp_ioapic_data
[i
]) {
3043 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3046 dev
= &mp_ioapic_data
[i
]->dev
;
3048 dev
->cls
= &ioapic_sysdev_class
;
3049 error
= sysdev_register(dev
);
3051 kfree(mp_ioapic_data
[i
]);
3052 mp_ioapic_data
[i
] = NULL
;
3053 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3061 device_initcall(ioapic_init_sysfs
);
3064 * Dynamic irq allocate and deallocation
3066 unsigned int create_irq_nr(unsigned int irq_want
)
3068 /* Allocate an unused irq */
3071 unsigned long flags
;
3072 struct irq_cfg
*cfg_new
;
3074 #ifndef CONFIG_HAVE_SPARSE_IRQ
3075 irq_want
= nr_irqs
- 1;
3079 spin_lock_irqsave(&vector_lock
, flags
);
3080 for (new = irq_want
; new > 0; new--) {
3081 if (platform_legacy_irq(new))
3083 cfg_new
= irq_cfg(new);
3084 if (cfg_new
&& cfg_new
->vector
!= 0)
3086 /* check if need to create one */
3088 cfg_new
= irq_cfg_alloc(new);
3089 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
3093 spin_unlock_irqrestore(&vector_lock
, flags
);
3096 dynamic_irq_init(irq
);
3101 int create_irq(void)
3105 irq
= create_irq_nr(nr_irqs
- 1);
3113 void destroy_irq(unsigned int irq
)
3115 unsigned long flags
;
3117 dynamic_irq_cleanup(irq
);
3119 #ifdef CONFIG_INTR_REMAP
3122 spin_lock_irqsave(&vector_lock
, flags
);
3123 __clear_irq_vector(irq
);
3124 spin_unlock_irqrestore(&vector_lock
, flags
);
3128 * MSI message composition
3130 #ifdef CONFIG_PCI_MSI
3131 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3133 struct irq_cfg
*cfg
;
3139 err
= assign_irq_vector(irq
, tmp
);
3144 cpus_and(tmp
, cfg
->domain
, tmp
);
3145 dest
= cpu_mask_to_apicid(tmp
);
3147 #ifdef CONFIG_INTR_REMAP
3148 if (irq_remapped(irq
)) {
3153 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3154 BUG_ON(ir_index
== -1);
3156 memset (&irte
, 0, sizeof(irte
));
3159 irte
.dst_mode
= INT_DEST_MODE
;
3160 irte
.trigger_mode
= 0; /* edge */
3161 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3162 irte
.vector
= cfg
->vector
;
3163 irte
.dest_id
= IRTE_DEST(dest
);
3165 modify_irte(irq
, &irte
);
3167 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3168 msg
->data
= sub_handle
;
3169 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3171 MSI_ADDR_IR_INDEX1(ir_index
) |
3172 MSI_ADDR_IR_INDEX2(ir_index
);
3176 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3179 ((INT_DEST_MODE
== 0) ?
3180 MSI_ADDR_DEST_MODE_PHYSICAL
:
3181 MSI_ADDR_DEST_MODE_LOGICAL
) |
3182 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3183 MSI_ADDR_REDIRECTION_CPU
:
3184 MSI_ADDR_REDIRECTION_LOWPRI
) |
3185 MSI_ADDR_DEST_ID(dest
);
3188 MSI_DATA_TRIGGER_EDGE
|
3189 MSI_DATA_LEVEL_ASSERT
|
3190 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3191 MSI_DATA_DELIVERY_FIXED
:
3192 MSI_DATA_DELIVERY_LOWPRI
) |
3193 MSI_DATA_VECTOR(cfg
->vector
);
3199 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3201 struct irq_cfg
*cfg
;
3205 struct irq_desc
*desc
;
3207 cpus_and(tmp
, mask
, cpu_online_map
);
3208 if (cpus_empty(tmp
))
3211 if (assign_irq_vector(irq
, mask
))
3215 cpus_and(tmp
, cfg
->domain
, mask
);
3216 dest
= cpu_mask_to_apicid(tmp
);
3218 read_msi_msg(irq
, &msg
);
3220 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3221 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3222 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3223 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3225 write_msi_msg(irq
, &msg
);
3226 desc
= irq_to_desc(irq
);
3227 desc
->affinity
= mask
;
3230 #ifdef CONFIG_INTR_REMAP
3232 * Migrate the MSI irq to another cpumask. This migration is
3233 * done in the process context using interrupt-remapping hardware.
3235 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
3237 struct irq_cfg
*cfg
;
3239 cpumask_t tmp
, cleanup_mask
;
3241 struct irq_desc
*desc
;
3243 cpus_and(tmp
, mask
, cpu_online_map
);
3244 if (cpus_empty(tmp
))
3247 if (get_irte(irq
, &irte
))
3250 if (assign_irq_vector(irq
, mask
))
3254 cpus_and(tmp
, cfg
->domain
, mask
);
3255 dest
= cpu_mask_to_apicid(tmp
);
3257 irte
.vector
= cfg
->vector
;
3258 irte
.dest_id
= IRTE_DEST(dest
);
3261 * atomically update the IRTE with the new destination and vector.
3263 modify_irte(irq
, &irte
);
3266 * After this point, all the interrupts will start arriving
3267 * at the new destination. So, time to cleanup the previous
3268 * vector allocation.
3270 if (cfg
->move_in_progress
) {
3271 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
3272 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
3273 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
3274 cfg
->move_in_progress
= 0;
3277 desc
= irq_to_desc(irq
);
3278 desc
->affinity
= mask
;
3281 #endif /* CONFIG_SMP */
3284 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3285 * which implement the MSI or MSI-X Capability Structure.
3287 static struct irq_chip msi_chip
= {
3289 .unmask
= unmask_msi_irq
,
3290 .mask
= mask_msi_irq
,
3291 .ack
= ack_apic_edge
,
3293 .set_affinity
= set_msi_irq_affinity
,
3295 .retrigger
= ioapic_retrigger_irq
,
3298 #ifdef CONFIG_INTR_REMAP
3299 static struct irq_chip msi_ir_chip
= {
3300 .name
= "IR-PCI-MSI",
3301 .unmask
= unmask_msi_irq
,
3302 .mask
= mask_msi_irq
,
3303 .ack
= ack_x2apic_edge
,
3305 .set_affinity
= ir_set_msi_irq_affinity
,
3307 .retrigger
= ioapic_retrigger_irq
,
3311 * Map the PCI dev to the corresponding remapping hardware unit
3312 * and allocate 'nvec' consecutive interrupt-remapping table entries
3315 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3317 struct intel_iommu
*iommu
;
3320 iommu
= map_dev_to_ir(dev
);
3323 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3327 index
= alloc_irte(iommu
, irq
, nvec
);
3330 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3338 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
3343 ret
= msi_compose_msg(dev
, irq
, &msg
);
3347 set_irq_msi(irq
, desc
);
3348 write_msi_msg(irq
, &msg
);
3350 #ifdef CONFIG_INTR_REMAP
3351 if (irq_remapped(irq
)) {
3352 struct irq_desc
*desc
= irq_to_desc(irq
);
3354 * irq migration in process context
3356 desc
->status
|= IRQ_MOVE_PCNTXT
;
3357 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3360 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3365 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
3369 irq
= dev
->bus
->number
;
3377 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
3381 unsigned int irq_want
;
3383 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3385 irq
= create_irq_nr(irq_want
);
3389 #ifdef CONFIG_INTR_REMAP
3390 if (!intr_remapping_enabled
)
3393 ret
= msi_alloc_irte(dev
, irq
, 1);
3398 ret
= setup_msi_irq(dev
, desc
, irq
);
3405 #ifdef CONFIG_INTR_REMAP
3412 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3415 int ret
, sub_handle
;
3416 struct msi_desc
*desc
;
3417 unsigned int irq_want
;
3419 #ifdef CONFIG_INTR_REMAP
3420 struct intel_iommu
*iommu
= 0;
3424 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
3426 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
3427 irq
= create_irq_nr(irq_want
--);
3430 #ifdef CONFIG_INTR_REMAP
3431 if (!intr_remapping_enabled
)
3436 * allocate the consecutive block of IRTE's
3439 index
= msi_alloc_irte(dev
, irq
, nvec
);
3445 iommu
= map_dev_to_ir(dev
);
3451 * setup the mapping between the irq and the IRTE
3452 * base index, the sub_handle pointing to the
3453 * appropriate interrupt remap table entry.
3455 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3459 ret
= setup_msi_irq(dev
, desc
, irq
);
3471 void arch_teardown_msi_irq(unsigned int irq
)
3478 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
3480 struct irq_cfg
*cfg
;
3484 struct irq_desc
*desc
;
3486 cpus_and(tmp
, mask
, cpu_online_map
);
3487 if (cpus_empty(tmp
))
3490 if (assign_irq_vector(irq
, mask
))
3494 cpus_and(tmp
, cfg
->domain
, mask
);
3495 dest
= cpu_mask_to_apicid(tmp
);
3497 dmar_msi_read(irq
, &msg
);
3499 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3500 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3501 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3502 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3504 dmar_msi_write(irq
, &msg
);
3505 desc
= irq_to_desc(irq
);
3506 desc
->affinity
= mask
;
3508 #endif /* CONFIG_SMP */
3510 struct irq_chip dmar_msi_type
= {
3512 .unmask
= dmar_msi_unmask
,
3513 .mask
= dmar_msi_mask
,
3514 .ack
= ack_apic_edge
,
3516 .set_affinity
= dmar_msi_set_affinity
,
3518 .retrigger
= ioapic_retrigger_irq
,
3521 int arch_setup_dmar_msi(unsigned int irq
)
3526 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3529 dmar_msi_write(irq
, &msg
);
3530 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3536 #ifdef CONFIG_HPET_TIMER
3539 static void hpet_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
3541 struct irq_cfg
*cfg
;
3542 struct irq_desc
*desc
;
3547 cpus_and(tmp
, mask
, cpu_online_map
);
3548 if (cpus_empty(tmp
))
3551 if (assign_irq_vector(irq
, mask
))
3555 cpus_and(tmp
, cfg
->domain
, mask
);
3556 dest
= cpu_mask_to_apicid(tmp
);
3558 hpet_msi_read(irq
, &msg
);
3560 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3561 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3562 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3563 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3565 hpet_msi_write(irq
, &msg
);
3566 desc
= irq_to_desc(irq
);
3567 desc
->affinity
= mask
;
3569 #endif /* CONFIG_SMP */
3571 struct irq_chip hpet_msi_type
= {
3573 .unmask
= hpet_msi_unmask
,
3574 .mask
= hpet_msi_mask
,
3575 .ack
= ack_apic_edge
,
3577 .set_affinity
= hpet_msi_set_affinity
,
3579 .retrigger
= ioapic_retrigger_irq
,
3582 int arch_setup_hpet_msi(unsigned int irq
)
3587 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3591 hpet_msi_write(irq
, &msg
);
3592 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3598 #endif /* CONFIG_PCI_MSI */
3600 * Hypertransport interrupt support
3602 #ifdef CONFIG_HT_IRQ
3606 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3608 struct ht_irq_msg msg
;
3609 fetch_ht_irq_msg(irq
, &msg
);
3611 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3612 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3614 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3615 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3617 write_ht_irq_msg(irq
, &msg
);
3620 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
3622 struct irq_cfg
*cfg
;
3625 struct irq_desc
*desc
;
3627 cpus_and(tmp
, mask
, cpu_online_map
);
3628 if (cpus_empty(tmp
))
3631 if (assign_irq_vector(irq
, mask
))
3635 cpus_and(tmp
, cfg
->domain
, mask
);
3636 dest
= cpu_mask_to_apicid(tmp
);
3638 target_ht_irq(irq
, dest
, cfg
->vector
);
3639 desc
= irq_to_desc(irq
);
3640 desc
->affinity
= mask
;
3644 static struct irq_chip ht_irq_chip
= {
3646 .mask
= mask_ht_irq
,
3647 .unmask
= unmask_ht_irq
,
3648 .ack
= ack_apic_edge
,
3650 .set_affinity
= set_ht_irq_affinity
,
3652 .retrigger
= ioapic_retrigger_irq
,
3655 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3657 struct irq_cfg
*cfg
;
3662 err
= assign_irq_vector(irq
, tmp
);
3664 struct ht_irq_msg msg
;
3668 cpus_and(tmp
, cfg
->domain
, tmp
);
3669 dest
= cpu_mask_to_apicid(tmp
);
3671 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3675 HT_IRQ_LOW_DEST_ID(dest
) |
3676 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3677 ((INT_DEST_MODE
== 0) ?
3678 HT_IRQ_LOW_DM_PHYSICAL
:
3679 HT_IRQ_LOW_DM_LOGICAL
) |
3680 HT_IRQ_LOW_RQEOI_EDGE
|
3681 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3682 HT_IRQ_LOW_MT_FIXED
:
3683 HT_IRQ_LOW_MT_ARBITRATED
) |
3684 HT_IRQ_LOW_IRQ_MASKED
;
3686 write_ht_irq_msg(irq
, &msg
);
3688 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3689 handle_edge_irq
, "edge");
3693 #endif /* CONFIG_HT_IRQ */
3695 int __init
io_apic_get_redir_entries (int ioapic
)
3697 union IO_APIC_reg_01 reg_01
;
3698 unsigned long flags
;
3700 spin_lock_irqsave(&ioapic_lock
, flags
);
3701 reg_01
.raw
= io_apic_read(ioapic
, 1);
3702 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3704 return reg_01
.bits
.entries
;
3707 int __init
probe_nr_irqs(void)
3714 int nr_min
= NR_IRQS
;
3717 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3718 nr
+= io_apic_get_redir_entries(idx
) + 1;
3720 /* double it for hotplug and msi and nmi */
3723 /* something wrong ? */
3730 /* --------------------------------------------------------------------------
3731 ACPI-based IOAPIC Configuration
3732 -------------------------------------------------------------------------- */
3736 #ifdef CONFIG_X86_32
3737 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3739 union IO_APIC_reg_00 reg_00
;
3740 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3742 unsigned long flags
;
3746 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3747 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3748 * supports up to 16 on one shared APIC bus.
3750 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3751 * advantage of new APIC bus architecture.
3754 if (physids_empty(apic_id_map
))
3755 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3757 spin_lock_irqsave(&ioapic_lock
, flags
);
3758 reg_00
.raw
= io_apic_read(ioapic
, 0);
3759 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3761 if (apic_id
>= get_physical_broadcast()) {
3762 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3763 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3764 apic_id
= reg_00
.bits
.ID
;
3768 * Every APIC in a system must have a unique ID or we get lots of nice
3769 * 'stuck on smp_invalidate_needed IPI wait' messages.
3771 if (check_apicid_used(apic_id_map
, apic_id
)) {
3773 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3774 if (!check_apicid_used(apic_id_map
, i
))
3778 if (i
== get_physical_broadcast())
3779 panic("Max apic_id exceeded!\n");
3781 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3782 "trying %d\n", ioapic
, apic_id
, i
);
3787 tmp
= apicid_to_cpu_present(apic_id
);
3788 physids_or(apic_id_map
, apic_id_map
, tmp
);
3790 if (reg_00
.bits
.ID
!= apic_id
) {
3791 reg_00
.bits
.ID
= apic_id
;
3793 spin_lock_irqsave(&ioapic_lock
, flags
);
3794 io_apic_write(ioapic
, 0, reg_00
.raw
);
3795 reg_00
.raw
= io_apic_read(ioapic
, 0);
3796 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3799 if (reg_00
.bits
.ID
!= apic_id
) {
3800 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3805 apic_printk(APIC_VERBOSE
, KERN_INFO
3806 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3811 int __init
io_apic_get_version(int ioapic
)
3813 union IO_APIC_reg_01 reg_01
;
3814 unsigned long flags
;
3816 spin_lock_irqsave(&ioapic_lock
, flags
);
3817 reg_01
.raw
= io_apic_read(ioapic
, 1);
3818 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3820 return reg_01
.bits
.version
;
3824 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3826 if (!IO_APIC_IRQ(irq
)) {
3827 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3833 * IRQs < 16 are already in the irq_2_pin[] map
3836 add_pin_to_irq(irq
, ioapic
, pin
);
3838 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
3844 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3848 if (skip_ioapic_setup
)
3851 for (i
= 0; i
< mp_irq_entries
; i
++)
3852 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3853 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3855 if (i
>= mp_irq_entries
)
3858 *trigger
= irq_trigger(i
);
3859 *polarity
= irq_polarity(i
);
3863 #endif /* CONFIG_ACPI */
3866 * This function currently is only a helper for the i386 smp boot process where
3867 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3868 * so mask in all cases should simply be TARGET_CPUS
3871 void __init
setup_ioapic_dest(void)
3873 int pin
, ioapic
, irq
, irq_entry
;
3874 struct irq_cfg
*cfg
;
3876 if (skip_ioapic_setup
== 1)
3879 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3880 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3881 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3882 if (irq_entry
== -1)
3884 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3886 /* setup_IO_APIC_irqs could fail to get vector for some device
3887 * when you have too many devices, because at that time only boot
3892 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3893 irq_trigger(irq_entry
),
3894 irq_polarity(irq_entry
));
3895 #ifdef CONFIG_INTR_REMAP
3896 else if (intr_remapping_enabled
)
3897 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3900 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3907 #define IOAPIC_RESOURCE_NAME_SIZE 11
3909 static struct resource
*ioapic_resources
;
3911 static struct resource
* __init
ioapic_setup_resources(void)
3914 struct resource
*res
;
3918 if (nr_ioapics
<= 0)
3921 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3924 mem
= alloc_bootmem(n
);
3928 mem
+= sizeof(struct resource
) * nr_ioapics
;
3930 for (i
= 0; i
< nr_ioapics
; i
++) {
3932 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3933 sprintf(mem
, "IOAPIC %u", i
);
3934 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3938 ioapic_resources
= res
;
3943 void __init
ioapic_init_mappings(void)
3945 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3947 struct resource
*ioapic_res
;
3949 ioapic_res
= ioapic_setup_resources();
3950 for (i
= 0; i
< nr_ioapics
; i
++) {
3951 if (smp_found_config
) {
3952 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3953 #ifdef CONFIG_X86_32
3956 "WARNING: bogus zero IO-APIC "
3957 "address found in MPTABLE, "
3958 "disabling IO/APIC support!\n");
3959 smp_found_config
= 0;
3960 skip_ioapic_setup
= 1;
3961 goto fake_ioapic_page
;
3965 #ifdef CONFIG_X86_32
3968 ioapic_phys
= (unsigned long)
3969 alloc_bootmem_pages(PAGE_SIZE
);
3970 ioapic_phys
= __pa(ioapic_phys
);
3972 set_fixmap_nocache(idx
, ioapic_phys
);
3973 apic_printk(APIC_VERBOSE
,
3974 "mapped IOAPIC to %08lx (%08lx)\n",
3975 __fix_to_virt(idx
), ioapic_phys
);
3978 if (ioapic_res
!= NULL
) {
3979 ioapic_res
->start
= ioapic_phys
;
3980 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3986 static int __init
ioapic_insert_resources(void)
3989 struct resource
*r
= ioapic_resources
;
3993 "IO APIC resources could be not be allocated.\n");
3997 for (i
= 0; i
< nr_ioapics
; i
++) {
3998 insert_resource(&iomem_resource
, r
);
4005 /* Insert the IO APIC resources after PCI initialization has occured to handle
4006 * IO APICS that are mapped in on a BAR in PCI space. */
4007 late_initcall(ioapic_insert_resources
);