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033ad953bee33a60d37f8971d064b76f5b03cd37
[deliverable/linux.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
40
41 #include <asm/io.h>
42 #include <asm/smp.h>
43 #include <asm/desc.h>
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
50
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
53
54 #define __apicdebuginit(type) static type __init
55
56 int (*ioapic_renumber_irq)(int ioapic, int irq);
57 atomic_t irq_mis_count;
58
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
61
62 static DEFINE_SPINLOCK(ioapic_lock);
63 DEFINE_SPINLOCK(vector_lock);
64
65 int timer_through_8259 __initdata;
66
67 /*
68 * Is the SiS APIC rmw bug present ?
69 * -1 = don't know, 0 = no, 1 = yes
70 */
71 int sis_apic_bug = -1;
72
73 int first_free_entry;
74 /*
75 * # of IRQ routing registers
76 */
77 int nr_ioapic_registers[MAX_IO_APICS];
78
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
81 int nr_ioapics;
82
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
85
86 /* # of MP IRQ source entries */
87 int mp_irq_entries;
88
89 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
90 int mp_bus_id_to_type[MAX_MP_BUSSES];
91 #endif
92
93 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
94
95 static int disable_timer_pin_1 __initdata;
96
97 struct irq_cfg {
98 u8 vector;
99 };
100
101
102 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
103 static struct irq_cfg irq_cfg_legacy[] __initdata = {
104 [0] = { .vector = FIRST_DEVICE_VECTOR, },
105 };
106
107 static void __init init_work(void *data)
108 {
109 struct dyn_array *da = data;
110 struct irq_cfg *cfg;
111 int legacy_count;
112 int i;
113
114 cfg = *da->name;
115
116 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
117
118 BUG_ON(legacy_count > nr_irqs);
119
120 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
121 }
122
123 static struct irq_cfg *irq_cfgx;
124 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
125
126 static struct irq_cfg *irq_cfg(unsigned int irq)
127 {
128 if (irq >= nr_irqs)
129 return NULL;
130
131 return &irq_cfgx[irq];
132 }
133
134 /*
135 * Rough estimation of how many shared IRQs there are, can
136 * be changed anytime.
137 */
138 int pin_map_size;
139
140 /*
141 * This is performance-critical, we want to do it O(1)
142 *
143 * the indexing order of this array favors 1:1 mappings
144 * between pins and IRQs.
145 */
146
147 static struct irq_pin_list {
148 int apic, pin, next;
149 } *irq_2_pin;
150
151 DEFINE_DYN_ARRAY(irq_2_pin, sizeof(struct irq_pin_list), pin_map_size, 16, NULL);
152
153 struct io_apic {
154 unsigned int index;
155 unsigned int unused[3];
156 unsigned int data;
157 };
158
159 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
160 {
161 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
162 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
163 }
164
165 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
166 {
167 struct io_apic __iomem *io_apic = io_apic_base(apic);
168 writel(reg, &io_apic->index);
169 return readl(&io_apic->data);
170 }
171
172 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
173 {
174 struct io_apic __iomem *io_apic = io_apic_base(apic);
175 writel(reg, &io_apic->index);
176 writel(value, &io_apic->data);
177 }
178
179 /*
180 * Re-write a value: to be used for read-modify-write
181 * cycles where the read already set up the index register.
182 *
183 * Older SiS APIC requires we rewrite the index register
184 */
185 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
186 {
187 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
188 if (sis_apic_bug)
189 writel(reg, &io_apic->index);
190 writel(value, &io_apic->data);
191 }
192
193 union entry_union {
194 struct { u32 w1, w2; };
195 struct IO_APIC_route_entry entry;
196 };
197
198 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
199 {
200 union entry_union eu;
201 unsigned long flags;
202 spin_lock_irqsave(&ioapic_lock, flags);
203 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
204 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
205 spin_unlock_irqrestore(&ioapic_lock, flags);
206 return eu.entry;
207 }
208
209 /*
210 * When we write a new IO APIC routing entry, we need to write the high
211 * word first! If the mask bit in the low word is clear, we will enable
212 * the interrupt, and we need to make sure the entry is fully populated
213 * before that happens.
214 */
215 static void
216 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
217 {
218 union entry_union eu;
219 eu.entry = e;
220 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
221 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
222 }
223
224 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
225 {
226 unsigned long flags;
227 spin_lock_irqsave(&ioapic_lock, flags);
228 __ioapic_write_entry(apic, pin, e);
229 spin_unlock_irqrestore(&ioapic_lock, flags);
230 }
231
232 /*
233 * When we mask an IO APIC routing entry, we need to write the low
234 * word first, in order to set the mask bit before we change the
235 * high bits!
236 */
237 static void ioapic_mask_entry(int apic, int pin)
238 {
239 unsigned long flags;
240 union entry_union eu = { .entry.mask = 1 };
241
242 spin_lock_irqsave(&ioapic_lock, flags);
243 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
244 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
245 spin_unlock_irqrestore(&ioapic_lock, flags);
246 }
247
248 /*
249 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
250 * shared ISA-space IRQs, so we have to support them. We are super
251 * fast in the common case, and fast for shared ISA-space IRQs.
252 */
253 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
254 {
255 struct irq_pin_list *entry = irq_2_pin + irq;
256
257 while (entry->next)
258 entry = irq_2_pin + entry->next;
259
260 if (entry->pin != -1) {
261 entry->next = first_free_entry;
262 entry = irq_2_pin + entry->next;
263 if (++first_free_entry >= pin_map_size)
264 panic("io_apic.c: whoops");
265 }
266 entry->apic = apic;
267 entry->pin = pin;
268 }
269
270 /*
271 * Reroute an IRQ to a different pin.
272 */
273 static void __init replace_pin_at_irq(unsigned int irq,
274 int oldapic, int oldpin,
275 int newapic, int newpin)
276 {
277 struct irq_pin_list *entry = irq_2_pin + irq;
278
279 while (1) {
280 if (entry->apic == oldapic && entry->pin == oldpin) {
281 entry->apic = newapic;
282 entry->pin = newpin;
283 }
284 if (!entry->next)
285 break;
286 entry = irq_2_pin + entry->next;
287 }
288 }
289
290 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
291 {
292 struct irq_pin_list *entry = irq_2_pin + irq;
293 unsigned int pin, reg;
294
295 for (;;) {
296 pin = entry->pin;
297 if (pin == -1)
298 break;
299 reg = io_apic_read(entry->apic, 0x10 + pin*2);
300 reg &= ~disable;
301 reg |= enable;
302 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
303 if (!entry->next)
304 break;
305 entry = irq_2_pin + entry->next;
306 }
307 }
308
309 /* mask = 1 */
310 static void __mask_IO_APIC_irq(unsigned int irq)
311 {
312 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
313 }
314
315 /* mask = 0 */
316 static void __unmask_IO_APIC_irq(unsigned int irq)
317 {
318 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
319 }
320
321 /* mask = 1, trigger = 0 */
322 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
323 {
324 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
325 IO_APIC_REDIR_LEVEL_TRIGGER);
326 }
327
328 /* mask = 0, trigger = 1 */
329 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
330 {
331 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
332 IO_APIC_REDIR_MASKED);
333 }
334
335 static void mask_IO_APIC_irq(unsigned int irq)
336 {
337 unsigned long flags;
338
339 spin_lock_irqsave(&ioapic_lock, flags);
340 __mask_IO_APIC_irq(irq);
341 spin_unlock_irqrestore(&ioapic_lock, flags);
342 }
343
344 static void unmask_IO_APIC_irq(unsigned int irq)
345 {
346 unsigned long flags;
347
348 spin_lock_irqsave(&ioapic_lock, flags);
349 __unmask_IO_APIC_irq(irq);
350 spin_unlock_irqrestore(&ioapic_lock, flags);
351 }
352
353 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
354 {
355 struct IO_APIC_route_entry entry;
356
357 /* Check delivery_mode to be sure we're not clearing an SMI pin */
358 entry = ioapic_read_entry(apic, pin);
359 if (entry.delivery_mode == dest_SMI)
360 return;
361
362 /*
363 * Disable it in the IO-APIC irq-routing table:
364 */
365 ioapic_mask_entry(apic, pin);
366 }
367
368 static void clear_IO_APIC(void)
369 {
370 int apic, pin;
371
372 for (apic = 0; apic < nr_ioapics; apic++)
373 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
374 clear_IO_APIC_pin(apic, pin);
375 }
376
377 #ifdef CONFIG_SMP
378 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
379 {
380 unsigned long flags;
381 int pin;
382 struct irq_pin_list *entry = irq_2_pin + irq;
383 unsigned int apicid_value;
384 cpumask_t tmp;
385 struct irq_desc *desc;
386
387 cpus_and(tmp, cpumask, cpu_online_map);
388 if (cpus_empty(tmp))
389 tmp = TARGET_CPUS;
390
391 cpus_and(cpumask, tmp, CPU_MASK_ALL);
392
393 apicid_value = cpu_mask_to_apicid(cpumask);
394 /* Prepare to do the io_apic_write */
395 apicid_value = apicid_value << 24;
396 spin_lock_irqsave(&ioapic_lock, flags);
397 for (;;) {
398 pin = entry->pin;
399 if (pin == -1)
400 break;
401 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
402 if (!entry->next)
403 break;
404 entry = irq_2_pin + entry->next;
405 }
406 desc = irq_to_desc(irq);
407 desc->affinity = cpumask;
408 spin_unlock_irqrestore(&ioapic_lock, flags);
409 }
410
411 #endif /* CONFIG_SMP */
412
413 #ifndef CONFIG_SMP
414 void send_IPI_self(int vector)
415 {
416 unsigned int cfg;
417
418 /*
419 * Wait for idle.
420 */
421 apic_wait_icr_idle();
422 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
423 /*
424 * Send the IPI. The write to APIC_ICR fires this off.
425 */
426 apic_write(APIC_ICR, cfg);
427 }
428 #endif /* !CONFIG_SMP */
429
430
431 /*
432 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
433 * specific CPU-side IRQs.
434 */
435
436 #define MAX_PIRQS 8
437 static int pirq_entries [MAX_PIRQS];
438 static int pirqs_enabled;
439 int skip_ioapic_setup;
440
441 static int __init ioapic_pirq_setup(char *str)
442 {
443 int i, max;
444 int ints[MAX_PIRQS+1];
445
446 get_options(str, ARRAY_SIZE(ints), ints);
447
448 for (i = 0; i < MAX_PIRQS; i++)
449 pirq_entries[i] = -1;
450
451 pirqs_enabled = 1;
452 apic_printk(APIC_VERBOSE, KERN_INFO
453 "PIRQ redirection, working around broken MP-BIOS.\n");
454 max = MAX_PIRQS;
455 if (ints[0] < MAX_PIRQS)
456 max = ints[0];
457
458 for (i = 0; i < max; i++) {
459 apic_printk(APIC_VERBOSE, KERN_DEBUG
460 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
461 /*
462 * PIRQs are mapped upside down, usually.
463 */
464 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
465 }
466 return 1;
467 }
468
469 __setup("pirq=", ioapic_pirq_setup);
470
471 /*
472 * Find the IRQ entry number of a certain pin.
473 */
474 static int find_irq_entry(int apic, int pin, int type)
475 {
476 int i;
477
478 for (i = 0; i < mp_irq_entries; i++)
479 if (mp_irqs[i].mp_irqtype == type &&
480 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
481 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
482 mp_irqs[i].mp_dstirq == pin)
483 return i;
484
485 return -1;
486 }
487
488 /*
489 * Find the pin to which IRQ[irq] (ISA) is connected
490 */
491 static int __init find_isa_irq_pin(int irq, int type)
492 {
493 int i;
494
495 for (i = 0; i < mp_irq_entries; i++) {
496 int lbus = mp_irqs[i].mp_srcbus;
497
498 if (test_bit(lbus, mp_bus_not_pci) &&
499 (mp_irqs[i].mp_irqtype == type) &&
500 (mp_irqs[i].mp_srcbusirq == irq))
501
502 return mp_irqs[i].mp_dstirq;
503 }
504 return -1;
505 }
506
507 static int __init find_isa_irq_apic(int irq, int type)
508 {
509 int i;
510
511 for (i = 0; i < mp_irq_entries; i++) {
512 int lbus = mp_irqs[i].mp_srcbus;
513
514 if (test_bit(lbus, mp_bus_not_pci) &&
515 (mp_irqs[i].mp_irqtype == type) &&
516 (mp_irqs[i].mp_srcbusirq == irq))
517 break;
518 }
519 if (i < mp_irq_entries) {
520 int apic;
521 for (apic = 0; apic < nr_ioapics; apic++) {
522 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
523 return apic;
524 }
525 }
526
527 return -1;
528 }
529
530 /*
531 * Find a specific PCI IRQ entry.
532 * Not an __init, possibly needed by modules
533 */
534 static int pin_2_irq(int idx, int apic, int pin);
535
536 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
537 {
538 int apic, i, best_guess = -1;
539
540 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
541 "slot:%d, pin:%d.\n", bus, slot, pin);
542 if (test_bit(bus, mp_bus_not_pci)) {
543 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
544 return -1;
545 }
546 for (i = 0; i < mp_irq_entries; i++) {
547 int lbus = mp_irqs[i].mp_srcbus;
548
549 for (apic = 0; apic < nr_ioapics; apic++)
550 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
551 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
552 break;
553
554 if (!test_bit(lbus, mp_bus_not_pci) &&
555 !mp_irqs[i].mp_irqtype &&
556 (bus == lbus) &&
557 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
558 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
559
560 if (!(apic || IO_APIC_IRQ(irq)))
561 continue;
562
563 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
564 return irq;
565 /*
566 * Use the first all-but-pin matching entry as a
567 * best-guess fuzzy result for broken mptables.
568 */
569 if (best_guess < 0)
570 best_guess = irq;
571 }
572 }
573 return best_guess;
574 }
575 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
576
577 /*
578 * This function currently is only a helper for the i386 smp boot process where
579 * we need to reprogram the ioredtbls to cater for the cpus which have come online
580 * so mask in all cases should simply be TARGET_CPUS
581 */
582 #ifdef CONFIG_SMP
583 void __init setup_ioapic_dest(void)
584 {
585 int pin, ioapic, irq, irq_entry;
586
587 if (skip_ioapic_setup == 1)
588 return;
589
590 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
591 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
592 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
593 if (irq_entry == -1)
594 continue;
595 irq = pin_2_irq(irq_entry, ioapic, pin);
596 set_ioapic_affinity_irq(irq, TARGET_CPUS);
597 }
598
599 }
600 }
601 #endif
602
603 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
604 /*
605 * EISA Edge/Level control register, ELCR
606 */
607 static int EISA_ELCR(unsigned int irq)
608 {
609 if (irq < 16) {
610 unsigned int port = 0x4d0 + (irq >> 3);
611 return (inb(port) >> (irq & 7)) & 1;
612 }
613 apic_printk(APIC_VERBOSE, KERN_INFO
614 "Broken MPtable reports ISA irq %d\n", irq);
615 return 0;
616 }
617 #endif
618
619 /* ISA interrupts are always polarity zero edge triggered,
620 * when listed as conforming in the MP table. */
621
622 #define default_ISA_trigger(idx) (0)
623 #define default_ISA_polarity(idx) (0)
624
625 /* EISA interrupts are always polarity zero and can be edge or level
626 * trigger depending on the ELCR value. If an interrupt is listed as
627 * EISA conforming in the MP table, that means its trigger type must
628 * be read in from the ELCR */
629
630 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
631 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
632
633 /* PCI interrupts are always polarity one level triggered,
634 * when listed as conforming in the MP table. */
635
636 #define default_PCI_trigger(idx) (1)
637 #define default_PCI_polarity(idx) (1)
638
639 /* MCA interrupts are always polarity zero level triggered,
640 * when listed as conforming in the MP table. */
641
642 #define default_MCA_trigger(idx) (1)
643 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
644
645 static int MPBIOS_polarity(int idx)
646 {
647 int bus = mp_irqs[idx].mp_srcbus;
648 int polarity;
649
650 /*
651 * Determine IRQ line polarity (high active or low active):
652 */
653 switch (mp_irqs[idx].mp_irqflag & 3) {
654 case 0: /* conforms, ie. bus-type dependent polarity */
655 {
656 polarity = test_bit(bus, mp_bus_not_pci)?
657 default_ISA_polarity(idx):
658 default_PCI_polarity(idx);
659 break;
660 }
661 case 1: /* high active */
662 {
663 polarity = 0;
664 break;
665 }
666 case 2: /* reserved */
667 {
668 printk(KERN_WARNING "broken BIOS!!\n");
669 polarity = 1;
670 break;
671 }
672 case 3: /* low active */
673 {
674 polarity = 1;
675 break;
676 }
677 default: /* invalid */
678 {
679 printk(KERN_WARNING "broken BIOS!!\n");
680 polarity = 1;
681 break;
682 }
683 }
684 return polarity;
685 }
686
687 static int MPBIOS_trigger(int idx)
688 {
689 int bus = mp_irqs[idx].mp_srcbus;
690 int trigger;
691
692 /*
693 * Determine IRQ trigger mode (edge or level sensitive):
694 */
695 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
696 case 0: /* conforms, ie. bus-type dependent */
697 {
698 trigger = test_bit(bus, mp_bus_not_pci)?
699 default_ISA_trigger(idx):
700 default_PCI_trigger(idx);
701 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
702 switch (mp_bus_id_to_type[bus]) {
703 case MP_BUS_ISA: /* ISA pin */
704 {
705 /* set before the switch */
706 break;
707 }
708 case MP_BUS_EISA: /* EISA pin */
709 {
710 trigger = default_EISA_trigger(idx);
711 break;
712 }
713 case MP_BUS_PCI: /* PCI pin */
714 {
715 /* set before the switch */
716 break;
717 }
718 case MP_BUS_MCA: /* MCA pin */
719 {
720 trigger = default_MCA_trigger(idx);
721 break;
722 }
723 default:
724 {
725 printk(KERN_WARNING "broken BIOS!!\n");
726 trigger = 1;
727 break;
728 }
729 }
730 #endif
731 break;
732 }
733 case 1: /* edge */
734 {
735 trigger = 0;
736 break;
737 }
738 case 2: /* reserved */
739 {
740 printk(KERN_WARNING "broken BIOS!!\n");
741 trigger = 1;
742 break;
743 }
744 case 3: /* level */
745 {
746 trigger = 1;
747 break;
748 }
749 default: /* invalid */
750 {
751 printk(KERN_WARNING "broken BIOS!!\n");
752 trigger = 0;
753 break;
754 }
755 }
756 return trigger;
757 }
758
759 static inline int irq_polarity(int idx)
760 {
761 return MPBIOS_polarity(idx);
762 }
763
764 static inline int irq_trigger(int idx)
765 {
766 return MPBIOS_trigger(idx);
767 }
768
769 static int pin_2_irq(int idx, int apic, int pin)
770 {
771 int irq, i;
772 int bus = mp_irqs[idx].mp_srcbus;
773
774 /*
775 * Debugging check, we are in big trouble if this message pops up!
776 */
777 if (mp_irqs[idx].mp_dstirq != pin)
778 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
779
780 if (test_bit(bus, mp_bus_not_pci))
781 irq = mp_irqs[idx].mp_srcbusirq;
782 else {
783 /*
784 * PCI IRQs are mapped in order
785 */
786 i = irq = 0;
787 while (i < apic)
788 irq += nr_ioapic_registers[i++];
789 irq += pin;
790
791 /*
792 * For MPS mode, so far only needed by ES7000 platform
793 */
794 if (ioapic_renumber_irq)
795 irq = ioapic_renumber_irq(apic, irq);
796 }
797
798 /*
799 * PCI IRQ command line redirection. Yes, limits are hardcoded.
800 */
801 if ((pin >= 16) && (pin <= 23)) {
802 if (pirq_entries[pin-16] != -1) {
803 if (!pirq_entries[pin-16]) {
804 apic_printk(APIC_VERBOSE, KERN_DEBUG
805 "disabling PIRQ%d\n", pin-16);
806 } else {
807 irq = pirq_entries[pin-16];
808 apic_printk(APIC_VERBOSE, KERN_DEBUG
809 "using PIRQ%d -> IRQ %d\n",
810 pin-16, irq);
811 }
812 }
813 }
814 return irq;
815 }
816
817 static inline int IO_APIC_irq_trigger(int irq)
818 {
819 int apic, idx, pin;
820
821 for (apic = 0; apic < nr_ioapics; apic++) {
822 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
823 idx = find_irq_entry(apic, pin, mp_INT);
824 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
825 return irq_trigger(idx);
826 }
827 }
828 /*
829 * nonexistent IRQs are edge default
830 */
831 return 0;
832 }
833
834
835 static int __assign_irq_vector(int irq)
836 {
837 static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
838 int vector, offset;
839
840 BUG_ON((unsigned)irq >= nr_irqs);
841
842 if (irq_cfg(irq)->vector > 0)
843 return irq_cfg(irq)->vector;
844
845 vector = current_vector;
846 offset = current_offset;
847 next:
848 vector += 8;
849 if (vector >= first_system_vector) {
850 offset = (offset + 1) % 8;
851 vector = FIRST_DEVICE_VECTOR + offset;
852 }
853 if (vector == current_vector)
854 return -ENOSPC;
855 if (test_and_set_bit(vector, used_vectors))
856 goto next;
857
858 current_vector = vector;
859 current_offset = offset;
860 irq_cfg(irq)->vector = vector;
861
862 return vector;
863 }
864
865 static int assign_irq_vector(int irq)
866 {
867 unsigned long flags;
868 int vector;
869
870 spin_lock_irqsave(&vector_lock, flags);
871 vector = __assign_irq_vector(irq);
872 spin_unlock_irqrestore(&vector_lock, flags);
873
874 return vector;
875 }
876
877 static struct irq_chip ioapic_chip;
878
879 #define IOAPIC_AUTO -1
880 #define IOAPIC_EDGE 0
881 #define IOAPIC_LEVEL 1
882
883 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
884 {
885 struct irq_desc *desc;
886
887 desc = irq_to_desc(irq);
888 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
889 trigger == IOAPIC_LEVEL) {
890 desc->status |= IRQ_LEVEL;
891 set_irq_chip_and_handler_name(irq, &ioapic_chip,
892 handle_fasteoi_irq, "fasteoi");
893 } else {
894 desc->status &= ~IRQ_LEVEL;
895 set_irq_chip_and_handler_name(irq, &ioapic_chip,
896 handle_edge_irq, "edge");
897 }
898 set_intr_gate(vector, interrupt[irq]);
899 }
900
901 static void __init setup_IO_APIC_irqs(void)
902 {
903 struct IO_APIC_route_entry entry;
904 int apic, pin, idx, irq, first_notcon = 1, vector;
905
906 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
907
908 for (apic = 0; apic < nr_ioapics; apic++) {
909 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
910
911 /*
912 * add it to the IO-APIC irq-routing table:
913 */
914 memset(&entry, 0, sizeof(entry));
915
916 entry.delivery_mode = INT_DELIVERY_MODE;
917 entry.dest_mode = INT_DEST_MODE;
918 entry.mask = 0; /* enable IRQ */
919 entry.dest.logical.logical_dest =
920 cpu_mask_to_apicid(TARGET_CPUS);
921
922 idx = find_irq_entry(apic, pin, mp_INT);
923 if (idx == -1) {
924 if (first_notcon) {
925 apic_printk(APIC_VERBOSE, KERN_DEBUG
926 " IO-APIC (apicid-pin) %d-%d",
927 mp_ioapics[apic].mp_apicid,
928 pin);
929 first_notcon = 0;
930 } else
931 apic_printk(APIC_VERBOSE, ", %d-%d",
932 mp_ioapics[apic].mp_apicid, pin);
933 continue;
934 }
935
936 if (!first_notcon) {
937 apic_printk(APIC_VERBOSE, " not connected.\n");
938 first_notcon = 1;
939 }
940
941 entry.trigger = irq_trigger(idx);
942 entry.polarity = irq_polarity(idx);
943
944 if (irq_trigger(idx)) {
945 entry.trigger = 1;
946 entry.mask = 1;
947 }
948
949 irq = pin_2_irq(idx, apic, pin);
950 /*
951 * skip adding the timer int on secondary nodes, which causes
952 * a small but painful rift in the time-space continuum
953 */
954 if (multi_timer_check(apic, irq))
955 continue;
956 else
957 add_pin_to_irq(irq, apic, pin);
958
959 if (!apic && !IO_APIC_IRQ(irq))
960 continue;
961
962 if (IO_APIC_IRQ(irq)) {
963 vector = assign_irq_vector(irq);
964 entry.vector = vector;
965 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
966
967 if (!apic && (irq < 16))
968 disable_8259A_irq(irq);
969 }
970 ioapic_write_entry(apic, pin, entry);
971 }
972 }
973
974 if (!first_notcon)
975 apic_printk(APIC_VERBOSE, " not connected.\n");
976 }
977
978 /*
979 * Set up the timer pin, possibly with the 8259A-master behind.
980 */
981 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
982 int vector)
983 {
984 struct IO_APIC_route_entry entry;
985
986 memset(&entry, 0, sizeof(entry));
987
988 /*
989 * We use logical delivery to get the timer IRQ
990 * to the first CPU.
991 */
992 entry.dest_mode = INT_DEST_MODE;
993 entry.mask = 1; /* mask IRQ now */
994 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
995 entry.delivery_mode = INT_DELIVERY_MODE;
996 entry.polarity = 0;
997 entry.trigger = 0;
998 entry.vector = vector;
999
1000 /*
1001 * The timer IRQ doesn't have to know that behind the
1002 * scene we may have a 8259A-master in AEOI mode ...
1003 */
1004 ioapic_register_intr(0, vector, IOAPIC_EDGE);
1005
1006 /*
1007 * Add it to the IO-APIC irq-routing table:
1008 */
1009 ioapic_write_entry(apic, pin, entry);
1010 }
1011
1012
1013 __apicdebuginit(void) print_IO_APIC(void)
1014 {
1015 int apic, i;
1016 union IO_APIC_reg_00 reg_00;
1017 union IO_APIC_reg_01 reg_01;
1018 union IO_APIC_reg_02 reg_02;
1019 union IO_APIC_reg_03 reg_03;
1020 unsigned long flags;
1021
1022 if (apic_verbosity == APIC_QUIET)
1023 return;
1024
1025 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1026 for (i = 0; i < nr_ioapics; i++)
1027 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1028 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1029
1030 /*
1031 * We are a bit conservative about what we expect. We have to
1032 * know about every hardware change ASAP.
1033 */
1034 printk(KERN_INFO "testing the IO APIC.......................\n");
1035
1036 for (apic = 0; apic < nr_ioapics; apic++) {
1037
1038 spin_lock_irqsave(&ioapic_lock, flags);
1039 reg_00.raw = io_apic_read(apic, 0);
1040 reg_01.raw = io_apic_read(apic, 1);
1041 if (reg_01.bits.version >= 0x10)
1042 reg_02.raw = io_apic_read(apic, 2);
1043 if (reg_01.bits.version >= 0x20)
1044 reg_03.raw = io_apic_read(apic, 3);
1045 spin_unlock_irqrestore(&ioapic_lock, flags);
1046
1047 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1048 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1049 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1050 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1051 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1052
1053 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1054 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1055
1056 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1057 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1058
1059 /*
1060 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1061 * but the value of reg_02 is read as the previous read register
1062 * value, so ignore it if reg_02 == reg_01.
1063 */
1064 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1065 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1066 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1067 }
1068
1069 /*
1070 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1071 * or reg_03, but the value of reg_0[23] is read as the previous read
1072 * register value, so ignore it if reg_03 == reg_0[12].
1073 */
1074 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1075 reg_03.raw != reg_01.raw) {
1076 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1077 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1078 }
1079
1080 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1081
1082 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1083 " Stat Dest Deli Vect: \n");
1084
1085 for (i = 0; i <= reg_01.bits.entries; i++) {
1086 struct IO_APIC_route_entry entry;
1087
1088 entry = ioapic_read_entry(apic, i);
1089
1090 printk(KERN_DEBUG " %02x %03X %02X ",
1091 i,
1092 entry.dest.logical.logical_dest,
1093 entry.dest.physical.physical_dest
1094 );
1095
1096 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1097 entry.mask,
1098 entry.trigger,
1099 entry.irr,
1100 entry.polarity,
1101 entry.delivery_status,
1102 entry.dest_mode,
1103 entry.delivery_mode,
1104 entry.vector
1105 );
1106 }
1107 }
1108 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1109 for (i = 0; i < nr_irqs; i++) {
1110 struct irq_pin_list *entry = irq_2_pin + i;
1111 if (entry->pin < 0)
1112 continue;
1113 printk(KERN_DEBUG "IRQ%d ", i);
1114 for (;;) {
1115 printk("-> %d:%d", entry->apic, entry->pin);
1116 if (!entry->next)
1117 break;
1118 entry = irq_2_pin + entry->next;
1119 }
1120 printk("\n");
1121 }
1122
1123 printk(KERN_INFO ".................................... done.\n");
1124
1125 return;
1126 }
1127
1128 __apicdebuginit(void) print_APIC_bitfield(int base)
1129 {
1130 unsigned int v;
1131 int i, j;
1132
1133 if (apic_verbosity == APIC_QUIET)
1134 return;
1135
1136 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1137 for (i = 0; i < 8; i++) {
1138 v = apic_read(base + i*0x10);
1139 for (j = 0; j < 32; j++) {
1140 if (v & (1<<j))
1141 printk("1");
1142 else
1143 printk("0");
1144 }
1145 printk("\n");
1146 }
1147 }
1148
1149 __apicdebuginit(void) print_local_APIC(void *dummy)
1150 {
1151 unsigned int v, ver, maxlvt;
1152 u64 icr;
1153
1154 if (apic_verbosity == APIC_QUIET)
1155 return;
1156
1157 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1158 smp_processor_id(), hard_smp_processor_id());
1159 v = apic_read(APIC_ID);
1160 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1161 GET_APIC_ID(v));
1162 v = apic_read(APIC_LVR);
1163 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1164 ver = GET_APIC_VERSION(v);
1165 maxlvt = lapic_get_maxlvt();
1166
1167 v = apic_read(APIC_TASKPRI);
1168 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1169
1170 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1171 v = apic_read(APIC_ARBPRI);
1172 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1173 v & APIC_ARBPRI_MASK);
1174 v = apic_read(APIC_PROCPRI);
1175 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1176 }
1177
1178 v = apic_read(APIC_EOI);
1179 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1180 v = apic_read(APIC_RRR);
1181 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1182 v = apic_read(APIC_LDR);
1183 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1184 v = apic_read(APIC_DFR);
1185 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1186 v = apic_read(APIC_SPIV);
1187 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1188
1189 printk(KERN_DEBUG "... APIC ISR field:\n");
1190 print_APIC_bitfield(APIC_ISR);
1191 printk(KERN_DEBUG "... APIC TMR field:\n");
1192 print_APIC_bitfield(APIC_TMR);
1193 printk(KERN_DEBUG "... APIC IRR field:\n");
1194 print_APIC_bitfield(APIC_IRR);
1195
1196 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1197 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1198 apic_write(APIC_ESR, 0);
1199 v = apic_read(APIC_ESR);
1200 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1201 }
1202
1203 icr = apic_icr_read();
1204 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1205 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1206
1207 v = apic_read(APIC_LVTT);
1208 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1209
1210 if (maxlvt > 3) { /* PC is LVT#4. */
1211 v = apic_read(APIC_LVTPC);
1212 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1213 }
1214 v = apic_read(APIC_LVT0);
1215 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1216 v = apic_read(APIC_LVT1);
1217 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1218
1219 if (maxlvt > 2) { /* ERR is LVT#3. */
1220 v = apic_read(APIC_LVTERR);
1221 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1222 }
1223
1224 v = apic_read(APIC_TMICT);
1225 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1226 v = apic_read(APIC_TMCCT);
1227 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1228 v = apic_read(APIC_TDCR);
1229 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1230 printk("\n");
1231 }
1232
1233 __apicdebuginit(void) print_all_local_APICs(void)
1234 {
1235 on_each_cpu(print_local_APIC, NULL, 1);
1236 }
1237
1238 __apicdebuginit(void) print_PIC(void)
1239 {
1240 unsigned int v;
1241 unsigned long flags;
1242
1243 if (apic_verbosity == APIC_QUIET)
1244 return;
1245
1246 printk(KERN_DEBUG "\nprinting PIC contents\n");
1247
1248 spin_lock_irqsave(&i8259A_lock, flags);
1249
1250 v = inb(0xa1) << 8 | inb(0x21);
1251 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1252
1253 v = inb(0xa0) << 8 | inb(0x20);
1254 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1255
1256 outb(0x0b, 0xa0);
1257 outb(0x0b, 0x20);
1258 v = inb(0xa0) << 8 | inb(0x20);
1259 outb(0x0a, 0xa0);
1260 outb(0x0a, 0x20);
1261
1262 spin_unlock_irqrestore(&i8259A_lock, flags);
1263
1264 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1265
1266 v = inb(0x4d1) << 8 | inb(0x4d0);
1267 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1268 }
1269
1270 __apicdebuginit(int) print_all_ICs(void)
1271 {
1272 print_PIC();
1273 print_all_local_APICs();
1274 print_IO_APIC();
1275
1276 return 0;
1277 }
1278
1279 fs_initcall(print_all_ICs);
1280
1281
1282 static void __init enable_IO_APIC(void)
1283 {
1284 union IO_APIC_reg_01 reg_01;
1285 int i8259_apic, i8259_pin;
1286 int i, apic;
1287 unsigned long flags;
1288
1289 for (i = 0; i < pin_map_size; i++) {
1290 irq_2_pin[i].pin = -1;
1291 irq_2_pin[i].next = 0;
1292 }
1293 if (!pirqs_enabled)
1294 for (i = 0; i < MAX_PIRQS; i++)
1295 pirq_entries[i] = -1;
1296
1297 /*
1298 * The number of IO-APIC IRQ registers (== #pins):
1299 */
1300 for (apic = 0; apic < nr_ioapics; apic++) {
1301 spin_lock_irqsave(&ioapic_lock, flags);
1302 reg_01.raw = io_apic_read(apic, 1);
1303 spin_unlock_irqrestore(&ioapic_lock, flags);
1304 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1305 }
1306 for (apic = 0; apic < nr_ioapics; apic++) {
1307 int pin;
1308 /* See if any of the pins is in ExtINT mode */
1309 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1310 struct IO_APIC_route_entry entry;
1311 entry = ioapic_read_entry(apic, pin);
1312
1313
1314 /* If the interrupt line is enabled and in ExtInt mode
1315 * I have found the pin where the i8259 is connected.
1316 */
1317 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1318 ioapic_i8259.apic = apic;
1319 ioapic_i8259.pin = pin;
1320 goto found_i8259;
1321 }
1322 }
1323 }
1324 found_i8259:
1325 /* Look to see what if the MP table has reported the ExtINT */
1326 /* If we could not find the appropriate pin by looking at the ioapic
1327 * the i8259 probably is not connected the ioapic but give the
1328 * mptable a chance anyway.
1329 */
1330 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1331 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1332 /* Trust the MP table if nothing is setup in the hardware */
1333 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1334 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1335 ioapic_i8259.pin = i8259_pin;
1336 ioapic_i8259.apic = i8259_apic;
1337 }
1338 /* Complain if the MP table and the hardware disagree */
1339 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1340 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1341 {
1342 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1343 }
1344
1345 /*
1346 * Do not trust the IO-APIC being empty at bootup
1347 */
1348 clear_IO_APIC();
1349 }
1350
1351 /*
1352 * Not an __init, needed by the reboot code
1353 */
1354 void disable_IO_APIC(void)
1355 {
1356 /*
1357 * Clear the IO-APIC before rebooting:
1358 */
1359 clear_IO_APIC();
1360
1361 /*
1362 * If the i8259 is routed through an IOAPIC
1363 * Put that IOAPIC in virtual wire mode
1364 * so legacy interrupts can be delivered.
1365 */
1366 if (ioapic_i8259.pin != -1) {
1367 struct IO_APIC_route_entry entry;
1368
1369 memset(&entry, 0, sizeof(entry));
1370 entry.mask = 0; /* Enabled */
1371 entry.trigger = 0; /* Edge */
1372 entry.irr = 0;
1373 entry.polarity = 0; /* High */
1374 entry.delivery_status = 0;
1375 entry.dest_mode = 0; /* Physical */
1376 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1377 entry.vector = 0;
1378 entry.dest.physical.physical_dest = read_apic_id();
1379
1380 /*
1381 * Add it to the IO-APIC irq-routing table:
1382 */
1383 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1384 }
1385 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1386 }
1387
1388 /*
1389 * function to set the IO-APIC physical IDs based on the
1390 * values stored in the MPC table.
1391 *
1392 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1393 */
1394
1395 static void __init setup_ioapic_ids_from_mpc(void)
1396 {
1397 union IO_APIC_reg_00 reg_00;
1398 physid_mask_t phys_id_present_map;
1399 int apic;
1400 int i;
1401 unsigned char old_id;
1402 unsigned long flags;
1403
1404 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1405 return;
1406
1407 /*
1408 * Don't check I/O APIC IDs for xAPIC systems. They have
1409 * no meaning without the serial APIC bus.
1410 */
1411 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1412 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1413 return;
1414 /*
1415 * This is broken; anything with a real cpu count has to
1416 * circumvent this idiocy regardless.
1417 */
1418 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1419
1420 /*
1421 * Set the IOAPIC ID to the value stored in the MPC table.
1422 */
1423 for (apic = 0; apic < nr_ioapics; apic++) {
1424
1425 /* Read the register 0 value */
1426 spin_lock_irqsave(&ioapic_lock, flags);
1427 reg_00.raw = io_apic_read(apic, 0);
1428 spin_unlock_irqrestore(&ioapic_lock, flags);
1429
1430 old_id = mp_ioapics[apic].mp_apicid;
1431
1432 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1433 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1434 apic, mp_ioapics[apic].mp_apicid);
1435 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1436 reg_00.bits.ID);
1437 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1438 }
1439
1440 /*
1441 * Sanity check, is the ID really free? Every APIC in a
1442 * system must have a unique ID or we get lots of nice
1443 * 'stuck on smp_invalidate_needed IPI wait' messages.
1444 */
1445 if (check_apicid_used(phys_id_present_map,
1446 mp_ioapics[apic].mp_apicid)) {
1447 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1448 apic, mp_ioapics[apic].mp_apicid);
1449 for (i = 0; i < get_physical_broadcast(); i++)
1450 if (!physid_isset(i, phys_id_present_map))
1451 break;
1452 if (i >= get_physical_broadcast())
1453 panic("Max APIC ID exceeded!\n");
1454 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1455 i);
1456 physid_set(i, phys_id_present_map);
1457 mp_ioapics[apic].mp_apicid = i;
1458 } else {
1459 physid_mask_t tmp;
1460 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1461 apic_printk(APIC_VERBOSE, "Setting %d in the "
1462 "phys_id_present_map\n",
1463 mp_ioapics[apic].mp_apicid);
1464 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1465 }
1466
1467
1468 /*
1469 * We need to adjust the IRQ routing table
1470 * if the ID changed.
1471 */
1472 if (old_id != mp_ioapics[apic].mp_apicid)
1473 for (i = 0; i < mp_irq_entries; i++)
1474 if (mp_irqs[i].mp_dstapic == old_id)
1475 mp_irqs[i].mp_dstapic
1476 = mp_ioapics[apic].mp_apicid;
1477
1478 /*
1479 * Read the right value from the MPC table and
1480 * write it into the ID register.
1481 */
1482 apic_printk(APIC_VERBOSE, KERN_INFO
1483 "...changing IO-APIC physical APIC ID to %d ...",
1484 mp_ioapics[apic].mp_apicid);
1485
1486 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1487 spin_lock_irqsave(&ioapic_lock, flags);
1488 io_apic_write(apic, 0, reg_00.raw);
1489 spin_unlock_irqrestore(&ioapic_lock, flags);
1490
1491 /*
1492 * Sanity check
1493 */
1494 spin_lock_irqsave(&ioapic_lock, flags);
1495 reg_00.raw = io_apic_read(apic, 0);
1496 spin_unlock_irqrestore(&ioapic_lock, flags);
1497 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1498 printk("could not set ID!\n");
1499 else
1500 apic_printk(APIC_VERBOSE, " ok.\n");
1501 }
1502 }
1503
1504 int no_timer_check __initdata;
1505
1506 static int __init notimercheck(char *s)
1507 {
1508 no_timer_check = 1;
1509 return 1;
1510 }
1511 __setup("no_timer_check", notimercheck);
1512
1513 /*
1514 * There is a nasty bug in some older SMP boards, their mptable lies
1515 * about the timer IRQ. We do the following to work around the situation:
1516 *
1517 * - timer IRQ defaults to IO-APIC IRQ
1518 * - if this function detects that timer IRQs are defunct, then we fall
1519 * back to ISA timer IRQs
1520 */
1521 static int __init timer_irq_works(void)
1522 {
1523 unsigned long t1 = jiffies;
1524 unsigned long flags;
1525
1526 if (no_timer_check)
1527 return 1;
1528
1529 local_save_flags(flags);
1530 local_irq_enable();
1531 /* Let ten ticks pass... */
1532 mdelay((10 * 1000) / HZ);
1533 local_irq_restore(flags);
1534
1535 /*
1536 * Expect a few ticks at least, to be sure some possible
1537 * glue logic does not lock up after one or two first
1538 * ticks in a non-ExtINT mode. Also the local APIC
1539 * might have cached one ExtINT interrupt. Finally, at
1540 * least one tick may be lost due to delays.
1541 */
1542 if (time_after(jiffies, t1 + 4))
1543 return 1;
1544
1545 return 0;
1546 }
1547
1548 /*
1549 * In the SMP+IOAPIC case it might happen that there are an unspecified
1550 * number of pending IRQ events unhandled. These cases are very rare,
1551 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1552 * better to do it this way as thus we do not have to be aware of
1553 * 'pending' interrupts in the IRQ path, except at this point.
1554 */
1555 /*
1556 * Edge triggered needs to resend any interrupt
1557 * that was delayed but this is now handled in the device
1558 * independent code.
1559 */
1560
1561 /*
1562 * Startup quirk:
1563 *
1564 * Starting up a edge-triggered IO-APIC interrupt is
1565 * nasty - we need to make sure that we get the edge.
1566 * If it is already asserted for some reason, we need
1567 * return 1 to indicate that is was pending.
1568 *
1569 * This is not complete - we should be able to fake
1570 * an edge even if it isn't on the 8259A...
1571 *
1572 * (We do this for level-triggered IRQs too - it cannot hurt.)
1573 */
1574 static unsigned int startup_ioapic_irq(unsigned int irq)
1575 {
1576 int was_pending = 0;
1577 unsigned long flags;
1578
1579 spin_lock_irqsave(&ioapic_lock, flags);
1580 if (irq < 16) {
1581 disable_8259A_irq(irq);
1582 if (i8259A_irq_pending(irq))
1583 was_pending = 1;
1584 }
1585 __unmask_IO_APIC_irq(irq);
1586 spin_unlock_irqrestore(&ioapic_lock, flags);
1587
1588 return was_pending;
1589 }
1590
1591 static void ack_ioapic_irq(unsigned int irq)
1592 {
1593 move_native_irq(irq);
1594 ack_APIC_irq();
1595 }
1596
1597 static void ack_ioapic_quirk_irq(unsigned int irq)
1598 {
1599 unsigned long v;
1600 int i;
1601
1602 move_native_irq(irq);
1603 /*
1604 * It appears there is an erratum which affects at least version 0x11
1605 * of I/O APIC (that's the 82093AA and cores integrated into various
1606 * chipsets). Under certain conditions a level-triggered interrupt is
1607 * erroneously delivered as edge-triggered one but the respective IRR
1608 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1609 * message but it will never arrive and further interrupts are blocked
1610 * from the source. The exact reason is so far unknown, but the
1611 * phenomenon was observed when two consecutive interrupt requests
1612 * from a given source get delivered to the same CPU and the source is
1613 * temporarily disabled in between.
1614 *
1615 * A workaround is to simulate an EOI message manually. We achieve it
1616 * by setting the trigger mode to edge and then to level when the edge
1617 * trigger mode gets detected in the TMR of a local APIC for a
1618 * level-triggered interrupt. We mask the source for the time of the
1619 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1620 * The idea is from Manfred Spraul. --macro
1621 */
1622 i = irq_cfg(irq)->vector;
1623
1624 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1625
1626 ack_APIC_irq();
1627
1628 if (!(v & (1 << (i & 0x1f)))) {
1629 atomic_inc(&irq_mis_count);
1630 spin_lock(&ioapic_lock);
1631 __mask_and_edge_IO_APIC_irq(irq);
1632 __unmask_and_level_IO_APIC_irq(irq);
1633 spin_unlock(&ioapic_lock);
1634 }
1635 }
1636
1637 static int ioapic_retrigger_irq(unsigned int irq)
1638 {
1639 send_IPI_self(irq_cfg(irq)->vector);
1640
1641 return 1;
1642 }
1643
1644 static struct irq_chip ioapic_chip __read_mostly = {
1645 .name = "IO-APIC",
1646 .startup = startup_ioapic_irq,
1647 .mask = mask_IO_APIC_irq,
1648 .unmask = unmask_IO_APIC_irq,
1649 .ack = ack_ioapic_irq,
1650 .eoi = ack_ioapic_quirk_irq,
1651 #ifdef CONFIG_SMP
1652 .set_affinity = set_ioapic_affinity_irq,
1653 #endif
1654 .retrigger = ioapic_retrigger_irq,
1655 };
1656
1657
1658 static inline void init_IO_APIC_traps(void)
1659 {
1660 int irq;
1661 struct irq_desc *desc;
1662
1663 /*
1664 * NOTE! The local APIC isn't very good at handling
1665 * multiple interrupts at the same interrupt level.
1666 * As the interrupt level is determined by taking the
1667 * vector number and shifting that right by 4, we
1668 * want to spread these out a bit so that they don't
1669 * all fall in the same interrupt level.
1670 *
1671 * Also, we've got to be careful not to trash gate
1672 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1673 */
1674 for (irq = 0; irq < nr_irqs ; irq++) {
1675 if (IO_APIC_IRQ(irq) && !irq_cfg(irq)->vector) {
1676 /*
1677 * Hmm.. We don't have an entry for this,
1678 * so default to an old-fashioned 8259
1679 * interrupt if we can..
1680 */
1681 if (irq < 16)
1682 make_8259A_irq(irq);
1683 else {
1684 desc = irq_to_desc(irq);
1685 /* Strange. Oh, well.. */
1686 desc->chip = &no_irq_chip;
1687 }
1688 }
1689 }
1690 }
1691
1692 /*
1693 * The local APIC irq-chip implementation:
1694 */
1695
1696 static void ack_lapic_irq(unsigned int irq)
1697 {
1698 ack_APIC_irq();
1699 }
1700
1701 static void mask_lapic_irq(unsigned int irq)
1702 {
1703 unsigned long v;
1704
1705 v = apic_read(APIC_LVT0);
1706 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1707 }
1708
1709 static void unmask_lapic_irq(unsigned int irq)
1710 {
1711 unsigned long v;
1712
1713 v = apic_read(APIC_LVT0);
1714 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1715 }
1716
1717 static struct irq_chip lapic_chip __read_mostly = {
1718 .name = "local-APIC",
1719 .mask = mask_lapic_irq,
1720 .unmask = unmask_lapic_irq,
1721 .ack = ack_lapic_irq,
1722 };
1723
1724 static void lapic_register_intr(int irq, int vector)
1725 {
1726 struct irq_desc *desc;
1727
1728 desc = irq_to_desc(irq);
1729 desc->status &= ~IRQ_LEVEL;
1730 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1731 "edge");
1732 set_intr_gate(vector, interrupt[irq]);
1733 }
1734
1735 static void __init setup_nmi(void)
1736 {
1737 /*
1738 * Dirty trick to enable the NMI watchdog ...
1739 * We put the 8259A master into AEOI mode and
1740 * unmask on all local APICs LVT0 as NMI.
1741 *
1742 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1743 * is from Maciej W. Rozycki - so we do not have to EOI from
1744 * the NMI handler or the timer interrupt.
1745 */
1746 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
1747
1748 enable_NMI_through_LVT0();
1749
1750 apic_printk(APIC_VERBOSE, " done.\n");
1751 }
1752
1753 /*
1754 * This looks a bit hackish but it's about the only one way of sending
1755 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1756 * not support the ExtINT mode, unfortunately. We need to send these
1757 * cycles as some i82489DX-based boards have glue logic that keeps the
1758 * 8259A interrupt line asserted until INTA. --macro
1759 */
1760 static inline void __init unlock_ExtINT_logic(void)
1761 {
1762 int apic, pin, i;
1763 struct IO_APIC_route_entry entry0, entry1;
1764 unsigned char save_control, save_freq_select;
1765
1766 pin = find_isa_irq_pin(8, mp_INT);
1767 if (pin == -1) {
1768 WARN_ON_ONCE(1);
1769 return;
1770 }
1771 apic = find_isa_irq_apic(8, mp_INT);
1772 if (apic == -1) {
1773 WARN_ON_ONCE(1);
1774 return;
1775 }
1776
1777 entry0 = ioapic_read_entry(apic, pin);
1778 clear_IO_APIC_pin(apic, pin);
1779
1780 memset(&entry1, 0, sizeof(entry1));
1781
1782 entry1.dest_mode = 0; /* physical delivery */
1783 entry1.mask = 0; /* unmask IRQ now */
1784 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1785 entry1.delivery_mode = dest_ExtINT;
1786 entry1.polarity = entry0.polarity;
1787 entry1.trigger = 0;
1788 entry1.vector = 0;
1789
1790 ioapic_write_entry(apic, pin, entry1);
1791
1792 save_control = CMOS_READ(RTC_CONTROL);
1793 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1794 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1795 RTC_FREQ_SELECT);
1796 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1797
1798 i = 100;
1799 while (i-- > 0) {
1800 mdelay(10);
1801 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1802 i -= 10;
1803 }
1804
1805 CMOS_WRITE(save_control, RTC_CONTROL);
1806 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1807 clear_IO_APIC_pin(apic, pin);
1808
1809 ioapic_write_entry(apic, pin, entry0);
1810 }
1811
1812 /*
1813 * This code may look a bit paranoid, but it's supposed to cooperate with
1814 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1815 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1816 * fanatically on his truly buggy board.
1817 */
1818 static inline void __init check_timer(void)
1819 {
1820 int apic1, pin1, apic2, pin2;
1821 int no_pin1 = 0;
1822 int vector;
1823 unsigned int ver;
1824 unsigned long flags;
1825
1826 local_irq_save(flags);
1827
1828 ver = apic_read(APIC_LVR);
1829 ver = GET_APIC_VERSION(ver);
1830
1831 /*
1832 * get/set the timer IRQ vector:
1833 */
1834 disable_8259A_irq(0);
1835 vector = assign_irq_vector(0);
1836 set_intr_gate(vector, interrupt[0]);
1837
1838 /*
1839 * As IRQ0 is to be enabled in the 8259A, the virtual
1840 * wire has to be disabled in the local APIC. Also
1841 * timer interrupts need to be acknowledged manually in
1842 * the 8259A for the i82489DX when using the NMI
1843 * watchdog as that APIC treats NMIs as level-triggered.
1844 * The AEOI mode will finish them in the 8259A
1845 * automatically.
1846 */
1847 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1848 init_8259A(1);
1849 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
1850
1851 pin1 = find_isa_irq_pin(0, mp_INT);
1852 apic1 = find_isa_irq_apic(0, mp_INT);
1853 pin2 = ioapic_i8259.pin;
1854 apic2 = ioapic_i8259.apic;
1855
1856 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
1857 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
1858 vector, apic1, pin1, apic2, pin2);
1859
1860 /*
1861 * Some BIOS writers are clueless and report the ExtINTA
1862 * I/O APIC input from the cascaded 8259A as the timer
1863 * interrupt input. So just in case, if only one pin
1864 * was found above, try it both directly and through the
1865 * 8259A.
1866 */
1867 if (pin1 == -1) {
1868 pin1 = pin2;
1869 apic1 = apic2;
1870 no_pin1 = 1;
1871 } else if (pin2 == -1) {
1872 pin2 = pin1;
1873 apic2 = apic1;
1874 }
1875
1876 if (pin1 != -1) {
1877 /*
1878 * Ok, does IRQ0 through the IOAPIC work?
1879 */
1880 if (no_pin1) {
1881 add_pin_to_irq(0, apic1, pin1);
1882 setup_timer_IRQ0_pin(apic1, pin1, vector);
1883 }
1884 unmask_IO_APIC_irq(0);
1885 if (timer_irq_works()) {
1886 if (nmi_watchdog == NMI_IO_APIC) {
1887 setup_nmi();
1888 enable_8259A_irq(0);
1889 }
1890 if (disable_timer_pin_1 > 0)
1891 clear_IO_APIC_pin(0, pin1);
1892 goto out;
1893 }
1894 clear_IO_APIC_pin(apic1, pin1);
1895 if (!no_pin1)
1896 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
1897 "8254 timer not connected to IO-APIC\n");
1898
1899 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
1900 "(IRQ0) through the 8259A ...\n");
1901 apic_printk(APIC_QUIET, KERN_INFO
1902 "..... (found apic %d pin %d) ...\n", apic2, pin2);
1903 /*
1904 * legacy devices should be connected to IO APIC #0
1905 */
1906 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1907 setup_timer_IRQ0_pin(apic2, pin2, vector);
1908 unmask_IO_APIC_irq(0);
1909 enable_8259A_irq(0);
1910 if (timer_irq_works()) {
1911 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
1912 timer_through_8259 = 1;
1913 if (nmi_watchdog == NMI_IO_APIC) {
1914 disable_8259A_irq(0);
1915 setup_nmi();
1916 enable_8259A_irq(0);
1917 }
1918 goto out;
1919 }
1920 /*
1921 * Cleanup, just in case ...
1922 */
1923 disable_8259A_irq(0);
1924 clear_IO_APIC_pin(apic2, pin2);
1925 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1926 }
1927
1928 if (nmi_watchdog == NMI_IO_APIC) {
1929 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
1930 "through the IO-APIC - disabling NMI Watchdog!\n");
1931 nmi_watchdog = NMI_NONE;
1932 }
1933 timer_ack = 0;
1934
1935 apic_printk(APIC_QUIET, KERN_INFO
1936 "...trying to set up timer as Virtual Wire IRQ...\n");
1937
1938 lapic_register_intr(0, vector);
1939 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1940 enable_8259A_irq(0);
1941
1942 if (timer_irq_works()) {
1943 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
1944 goto out;
1945 }
1946 disable_8259A_irq(0);
1947 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1948 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1949
1950 apic_printk(APIC_QUIET, KERN_INFO
1951 "...trying to set up timer as ExtINT IRQ...\n");
1952
1953 init_8259A(0);
1954 make_8259A_irq(0);
1955 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1956
1957 unlock_ExtINT_logic();
1958
1959 if (timer_irq_works()) {
1960 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
1961 goto out;
1962 }
1963 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
1964 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1965 "report. Then try booting with the 'noapic' option.\n");
1966 out:
1967 local_irq_restore(flags);
1968 }
1969
1970 /*
1971 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
1972 * to devices. However there may be an I/O APIC pin available for
1973 * this interrupt regardless. The pin may be left unconnected, but
1974 * typically it will be reused as an ExtINT cascade interrupt for
1975 * the master 8259A. In the MPS case such a pin will normally be
1976 * reported as an ExtINT interrupt in the MP table. With ACPI
1977 * there is no provision for ExtINT interrupts, and in the absence
1978 * of an override it would be treated as an ordinary ISA I/O APIC
1979 * interrupt, that is edge-triggered and unmasked by default. We
1980 * used to do this, but it caused problems on some systems because
1981 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
1982 * the same ExtINT cascade interrupt to drive the local APIC of the
1983 * bootstrap processor. Therefore we refrain from routing IRQ2 to
1984 * the I/O APIC in all cases now. No actual device should request
1985 * it anyway. --macro
1986 */
1987 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1988
1989 void __init setup_IO_APIC(void)
1990 {
1991 int i;
1992
1993 /* Reserve all the system vectors. */
1994 for (i = first_system_vector; i < NR_VECTORS; i++)
1995 set_bit(i, used_vectors);
1996
1997 enable_IO_APIC();
1998
1999 io_apic_irqs = ~PIC_IRQS;
2000
2001 printk("ENABLING IO-APIC IRQs\n");
2002
2003 /*
2004 * Set up IO-APIC IRQ routing.
2005 */
2006 if (!acpi_ioapic)
2007 setup_ioapic_ids_from_mpc();
2008 sync_Arb_IDs();
2009 setup_IO_APIC_irqs();
2010 init_IO_APIC_traps();
2011 check_timer();
2012 }
2013
2014 /*
2015 * Called after all the initialization is done. If we didnt find any
2016 * APIC bugs then we can allow the modify fast path
2017 */
2018
2019 static int __init io_apic_bug_finalize(void)
2020 {
2021 if (sis_apic_bug == -1)
2022 sis_apic_bug = 0;
2023 return 0;
2024 }
2025
2026 late_initcall(io_apic_bug_finalize);
2027
2028 struct sysfs_ioapic_data {
2029 struct sys_device dev;
2030 struct IO_APIC_route_entry entry[0];
2031 };
2032 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2033
2034 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2035 {
2036 struct IO_APIC_route_entry *entry;
2037 struct sysfs_ioapic_data *data;
2038 int i;
2039
2040 data = container_of(dev, struct sysfs_ioapic_data, dev);
2041 entry = data->entry;
2042 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2043 entry[i] = ioapic_read_entry(dev->id, i);
2044
2045 return 0;
2046 }
2047
2048 static int ioapic_resume(struct sys_device *dev)
2049 {
2050 struct IO_APIC_route_entry *entry;
2051 struct sysfs_ioapic_data *data;
2052 unsigned long flags;
2053 union IO_APIC_reg_00 reg_00;
2054 int i;
2055
2056 data = container_of(dev, struct sysfs_ioapic_data, dev);
2057 entry = data->entry;
2058
2059 spin_lock_irqsave(&ioapic_lock, flags);
2060 reg_00.raw = io_apic_read(dev->id, 0);
2061 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2062 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2063 io_apic_write(dev->id, 0, reg_00.raw);
2064 }
2065 spin_unlock_irqrestore(&ioapic_lock, flags);
2066 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2067 ioapic_write_entry(dev->id, i, entry[i]);
2068
2069 return 0;
2070 }
2071
2072 static struct sysdev_class ioapic_sysdev_class = {
2073 .name = "ioapic",
2074 .suspend = ioapic_suspend,
2075 .resume = ioapic_resume,
2076 };
2077
2078 static int __init ioapic_init_sysfs(void)
2079 {
2080 struct sys_device *dev;
2081 int i, size, error = 0;
2082
2083 error = sysdev_class_register(&ioapic_sysdev_class);
2084 if (error)
2085 return error;
2086
2087 for (i = 0; i < nr_ioapics; i++) {
2088 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2089 * sizeof(struct IO_APIC_route_entry);
2090 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2091 if (!mp_ioapic_data[i]) {
2092 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2093 continue;
2094 }
2095 dev = &mp_ioapic_data[i]->dev;
2096 dev->id = i;
2097 dev->cls = &ioapic_sysdev_class;
2098 error = sysdev_register(dev);
2099 if (error) {
2100 kfree(mp_ioapic_data[i]);
2101 mp_ioapic_data[i] = NULL;
2102 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2103 continue;
2104 }
2105 }
2106
2107 return 0;
2108 }
2109
2110 device_initcall(ioapic_init_sysfs);
2111
2112 /*
2113 * Dynamic irq allocate and deallocation
2114 */
2115 int create_irq(void)
2116 {
2117 /* Allocate an unused irq */
2118 int irq, new, vector = 0;
2119 unsigned long flags;
2120
2121 irq = -ENOSPC;
2122 spin_lock_irqsave(&vector_lock, flags);
2123 for (new = (nr_irqs - 1); new >= 0; new--) {
2124 if (platform_legacy_irq(new))
2125 continue;
2126 if (irq_cfg(new)->vector != 0)
2127 continue;
2128 vector = __assign_irq_vector(new);
2129 if (likely(vector > 0))
2130 irq = new;
2131 break;
2132 }
2133 spin_unlock_irqrestore(&vector_lock, flags);
2134
2135 if (irq >= 0) {
2136 set_intr_gate(vector, interrupt[irq]);
2137 dynamic_irq_init(irq);
2138 }
2139 return irq;
2140 }
2141
2142 void destroy_irq(unsigned int irq)
2143 {
2144 unsigned long flags;
2145
2146 dynamic_irq_cleanup(irq);
2147
2148 spin_lock_irqsave(&vector_lock, flags);
2149 clear_bit(irq_cfg(irq)->vector, used_vectors);
2150 irq_cfg(irq)->vector = 0;
2151 spin_unlock_irqrestore(&vector_lock, flags);
2152 }
2153
2154 /*
2155 * MSI message composition
2156 */
2157 #ifdef CONFIG_PCI_MSI
2158 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2159 {
2160 int vector;
2161 unsigned dest;
2162
2163 vector = assign_irq_vector(irq);
2164 if (vector >= 0) {
2165 dest = cpu_mask_to_apicid(TARGET_CPUS);
2166
2167 msg->address_hi = MSI_ADDR_BASE_HI;
2168 msg->address_lo =
2169 MSI_ADDR_BASE_LO |
2170 ((INT_DEST_MODE == 0) ?
2171 MSI_ADDR_DEST_MODE_PHYSICAL:
2172 MSI_ADDR_DEST_MODE_LOGICAL) |
2173 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2174 MSI_ADDR_REDIRECTION_CPU:
2175 MSI_ADDR_REDIRECTION_LOWPRI) |
2176 MSI_ADDR_DEST_ID(dest);
2177
2178 msg->data =
2179 MSI_DATA_TRIGGER_EDGE |
2180 MSI_DATA_LEVEL_ASSERT |
2181 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2182 MSI_DATA_DELIVERY_FIXED:
2183 MSI_DATA_DELIVERY_LOWPRI) |
2184 MSI_DATA_VECTOR(vector);
2185 }
2186 return vector;
2187 }
2188
2189 #ifdef CONFIG_SMP
2190 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2191 {
2192 struct msi_msg msg;
2193 unsigned int dest;
2194 cpumask_t tmp;
2195 int vector;
2196 struct irq_desc *desc;
2197
2198 cpus_and(tmp, mask, cpu_online_map);
2199 if (cpus_empty(tmp))
2200 tmp = TARGET_CPUS;
2201
2202 vector = assign_irq_vector(irq);
2203 if (vector < 0)
2204 return;
2205
2206 dest = cpu_mask_to_apicid(mask);
2207
2208 read_msi_msg(irq, &msg);
2209
2210 msg.data &= ~MSI_DATA_VECTOR_MASK;
2211 msg.data |= MSI_DATA_VECTOR(vector);
2212 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2213 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2214
2215 write_msi_msg(irq, &msg);
2216 desc = irq_to_desc(irq);
2217 desc->affinity = mask;
2218 }
2219 #endif /* CONFIG_SMP */
2220
2221 /*
2222 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2223 * which implement the MSI or MSI-X Capability Structure.
2224 */
2225 static struct irq_chip msi_chip = {
2226 .name = "PCI-MSI",
2227 .unmask = unmask_msi_irq,
2228 .mask = mask_msi_irq,
2229 .ack = ack_ioapic_irq,
2230 #ifdef CONFIG_SMP
2231 .set_affinity = set_msi_irq_affinity,
2232 #endif
2233 .retrigger = ioapic_retrigger_irq,
2234 };
2235
2236 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2237 {
2238 struct msi_msg msg;
2239 int irq, ret;
2240 irq = create_irq();
2241 if (irq < 0)
2242 return irq;
2243
2244 ret = msi_compose_msg(dev, irq, &msg);
2245 if (ret < 0) {
2246 destroy_irq(irq);
2247 return ret;
2248 }
2249
2250 set_irq_msi(irq, desc);
2251 write_msi_msg(irq, &msg);
2252
2253 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2254 "edge");
2255
2256 return 0;
2257 }
2258
2259 void arch_teardown_msi_irq(unsigned int irq)
2260 {
2261 destroy_irq(irq);
2262 }
2263
2264 #endif /* CONFIG_PCI_MSI */
2265
2266 /*
2267 * Hypertransport interrupt support
2268 */
2269 #ifdef CONFIG_HT_IRQ
2270
2271 #ifdef CONFIG_SMP
2272
2273 static void target_ht_irq(unsigned int irq, unsigned int dest)
2274 {
2275 struct ht_irq_msg msg;
2276 fetch_ht_irq_msg(irq, &msg);
2277
2278 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2279 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2280
2281 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2282 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2283
2284 write_ht_irq_msg(irq, &msg);
2285 }
2286
2287 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2288 {
2289 unsigned int dest;
2290 cpumask_t tmp;
2291 struct irq_desc *desc;
2292
2293 cpus_and(tmp, mask, cpu_online_map);
2294 if (cpus_empty(tmp))
2295 tmp = TARGET_CPUS;
2296
2297 cpus_and(mask, tmp, CPU_MASK_ALL);
2298
2299 dest = cpu_mask_to_apicid(mask);
2300
2301 target_ht_irq(irq, dest);
2302 desc = irq_to_desc(irq);
2303 desc->affinity = mask;
2304 }
2305 #endif
2306
2307 static struct irq_chip ht_irq_chip = {
2308 .name = "PCI-HT",
2309 .mask = mask_ht_irq,
2310 .unmask = unmask_ht_irq,
2311 .ack = ack_ioapic_irq,
2312 #ifdef CONFIG_SMP
2313 .set_affinity = set_ht_irq_affinity,
2314 #endif
2315 .retrigger = ioapic_retrigger_irq,
2316 };
2317
2318 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2319 {
2320 int vector;
2321
2322 vector = assign_irq_vector(irq);
2323 if (vector >= 0) {
2324 struct ht_irq_msg msg;
2325 unsigned dest;
2326 cpumask_t tmp;
2327
2328 cpus_clear(tmp);
2329 cpu_set(vector >> 8, tmp);
2330 dest = cpu_mask_to_apicid(tmp);
2331
2332 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2333
2334 msg.address_lo =
2335 HT_IRQ_LOW_BASE |
2336 HT_IRQ_LOW_DEST_ID(dest) |
2337 HT_IRQ_LOW_VECTOR(vector) |
2338 ((INT_DEST_MODE == 0) ?
2339 HT_IRQ_LOW_DM_PHYSICAL :
2340 HT_IRQ_LOW_DM_LOGICAL) |
2341 HT_IRQ_LOW_RQEOI_EDGE |
2342 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2343 HT_IRQ_LOW_MT_FIXED :
2344 HT_IRQ_LOW_MT_ARBITRATED) |
2345 HT_IRQ_LOW_IRQ_MASKED;
2346
2347 write_ht_irq_msg(irq, &msg);
2348
2349 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2350 handle_edge_irq, "edge");
2351 }
2352 return vector;
2353 }
2354 #endif /* CONFIG_HT_IRQ */
2355
2356 /* --------------------------------------------------------------------------
2357 ACPI-based IOAPIC Configuration
2358 -------------------------------------------------------------------------- */
2359
2360 #ifdef CONFIG_ACPI
2361
2362 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2363 {
2364 union IO_APIC_reg_00 reg_00;
2365 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2366 physid_mask_t tmp;
2367 unsigned long flags;
2368 int i = 0;
2369
2370 /*
2371 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2372 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2373 * supports up to 16 on one shared APIC bus.
2374 *
2375 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2376 * advantage of new APIC bus architecture.
2377 */
2378
2379 if (physids_empty(apic_id_map))
2380 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2381
2382 spin_lock_irqsave(&ioapic_lock, flags);
2383 reg_00.raw = io_apic_read(ioapic, 0);
2384 spin_unlock_irqrestore(&ioapic_lock, flags);
2385
2386 if (apic_id >= get_physical_broadcast()) {
2387 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2388 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2389 apic_id = reg_00.bits.ID;
2390 }
2391
2392 /*
2393 * Every APIC in a system must have a unique ID or we get lots of nice
2394 * 'stuck on smp_invalidate_needed IPI wait' messages.
2395 */
2396 if (check_apicid_used(apic_id_map, apic_id)) {
2397
2398 for (i = 0; i < get_physical_broadcast(); i++) {
2399 if (!check_apicid_used(apic_id_map, i))
2400 break;
2401 }
2402
2403 if (i == get_physical_broadcast())
2404 panic("Max apic_id exceeded!\n");
2405
2406 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2407 "trying %d\n", ioapic, apic_id, i);
2408
2409 apic_id = i;
2410 }
2411
2412 tmp = apicid_to_cpu_present(apic_id);
2413 physids_or(apic_id_map, apic_id_map, tmp);
2414
2415 if (reg_00.bits.ID != apic_id) {
2416 reg_00.bits.ID = apic_id;
2417
2418 spin_lock_irqsave(&ioapic_lock, flags);
2419 io_apic_write(ioapic, 0, reg_00.raw);
2420 reg_00.raw = io_apic_read(ioapic, 0);
2421 spin_unlock_irqrestore(&ioapic_lock, flags);
2422
2423 /* Sanity check */
2424 if (reg_00.bits.ID != apic_id) {
2425 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2426 return -1;
2427 }
2428 }
2429
2430 apic_printk(APIC_VERBOSE, KERN_INFO
2431 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2432
2433 return apic_id;
2434 }
2435
2436
2437 int __init io_apic_get_version(int ioapic)
2438 {
2439 union IO_APIC_reg_01 reg_01;
2440 unsigned long flags;
2441
2442 spin_lock_irqsave(&ioapic_lock, flags);
2443 reg_01.raw = io_apic_read(ioapic, 1);
2444 spin_unlock_irqrestore(&ioapic_lock, flags);
2445
2446 return reg_01.bits.version;
2447 }
2448
2449
2450 int __init io_apic_get_redir_entries(int ioapic)
2451 {
2452 union IO_APIC_reg_01 reg_01;
2453 unsigned long flags;
2454
2455 spin_lock_irqsave(&ioapic_lock, flags);
2456 reg_01.raw = io_apic_read(ioapic, 1);
2457 spin_unlock_irqrestore(&ioapic_lock, flags);
2458
2459 return reg_01.bits.entries;
2460 }
2461
2462
2463 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2464 {
2465 struct IO_APIC_route_entry entry;
2466
2467 if (!IO_APIC_IRQ(irq)) {
2468 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2469 ioapic);
2470 return -EINVAL;
2471 }
2472
2473 /*
2474 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2475 * Note that we mask (disable) IRQs now -- these get enabled when the
2476 * corresponding device driver registers for this IRQ.
2477 */
2478
2479 memset(&entry, 0, sizeof(entry));
2480
2481 entry.delivery_mode = INT_DELIVERY_MODE;
2482 entry.dest_mode = INT_DEST_MODE;
2483 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2484 entry.trigger = edge_level;
2485 entry.polarity = active_high_low;
2486 entry.mask = 1;
2487
2488 /*
2489 * IRQs < 16 are already in the irq_2_pin[] map
2490 */
2491 if (irq >= 16)
2492 add_pin_to_irq(irq, ioapic, pin);
2493
2494 entry.vector = assign_irq_vector(irq);
2495
2496 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2497 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2498 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2499 edge_level, active_high_low);
2500
2501 ioapic_register_intr(irq, entry.vector, edge_level);
2502
2503 if (!ioapic && (irq < 16))
2504 disable_8259A_irq(irq);
2505
2506 ioapic_write_entry(ioapic, pin, entry);
2507
2508 return 0;
2509 }
2510
2511 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2512 {
2513 int i;
2514
2515 if (skip_ioapic_setup)
2516 return -1;
2517
2518 for (i = 0; i < mp_irq_entries; i++)
2519 if (mp_irqs[i].mp_irqtype == mp_INT &&
2520 mp_irqs[i].mp_srcbusirq == bus_irq)
2521 break;
2522 if (i >= mp_irq_entries)
2523 return -1;
2524
2525 *trigger = irq_trigger(i);
2526 *polarity = irq_polarity(i);
2527 return 0;
2528 }
2529
2530 #endif /* CONFIG_ACPI */
2531
2532 static int __init parse_disable_timer_pin_1(char *arg)
2533 {
2534 disable_timer_pin_1 = 1;
2535 return 0;
2536 }
2537 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2538
2539 static int __init parse_enable_timer_pin_1(char *arg)
2540 {
2541 disable_timer_pin_1 = -1;
2542 return 0;
2543 }
2544 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2545
2546 static int __init parse_noapic(char *arg)
2547 {
2548 /* disable IO-APIC */
2549 disable_ioapic_setup();
2550 return 0;
2551 }
2552 early_param("noapic", parse_noapic);
2553
2554 void __init ioapic_init_mappings(void)
2555 {
2556 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2557 int i;
2558
2559 for (i = 0; i < nr_ioapics; i++) {
2560 if (smp_found_config) {
2561 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2562 if (!ioapic_phys) {
2563 printk(KERN_ERR
2564 "WARNING: bogus zero IO-APIC "
2565 "address found in MPTABLE, "
2566 "disabling IO/APIC support!\n");
2567 smp_found_config = 0;
2568 skip_ioapic_setup = 1;
2569 goto fake_ioapic_page;
2570 }
2571 } else {
2572 fake_ioapic_page:
2573 ioapic_phys = (unsigned long)
2574 alloc_bootmem_pages(PAGE_SIZE);
2575 ioapic_phys = __pa(ioapic_phys);
2576 }
2577 set_fixmap_nocache(idx, ioapic_phys);
2578 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
2579 __fix_to_virt(idx), ioapic_phys);
2580 idx++;
2581 }
2582 }
2583
Linux kernel - Deliverables
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