2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
54 #define __apicdebuginit(type) static type __init
56 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
57 atomic_t irq_mis_count
;
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
62 static DEFINE_SPINLOCK(ioapic_lock
);
63 DEFINE_SPINLOCK(vector_lock
);
65 int timer_through_8259 __initdata
;
68 * Is the SiS APIC rmw bug present ?
69 * -1 = don't know, 0 = no, 1 = yes
71 int sis_apic_bug
= -1;
75 * # of IRQ routing registers
77 int nr_ioapic_registers
[MAX_IO_APICS
];
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
86 /* # of MP IRQ source entries */
89 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
90 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
93 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
95 static int disable_timer_pin_1 __initdata
;
98 * Rough estimation of how many shared IRQs there are, can
104 * This is performance-critical, we want to do it O(1)
106 * the indexing order of this array favors 1:1 mappings
107 * between pins and IRQs.
110 static struct irq_pin_list
{
114 DEFINE_DYN_ARRAY(irq_2_pin
, sizeof(struct irq_pin_list
), pin_map_size
, 16, NULL
);
118 unsigned int unused
[3];
122 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
124 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
125 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
128 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
130 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
131 writel(reg
, &io_apic
->index
);
132 return readl(&io_apic
->data
);
135 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
137 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
138 writel(reg
, &io_apic
->index
);
139 writel(value
, &io_apic
->data
);
143 * Re-write a value: to be used for read-modify-write
144 * cycles where the read already set up the index register.
146 * Older SiS APIC requires we rewrite the index register
148 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
150 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
152 writel(reg
, &io_apic
->index
);
153 writel(value
, &io_apic
->data
);
157 struct { u32 w1
, w2
; };
158 struct IO_APIC_route_entry entry
;
161 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
163 union entry_union eu
;
165 spin_lock_irqsave(&ioapic_lock
, flags
);
166 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
167 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
168 spin_unlock_irqrestore(&ioapic_lock
, flags
);
173 * When we write a new IO APIC routing entry, we need to write the high
174 * word first! If the mask bit in the low word is clear, we will enable
175 * the interrupt, and we need to make sure the entry is fully populated
176 * before that happens.
179 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
181 union entry_union eu
;
183 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
184 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
187 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
190 spin_lock_irqsave(&ioapic_lock
, flags
);
191 __ioapic_write_entry(apic
, pin
, e
);
192 spin_unlock_irqrestore(&ioapic_lock
, flags
);
196 * When we mask an IO APIC routing entry, we need to write the low
197 * word first, in order to set the mask bit before we change the
200 static void ioapic_mask_entry(int apic
, int pin
)
203 union entry_union eu
= { .entry
.mask
= 1 };
205 spin_lock_irqsave(&ioapic_lock
, flags
);
206 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
207 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
208 spin_unlock_irqrestore(&ioapic_lock
, flags
);
212 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
213 * shared ISA-space IRQs, so we have to support them. We are super
214 * fast in the common case, and fast for shared ISA-space IRQs.
216 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
218 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
221 entry
= irq_2_pin
+ entry
->next
;
223 if (entry
->pin
!= -1) {
224 entry
->next
= first_free_entry
;
225 entry
= irq_2_pin
+ entry
->next
;
226 if (++first_free_entry
>= pin_map_size
)
227 panic("io_apic.c: whoops");
234 * Reroute an IRQ to a different pin.
236 static void __init
replace_pin_at_irq(unsigned int irq
,
237 int oldapic
, int oldpin
,
238 int newapic
, int newpin
)
240 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
243 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
244 entry
->apic
= newapic
;
249 entry
= irq_2_pin
+ entry
->next
;
253 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
255 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
256 unsigned int pin
, reg
;
262 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
265 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
268 entry
= irq_2_pin
+ entry
->next
;
273 static void __mask_IO_APIC_irq(unsigned int irq
)
275 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
279 static void __unmask_IO_APIC_irq(unsigned int irq
)
281 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
284 /* mask = 1, trigger = 0 */
285 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
287 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
288 IO_APIC_REDIR_LEVEL_TRIGGER
);
291 /* mask = 0, trigger = 1 */
292 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
294 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
295 IO_APIC_REDIR_MASKED
);
298 static void mask_IO_APIC_irq(unsigned int irq
)
302 spin_lock_irqsave(&ioapic_lock
, flags
);
303 __mask_IO_APIC_irq(irq
);
304 spin_unlock_irqrestore(&ioapic_lock
, flags
);
307 static void unmask_IO_APIC_irq(unsigned int irq
)
311 spin_lock_irqsave(&ioapic_lock
, flags
);
312 __unmask_IO_APIC_irq(irq
);
313 spin_unlock_irqrestore(&ioapic_lock
, flags
);
316 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
318 struct IO_APIC_route_entry entry
;
320 /* Check delivery_mode to be sure we're not clearing an SMI pin */
321 entry
= ioapic_read_entry(apic
, pin
);
322 if (entry
.delivery_mode
== dest_SMI
)
326 * Disable it in the IO-APIC irq-routing table:
328 ioapic_mask_entry(apic
, pin
);
331 static void clear_IO_APIC(void)
335 for (apic
= 0; apic
< nr_ioapics
; apic
++)
336 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
337 clear_IO_APIC_pin(apic
, pin
);
341 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
345 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
346 unsigned int apicid_value
;
348 struct irq_desc
*desc
;
350 cpus_and(tmp
, cpumask
, cpu_online_map
);
354 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
356 apicid_value
= cpu_mask_to_apicid(cpumask
);
357 /* Prepare to do the io_apic_write */
358 apicid_value
= apicid_value
<< 24;
359 spin_lock_irqsave(&ioapic_lock
, flags
);
364 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
367 entry
= irq_2_pin
+ entry
->next
;
369 desc
= irq_to_desc(irq
);
370 desc
->affinity
= cpumask
;
371 spin_unlock_irqrestore(&ioapic_lock
, flags
);
374 #if defined(CONFIG_IRQBALANCE)
375 # include <asm/processor.h> /* kernel_thread() */
376 # include <linux/kernel_stat.h> /* kstat */
377 # include <linux/slab.h> /* kmalloc() */
378 # include <linux/timer.h>
380 #define IRQBALANCE_CHECK_ARCH -999
381 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
382 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
383 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
384 #define BALANCED_IRQ_LESS_DELTA (HZ)
386 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
387 static int physical_balance __read_mostly
;
388 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
390 static struct irq_cpu_info
{
391 unsigned long *last_irq
;
392 unsigned long *irq_delta
;
394 } irq_cpu_data
[NR_CPUS
];
396 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
397 #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
398 #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
400 #define IDLE_ENOUGH(cpu,now) \
401 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
403 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
405 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
407 static cpumask_t balance_irq_affinity_init __initdata
= CPU_MASK_ALL
;
409 static cpumask_t
*balance_irq_affinity
;
412 static void __init
irq_affinity_init_work(void *data
)
414 struct dyn_array
*da
= data
;
417 struct balance_irq_affinity
*affinity
;
419 affinity
= *da
->name
;
421 for (i
= 0; i
< *da
->nr
; i
++)
422 memcpy(&affinity
[i
], &balance_irq_affinity_init
,
423 sizeof(struct balance_irq_affinity
));
427 DEFINE_DYN_ARRAY(balance_irq_affinity
, sizeof(struct balance_irq_affinity
), nr_irqs
, PAGE_SIZE
, irq_affinity_init_work
);
430 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
432 balance_irq_affinity
[irq
] = mask
;
435 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
436 unsigned long now
, int direction
)
444 if (unlikely(cpu
== curr_cpu
))
447 if (direction
== 1) {
456 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
, allowed_mask
) ||
457 (search_idle
&& !IDLE_ENOUGH(cpu
, now
)));
462 static inline void balance_irq(int cpu
, int irq
)
464 unsigned long now
= jiffies
;
465 cpumask_t allowed_mask
;
466 unsigned int new_cpu
;
468 if (irqbalance_disabled
)
471 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
472 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
474 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
477 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
480 struct irq_desc
*desc
;
482 for_each_online_cpu(i
) {
483 for (j
= 0; j
< nr_irqs
; j
++) {
484 desc
= irq_to_desc(j
);
487 /* Is it a significant load ? */
488 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
), j
) <
489 useful_load_threshold
)
494 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
495 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
499 static void do_irq_balance(void)
502 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
503 unsigned long move_this_load
= 0;
504 int max_loaded
= 0, min_loaded
= 0;
506 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
508 int tmp_loaded
, first_attempt
= 1;
509 unsigned long tmp_cpu_irq
;
510 unsigned long imbalance
= 0;
511 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
512 struct irq_desc
*desc
;
514 for_each_possible_cpu(i
) {
519 package_index
= CPU_TO_PACKAGEINDEX(i
);
520 for (j
= 0; j
< nr_irqs
; j
++) {
521 unsigned long value_now
, delta
;
522 /* Is this an active IRQ or balancing disabled ? */
523 desc
= irq_to_desc(j
);
524 if (!desc
->action
|| irq_balancing_disabled(j
))
526 if (package_index
== i
)
527 IRQ_DELTA(package_index
, j
) = 0;
528 /* Determine the total count per processor per IRQ */
529 value_now
= (unsigned long) kstat_irqs_cpu(j
, i
);
531 /* Determine the activity per processor per IRQ */
532 delta
= value_now
- LAST_CPU_IRQ(i
, j
);
534 /* Update last_cpu_irq[][] for the next time */
535 LAST_CPU_IRQ(i
, j
) = value_now
;
537 /* Ignore IRQs whose rate is less than the clock */
538 if (delta
< useful_load_threshold
)
540 /* update the load for the processor or package total */
541 IRQ_DELTA(package_index
, j
) += delta
;
543 /* Keep track of the higher numbered sibling as well */
544 if (i
!= package_index
)
547 * We have sibling A and sibling B in the package
549 * cpu_irq[A] = load for cpu A + load for cpu B
550 * cpu_irq[B] = load for cpu B
552 CPU_IRQ(package_index
) += delta
;
555 /* Find the least loaded processor package */
556 for_each_online_cpu(i
) {
557 if (i
!= CPU_TO_PACKAGEINDEX(i
))
559 if (min_cpu_irq
> CPU_IRQ(i
)) {
560 min_cpu_irq
= CPU_IRQ(i
);
564 max_cpu_irq
= ULONG_MAX
;
568 * Look for heaviest loaded processor.
569 * We may come back to get the next heaviest loaded processor.
570 * Skip processors with trivial loads.
574 for_each_online_cpu(i
) {
575 if (i
!= CPU_TO_PACKAGEINDEX(i
))
577 if (max_cpu_irq
<= CPU_IRQ(i
))
579 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
580 tmp_cpu_irq
= CPU_IRQ(i
);
585 if (tmp_loaded
== -1) {
587 * In the case of small number of heavy interrupt sources,
588 * loading some of the cpus too much. We use Ingo's original
589 * approach to rotate them around.
591 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
592 rotate_irqs_among_cpus(useful_load_threshold
);
595 goto not_worth_the_effort
;
598 first_attempt
= 0; /* heaviest search */
599 max_cpu_irq
= tmp_cpu_irq
; /* load */
600 max_loaded
= tmp_loaded
; /* processor */
601 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
604 * if imbalance is less than approx 10% of max load, then
605 * observe diminishing returns action. - quit
607 if (imbalance
< (max_cpu_irq
>> 3))
608 goto not_worth_the_effort
;
611 /* if we select an IRQ to move that can't go where we want, then
612 * see if there is another one to try.
616 for (j
= 0; j
< nr_irqs
; j
++) {
617 /* Is this an active IRQ? */
618 desc
= irq_to_desc(j
);
621 if (imbalance
<= IRQ_DELTA(max_loaded
, j
))
623 /* Try to find the IRQ that is closest to the imbalance
624 * without going over.
626 if (move_this_load
< IRQ_DELTA(max_loaded
, j
)) {
627 move_this_load
= IRQ_DELTA(max_loaded
, j
);
631 if (selected_irq
== -1)
634 imbalance
= move_this_load
;
636 /* For physical_balance case, we accumulated both load
637 * values in the one of the siblings cpu_irq[],
638 * to use the same code for physical and logical processors
639 * as much as possible.
641 * NOTE: the cpu_irq[] array holds the sum of the load for
642 * sibling A and sibling B in the slot for the lowest numbered
643 * sibling (A), _AND_ the load for sibling B in the slot for
644 * the higher numbered sibling.
646 * We seek the least loaded sibling by making the comparison
649 load
= CPU_IRQ(min_loaded
) >> 1;
650 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
651 if (load
> CPU_IRQ(j
)) {
652 /* This won't change cpu_sibling_map[min_loaded] */
658 cpus_and(allowed_mask
,
660 balance_irq_affinity
[selected_irq
]);
661 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
662 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
664 if (!cpus_empty(tmp
)) {
665 /* mark for change destination */
666 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
668 /* Since we made a change, come back sooner to
669 * check for more variation.
671 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
672 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
677 not_worth_the_effort
:
679 * if we did not find an IRQ to move, then adjust the time interval
682 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
683 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
687 static int balanced_irq(void *unused
)
690 unsigned long prev_balance_time
= jiffies
;
691 long time_remaining
= balanced_irq_interval
;
692 struct irq_desc
*desc
;
694 /* push everything to CPU 0 to give us a starting point. */
695 for (i
= 0 ; i
< nr_irqs
; i
++) {
696 desc
= irq_to_desc(i
);
697 desc
->pending_mask
= cpumask_of_cpu(0);
698 set_pending_irq(i
, cpumask_of_cpu(0));
703 time_remaining
= schedule_timeout_interruptible(time_remaining
);
705 if (time_after(jiffies
,
706 prev_balance_time
+balanced_irq_interval
)) {
709 prev_balance_time
= jiffies
;
710 time_remaining
= balanced_irq_interval
;
717 static int __init
balanced_irq_init(void)
720 struct cpuinfo_x86
*c
;
723 cpus_shift_right(tmp
, cpu_online_map
, 2);
725 /* When not overwritten by the command line ask subarchitecture. */
726 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
727 irqbalance_disabled
= NO_BALANCE_IRQ
;
728 if (irqbalance_disabled
)
731 /* disable irqbalance completely if there is only one processor online */
732 if (num_online_cpus() < 2) {
733 irqbalance_disabled
= 1;
737 * Enable physical balance only if more than 1 physical processor
740 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
741 physical_balance
= 1;
743 for_each_online_cpu(i
) {
744 irq_cpu_data
[i
].irq_delta
= kzalloc(sizeof(unsigned long) * nr_irqs
, GFP_KERNEL
);
745 irq_cpu_data
[i
].last_irq
= kzalloc(sizeof(unsigned long) * nr_irqs
, GFP_KERNEL
);
746 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
747 printk(KERN_ERR
"balanced_irq_init: out of memory");
752 printk(KERN_INFO
"Starting balanced_irq\n");
753 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
755 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
757 for_each_possible_cpu(i
) {
758 kfree(irq_cpu_data
[i
].irq_delta
);
759 irq_cpu_data
[i
].irq_delta
= NULL
;
760 kfree(irq_cpu_data
[i
].last_irq
);
761 irq_cpu_data
[i
].last_irq
= NULL
;
766 int __devinit
irqbalance_disable(char *str
)
768 irqbalance_disabled
= 1;
772 __setup("noirqbalance", irqbalance_disable
);
774 late_initcall(balanced_irq_init
);
775 #endif /* CONFIG_IRQBALANCE */
776 #endif /* CONFIG_SMP */
779 void send_IPI_self(int vector
)
786 apic_wait_icr_idle();
787 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
789 * Send the IPI. The write to APIC_ICR fires this off.
791 apic_write(APIC_ICR
, cfg
);
793 #endif /* !CONFIG_SMP */
797 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
798 * specific CPU-side IRQs.
802 static int pirq_entries
[MAX_PIRQS
];
803 static int pirqs_enabled
;
804 int skip_ioapic_setup
;
806 static int __init
ioapic_pirq_setup(char *str
)
809 int ints
[MAX_PIRQS
+1];
811 get_options(str
, ARRAY_SIZE(ints
), ints
);
813 for (i
= 0; i
< MAX_PIRQS
; i
++)
814 pirq_entries
[i
] = -1;
817 apic_printk(APIC_VERBOSE
, KERN_INFO
818 "PIRQ redirection, working around broken MP-BIOS.\n");
820 if (ints
[0] < MAX_PIRQS
)
823 for (i
= 0; i
< max
; i
++) {
824 apic_printk(APIC_VERBOSE
, KERN_DEBUG
825 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
827 * PIRQs are mapped upside down, usually.
829 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
834 __setup("pirq=", ioapic_pirq_setup
);
837 * Find the IRQ entry number of a certain pin.
839 static int find_irq_entry(int apic
, int pin
, int type
)
843 for (i
= 0; i
< mp_irq_entries
; i
++)
844 if (mp_irqs
[i
].mp_irqtype
== type
&&
845 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
846 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
847 mp_irqs
[i
].mp_dstirq
== pin
)
854 * Find the pin to which IRQ[irq] (ISA) is connected
856 static int __init
find_isa_irq_pin(int irq
, int type
)
860 for (i
= 0; i
< mp_irq_entries
; i
++) {
861 int lbus
= mp_irqs
[i
].mp_srcbus
;
863 if (test_bit(lbus
, mp_bus_not_pci
) &&
864 (mp_irqs
[i
].mp_irqtype
== type
) &&
865 (mp_irqs
[i
].mp_srcbusirq
== irq
))
867 return mp_irqs
[i
].mp_dstirq
;
872 static int __init
find_isa_irq_apic(int irq
, int type
)
876 for (i
= 0; i
< mp_irq_entries
; i
++) {
877 int lbus
= mp_irqs
[i
].mp_srcbus
;
879 if (test_bit(lbus
, mp_bus_not_pci
) &&
880 (mp_irqs
[i
].mp_irqtype
== type
) &&
881 (mp_irqs
[i
].mp_srcbusirq
== irq
))
884 if (i
< mp_irq_entries
) {
886 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
887 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
896 * Find a specific PCI IRQ entry.
897 * Not an __init, possibly needed by modules
899 static int pin_2_irq(int idx
, int apic
, int pin
);
901 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
903 int apic
, i
, best_guess
= -1;
905 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
906 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
907 if (test_bit(bus
, mp_bus_not_pci
)) {
908 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
911 for (i
= 0; i
< mp_irq_entries
; i
++) {
912 int lbus
= mp_irqs
[i
].mp_srcbus
;
914 for (apic
= 0; apic
< nr_ioapics
; apic
++)
915 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
916 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
919 if (!test_bit(lbus
, mp_bus_not_pci
) &&
920 !mp_irqs
[i
].mp_irqtype
&&
922 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
923 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
925 if (!(apic
|| IO_APIC_IRQ(irq
)))
928 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
931 * Use the first all-but-pin matching entry as a
932 * best-guess fuzzy result for broken mptables.
940 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
943 * This function currently is only a helper for the i386 smp boot process where
944 * we need to reprogram the ioredtbls to cater for the cpus which have come online
945 * so mask in all cases should simply be TARGET_CPUS
948 void __init
setup_ioapic_dest(void)
950 int pin
, ioapic
, irq
, irq_entry
;
952 if (skip_ioapic_setup
== 1)
955 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
956 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
957 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
960 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
961 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
968 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
970 * EISA Edge/Level control register, ELCR
972 static int EISA_ELCR(unsigned int irq
)
975 unsigned int port
= 0x4d0 + (irq
>> 3);
976 return (inb(port
) >> (irq
& 7)) & 1;
978 apic_printk(APIC_VERBOSE
, KERN_INFO
979 "Broken MPtable reports ISA irq %d\n", irq
);
984 /* ISA interrupts are always polarity zero edge triggered,
985 * when listed as conforming in the MP table. */
987 #define default_ISA_trigger(idx) (0)
988 #define default_ISA_polarity(idx) (0)
990 /* EISA interrupts are always polarity zero and can be edge or level
991 * trigger depending on the ELCR value. If an interrupt is listed as
992 * EISA conforming in the MP table, that means its trigger type must
993 * be read in from the ELCR */
995 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
996 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
998 /* PCI interrupts are always polarity one level triggered,
999 * when listed as conforming in the MP table. */
1001 #define default_PCI_trigger(idx) (1)
1002 #define default_PCI_polarity(idx) (1)
1004 /* MCA interrupts are always polarity zero level triggered,
1005 * when listed as conforming in the MP table. */
1007 #define default_MCA_trigger(idx) (1)
1008 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1010 static int MPBIOS_polarity(int idx
)
1012 int bus
= mp_irqs
[idx
].mp_srcbus
;
1016 * Determine IRQ line polarity (high active or low active):
1018 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
1019 case 0: /* conforms, ie. bus-type dependent polarity */
1021 polarity
= test_bit(bus
, mp_bus_not_pci
)?
1022 default_ISA_polarity(idx
):
1023 default_PCI_polarity(idx
);
1026 case 1: /* high active */
1031 case 2: /* reserved */
1033 printk(KERN_WARNING
"broken BIOS!!\n");
1037 case 3: /* low active */
1042 default: /* invalid */
1044 printk(KERN_WARNING
"broken BIOS!!\n");
1052 static int MPBIOS_trigger(int idx
)
1054 int bus
= mp_irqs
[idx
].mp_srcbus
;
1058 * Determine IRQ trigger mode (edge or level sensitive):
1060 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
1061 case 0: /* conforms, ie. bus-type dependent */
1063 trigger
= test_bit(bus
, mp_bus_not_pci
)?
1064 default_ISA_trigger(idx
):
1065 default_PCI_trigger(idx
);
1066 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1067 switch (mp_bus_id_to_type
[bus
]) {
1068 case MP_BUS_ISA
: /* ISA pin */
1070 /* set before the switch */
1073 case MP_BUS_EISA
: /* EISA pin */
1075 trigger
= default_EISA_trigger(idx
);
1078 case MP_BUS_PCI
: /* PCI pin */
1080 /* set before the switch */
1083 case MP_BUS_MCA
: /* MCA pin */
1085 trigger
= default_MCA_trigger(idx
);
1090 printk(KERN_WARNING
"broken BIOS!!\n");
1103 case 2: /* reserved */
1105 printk(KERN_WARNING
"broken BIOS!!\n");
1114 default: /* invalid */
1116 printk(KERN_WARNING
"broken BIOS!!\n");
1124 static inline int irq_polarity(int idx
)
1126 return MPBIOS_polarity(idx
);
1129 static inline int irq_trigger(int idx
)
1131 return MPBIOS_trigger(idx
);
1134 static int pin_2_irq(int idx
, int apic
, int pin
)
1137 int bus
= mp_irqs
[idx
].mp_srcbus
;
1140 * Debugging check, we are in big trouble if this message pops up!
1142 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1143 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1145 if (test_bit(bus
, mp_bus_not_pci
))
1146 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1149 * PCI IRQs are mapped in order
1153 irq
+= nr_ioapic_registers
[i
++];
1157 * For MPS mode, so far only needed by ES7000 platform
1159 if (ioapic_renumber_irq
)
1160 irq
= ioapic_renumber_irq(apic
, irq
);
1164 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1166 if ((pin
>= 16) && (pin
<= 23)) {
1167 if (pirq_entries
[pin
-16] != -1) {
1168 if (!pirq_entries
[pin
-16]) {
1169 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1170 "disabling PIRQ%d\n", pin
-16);
1172 irq
= pirq_entries
[pin
-16];
1173 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1174 "using PIRQ%d -> IRQ %d\n",
1182 static inline int IO_APIC_irq_trigger(int irq
)
1186 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1187 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1188 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1189 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1190 return irq_trigger(idx
);
1194 * nonexistent IRQs are edge default
1199 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1200 static u8 irq_vector_init_first __initdata
= FIRST_DEVICE_VECTOR
;
1201 static u8
*irq_vector
;
1203 static void __init
irq_vector_init_work(void *data
)
1205 struct dyn_array
*da
= data
;
1209 irq_vec
= *da
->name
;
1211 irq_vec
[0] = irq_vector_init_first
;
1214 DEFINE_DYN_ARRAY(irq_vector
, sizeof(u8
), nr_irqs
, PAGE_SIZE
, irq_vector_init_work
);
1216 static int __assign_irq_vector(int irq
)
1218 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
;
1221 BUG_ON((unsigned)irq
>= nr_irqs
);
1223 if (irq_vector
[irq
] > 0)
1224 return irq_vector
[irq
];
1226 vector
= current_vector
;
1227 offset
= current_offset
;
1230 if (vector
>= first_system_vector
) {
1231 offset
= (offset
+ 1) % 8;
1232 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1234 if (vector
== current_vector
)
1236 if (test_and_set_bit(vector
, used_vectors
))
1239 current_vector
= vector
;
1240 current_offset
= offset
;
1241 irq_vector
[irq
] = vector
;
1246 static int assign_irq_vector(int irq
)
1248 unsigned long flags
;
1251 spin_lock_irqsave(&vector_lock
, flags
);
1252 vector
= __assign_irq_vector(irq
);
1253 spin_unlock_irqrestore(&vector_lock
, flags
);
1258 static struct irq_chip ioapic_chip
;
1260 #define IOAPIC_AUTO -1
1261 #define IOAPIC_EDGE 0
1262 #define IOAPIC_LEVEL 1
1264 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1266 struct irq_desc
*desc
;
1268 desc
= irq_to_desc(irq
);
1269 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1270 trigger
== IOAPIC_LEVEL
) {
1271 desc
->status
|= IRQ_LEVEL
;
1272 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1273 handle_fasteoi_irq
, "fasteoi");
1275 desc
->status
&= ~IRQ_LEVEL
;
1276 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1277 handle_edge_irq
, "edge");
1279 set_intr_gate(vector
, interrupt
[irq
]);
1282 static void __init
setup_IO_APIC_irqs(void)
1284 struct IO_APIC_route_entry entry
;
1285 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1287 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1289 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1290 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1293 * add it to the IO-APIC irq-routing table:
1295 memset(&entry
, 0, sizeof(entry
));
1297 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1298 entry
.dest_mode
= INT_DEST_MODE
;
1299 entry
.mask
= 0; /* enable IRQ */
1300 entry
.dest
.logical
.logical_dest
=
1301 cpu_mask_to_apicid(TARGET_CPUS
);
1303 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1306 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1307 " IO-APIC (apicid-pin) %d-%d",
1308 mp_ioapics
[apic
].mp_apicid
,
1312 apic_printk(APIC_VERBOSE
, ", %d-%d",
1313 mp_ioapics
[apic
].mp_apicid
, pin
);
1317 if (!first_notcon
) {
1318 apic_printk(APIC_VERBOSE
, " not connected.\n");
1322 entry
.trigger
= irq_trigger(idx
);
1323 entry
.polarity
= irq_polarity(idx
);
1325 if (irq_trigger(idx
)) {
1330 irq
= pin_2_irq(idx
, apic
, pin
);
1332 * skip adding the timer int on secondary nodes, which causes
1333 * a small but painful rift in the time-space continuum
1335 if (multi_timer_check(apic
, irq
))
1338 add_pin_to_irq(irq
, apic
, pin
);
1340 if (!apic
&& !IO_APIC_IRQ(irq
))
1343 if (IO_APIC_IRQ(irq
)) {
1344 vector
= assign_irq_vector(irq
);
1345 entry
.vector
= vector
;
1346 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1348 if (!apic
&& (irq
< 16))
1349 disable_8259A_irq(irq
);
1351 ioapic_write_entry(apic
, pin
, entry
);
1356 apic_printk(APIC_VERBOSE
, " not connected.\n");
1360 * Set up the timer pin, possibly with the 8259A-master behind.
1362 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1365 struct IO_APIC_route_entry entry
;
1367 memset(&entry
, 0, sizeof(entry
));
1370 * We use logical delivery to get the timer IRQ
1373 entry
.dest_mode
= INT_DEST_MODE
;
1374 entry
.mask
= 1; /* mask IRQ now */
1375 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1376 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1379 entry
.vector
= vector
;
1382 * The timer IRQ doesn't have to know that behind the
1383 * scene we may have a 8259A-master in AEOI mode ...
1385 ioapic_register_intr(0, vector
, IOAPIC_EDGE
);
1388 * Add it to the IO-APIC irq-routing table:
1390 ioapic_write_entry(apic
, pin
, entry
);
1394 __apicdebuginit(void) print_IO_APIC(void)
1397 union IO_APIC_reg_00 reg_00
;
1398 union IO_APIC_reg_01 reg_01
;
1399 union IO_APIC_reg_02 reg_02
;
1400 union IO_APIC_reg_03 reg_03
;
1401 unsigned long flags
;
1403 if (apic_verbosity
== APIC_QUIET
)
1406 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1407 for (i
= 0; i
< nr_ioapics
; i
++)
1408 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1409 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1412 * We are a bit conservative about what we expect. We have to
1413 * know about every hardware change ASAP.
1415 printk(KERN_INFO
"testing the IO APIC.......................\n");
1417 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1419 spin_lock_irqsave(&ioapic_lock
, flags
);
1420 reg_00
.raw
= io_apic_read(apic
, 0);
1421 reg_01
.raw
= io_apic_read(apic
, 1);
1422 if (reg_01
.bits
.version
>= 0x10)
1423 reg_02
.raw
= io_apic_read(apic
, 2);
1424 if (reg_01
.bits
.version
>= 0x20)
1425 reg_03
.raw
= io_apic_read(apic
, 3);
1426 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1428 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1429 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1430 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1431 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1432 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1434 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1435 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1437 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1438 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1441 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1442 * but the value of reg_02 is read as the previous read register
1443 * value, so ignore it if reg_02 == reg_01.
1445 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1446 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1447 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1451 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1452 * or reg_03, but the value of reg_0[23] is read as the previous read
1453 * register value, so ignore it if reg_03 == reg_0[12].
1455 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1456 reg_03
.raw
!= reg_01
.raw
) {
1457 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1458 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1461 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1463 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1464 " Stat Dest Deli Vect: \n");
1466 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1467 struct IO_APIC_route_entry entry
;
1469 entry
= ioapic_read_entry(apic
, i
);
1471 printk(KERN_DEBUG
" %02x %03X %02X ",
1473 entry
.dest
.logical
.logical_dest
,
1474 entry
.dest
.physical
.physical_dest
1477 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1482 entry
.delivery_status
,
1484 entry
.delivery_mode
,
1489 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1490 for (i
= 0; i
< nr_irqs
; i
++) {
1491 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1494 printk(KERN_DEBUG
"IRQ%d ", i
);
1496 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1499 entry
= irq_2_pin
+ entry
->next
;
1504 printk(KERN_INFO
".................................... done.\n");
1509 __apicdebuginit(void) print_APIC_bitfield(int base
)
1514 if (apic_verbosity
== APIC_QUIET
)
1517 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1518 for (i
= 0; i
< 8; i
++) {
1519 v
= apic_read(base
+ i
*0x10);
1520 for (j
= 0; j
< 32; j
++) {
1530 __apicdebuginit(void) print_local_APIC(void *dummy
)
1532 unsigned int v
, ver
, maxlvt
;
1535 if (apic_verbosity
== APIC_QUIET
)
1538 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1539 smp_processor_id(), hard_smp_processor_id());
1540 v
= apic_read(APIC_ID
);
1541 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1543 v
= apic_read(APIC_LVR
);
1544 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1545 ver
= GET_APIC_VERSION(v
);
1546 maxlvt
= lapic_get_maxlvt();
1548 v
= apic_read(APIC_TASKPRI
);
1549 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1551 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1552 v
= apic_read(APIC_ARBPRI
);
1553 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1554 v
& APIC_ARBPRI_MASK
);
1555 v
= apic_read(APIC_PROCPRI
);
1556 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1559 v
= apic_read(APIC_EOI
);
1560 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1561 v
= apic_read(APIC_RRR
);
1562 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1563 v
= apic_read(APIC_LDR
);
1564 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1565 v
= apic_read(APIC_DFR
);
1566 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1567 v
= apic_read(APIC_SPIV
);
1568 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1570 printk(KERN_DEBUG
"... APIC ISR field:\n");
1571 print_APIC_bitfield(APIC_ISR
);
1572 printk(KERN_DEBUG
"... APIC TMR field:\n");
1573 print_APIC_bitfield(APIC_TMR
);
1574 printk(KERN_DEBUG
"... APIC IRR field:\n");
1575 print_APIC_bitfield(APIC_IRR
);
1577 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1578 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1579 apic_write(APIC_ESR
, 0);
1580 v
= apic_read(APIC_ESR
);
1581 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1584 icr
= apic_icr_read();
1585 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1586 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1588 v
= apic_read(APIC_LVTT
);
1589 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1591 if (maxlvt
> 3) { /* PC is LVT#4. */
1592 v
= apic_read(APIC_LVTPC
);
1593 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1595 v
= apic_read(APIC_LVT0
);
1596 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1597 v
= apic_read(APIC_LVT1
);
1598 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1600 if (maxlvt
> 2) { /* ERR is LVT#3. */
1601 v
= apic_read(APIC_LVTERR
);
1602 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1605 v
= apic_read(APIC_TMICT
);
1606 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1607 v
= apic_read(APIC_TMCCT
);
1608 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1609 v
= apic_read(APIC_TDCR
);
1610 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1614 __apicdebuginit(void) print_all_local_APICs(void)
1616 on_each_cpu(print_local_APIC
, NULL
, 1);
1619 __apicdebuginit(void) print_PIC(void)
1622 unsigned long flags
;
1624 if (apic_verbosity
== APIC_QUIET
)
1627 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1629 spin_lock_irqsave(&i8259A_lock
, flags
);
1631 v
= inb(0xa1) << 8 | inb(0x21);
1632 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1634 v
= inb(0xa0) << 8 | inb(0x20);
1635 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1639 v
= inb(0xa0) << 8 | inb(0x20);
1643 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1645 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1647 v
= inb(0x4d1) << 8 | inb(0x4d0);
1648 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1651 __apicdebuginit(int) print_all_ICs(void)
1654 print_all_local_APICs();
1660 fs_initcall(print_all_ICs
);
1663 static void __init
enable_IO_APIC(void)
1665 union IO_APIC_reg_01 reg_01
;
1666 int i8259_apic
, i8259_pin
;
1668 unsigned long flags
;
1670 for (i
= 0; i
< pin_map_size
; i
++) {
1671 irq_2_pin
[i
].pin
= -1;
1672 irq_2_pin
[i
].next
= 0;
1675 for (i
= 0; i
< MAX_PIRQS
; i
++)
1676 pirq_entries
[i
] = -1;
1679 * The number of IO-APIC IRQ registers (== #pins):
1681 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1682 spin_lock_irqsave(&ioapic_lock
, flags
);
1683 reg_01
.raw
= io_apic_read(apic
, 1);
1684 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1685 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1687 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1689 /* See if any of the pins is in ExtINT mode */
1690 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1691 struct IO_APIC_route_entry entry
;
1692 entry
= ioapic_read_entry(apic
, pin
);
1695 /* If the interrupt line is enabled and in ExtInt mode
1696 * I have found the pin where the i8259 is connected.
1698 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1699 ioapic_i8259
.apic
= apic
;
1700 ioapic_i8259
.pin
= pin
;
1706 /* Look to see what if the MP table has reported the ExtINT */
1707 /* If we could not find the appropriate pin by looking at the ioapic
1708 * the i8259 probably is not connected the ioapic but give the
1709 * mptable a chance anyway.
1711 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1712 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1713 /* Trust the MP table if nothing is setup in the hardware */
1714 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1715 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1716 ioapic_i8259
.pin
= i8259_pin
;
1717 ioapic_i8259
.apic
= i8259_apic
;
1719 /* Complain if the MP table and the hardware disagree */
1720 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1721 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1723 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1727 * Do not trust the IO-APIC being empty at bootup
1733 * Not an __init, needed by the reboot code
1735 void disable_IO_APIC(void)
1738 * Clear the IO-APIC before rebooting:
1743 * If the i8259 is routed through an IOAPIC
1744 * Put that IOAPIC in virtual wire mode
1745 * so legacy interrupts can be delivered.
1747 if (ioapic_i8259
.pin
!= -1) {
1748 struct IO_APIC_route_entry entry
;
1750 memset(&entry
, 0, sizeof(entry
));
1751 entry
.mask
= 0; /* Enabled */
1752 entry
.trigger
= 0; /* Edge */
1754 entry
.polarity
= 0; /* High */
1755 entry
.delivery_status
= 0;
1756 entry
.dest_mode
= 0; /* Physical */
1757 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1759 entry
.dest
.physical
.physical_dest
= read_apic_id();
1762 * Add it to the IO-APIC irq-routing table:
1764 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1766 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1770 * function to set the IO-APIC physical IDs based on the
1771 * values stored in the MPC table.
1773 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1776 static void __init
setup_ioapic_ids_from_mpc(void)
1778 union IO_APIC_reg_00 reg_00
;
1779 physid_mask_t phys_id_present_map
;
1782 unsigned char old_id
;
1783 unsigned long flags
;
1785 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1789 * Don't check I/O APIC IDs for xAPIC systems. They have
1790 * no meaning without the serial APIC bus.
1792 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1793 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1796 * This is broken; anything with a real cpu count has to
1797 * circumvent this idiocy regardless.
1799 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1802 * Set the IOAPIC ID to the value stored in the MPC table.
1804 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1806 /* Read the register 0 value */
1807 spin_lock_irqsave(&ioapic_lock
, flags
);
1808 reg_00
.raw
= io_apic_read(apic
, 0);
1809 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1811 old_id
= mp_ioapics
[apic
].mp_apicid
;
1813 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1814 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1815 apic
, mp_ioapics
[apic
].mp_apicid
);
1816 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1818 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1822 * Sanity check, is the ID really free? Every APIC in a
1823 * system must have a unique ID or we get lots of nice
1824 * 'stuck on smp_invalidate_needed IPI wait' messages.
1826 if (check_apicid_used(phys_id_present_map
,
1827 mp_ioapics
[apic
].mp_apicid
)) {
1828 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1829 apic
, mp_ioapics
[apic
].mp_apicid
);
1830 for (i
= 0; i
< get_physical_broadcast(); i
++)
1831 if (!physid_isset(i
, phys_id_present_map
))
1833 if (i
>= get_physical_broadcast())
1834 panic("Max APIC ID exceeded!\n");
1835 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1837 physid_set(i
, phys_id_present_map
);
1838 mp_ioapics
[apic
].mp_apicid
= i
;
1841 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1842 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1843 "phys_id_present_map\n",
1844 mp_ioapics
[apic
].mp_apicid
);
1845 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1850 * We need to adjust the IRQ routing table
1851 * if the ID changed.
1853 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1854 for (i
= 0; i
< mp_irq_entries
; i
++)
1855 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1856 mp_irqs
[i
].mp_dstapic
1857 = mp_ioapics
[apic
].mp_apicid
;
1860 * Read the right value from the MPC table and
1861 * write it into the ID register.
1863 apic_printk(APIC_VERBOSE
, KERN_INFO
1864 "...changing IO-APIC physical APIC ID to %d ...",
1865 mp_ioapics
[apic
].mp_apicid
);
1867 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1868 spin_lock_irqsave(&ioapic_lock
, flags
);
1869 io_apic_write(apic
, 0, reg_00
.raw
);
1870 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1875 spin_lock_irqsave(&ioapic_lock
, flags
);
1876 reg_00
.raw
= io_apic_read(apic
, 0);
1877 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1878 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1879 printk("could not set ID!\n");
1881 apic_printk(APIC_VERBOSE
, " ok.\n");
1885 int no_timer_check __initdata
;
1887 static int __init
notimercheck(char *s
)
1892 __setup("no_timer_check", notimercheck
);
1895 * There is a nasty bug in some older SMP boards, their mptable lies
1896 * about the timer IRQ. We do the following to work around the situation:
1898 * - timer IRQ defaults to IO-APIC IRQ
1899 * - if this function detects that timer IRQs are defunct, then we fall
1900 * back to ISA timer IRQs
1902 static int __init
timer_irq_works(void)
1904 unsigned long t1
= jiffies
;
1905 unsigned long flags
;
1910 local_save_flags(flags
);
1912 /* Let ten ticks pass... */
1913 mdelay((10 * 1000) / HZ
);
1914 local_irq_restore(flags
);
1917 * Expect a few ticks at least, to be sure some possible
1918 * glue logic does not lock up after one or two first
1919 * ticks in a non-ExtINT mode. Also the local APIC
1920 * might have cached one ExtINT interrupt. Finally, at
1921 * least one tick may be lost due to delays.
1923 if (time_after(jiffies
, t1
+ 4))
1930 * In the SMP+IOAPIC case it might happen that there are an unspecified
1931 * number of pending IRQ events unhandled. These cases are very rare,
1932 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1933 * better to do it this way as thus we do not have to be aware of
1934 * 'pending' interrupts in the IRQ path, except at this point.
1937 * Edge triggered needs to resend any interrupt
1938 * that was delayed but this is now handled in the device
1945 * Starting up a edge-triggered IO-APIC interrupt is
1946 * nasty - we need to make sure that we get the edge.
1947 * If it is already asserted for some reason, we need
1948 * return 1 to indicate that is was pending.
1950 * This is not complete - we should be able to fake
1951 * an edge even if it isn't on the 8259A...
1953 * (We do this for level-triggered IRQs too - it cannot hurt.)
1955 static unsigned int startup_ioapic_irq(unsigned int irq
)
1957 int was_pending
= 0;
1958 unsigned long flags
;
1960 spin_lock_irqsave(&ioapic_lock
, flags
);
1962 disable_8259A_irq(irq
);
1963 if (i8259A_irq_pending(irq
))
1966 __unmask_IO_APIC_irq(irq
);
1967 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1972 static void ack_ioapic_irq(unsigned int irq
)
1974 move_native_irq(irq
);
1978 static void ack_ioapic_quirk_irq(unsigned int irq
)
1983 move_native_irq(irq
);
1985 * It appears there is an erratum which affects at least version 0x11
1986 * of I/O APIC (that's the 82093AA and cores integrated into various
1987 * chipsets). Under certain conditions a level-triggered interrupt is
1988 * erroneously delivered as edge-triggered one but the respective IRR
1989 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1990 * message but it will never arrive and further interrupts are blocked
1991 * from the source. The exact reason is so far unknown, but the
1992 * phenomenon was observed when two consecutive interrupt requests
1993 * from a given source get delivered to the same CPU and the source is
1994 * temporarily disabled in between.
1996 * A workaround is to simulate an EOI message manually. We achieve it
1997 * by setting the trigger mode to edge and then to level when the edge
1998 * trigger mode gets detected in the TMR of a local APIC for a
1999 * level-triggered interrupt. We mask the source for the time of the
2000 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2001 * The idea is from Manfred Spraul. --macro
2003 i
= irq_vector
[irq
];
2005 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2009 if (!(v
& (1 << (i
& 0x1f)))) {
2010 atomic_inc(&irq_mis_count
);
2011 spin_lock(&ioapic_lock
);
2012 __mask_and_edge_IO_APIC_irq(irq
);
2013 __unmask_and_level_IO_APIC_irq(irq
);
2014 spin_unlock(&ioapic_lock
);
2018 static int ioapic_retrigger_irq(unsigned int irq
)
2020 send_IPI_self(irq_vector
[irq
]);
2025 static struct irq_chip ioapic_chip __read_mostly
= {
2027 .startup
= startup_ioapic_irq
,
2028 .mask
= mask_IO_APIC_irq
,
2029 .unmask
= unmask_IO_APIC_irq
,
2030 .ack
= ack_ioapic_irq
,
2031 .eoi
= ack_ioapic_quirk_irq
,
2033 .set_affinity
= set_ioapic_affinity_irq
,
2035 .retrigger
= ioapic_retrigger_irq
,
2039 static inline void init_IO_APIC_traps(void)
2042 struct irq_desc
*desc
;
2045 * NOTE! The local APIC isn't very good at handling
2046 * multiple interrupts at the same interrupt level.
2047 * As the interrupt level is determined by taking the
2048 * vector number and shifting that right by 4, we
2049 * want to spread these out a bit so that they don't
2050 * all fall in the same interrupt level.
2052 * Also, we've got to be careful not to trash gate
2053 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2055 for (irq
= 0; irq
< nr_irqs
; irq
++) {
2056 if (IO_APIC_IRQ(irq
) && !irq_vector
[irq
]) {
2058 * Hmm.. We don't have an entry for this,
2059 * so default to an old-fashioned 8259
2060 * interrupt if we can..
2063 make_8259A_irq(irq
);
2065 desc
= irq_to_desc(irq
);
2066 /* Strange. Oh, well.. */
2067 desc
->chip
= &no_irq_chip
;
2074 * The local APIC irq-chip implementation:
2077 static void ack_lapic_irq(unsigned int irq
)
2082 static void mask_lapic_irq(unsigned int irq
)
2086 v
= apic_read(APIC_LVT0
);
2087 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2090 static void unmask_lapic_irq(unsigned int irq
)
2094 v
= apic_read(APIC_LVT0
);
2095 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2098 static struct irq_chip lapic_chip __read_mostly
= {
2099 .name
= "local-APIC",
2100 .mask
= mask_lapic_irq
,
2101 .unmask
= unmask_lapic_irq
,
2102 .ack
= ack_lapic_irq
,
2105 static void lapic_register_intr(int irq
, int vector
)
2107 struct irq_desc
*desc
;
2109 desc
= irq_to_desc(irq
);
2110 desc
->status
&= ~IRQ_LEVEL
;
2111 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2113 set_intr_gate(vector
, interrupt
[irq
]);
2116 static void __init
setup_nmi(void)
2119 * Dirty trick to enable the NMI watchdog ...
2120 * We put the 8259A master into AEOI mode and
2121 * unmask on all local APICs LVT0 as NMI.
2123 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2124 * is from Maciej W. Rozycki - so we do not have to EOI from
2125 * the NMI handler or the timer interrupt.
2127 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2129 enable_NMI_through_LVT0();
2131 apic_printk(APIC_VERBOSE
, " done.\n");
2135 * This looks a bit hackish but it's about the only one way of sending
2136 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2137 * not support the ExtINT mode, unfortunately. We need to send these
2138 * cycles as some i82489DX-based boards have glue logic that keeps the
2139 * 8259A interrupt line asserted until INTA. --macro
2141 static inline void __init
unlock_ExtINT_logic(void)
2144 struct IO_APIC_route_entry entry0
, entry1
;
2145 unsigned char save_control
, save_freq_select
;
2147 pin
= find_isa_irq_pin(8, mp_INT
);
2152 apic
= find_isa_irq_apic(8, mp_INT
);
2158 entry0
= ioapic_read_entry(apic
, pin
);
2159 clear_IO_APIC_pin(apic
, pin
);
2161 memset(&entry1
, 0, sizeof(entry1
));
2163 entry1
.dest_mode
= 0; /* physical delivery */
2164 entry1
.mask
= 0; /* unmask IRQ now */
2165 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2166 entry1
.delivery_mode
= dest_ExtINT
;
2167 entry1
.polarity
= entry0
.polarity
;
2171 ioapic_write_entry(apic
, pin
, entry1
);
2173 save_control
= CMOS_READ(RTC_CONTROL
);
2174 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2175 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2177 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2182 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2186 CMOS_WRITE(save_control
, RTC_CONTROL
);
2187 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2188 clear_IO_APIC_pin(apic
, pin
);
2190 ioapic_write_entry(apic
, pin
, entry0
);
2194 * This code may look a bit paranoid, but it's supposed to cooperate with
2195 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2196 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2197 * fanatically on his truly buggy board.
2199 static inline void __init
check_timer(void)
2201 int apic1
, pin1
, apic2
, pin2
;
2205 unsigned long flags
;
2207 local_irq_save(flags
);
2209 ver
= apic_read(APIC_LVR
);
2210 ver
= GET_APIC_VERSION(ver
);
2213 * get/set the timer IRQ vector:
2215 disable_8259A_irq(0);
2216 vector
= assign_irq_vector(0);
2217 set_intr_gate(vector
, interrupt
[0]);
2220 * As IRQ0 is to be enabled in the 8259A, the virtual
2221 * wire has to be disabled in the local APIC. Also
2222 * timer interrupts need to be acknowledged manually in
2223 * the 8259A for the i82489DX when using the NMI
2224 * watchdog as that APIC treats NMIs as level-triggered.
2225 * The AEOI mode will finish them in the 8259A
2228 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2230 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2232 pin1
= find_isa_irq_pin(0, mp_INT
);
2233 apic1
= find_isa_irq_apic(0, mp_INT
);
2234 pin2
= ioapic_i8259
.pin
;
2235 apic2
= ioapic_i8259
.apic
;
2237 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2238 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2239 vector
, apic1
, pin1
, apic2
, pin2
);
2242 * Some BIOS writers are clueless and report the ExtINTA
2243 * I/O APIC input from the cascaded 8259A as the timer
2244 * interrupt input. So just in case, if only one pin
2245 * was found above, try it both directly and through the
2252 } else if (pin2
== -1) {
2259 * Ok, does IRQ0 through the IOAPIC work?
2262 add_pin_to_irq(0, apic1
, pin1
);
2263 setup_timer_IRQ0_pin(apic1
, pin1
, vector
);
2265 unmask_IO_APIC_irq(0);
2266 if (timer_irq_works()) {
2267 if (nmi_watchdog
== NMI_IO_APIC
) {
2269 enable_8259A_irq(0);
2271 if (disable_timer_pin_1
> 0)
2272 clear_IO_APIC_pin(0, pin1
);
2275 clear_IO_APIC_pin(apic1
, pin1
);
2277 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2278 "8254 timer not connected to IO-APIC\n");
2280 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2281 "(IRQ0) through the 8259A ...\n");
2282 apic_printk(APIC_QUIET
, KERN_INFO
2283 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2285 * legacy devices should be connected to IO APIC #0
2287 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2288 setup_timer_IRQ0_pin(apic2
, pin2
, vector
);
2289 unmask_IO_APIC_irq(0);
2290 enable_8259A_irq(0);
2291 if (timer_irq_works()) {
2292 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2293 timer_through_8259
= 1;
2294 if (nmi_watchdog
== NMI_IO_APIC
) {
2295 disable_8259A_irq(0);
2297 enable_8259A_irq(0);
2302 * Cleanup, just in case ...
2304 disable_8259A_irq(0);
2305 clear_IO_APIC_pin(apic2
, pin2
);
2306 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2309 if (nmi_watchdog
== NMI_IO_APIC
) {
2310 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2311 "through the IO-APIC - disabling NMI Watchdog!\n");
2312 nmi_watchdog
= NMI_NONE
;
2316 apic_printk(APIC_QUIET
, KERN_INFO
2317 "...trying to set up timer as Virtual Wire IRQ...\n");
2319 lapic_register_intr(0, vector
);
2320 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2321 enable_8259A_irq(0);
2323 if (timer_irq_works()) {
2324 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2327 disable_8259A_irq(0);
2328 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2329 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2331 apic_printk(APIC_QUIET
, KERN_INFO
2332 "...trying to set up timer as ExtINT IRQ...\n");
2336 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2338 unlock_ExtINT_logic();
2340 if (timer_irq_works()) {
2341 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2344 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2345 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2346 "report. Then try booting with the 'noapic' option.\n");
2348 local_irq_restore(flags
);
2352 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2353 * to devices. However there may be an I/O APIC pin available for
2354 * this interrupt regardless. The pin may be left unconnected, but
2355 * typically it will be reused as an ExtINT cascade interrupt for
2356 * the master 8259A. In the MPS case such a pin will normally be
2357 * reported as an ExtINT interrupt in the MP table. With ACPI
2358 * there is no provision for ExtINT interrupts, and in the absence
2359 * of an override it would be treated as an ordinary ISA I/O APIC
2360 * interrupt, that is edge-triggered and unmasked by default. We
2361 * used to do this, but it caused problems on some systems because
2362 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2363 * the same ExtINT cascade interrupt to drive the local APIC of the
2364 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2365 * the I/O APIC in all cases now. No actual device should request
2366 * it anyway. --macro
2368 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2370 void __init
setup_IO_APIC(void)
2374 /* Reserve all the system vectors. */
2375 for (i
= first_system_vector
; i
< NR_VECTORS
; i
++)
2376 set_bit(i
, used_vectors
);
2380 io_apic_irqs
= ~PIC_IRQS
;
2382 printk("ENABLING IO-APIC IRQs\n");
2385 * Set up IO-APIC IRQ routing.
2388 setup_ioapic_ids_from_mpc();
2390 setup_IO_APIC_irqs();
2391 init_IO_APIC_traps();
2396 * Called after all the initialization is done. If we didnt find any
2397 * APIC bugs then we can allow the modify fast path
2400 static int __init
io_apic_bug_finalize(void)
2402 if (sis_apic_bug
== -1)
2407 late_initcall(io_apic_bug_finalize
);
2409 struct sysfs_ioapic_data
{
2410 struct sys_device dev
;
2411 struct IO_APIC_route_entry entry
[0];
2413 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2415 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2417 struct IO_APIC_route_entry
*entry
;
2418 struct sysfs_ioapic_data
*data
;
2421 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2422 entry
= data
->entry
;
2423 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2424 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2429 static int ioapic_resume(struct sys_device
*dev
)
2431 struct IO_APIC_route_entry
*entry
;
2432 struct sysfs_ioapic_data
*data
;
2433 unsigned long flags
;
2434 union IO_APIC_reg_00 reg_00
;
2437 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2438 entry
= data
->entry
;
2440 spin_lock_irqsave(&ioapic_lock
, flags
);
2441 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2442 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2443 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2444 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2446 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2447 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2448 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2453 static struct sysdev_class ioapic_sysdev_class
= {
2455 .suspend
= ioapic_suspend
,
2456 .resume
= ioapic_resume
,
2459 static int __init
ioapic_init_sysfs(void)
2461 struct sys_device
*dev
;
2462 int i
, size
, error
= 0;
2464 error
= sysdev_class_register(&ioapic_sysdev_class
);
2468 for (i
= 0; i
< nr_ioapics
; i
++) {
2469 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2470 * sizeof(struct IO_APIC_route_entry
);
2471 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2472 if (!mp_ioapic_data
[i
]) {
2473 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2476 dev
= &mp_ioapic_data
[i
]->dev
;
2478 dev
->cls
= &ioapic_sysdev_class
;
2479 error
= sysdev_register(dev
);
2481 kfree(mp_ioapic_data
[i
]);
2482 mp_ioapic_data
[i
] = NULL
;
2483 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2491 device_initcall(ioapic_init_sysfs
);
2494 * Dynamic irq allocate and deallocation
2496 int create_irq(void)
2498 /* Allocate an unused irq */
2499 int irq
, new, vector
= 0;
2500 unsigned long flags
;
2503 spin_lock_irqsave(&vector_lock
, flags
);
2504 for (new = (nr_irqs
- 1); new >= 0; new--) {
2505 if (platform_legacy_irq(new))
2507 if (irq_vector
[new] != 0)
2509 vector
= __assign_irq_vector(new);
2510 if (likely(vector
> 0))
2514 spin_unlock_irqrestore(&vector_lock
, flags
);
2517 set_intr_gate(vector
, interrupt
[irq
]);
2518 dynamic_irq_init(irq
);
2523 void destroy_irq(unsigned int irq
)
2525 unsigned long flags
;
2527 dynamic_irq_cleanup(irq
);
2529 spin_lock_irqsave(&vector_lock
, flags
);
2530 clear_bit(irq_vector
[irq
], used_vectors
);
2531 irq_vector
[irq
] = 0;
2532 spin_unlock_irqrestore(&vector_lock
, flags
);
2536 * MSI message composition
2538 #ifdef CONFIG_PCI_MSI
2539 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2544 vector
= assign_irq_vector(irq
);
2546 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2548 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2551 ((INT_DEST_MODE
== 0) ?
2552 MSI_ADDR_DEST_MODE_PHYSICAL
:
2553 MSI_ADDR_DEST_MODE_LOGICAL
) |
2554 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2555 MSI_ADDR_REDIRECTION_CPU
:
2556 MSI_ADDR_REDIRECTION_LOWPRI
) |
2557 MSI_ADDR_DEST_ID(dest
);
2560 MSI_DATA_TRIGGER_EDGE
|
2561 MSI_DATA_LEVEL_ASSERT
|
2562 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2563 MSI_DATA_DELIVERY_FIXED
:
2564 MSI_DATA_DELIVERY_LOWPRI
) |
2565 MSI_DATA_VECTOR(vector
);
2571 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2577 struct irq_desc
*desc
;
2579 cpus_and(tmp
, mask
, cpu_online_map
);
2580 if (cpus_empty(tmp
))
2583 vector
= assign_irq_vector(irq
);
2587 dest
= cpu_mask_to_apicid(mask
);
2589 read_msi_msg(irq
, &msg
);
2591 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2592 msg
.data
|= MSI_DATA_VECTOR(vector
);
2593 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2594 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2596 write_msi_msg(irq
, &msg
);
2597 desc
= irq_to_desc(irq
);
2598 desc
->affinity
= mask
;
2600 #endif /* CONFIG_SMP */
2603 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2604 * which implement the MSI or MSI-X Capability Structure.
2606 static struct irq_chip msi_chip
= {
2608 .unmask
= unmask_msi_irq
,
2609 .mask
= mask_msi_irq
,
2610 .ack
= ack_ioapic_irq
,
2612 .set_affinity
= set_msi_irq_affinity
,
2614 .retrigger
= ioapic_retrigger_irq
,
2617 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2625 ret
= msi_compose_msg(dev
, irq
, &msg
);
2631 set_irq_msi(irq
, desc
);
2632 write_msi_msg(irq
, &msg
);
2634 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2640 void arch_teardown_msi_irq(unsigned int irq
)
2645 #endif /* CONFIG_PCI_MSI */
2648 * Hypertransport interrupt support
2650 #ifdef CONFIG_HT_IRQ
2654 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2656 struct ht_irq_msg msg
;
2657 fetch_ht_irq_msg(irq
, &msg
);
2659 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2660 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2662 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2663 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2665 write_ht_irq_msg(irq
, &msg
);
2668 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2672 struct irq_desc
*desc
;
2674 cpus_and(tmp
, mask
, cpu_online_map
);
2675 if (cpus_empty(tmp
))
2678 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2680 dest
= cpu_mask_to_apicid(mask
);
2682 target_ht_irq(irq
, dest
);
2683 desc
= irq_to_desc(irq
);
2684 desc
->affinity
= mask
;
2688 static struct irq_chip ht_irq_chip
= {
2690 .mask
= mask_ht_irq
,
2691 .unmask
= unmask_ht_irq
,
2692 .ack
= ack_ioapic_irq
,
2694 .set_affinity
= set_ht_irq_affinity
,
2696 .retrigger
= ioapic_retrigger_irq
,
2699 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2703 vector
= assign_irq_vector(irq
);
2705 struct ht_irq_msg msg
;
2710 cpu_set(vector
>> 8, tmp
);
2711 dest
= cpu_mask_to_apicid(tmp
);
2713 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2717 HT_IRQ_LOW_DEST_ID(dest
) |
2718 HT_IRQ_LOW_VECTOR(vector
) |
2719 ((INT_DEST_MODE
== 0) ?
2720 HT_IRQ_LOW_DM_PHYSICAL
:
2721 HT_IRQ_LOW_DM_LOGICAL
) |
2722 HT_IRQ_LOW_RQEOI_EDGE
|
2723 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2724 HT_IRQ_LOW_MT_FIXED
:
2725 HT_IRQ_LOW_MT_ARBITRATED
) |
2726 HT_IRQ_LOW_IRQ_MASKED
;
2728 write_ht_irq_msg(irq
, &msg
);
2730 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2731 handle_edge_irq
, "edge");
2735 #endif /* CONFIG_HT_IRQ */
2737 /* --------------------------------------------------------------------------
2738 ACPI-based IOAPIC Configuration
2739 -------------------------------------------------------------------------- */
2743 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2745 union IO_APIC_reg_00 reg_00
;
2746 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2748 unsigned long flags
;
2752 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2753 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2754 * supports up to 16 on one shared APIC bus.
2756 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2757 * advantage of new APIC bus architecture.
2760 if (physids_empty(apic_id_map
))
2761 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2763 spin_lock_irqsave(&ioapic_lock
, flags
);
2764 reg_00
.raw
= io_apic_read(ioapic
, 0);
2765 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2767 if (apic_id
>= get_physical_broadcast()) {
2768 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2769 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2770 apic_id
= reg_00
.bits
.ID
;
2774 * Every APIC in a system must have a unique ID or we get lots of nice
2775 * 'stuck on smp_invalidate_needed IPI wait' messages.
2777 if (check_apicid_used(apic_id_map
, apic_id
)) {
2779 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2780 if (!check_apicid_used(apic_id_map
, i
))
2784 if (i
== get_physical_broadcast())
2785 panic("Max apic_id exceeded!\n");
2787 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2788 "trying %d\n", ioapic
, apic_id
, i
);
2793 tmp
= apicid_to_cpu_present(apic_id
);
2794 physids_or(apic_id_map
, apic_id_map
, tmp
);
2796 if (reg_00
.bits
.ID
!= apic_id
) {
2797 reg_00
.bits
.ID
= apic_id
;
2799 spin_lock_irqsave(&ioapic_lock
, flags
);
2800 io_apic_write(ioapic
, 0, reg_00
.raw
);
2801 reg_00
.raw
= io_apic_read(ioapic
, 0);
2802 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2805 if (reg_00
.bits
.ID
!= apic_id
) {
2806 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2811 apic_printk(APIC_VERBOSE
, KERN_INFO
2812 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2818 int __init
io_apic_get_version(int ioapic
)
2820 union IO_APIC_reg_01 reg_01
;
2821 unsigned long flags
;
2823 spin_lock_irqsave(&ioapic_lock
, flags
);
2824 reg_01
.raw
= io_apic_read(ioapic
, 1);
2825 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2827 return reg_01
.bits
.version
;
2831 int __init
io_apic_get_redir_entries(int ioapic
)
2833 union IO_APIC_reg_01 reg_01
;
2834 unsigned long flags
;
2836 spin_lock_irqsave(&ioapic_lock
, flags
);
2837 reg_01
.raw
= io_apic_read(ioapic
, 1);
2838 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2840 return reg_01
.bits
.entries
;
2844 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2846 struct IO_APIC_route_entry entry
;
2848 if (!IO_APIC_IRQ(irq
)) {
2849 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2855 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2856 * Note that we mask (disable) IRQs now -- these get enabled when the
2857 * corresponding device driver registers for this IRQ.
2860 memset(&entry
, 0, sizeof(entry
));
2862 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2863 entry
.dest_mode
= INT_DEST_MODE
;
2864 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2865 entry
.trigger
= edge_level
;
2866 entry
.polarity
= active_high_low
;
2870 * IRQs < 16 are already in the irq_2_pin[] map
2873 add_pin_to_irq(irq
, ioapic
, pin
);
2875 entry
.vector
= assign_irq_vector(irq
);
2877 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2878 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2879 mp_ioapics
[ioapic
].mp_apicid
, pin
, entry
.vector
, irq
,
2880 edge_level
, active_high_low
);
2882 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2884 if (!ioapic
&& (irq
< 16))
2885 disable_8259A_irq(irq
);
2887 ioapic_write_entry(ioapic
, pin
, entry
);
2892 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2896 if (skip_ioapic_setup
)
2899 for (i
= 0; i
< mp_irq_entries
; i
++)
2900 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2901 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2903 if (i
>= mp_irq_entries
)
2906 *trigger
= irq_trigger(i
);
2907 *polarity
= irq_polarity(i
);
2911 #endif /* CONFIG_ACPI */
2913 static int __init
parse_disable_timer_pin_1(char *arg
)
2915 disable_timer_pin_1
= 1;
2918 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2920 static int __init
parse_enable_timer_pin_1(char *arg
)
2922 disable_timer_pin_1
= -1;
2925 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2927 static int __init
parse_noapic(char *arg
)
2929 /* disable IO-APIC */
2930 disable_ioapic_setup();
2933 early_param("noapic", parse_noapic
);
2935 void __init
ioapic_init_mappings(void)
2937 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2940 for (i
= 0; i
< nr_ioapics
; i
++) {
2941 if (smp_found_config
) {
2942 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2945 "WARNING: bogus zero IO-APIC "
2946 "address found in MPTABLE, "
2947 "disabling IO/APIC support!\n");
2948 smp_found_config
= 0;
2949 skip_ioapic_setup
= 1;
2950 goto fake_ioapic_page
;
2954 ioapic_phys
= (unsigned long)
2955 alloc_bootmem_pages(PAGE_SIZE
);
2956 ioapic_phys
= __pa(ioapic_phys
);
2958 set_fixmap_nocache(idx
, ioapic_phys
);
2959 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
2960 __fix_to_virt(idx
), ioapic_phys
);