2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
52 #include <mach_apic.h>
53 #include <mach_apicdef.h>
55 #define __apicdebuginit(type) static type __init
58 * Is the SiS APIC rmw bug present ?
59 * -1 = don't know, 0 = no, 1 = yes
61 int sis_apic_bug
= -1;
63 static DEFINE_SPINLOCK(ioapic_lock
);
64 static DEFINE_SPINLOCK(vector_lock
);
68 * Rough estimation of how many shared IRQs there are, can
74 * # of IRQ routing registers
76 int nr_ioapic_registers
[MAX_IO_APICS
];
78 /* I/O APIC entries */
79 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
82 /* MP IRQ source entries */
83 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
85 /* # of MP IRQ source entries */
88 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
89 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
92 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
94 int skip_ioapic_setup
;
96 static int __init
parse_noapic(char *arg
)
99 disable_ioapic_setup();
102 early_param("noapic", parse_noapic
);
108 struct irq_cfg
*next
;
109 struct irq_pin_list
*irq_2_pin
;
111 cpumask_t old_domain
;
112 unsigned move_cleanup_count
;
114 u8 move_in_progress
: 1;
118 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
119 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
120 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
121 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
122 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
123 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
124 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
125 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
126 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
127 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
128 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
129 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
130 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
131 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
132 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
133 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
134 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
135 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
138 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
139 /* need to be biger than size of irq_cfg_legacy */
140 static int nr_irq_cfg
= 32;
142 static int __init
parse_nr_irq_cfg(char *arg
)
145 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
152 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
154 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
156 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
159 static struct irq_cfg
*irq_cfgx
;
160 static struct irq_cfg
*irq_cfgx_free
;
161 static void __init
init_work(void *data
)
163 struct dyn_array
*da
= data
;
170 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
172 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
173 for (i
= legacy_count
; i
< *da
->nr
; i
++)
174 init_one_irq_cfg(&cfg
[i
]);
176 for (i
= 1; i
< *da
->nr
; i
++)
177 cfg
[i
-1].next
= &cfg
[i
];
179 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
180 irq_cfgx
[legacy_count
- 1].next
= NULL
;
183 #define for_each_irq_cfg(cfg) \
184 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
186 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
188 static struct irq_cfg
*irq_cfg(unsigned int irq
)
203 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
205 struct irq_cfg
*cfg
, *cfg_pri
;
209 cfg_pri
= cfg
= irq_cfgx
;
219 if (!irq_cfgx_free
) {
221 unsigned long total_bytes
;
223 * we run out of pre-allocate ones, allocate more
225 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
227 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
229 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
231 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
234 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
237 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
239 for (i
= 0; i
< nr_irq_cfg
; i
++)
240 init_one_irq_cfg(&cfg
[i
]);
242 for (i
= 1; i
< nr_irq_cfg
; i
++)
243 cfg
[i
-1].next
= &cfg
[i
];
249 irq_cfgx_free
= irq_cfgx_free
->next
;
256 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
258 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
260 /* dump the results */
263 unsigned long bytes
= sizeof(struct irq_cfg
);
265 printk(KERN_DEBUG
"=========================== %d\n", irq
);
266 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
267 for_each_irq_cfg(cfg
) {
269 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
271 printk(KERN_DEBUG
"===========================\n");
278 * This is performance-critical, we want to do it O(1)
280 * the indexing order of this array favors 1:1 mappings
281 * between pins and IRQs.
284 struct irq_pin_list
{
286 struct irq_pin_list
*next
;
289 static struct irq_pin_list
*irq_2_pin_head
;
290 /* fill one page ? */
291 static int nr_irq_2_pin
= 0x100;
292 static struct irq_pin_list
*irq_2_pin_ptr
;
293 static void __init
irq_2_pin_init_work(void *data
)
295 struct dyn_array
*da
= data
;
296 struct irq_pin_list
*pin
;
301 for (i
= 1; i
< *da
->nr
; i
++)
302 pin
[i
-1].next
= &pin
[i
];
304 irq_2_pin_ptr
= &pin
[0];
306 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
308 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
310 struct irq_pin_list
*pin
;
316 irq_2_pin_ptr
= pin
->next
;
322 * we run out of pre-allocate ones, allocate more
324 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
327 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
330 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
331 nr_irq_2_pin
, PAGE_SIZE
, 0);
334 panic("can not get more irq_2_pin\n");
336 for (i
= 1; i
< nr_irq_2_pin
; i
++)
337 pin
[i
-1].next
= &pin
[i
];
339 irq_2_pin_ptr
= pin
->next
;
347 unsigned int unused
[3];
351 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
353 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
354 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
357 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
359 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
360 writel(reg
, &io_apic
->index
);
361 return readl(&io_apic
->data
);
364 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
366 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
367 writel(reg
, &io_apic
->index
);
368 writel(value
, &io_apic
->data
);
372 * Re-write a value: to be used for read-modify-write
373 * cycles where the read already set up the index register.
375 * Older SiS APIC requires we rewrite the index register
377 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
379 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
381 writel(reg
, &io_apic
->index
);
382 writel(value
, &io_apic
->data
);
386 struct { u32 w1
, w2
; };
387 struct IO_APIC_route_entry entry
;
390 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
392 union entry_union eu
;
394 spin_lock_irqsave(&ioapic_lock
, flags
);
395 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
396 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
397 spin_unlock_irqrestore(&ioapic_lock
, flags
);
402 * When we write a new IO APIC routing entry, we need to write the high
403 * word first! If the mask bit in the low word is clear, we will enable
404 * the interrupt, and we need to make sure the entry is fully populated
405 * before that happens.
408 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
410 union entry_union eu
;
412 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
413 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
416 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
419 spin_lock_irqsave(&ioapic_lock
, flags
);
420 __ioapic_write_entry(apic
, pin
, e
);
421 spin_unlock_irqrestore(&ioapic_lock
, flags
);
425 * When we mask an IO APIC routing entry, we need to write the low
426 * word first, in order to set the mask bit before we change the
429 static void ioapic_mask_entry(int apic
, int pin
)
432 union entry_union eu
= { .entry
.mask
= 1 };
434 spin_lock_irqsave(&ioapic_lock
, flags
);
435 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
436 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
437 spin_unlock_irqrestore(&ioapic_lock
, flags
);
441 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
445 struct irq_pin_list
*entry
;
448 entry
= cfg
->irq_2_pin
;
457 io_apic_write(apic
, 0x11 + pin
*2, dest
);
458 reg
= io_apic_read(apic
, 0x10 + pin
*2);
459 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
461 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
468 static int assign_irq_vector(int irq
, cpumask_t mask
);
470 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
479 cpus_and(tmp
, mask
, cpu_online_map
);
483 if (assign_irq_vector(irq
, mask
))
486 cpus_and(tmp
, cfg
->domain
, mask
);
488 dest
= cpu_mask_to_apicid(tmp
);
490 * Only the high 8 bits are valid.
492 dest
= SET_APIC_LOGICAL_ID(dest
);
494 spin_lock_irqsave(&ioapic_lock
, flags
);
495 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
496 irq_to_desc(irq
)->affinity
= mask
;
497 spin_unlock_irqrestore(&ioapic_lock
, flags
);
500 #endif /* CONFIG_SMP */
503 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
504 * shared ISA-space IRQs, so we have to support them. We are super
505 * fast in the common case, and fast for shared ISA-space IRQs.
507 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
510 struct irq_pin_list
*entry
;
512 /* first time to refer irq_cfg, so with new */
513 cfg
= irq_cfg_alloc(irq
);
514 entry
= cfg
->irq_2_pin
;
516 entry
= get_one_free_irq_2_pin();
517 cfg
->irq_2_pin
= entry
;
520 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
524 while (entry
->next
) {
525 /* not again, please */
526 if (entry
->apic
== apic
&& entry
->pin
== pin
)
532 entry
->next
= get_one_free_irq_2_pin();
536 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
540 * Reroute an IRQ to a different pin.
542 static void __init
replace_pin_at_irq(unsigned int irq
,
543 int oldapic
, int oldpin
,
544 int newapic
, int newpin
)
546 struct irq_cfg
*cfg
= irq_cfg(irq
);
547 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
551 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
552 entry
->apic
= newapic
;
555 /* every one is different, right? */
561 /* why? call replace before add? */
563 add_pin_to_irq(irq
, newapic
, newpin
);
566 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
569 struct irq_pin_list
*entry
;
570 unsigned int pin
, reg
;
573 entry
= cfg
->irq_2_pin
;
578 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
581 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
589 static void __mask_IO_APIC_irq(unsigned int irq
)
591 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
595 static void __unmask_IO_APIC_irq(unsigned int irq
)
597 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
600 /* mask = 1, trigger = 0 */
601 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
603 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
604 IO_APIC_REDIR_LEVEL_TRIGGER
);
607 /* mask = 0, trigger = 1 */
608 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
610 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
611 IO_APIC_REDIR_MASKED
);
614 static void mask_IO_APIC_irq(unsigned int irq
)
618 spin_lock_irqsave(&ioapic_lock
, flags
);
619 __mask_IO_APIC_irq(irq
);
620 spin_unlock_irqrestore(&ioapic_lock
, flags
);
623 static void unmask_IO_APIC_irq(unsigned int irq
)
627 spin_lock_irqsave(&ioapic_lock
, flags
);
628 __unmask_IO_APIC_irq(irq
);
629 spin_unlock_irqrestore(&ioapic_lock
, flags
);
632 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
634 struct IO_APIC_route_entry entry
;
636 /* Check delivery_mode to be sure we're not clearing an SMI pin */
637 entry
= ioapic_read_entry(apic
, pin
);
638 if (entry
.delivery_mode
== dest_SMI
)
642 * Disable it in the IO-APIC irq-routing table:
644 ioapic_mask_entry(apic
, pin
);
647 static void clear_IO_APIC(void)
651 for (apic
= 0; apic
< nr_ioapics
; apic
++)
652 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
653 clear_IO_APIC_pin(apic
, pin
);
657 void send_IPI_self(int vector
)
664 apic_wait_icr_idle();
665 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
667 * Send the IPI. The write to APIC_ICR fires this off.
669 apic_write(APIC_ICR
, cfg
);
671 #endif /* !CONFIG_SMP */
675 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
676 * specific CPU-side IRQs.
680 static int pirq_entries
[MAX_PIRQS
];
681 static int pirqs_enabled
;
683 static int __init
ioapic_pirq_setup(char *str
)
686 int ints
[MAX_PIRQS
+1];
688 get_options(str
, ARRAY_SIZE(ints
), ints
);
690 for (i
= 0; i
< MAX_PIRQS
; i
++)
691 pirq_entries
[i
] = -1;
694 apic_printk(APIC_VERBOSE
, KERN_INFO
695 "PIRQ redirection, working around broken MP-BIOS.\n");
697 if (ints
[0] < MAX_PIRQS
)
700 for (i
= 0; i
< max
; i
++) {
701 apic_printk(APIC_VERBOSE
, KERN_DEBUG
702 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
704 * PIRQs are mapped upside down, usually.
706 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
711 __setup("pirq=", ioapic_pirq_setup
);
714 * Find the IRQ entry number of a certain pin.
716 static int find_irq_entry(int apic
, int pin
, int type
)
720 for (i
= 0; i
< mp_irq_entries
; i
++)
721 if (mp_irqs
[i
].mp_irqtype
== type
&&
722 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
723 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
724 mp_irqs
[i
].mp_dstirq
== pin
)
731 * Find the pin to which IRQ[irq] (ISA) is connected
733 static int __init
find_isa_irq_pin(int irq
, int type
)
737 for (i
= 0; i
< mp_irq_entries
; i
++) {
738 int lbus
= mp_irqs
[i
].mp_srcbus
;
740 if (test_bit(lbus
, mp_bus_not_pci
) &&
741 (mp_irqs
[i
].mp_irqtype
== type
) &&
742 (mp_irqs
[i
].mp_srcbusirq
== irq
))
744 return mp_irqs
[i
].mp_dstirq
;
749 static int __init
find_isa_irq_apic(int irq
, int type
)
753 for (i
= 0; i
< mp_irq_entries
; i
++) {
754 int lbus
= mp_irqs
[i
].mp_srcbus
;
756 if (test_bit(lbus
, mp_bus_not_pci
) &&
757 (mp_irqs
[i
].mp_irqtype
== type
) &&
758 (mp_irqs
[i
].mp_srcbusirq
== irq
))
761 if (i
< mp_irq_entries
) {
763 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
764 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
773 * Find a specific PCI IRQ entry.
774 * Not an __init, possibly needed by modules
776 static int pin_2_irq(int idx
, int apic
, int pin
);
778 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
780 int apic
, i
, best_guess
= -1;
782 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
783 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
784 if (test_bit(bus
, mp_bus_not_pci
)) {
785 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
788 for (i
= 0; i
< mp_irq_entries
; i
++) {
789 int lbus
= mp_irqs
[i
].mp_srcbus
;
791 for (apic
= 0; apic
< nr_ioapics
; apic
++)
792 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
793 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
796 if (!test_bit(lbus
, mp_bus_not_pci
) &&
797 !mp_irqs
[i
].mp_irqtype
&&
799 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
800 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
802 if (!(apic
|| IO_APIC_IRQ(irq
)))
805 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
808 * Use the first all-but-pin matching entry as a
809 * best-guess fuzzy result for broken mptables.
817 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
819 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
821 * EISA Edge/Level control register, ELCR
823 static int EISA_ELCR(unsigned int irq
)
826 unsigned int port
= 0x4d0 + (irq
>> 3);
827 return (inb(port
) >> (irq
& 7)) & 1;
829 apic_printk(APIC_VERBOSE
, KERN_INFO
830 "Broken MPtable reports ISA irq %d\n", irq
);
835 /* ISA interrupts are always polarity zero edge triggered,
836 * when listed as conforming in the MP table. */
838 #define default_ISA_trigger(idx) (0)
839 #define default_ISA_polarity(idx) (0)
841 /* EISA interrupts are always polarity zero and can be edge or level
842 * trigger depending on the ELCR value. If an interrupt is listed as
843 * EISA conforming in the MP table, that means its trigger type must
844 * be read in from the ELCR */
846 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
847 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
849 /* PCI interrupts are always polarity one level triggered,
850 * when listed as conforming in the MP table. */
852 #define default_PCI_trigger(idx) (1)
853 #define default_PCI_polarity(idx) (1)
855 /* MCA interrupts are always polarity zero level triggered,
856 * when listed as conforming in the MP table. */
858 #define default_MCA_trigger(idx) (1)
859 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
861 static int MPBIOS_polarity(int idx
)
863 int bus
= mp_irqs
[idx
].mp_srcbus
;
867 * Determine IRQ line polarity (high active or low active):
869 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
870 case 0: /* conforms, ie. bus-type dependent polarity */
872 polarity
= test_bit(bus
, mp_bus_not_pci
)?
873 default_ISA_polarity(idx
):
874 default_PCI_polarity(idx
);
877 case 1: /* high active */
882 case 2: /* reserved */
884 printk(KERN_WARNING
"broken BIOS!!\n");
888 case 3: /* low active */
893 default: /* invalid */
895 printk(KERN_WARNING
"broken BIOS!!\n");
903 static int MPBIOS_trigger(int idx
)
905 int bus
= mp_irqs
[idx
].mp_srcbus
;
909 * Determine IRQ trigger mode (edge or level sensitive):
911 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
912 case 0: /* conforms, ie. bus-type dependent */
914 trigger
= test_bit(bus
, mp_bus_not_pci
)?
915 default_ISA_trigger(idx
):
916 default_PCI_trigger(idx
);
917 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
918 switch (mp_bus_id_to_type
[bus
]) {
919 case MP_BUS_ISA
: /* ISA pin */
921 /* set before the switch */
924 case MP_BUS_EISA
: /* EISA pin */
926 trigger
= default_EISA_trigger(idx
);
929 case MP_BUS_PCI
: /* PCI pin */
931 /* set before the switch */
934 case MP_BUS_MCA
: /* MCA pin */
936 trigger
= default_MCA_trigger(idx
);
941 printk(KERN_WARNING
"broken BIOS!!\n");
954 case 2: /* reserved */
956 printk(KERN_WARNING
"broken BIOS!!\n");
965 default: /* invalid */
967 printk(KERN_WARNING
"broken BIOS!!\n");
975 static inline int irq_polarity(int idx
)
977 return MPBIOS_polarity(idx
);
980 static inline int irq_trigger(int idx
)
982 return MPBIOS_trigger(idx
);
985 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
986 static int pin_2_irq(int idx
, int apic
, int pin
)
989 int bus
= mp_irqs
[idx
].mp_srcbus
;
992 * Debugging check, we are in big trouble if this message pops up!
994 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
995 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
997 if (test_bit(bus
, mp_bus_not_pci
))
998 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1001 * PCI IRQs are mapped in order
1005 irq
+= nr_ioapic_registers
[i
++];
1009 * For MPS mode, so far only needed by ES7000 platform
1011 if (ioapic_renumber_irq
)
1012 irq
= ioapic_renumber_irq(apic
, irq
);
1016 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1018 if ((pin
>= 16) && (pin
<= 23)) {
1019 if (pirq_entries
[pin
-16] != -1) {
1020 if (!pirq_entries
[pin
-16]) {
1021 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1022 "disabling PIRQ%d\n", pin
-16);
1024 irq
= pirq_entries
[pin
-16];
1025 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1026 "using PIRQ%d -> IRQ %d\n",
1034 void lock_vector_lock(void)
1036 /* Used to the online set of cpus does not change
1037 * during assign_irq_vector.
1039 spin_lock(&vector_lock
);
1042 void unlock_vector_lock(void)
1044 spin_unlock(&vector_lock
);
1047 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1049 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1050 unsigned int old_vector
;
1052 struct irq_cfg
*cfg
;
1056 /* Only try and allocate irqs on cpus that are present */
1057 cpus_and(mask
, mask
, cpu_online_map
);
1059 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1062 old_vector
= cfg
->vector
;
1065 cpus_and(tmp
, cfg
->domain
, mask
);
1066 if (!cpus_empty(tmp
))
1070 for_each_cpu_mask_nr(cpu
, mask
) {
1071 cpumask_t domain
, new_mask
;
1075 domain
= vector_allocation_domain(cpu
);
1076 cpus_and(new_mask
, domain
, cpu_online_map
);
1078 vector
= current_vector
;
1079 offset
= current_offset
;
1082 if (vector
>= first_system_vector
) {
1083 /* If we run out of vectors on large boxen, must share them. */
1084 offset
= (offset
+ 1) % 8;
1085 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1087 if (unlikely(current_vector
== vector
))
1089 if (vector
== SYSCALL_VECTOR
)
1092 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1093 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1096 current_vector
= vector
;
1097 current_offset
= offset
;
1099 cfg
->move_in_progress
= 1;
1100 cfg
->old_domain
= cfg
->domain
;
1102 printk(KERN_DEBUG
"assign_irq_vector: irq %d vector %#x cpu ", irq
, vector
);
1103 for_each_cpu_mask_nr(new_cpu
, new_mask
) {
1104 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1105 printk(KERN_CONT
" %d ", new_cpu
);
1107 printk(KERN_CONT
"\n");
1108 cfg
->vector
= vector
;
1109 cfg
->domain
= domain
;
1115 static int assign_irq_vector(int irq
, cpumask_t mask
)
1118 unsigned long flags
;
1120 spin_lock_irqsave(&vector_lock
, flags
);
1121 err
= __assign_irq_vector(irq
, mask
);
1122 spin_unlock_irqrestore(&vector_lock
, flags
);
1127 static void __clear_irq_vector(int irq
)
1129 struct irq_cfg
*cfg
;
1134 BUG_ON(!cfg
->vector
);
1136 vector
= cfg
->vector
;
1137 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1138 for_each_cpu_mask_nr(cpu
, mask
)
1139 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1142 cpus_clear(cfg
->domain
);
1145 void __setup_vector_irq(int cpu
)
1147 /* Initialize vector_irq on a new cpu */
1148 /* This function must be called with vector_lock held */
1150 struct irq_cfg
*cfg
;
1152 /* Mark the inuse vectors */
1153 for_each_irq_cfg(cfg
) {
1154 if (!cpu_isset(cpu
, cfg
->domain
))
1156 vector
= cfg
->vector
;
1158 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1160 /* Mark the free vectors */
1161 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1162 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1167 if (!cpu_isset(cpu
, cfg
->domain
))
1168 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1172 static struct irq_chip ioapic_chip
;
1174 #define IOAPIC_AUTO -1
1175 #define IOAPIC_EDGE 0
1176 #define IOAPIC_LEVEL 1
1178 static inline int IO_APIC_irq_trigger(int irq
)
1182 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1183 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1184 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1185 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1186 return irq_trigger(idx
);
1190 * nonexistent IRQs are edge default
1195 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1197 struct irq_desc
*desc
;
1199 /* first time to use this irq_desc */
1201 desc
= irq_to_desc(irq
);
1203 desc
= irq_to_desc_alloc(irq
);
1205 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1206 trigger
== IOAPIC_LEVEL
) {
1207 desc
->status
|= IRQ_LEVEL
;
1208 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1209 handle_fasteoi_irq
, "fasteoi");
1211 desc
->status
&= ~IRQ_LEVEL
;
1212 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1213 handle_edge_irq
, "edge");
1217 static int setup_ioapic_entry(int apic
, int irq
,
1218 struct IO_APIC_route_entry
*entry
,
1219 unsigned int destination
, int trigger
,
1220 int polarity
, int vector
)
1223 * add it to the IO-APIC irq-routing table:
1225 memset(entry
,0,sizeof(*entry
));
1227 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1228 entry
->dest_mode
= INT_DEST_MODE
;
1229 entry
->dest
= destination
;
1231 entry
->mask
= 0; /* enable IRQ */
1232 entry
->trigger
= trigger
;
1233 entry
->polarity
= polarity
;
1234 entry
->vector
= vector
;
1236 /* Mask level triggered irqs.
1237 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1245 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1246 int trigger
, int polarity
)
1248 struct irq_cfg
*cfg
;
1249 struct IO_APIC_route_entry entry
;
1252 if (!IO_APIC_IRQ(irq
))
1258 if (assign_irq_vector(irq
, mask
))
1261 cpus_and(mask
, cfg
->domain
, mask
);
1263 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1264 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1265 "IRQ %d Mode:%i Active:%i)\n",
1266 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1267 irq
, trigger
, polarity
);
1270 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1271 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1273 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1274 mp_ioapics
[apic
].mp_apicid
, pin
);
1275 __clear_irq_vector(irq
);
1279 ioapic_register_intr(irq
, trigger
);
1281 disable_8259A_irq(irq
);
1283 ioapic_write_entry(apic
, pin
, entry
);
1286 static void __init
setup_IO_APIC_irqs(void)
1288 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1290 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1292 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1293 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1295 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1298 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1301 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1304 if (!first_notcon
) {
1305 apic_printk(APIC_VERBOSE
, " not connected.\n");
1309 irq
= pin_2_irq(idx
, apic
, pin
);
1311 if (multi_timer_check(apic
, irq
))
1314 add_pin_to_irq(irq
, apic
, pin
);
1316 setup_IO_APIC_irq(apic
, pin
, irq
,
1317 irq_trigger(idx
), irq_polarity(idx
));
1322 apic_printk(APIC_VERBOSE
, " not connected.\n");
1326 * Set up the timer pin, possibly with the 8259A-master behind.
1328 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1331 struct IO_APIC_route_entry entry
;
1333 memset(&entry
, 0, sizeof(entry
));
1336 * We use logical delivery to get the timer IRQ
1339 entry
.dest_mode
= INT_DEST_MODE
;
1340 entry
.mask
= 1; /* mask IRQ now */
1341 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1342 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1345 entry
.vector
= vector
;
1348 * The timer IRQ doesn't have to know that behind the
1349 * scene we may have a 8259A-master in AEOI mode ...
1351 ioapic_register_intr(0, IOAPIC_EDGE
);
1354 * Add it to the IO-APIC irq-routing table:
1356 ioapic_write_entry(apic
, pin
, entry
);
1360 __apicdebuginit(void) print_IO_APIC(void)
1363 union IO_APIC_reg_00 reg_00
;
1364 union IO_APIC_reg_01 reg_01
;
1365 union IO_APIC_reg_02 reg_02
;
1366 union IO_APIC_reg_03 reg_03
;
1367 unsigned long flags
;
1368 struct irq_cfg
*cfg
;
1370 if (apic_verbosity
== APIC_QUIET
)
1373 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1374 for (i
= 0; i
< nr_ioapics
; i
++)
1375 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1376 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1379 * We are a bit conservative about what we expect. We have to
1380 * know about every hardware change ASAP.
1382 printk(KERN_INFO
"testing the IO APIC.......................\n");
1384 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1386 spin_lock_irqsave(&ioapic_lock
, flags
);
1387 reg_00
.raw
= io_apic_read(apic
, 0);
1388 reg_01
.raw
= io_apic_read(apic
, 1);
1389 if (reg_01
.bits
.version
>= 0x10)
1390 reg_02
.raw
= io_apic_read(apic
, 2);
1391 if (reg_01
.bits
.version
>= 0x20)
1392 reg_03
.raw
= io_apic_read(apic
, 3);
1393 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1395 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1396 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1397 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1398 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1399 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1401 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1402 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1404 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1405 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1408 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1409 * but the value of reg_02 is read as the previous read register
1410 * value, so ignore it if reg_02 == reg_01.
1412 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1413 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1414 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1418 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1419 * or reg_03, but the value of reg_0[23] is read as the previous read
1420 * register value, so ignore it if reg_03 == reg_0[12].
1422 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1423 reg_03
.raw
!= reg_01
.raw
) {
1424 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1425 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1428 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1430 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1431 " Stat Dmod Deli Vect: \n");
1433 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1434 struct IO_APIC_route_entry entry
;
1436 entry
= ioapic_read_entry(apic
, i
);
1438 printk(KERN_DEBUG
" %02x %02X ", i
, entry
.dest
);
1440 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1445 entry
.delivery_status
,
1447 entry
.delivery_mode
,
1452 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1453 for_each_irq_cfg(cfg
) {
1454 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1457 printk(KERN_DEBUG
"IRQ%d ", i
);
1459 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1462 entry
= entry
->next
;
1467 printk(KERN_INFO
".................................... done.\n");
1472 __apicdebuginit(void) print_APIC_bitfield(int base
)
1477 if (apic_verbosity
== APIC_QUIET
)
1480 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1481 for (i
= 0; i
< 8; i
++) {
1482 v
= apic_read(base
+ i
*0x10);
1483 for (j
= 0; j
< 32; j
++) {
1493 __apicdebuginit(void) print_local_APIC(void *dummy
)
1495 unsigned int v
, ver
, maxlvt
;
1498 if (apic_verbosity
== APIC_QUIET
)
1501 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1502 smp_processor_id(), hard_smp_processor_id());
1503 v
= apic_read(APIC_ID
);
1504 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1506 v
= apic_read(APIC_LVR
);
1507 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1508 ver
= GET_APIC_VERSION(v
);
1509 maxlvt
= lapic_get_maxlvt();
1511 v
= apic_read(APIC_TASKPRI
);
1512 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1514 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1515 v
= apic_read(APIC_ARBPRI
);
1516 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1517 v
& APIC_ARBPRI_MASK
);
1518 v
= apic_read(APIC_PROCPRI
);
1519 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1522 v
= apic_read(APIC_EOI
);
1523 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1524 v
= apic_read(APIC_RRR
);
1525 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1526 v
= apic_read(APIC_LDR
);
1527 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1528 v
= apic_read(APIC_DFR
);
1529 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1530 v
= apic_read(APIC_SPIV
);
1531 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1533 printk(KERN_DEBUG
"... APIC ISR field:\n");
1534 print_APIC_bitfield(APIC_ISR
);
1535 printk(KERN_DEBUG
"... APIC TMR field:\n");
1536 print_APIC_bitfield(APIC_TMR
);
1537 printk(KERN_DEBUG
"... APIC IRR field:\n");
1538 print_APIC_bitfield(APIC_IRR
);
1540 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1541 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1542 apic_write(APIC_ESR
, 0);
1543 v
= apic_read(APIC_ESR
);
1544 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1547 icr
= apic_icr_read();
1548 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1549 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1551 v
= apic_read(APIC_LVTT
);
1552 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1554 if (maxlvt
> 3) { /* PC is LVT#4. */
1555 v
= apic_read(APIC_LVTPC
);
1556 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1558 v
= apic_read(APIC_LVT0
);
1559 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1560 v
= apic_read(APIC_LVT1
);
1561 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1563 if (maxlvt
> 2) { /* ERR is LVT#3. */
1564 v
= apic_read(APIC_LVTERR
);
1565 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1568 v
= apic_read(APIC_TMICT
);
1569 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1570 v
= apic_read(APIC_TMCCT
);
1571 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1572 v
= apic_read(APIC_TDCR
);
1573 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1577 __apicdebuginit(void) print_all_local_APICs(void)
1579 on_each_cpu(print_local_APIC
, NULL
, 1);
1582 __apicdebuginit(void) print_PIC(void)
1585 unsigned long flags
;
1587 if (apic_verbosity
== APIC_QUIET
)
1590 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1592 spin_lock_irqsave(&i8259A_lock
, flags
);
1594 v
= inb(0xa1) << 8 | inb(0x21);
1595 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1597 v
= inb(0xa0) << 8 | inb(0x20);
1598 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1602 v
= inb(0xa0) << 8 | inb(0x20);
1606 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1608 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1610 v
= inb(0x4d1) << 8 | inb(0x4d0);
1611 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1614 __apicdebuginit(int) print_all_ICs(void)
1617 print_all_local_APICs();
1623 fs_initcall(print_all_ICs
);
1626 /* Where if anywhere is the i8259 connect in external int mode */
1627 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1629 static void __init
enable_IO_APIC(void)
1631 union IO_APIC_reg_01 reg_01
;
1632 int i8259_apic
, i8259_pin
;
1634 unsigned long flags
;
1637 for (i
= 0; i
< MAX_PIRQS
; i
++)
1638 pirq_entries
[i
] = -1;
1641 * The number of IO-APIC IRQ registers (== #pins):
1643 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1644 spin_lock_irqsave(&ioapic_lock
, flags
);
1645 reg_01
.raw
= io_apic_read(apic
, 1);
1646 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1647 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1649 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1651 /* See if any of the pins is in ExtINT mode */
1652 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1653 struct IO_APIC_route_entry entry
;
1654 entry
= ioapic_read_entry(apic
, pin
);
1657 /* If the interrupt line is enabled and in ExtInt mode
1658 * I have found the pin where the i8259 is connected.
1660 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1661 ioapic_i8259
.apic
= apic
;
1662 ioapic_i8259
.pin
= pin
;
1668 /* Look to see what if the MP table has reported the ExtINT */
1669 /* If we could not find the appropriate pin by looking at the ioapic
1670 * the i8259 probably is not connected the ioapic but give the
1671 * mptable a chance anyway.
1673 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1674 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1675 /* Trust the MP table if nothing is setup in the hardware */
1676 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1677 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1678 ioapic_i8259
.pin
= i8259_pin
;
1679 ioapic_i8259
.apic
= i8259_apic
;
1681 /* Complain if the MP table and the hardware disagree */
1682 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1683 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1685 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1689 * Do not trust the IO-APIC being empty at bootup
1695 * Not an __init, needed by the reboot code
1697 void disable_IO_APIC(void)
1700 * Clear the IO-APIC before rebooting:
1705 * If the i8259 is routed through an IOAPIC
1706 * Put that IOAPIC in virtual wire mode
1707 * so legacy interrupts can be delivered.
1709 if (ioapic_i8259
.pin
!= -1) {
1710 struct IO_APIC_route_entry entry
;
1712 memset(&entry
, 0, sizeof(entry
));
1713 entry
.mask
= 0; /* Enabled */
1714 entry
.trigger
= 0; /* Edge */
1716 entry
.polarity
= 0; /* High */
1717 entry
.delivery_status
= 0;
1718 entry
.dest_mode
= 0; /* Physical */
1719 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1721 entry
.dest
= read_apic_id();
1724 * Add it to the IO-APIC irq-routing table:
1726 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1728 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1732 * function to set the IO-APIC physical IDs based on the
1733 * values stored in the MPC table.
1735 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1738 static void __init
setup_ioapic_ids_from_mpc(void)
1740 union IO_APIC_reg_00 reg_00
;
1741 physid_mask_t phys_id_present_map
;
1744 unsigned char old_id
;
1745 unsigned long flags
;
1747 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1751 * Don't check I/O APIC IDs for xAPIC systems. They have
1752 * no meaning without the serial APIC bus.
1754 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1755 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1758 * This is broken; anything with a real cpu count has to
1759 * circumvent this idiocy regardless.
1761 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1764 * Set the IOAPIC ID to the value stored in the MPC table.
1766 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1768 /* Read the register 0 value */
1769 spin_lock_irqsave(&ioapic_lock
, flags
);
1770 reg_00
.raw
= io_apic_read(apic
, 0);
1771 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1773 old_id
= mp_ioapics
[apic
].mp_apicid
;
1775 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1776 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1777 apic
, mp_ioapics
[apic
].mp_apicid
);
1778 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1780 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1784 * Sanity check, is the ID really free? Every APIC in a
1785 * system must have a unique ID or we get lots of nice
1786 * 'stuck on smp_invalidate_needed IPI wait' messages.
1788 if (check_apicid_used(phys_id_present_map
,
1789 mp_ioapics
[apic
].mp_apicid
)) {
1790 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1791 apic
, mp_ioapics
[apic
].mp_apicid
);
1792 for (i
= 0; i
< get_physical_broadcast(); i
++)
1793 if (!physid_isset(i
, phys_id_present_map
))
1795 if (i
>= get_physical_broadcast())
1796 panic("Max APIC ID exceeded!\n");
1797 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1799 physid_set(i
, phys_id_present_map
);
1800 mp_ioapics
[apic
].mp_apicid
= i
;
1803 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1804 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1805 "phys_id_present_map\n",
1806 mp_ioapics
[apic
].mp_apicid
);
1807 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1812 * We need to adjust the IRQ routing table
1813 * if the ID changed.
1815 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1816 for (i
= 0; i
< mp_irq_entries
; i
++)
1817 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1818 mp_irqs
[i
].mp_dstapic
1819 = mp_ioapics
[apic
].mp_apicid
;
1822 * Read the right value from the MPC table and
1823 * write it into the ID register.
1825 apic_printk(APIC_VERBOSE
, KERN_INFO
1826 "...changing IO-APIC physical APIC ID to %d ...",
1827 mp_ioapics
[apic
].mp_apicid
);
1829 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1830 spin_lock_irqsave(&ioapic_lock
, flags
);
1831 io_apic_write(apic
, 0, reg_00
.raw
);
1832 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1837 spin_lock_irqsave(&ioapic_lock
, flags
);
1838 reg_00
.raw
= io_apic_read(apic
, 0);
1839 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1840 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1841 printk("could not set ID!\n");
1843 apic_printk(APIC_VERBOSE
, " ok.\n");
1847 int no_timer_check __initdata
;
1849 static int __init
notimercheck(char *s
)
1854 __setup("no_timer_check", notimercheck
);
1857 * There is a nasty bug in some older SMP boards, their mptable lies
1858 * about the timer IRQ. We do the following to work around the situation:
1860 * - timer IRQ defaults to IO-APIC IRQ
1861 * - if this function detects that timer IRQs are defunct, then we fall
1862 * back to ISA timer IRQs
1864 static int __init
timer_irq_works(void)
1866 unsigned long t1
= jiffies
;
1867 unsigned long flags
;
1872 local_save_flags(flags
);
1874 /* Let ten ticks pass... */
1875 mdelay((10 * 1000) / HZ
);
1876 local_irq_restore(flags
);
1879 * Expect a few ticks at least, to be sure some possible
1880 * glue logic does not lock up after one or two first
1881 * ticks in a non-ExtINT mode. Also the local APIC
1882 * might have cached one ExtINT interrupt. Finally, at
1883 * least one tick may be lost due to delays.
1885 if (time_after(jiffies
, t1
+ 4))
1892 * In the SMP+IOAPIC case it might happen that there are an unspecified
1893 * number of pending IRQ events unhandled. These cases are very rare,
1894 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1895 * better to do it this way as thus we do not have to be aware of
1896 * 'pending' interrupts in the IRQ path, except at this point.
1899 * Edge triggered needs to resend any interrupt
1900 * that was delayed but this is now handled in the device
1907 * Starting up a edge-triggered IO-APIC interrupt is
1908 * nasty - we need to make sure that we get the edge.
1909 * If it is already asserted for some reason, we need
1910 * return 1 to indicate that is was pending.
1912 * This is not complete - we should be able to fake
1913 * an edge even if it isn't on the 8259A...
1915 * (We do this for level-triggered IRQs too - it cannot hurt.)
1917 static unsigned int startup_ioapic_irq(unsigned int irq
)
1919 int was_pending
= 0;
1920 unsigned long flags
;
1922 spin_lock_irqsave(&ioapic_lock
, flags
);
1924 disable_8259A_irq(irq
);
1925 if (i8259A_irq_pending(irq
))
1928 __unmask_IO_APIC_irq(irq
);
1929 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1934 static int ioapic_retrigger_irq(unsigned int irq
)
1936 send_IPI_self(irq_cfg(irq
)->vector
);
1942 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1944 unsigned vector
, me
;
1948 me
= smp_processor_id();
1949 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1951 struct irq_desc
*desc
;
1952 struct irq_cfg
*cfg
;
1953 irq
= __get_cpu_var(vector_irq
)[vector
];
1955 desc
= irq_to_desc(irq
);
1960 spin_lock(&desc
->lock
);
1961 if (!cfg
->move_cleanup_count
)
1964 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1967 __get_cpu_var(vector_irq
)[vector
] = -1;
1968 cfg
->move_cleanup_count
--;
1970 spin_unlock(&desc
->lock
);
1976 static void irq_complete_move(unsigned int irq
)
1978 struct irq_cfg
*cfg
= irq_cfg(irq
);
1979 unsigned vector
, me
;
1981 if (likely(!cfg
->move_in_progress
))
1984 vector
= ~get_irq_regs()->orig_ax
;
1985 me
= smp_processor_id();
1986 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1987 cpumask_t cleanup_mask
;
1989 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1990 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1991 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1992 cfg
->move_in_progress
= 0;
1996 static inline void irq_complete_move(unsigned int irq
) {}
1999 static void ack_apic_edge(unsigned int irq
)
2001 irq_complete_move(irq
);
2002 move_native_irq(irq
);
2006 atomic_t irq_mis_count
;
2007 static void ack_apic_level(unsigned int irq
)
2012 irq_complete_move(irq
);
2013 move_native_irq(irq
);
2015 * It appears there is an erratum which affects at least version 0x11
2016 * of I/O APIC (that's the 82093AA and cores integrated into various
2017 * chipsets). Under certain conditions a level-triggered interrupt is
2018 * erroneously delivered as edge-triggered one but the respective IRR
2019 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2020 * message but it will never arrive and further interrupts are blocked
2021 * from the source. The exact reason is so far unknown, but the
2022 * phenomenon was observed when two consecutive interrupt requests
2023 * from a given source get delivered to the same CPU and the source is
2024 * temporarily disabled in between.
2026 * A workaround is to simulate an EOI message manually. We achieve it
2027 * by setting the trigger mode to edge and then to level when the edge
2028 * trigger mode gets detected in the TMR of a local APIC for a
2029 * level-triggered interrupt. We mask the source for the time of the
2030 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2031 * The idea is from Manfred Spraul. --macro
2033 i
= irq_cfg(irq
)->vector
;
2035 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2039 if (!(v
& (1 << (i
& 0x1f)))) {
2040 atomic_inc(&irq_mis_count
);
2041 spin_lock(&ioapic_lock
);
2042 __mask_and_edge_IO_APIC_irq(irq
);
2043 __unmask_and_level_IO_APIC_irq(irq
);
2044 spin_unlock(&ioapic_lock
);
2048 static struct irq_chip ioapic_chip __read_mostly
= {
2050 .startup
= startup_ioapic_irq
,
2051 .mask
= mask_IO_APIC_irq
,
2052 .unmask
= unmask_IO_APIC_irq
,
2053 .ack
= ack_apic_edge
,
2054 .eoi
= ack_apic_level
,
2056 .set_affinity
= set_ioapic_affinity_irq
,
2058 .retrigger
= ioapic_retrigger_irq
,
2062 static inline void init_IO_APIC_traps(void)
2065 struct irq_desc
*desc
;
2066 struct irq_cfg
*cfg
;
2069 * NOTE! The local APIC isn't very good at handling
2070 * multiple interrupts at the same interrupt level.
2071 * As the interrupt level is determined by taking the
2072 * vector number and shifting that right by 4, we
2073 * want to spread these out a bit so that they don't
2074 * all fall in the same interrupt level.
2076 * Also, we've got to be careful not to trash gate
2077 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2079 for_each_irq_cfg(cfg
) {
2081 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2083 * Hmm.. We don't have an entry for this,
2084 * so default to an old-fashioned 8259
2085 * interrupt if we can..
2088 make_8259A_irq(irq
);
2090 desc
= irq_to_desc(irq
);
2091 /* Strange. Oh, well.. */
2092 desc
->chip
= &no_irq_chip
;
2099 * The local APIC irq-chip implementation:
2102 static void mask_lapic_irq(unsigned int irq
)
2106 v
= apic_read(APIC_LVT0
);
2107 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2110 static void unmask_lapic_irq(unsigned int irq
)
2114 v
= apic_read(APIC_LVT0
);
2115 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2118 static void ack_lapic_irq(unsigned int irq
)
2123 static struct irq_chip lapic_chip __read_mostly
= {
2124 .name
= "local-APIC",
2125 .mask
= mask_lapic_irq
,
2126 .unmask
= unmask_lapic_irq
,
2127 .ack
= ack_lapic_irq
,
2130 static void lapic_register_intr(int irq
)
2132 struct irq_desc
*desc
;
2134 desc
= irq_to_desc(irq
);
2135 desc
->status
&= ~IRQ_LEVEL
;
2136 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2140 static void __init
setup_nmi(void)
2143 * Dirty trick to enable the NMI watchdog ...
2144 * We put the 8259A master into AEOI mode and
2145 * unmask on all local APICs LVT0 as NMI.
2147 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2148 * is from Maciej W. Rozycki - so we do not have to EOI from
2149 * the NMI handler or the timer interrupt.
2151 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2153 enable_NMI_through_LVT0();
2155 apic_printk(APIC_VERBOSE
, " done.\n");
2159 * This looks a bit hackish but it's about the only one way of sending
2160 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2161 * not support the ExtINT mode, unfortunately. We need to send these
2162 * cycles as some i82489DX-based boards have glue logic that keeps the
2163 * 8259A interrupt line asserted until INTA. --macro
2165 static inline void __init
unlock_ExtINT_logic(void)
2168 struct IO_APIC_route_entry entry0
, entry1
;
2169 unsigned char save_control
, save_freq_select
;
2171 pin
= find_isa_irq_pin(8, mp_INT
);
2176 apic
= find_isa_irq_apic(8, mp_INT
);
2182 entry0
= ioapic_read_entry(apic
, pin
);
2183 clear_IO_APIC_pin(apic
, pin
);
2185 memset(&entry1
, 0, sizeof(entry1
));
2187 entry1
.dest_mode
= 0; /* physical delivery */
2188 entry1
.mask
= 0; /* unmask IRQ now */
2189 entry1
.dest
= hard_smp_processor_id();
2190 entry1
.delivery_mode
= dest_ExtINT
;
2191 entry1
.polarity
= entry0
.polarity
;
2195 ioapic_write_entry(apic
, pin
, entry1
);
2197 save_control
= CMOS_READ(RTC_CONTROL
);
2198 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2199 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2201 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2206 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2210 CMOS_WRITE(save_control
, RTC_CONTROL
);
2211 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2212 clear_IO_APIC_pin(apic
, pin
);
2214 ioapic_write_entry(apic
, pin
, entry0
);
2217 static int disable_timer_pin_1 __initdata
;
2219 static int __init
parse_disable_timer_pin_1(char *arg
)
2221 disable_timer_pin_1
= 1;
2224 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2226 int timer_through_8259 __initdata
;
2229 * This code may look a bit paranoid, but it's supposed to cooperate with
2230 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2231 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2232 * fanatically on his truly buggy board.
2234 static inline void __init
check_timer(void)
2236 struct irq_cfg
*cfg
= irq_cfg(0);
2237 int apic1
, pin1
, apic2
, pin2
;
2240 unsigned long flags
;
2242 local_irq_save(flags
);
2244 ver
= apic_read(APIC_LVR
);
2245 ver
= GET_APIC_VERSION(ver
);
2248 * get/set the timer IRQ vector:
2250 disable_8259A_irq(0);
2251 assign_irq_vector(0, TARGET_CPUS
);
2254 * As IRQ0 is to be enabled in the 8259A, the virtual
2255 * wire has to be disabled in the local APIC. Also
2256 * timer interrupts need to be acknowledged manually in
2257 * the 8259A for the i82489DX when using the NMI
2258 * watchdog as that APIC treats NMIs as level-triggered.
2259 * The AEOI mode will finish them in the 8259A
2262 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2264 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2266 pin1
= find_isa_irq_pin(0, mp_INT
);
2267 apic1
= find_isa_irq_apic(0, mp_INT
);
2268 pin2
= ioapic_i8259
.pin
;
2269 apic2
= ioapic_i8259
.apic
;
2271 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2272 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2273 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2276 * Some BIOS writers are clueless and report the ExtINTA
2277 * I/O APIC input from the cascaded 8259A as the timer
2278 * interrupt input. So just in case, if only one pin
2279 * was found above, try it both directly and through the
2286 } else if (pin2
== -1) {
2293 * Ok, does IRQ0 through the IOAPIC work?
2296 add_pin_to_irq(0, apic1
, pin1
);
2297 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2299 unmask_IO_APIC_irq(0);
2300 if (timer_irq_works()) {
2301 if (nmi_watchdog
== NMI_IO_APIC
) {
2303 enable_8259A_irq(0);
2305 if (disable_timer_pin_1
> 0)
2306 clear_IO_APIC_pin(0, pin1
);
2309 clear_IO_APIC_pin(apic1
, pin1
);
2311 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2312 "8254 timer not connected to IO-APIC\n");
2314 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2315 "(IRQ0) through the 8259A ...\n");
2316 apic_printk(APIC_QUIET
, KERN_INFO
2317 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2319 * legacy devices should be connected to IO APIC #0
2321 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2322 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2323 unmask_IO_APIC_irq(0);
2324 enable_8259A_irq(0);
2325 if (timer_irq_works()) {
2326 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2327 timer_through_8259
= 1;
2328 if (nmi_watchdog
== NMI_IO_APIC
) {
2329 disable_8259A_irq(0);
2331 enable_8259A_irq(0);
2336 * Cleanup, just in case ...
2338 disable_8259A_irq(0);
2339 clear_IO_APIC_pin(apic2
, pin2
);
2340 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2343 if (nmi_watchdog
== NMI_IO_APIC
) {
2344 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2345 "through the IO-APIC - disabling NMI Watchdog!\n");
2346 nmi_watchdog
= NMI_NONE
;
2350 apic_printk(APIC_QUIET
, KERN_INFO
2351 "...trying to set up timer as Virtual Wire IRQ...\n");
2353 lapic_register_intr(0);
2354 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2355 enable_8259A_irq(0);
2357 if (timer_irq_works()) {
2358 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2361 disable_8259A_irq(0);
2362 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2363 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2365 apic_printk(APIC_QUIET
, KERN_INFO
2366 "...trying to set up timer as ExtINT IRQ...\n");
2370 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2372 unlock_ExtINT_logic();
2374 if (timer_irq_works()) {
2375 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2378 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2379 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2380 "report. Then try booting with the 'noapic' option.\n");
2382 local_irq_restore(flags
);
2386 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2387 * to devices. However there may be an I/O APIC pin available for
2388 * this interrupt regardless. The pin may be left unconnected, but
2389 * typically it will be reused as an ExtINT cascade interrupt for
2390 * the master 8259A. In the MPS case such a pin will normally be
2391 * reported as an ExtINT interrupt in the MP table. With ACPI
2392 * there is no provision for ExtINT interrupts, and in the absence
2393 * of an override it would be treated as an ordinary ISA I/O APIC
2394 * interrupt, that is edge-triggered and unmasked by default. We
2395 * used to do this, but it caused problems on some systems because
2396 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2397 * the same ExtINT cascade interrupt to drive the local APIC of the
2398 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2399 * the I/O APIC in all cases now. No actual device should request
2400 * it anyway. --macro
2402 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2404 void __init
setup_IO_APIC(void)
2408 io_apic_irqs
= ~PIC_IRQS
;
2410 printk("ENABLING IO-APIC IRQs\n");
2413 * Set up IO-APIC IRQ routing.
2416 setup_ioapic_ids_from_mpc();
2418 setup_IO_APIC_irqs();
2419 init_IO_APIC_traps();
2424 * Called after all the initialization is done. If we didnt find any
2425 * APIC bugs then we can allow the modify fast path
2428 static int __init
io_apic_bug_finalize(void)
2430 if (sis_apic_bug
== -1)
2435 late_initcall(io_apic_bug_finalize
);
2437 struct sysfs_ioapic_data
{
2438 struct sys_device dev
;
2439 struct IO_APIC_route_entry entry
[0];
2441 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2443 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2445 struct IO_APIC_route_entry
*entry
;
2446 struct sysfs_ioapic_data
*data
;
2449 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2450 entry
= data
->entry
;
2451 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2452 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2457 static int ioapic_resume(struct sys_device
*dev
)
2459 struct IO_APIC_route_entry
*entry
;
2460 struct sysfs_ioapic_data
*data
;
2461 unsigned long flags
;
2462 union IO_APIC_reg_00 reg_00
;
2465 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2466 entry
= data
->entry
;
2468 spin_lock_irqsave(&ioapic_lock
, flags
);
2469 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2470 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2471 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2472 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2474 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2475 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2476 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2481 static struct sysdev_class ioapic_sysdev_class
= {
2483 .suspend
= ioapic_suspend
,
2484 .resume
= ioapic_resume
,
2487 static int __init
ioapic_init_sysfs(void)
2489 struct sys_device
*dev
;
2490 int i
, size
, error
= 0;
2492 error
= sysdev_class_register(&ioapic_sysdev_class
);
2496 for (i
= 0; i
< nr_ioapics
; i
++) {
2497 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2498 * sizeof(struct IO_APIC_route_entry
);
2499 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2500 if (!mp_ioapic_data
[i
]) {
2501 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2504 dev
= &mp_ioapic_data
[i
]->dev
;
2506 dev
->cls
= &ioapic_sysdev_class
;
2507 error
= sysdev_register(dev
);
2509 kfree(mp_ioapic_data
[i
]);
2510 mp_ioapic_data
[i
] = NULL
;
2511 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2519 device_initcall(ioapic_init_sysfs
);
2522 * Dynamic irq allocate and deallocation
2524 unsigned int create_irq_nr(unsigned int irq_want
)
2526 /* Allocate an unused irq */
2527 unsigned int irq
, new;
2528 unsigned long flags
;
2529 struct irq_cfg
*cfg_new
;
2531 #ifndef CONFIG_HAVE_SPARSE_IRQ
2532 /* only can use bus/dev/fn.. when per_cpu vector is used */
2533 irq_want
= nr_irqs
- 1;
2537 spin_lock_irqsave(&vector_lock
, flags
);
2538 for (new = (nr_irqs
- 1); new > 0; new--) {
2539 if (platform_legacy_irq(new))
2541 cfg_new
= irq_cfg(new);
2542 if (cfg_new
&& cfg_new
->vector
!= 0)
2545 cfg_new
= irq_cfg_alloc(new);
2546 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2550 spin_unlock_irqrestore(&vector_lock
, flags
);
2553 dynamic_irq_init(irq
);
2558 int create_irq(void)
2560 return create_irq_nr(nr_irqs
- 1);
2563 void destroy_irq(unsigned int irq
)
2565 unsigned long flags
;
2567 dynamic_irq_cleanup(irq
);
2569 spin_lock_irqsave(&vector_lock
, flags
);
2570 __clear_irq_vector(irq
);
2571 spin_unlock_irqrestore(&vector_lock
, flags
);
2575 * MSI message composition
2577 #ifdef CONFIG_PCI_MSI
2578 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2580 struct irq_cfg
*cfg
;
2586 err
= assign_irq_vector(irq
, tmp
);
2591 cpus_and(tmp
, cfg
->domain
, tmp
);
2592 dest
= cpu_mask_to_apicid(tmp
);
2594 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2597 ((INT_DEST_MODE
== 0) ?
2598 MSI_ADDR_DEST_MODE_PHYSICAL
:
2599 MSI_ADDR_DEST_MODE_LOGICAL
) |
2600 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2601 MSI_ADDR_REDIRECTION_CPU
:
2602 MSI_ADDR_REDIRECTION_LOWPRI
) |
2603 MSI_ADDR_DEST_ID(dest
);
2606 MSI_DATA_TRIGGER_EDGE
|
2607 MSI_DATA_LEVEL_ASSERT
|
2608 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2609 MSI_DATA_DELIVERY_FIXED
:
2610 MSI_DATA_DELIVERY_LOWPRI
) |
2611 MSI_DATA_VECTOR(cfg
->vector
);
2617 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2619 struct irq_cfg
*cfg
;
2624 cpus_and(tmp
, mask
, cpu_online_map
);
2625 if (cpus_empty(tmp
))
2628 if (assign_irq_vector(irq
, mask
))
2632 cpus_and(tmp
, cfg
->domain
, mask
);
2633 dest
= cpu_mask_to_apicid(tmp
);
2635 read_msi_msg(irq
, &msg
);
2637 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2638 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2639 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2640 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2642 write_msi_msg(irq
, &msg
);
2643 irq_to_desc(irq
)->affinity
= mask
;
2645 #endif /* CONFIG_SMP */
2648 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2649 * which implement the MSI or MSI-X Capability Structure.
2651 static struct irq_chip msi_chip
= {
2653 .unmask
= unmask_msi_irq
,
2654 .mask
= mask_msi_irq
,
2655 .ack
= ack_apic_edge
,
2657 .set_affinity
= set_msi_irq_affinity
,
2659 .retrigger
= ioapic_retrigger_irq
,
2663 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2668 ret
= msi_compose_msg(dev
, irq
, &msg
);
2672 set_irq_msi(irq
, desc
);
2673 write_msi_msg(irq
, &msg
);
2675 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2680 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
2684 irq
= dev
->bus
->number
;
2692 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2696 unsigned int irq_want
;
2698 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
2700 irq
= create_irq_nr(irq_want
);
2705 ret
= setup_msi_irq(dev
, desc
, irq
);
2714 void arch_teardown_msi_irq(unsigned int irq
)
2719 #endif /* CONFIG_PCI_MSI */
2722 * Hypertransport interrupt support
2724 #ifdef CONFIG_HT_IRQ
2728 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2730 struct ht_irq_msg msg
;
2731 fetch_ht_irq_msg(irq
, &msg
);
2733 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2734 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2736 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2737 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2739 write_ht_irq_msg(irq
, &msg
);
2742 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2744 struct irq_cfg
*cfg
;
2748 cpus_and(tmp
, mask
, cpu_online_map
);
2749 if (cpus_empty(tmp
))
2752 if (assign_irq_vector(irq
, mask
))
2756 cpus_and(tmp
, cfg
->domain
, mask
);
2757 dest
= cpu_mask_to_apicid(tmp
);
2759 target_ht_irq(irq
, dest
, cfg
->vector
);
2760 irq_to_desc(irq
)->affinity
= mask
;
2764 static struct irq_chip ht_irq_chip
= {
2766 .mask
= mask_ht_irq
,
2767 .unmask
= unmask_ht_irq
,
2768 .ack
= ack_apic_edge
,
2770 .set_affinity
= set_ht_irq_affinity
,
2772 .retrigger
= ioapic_retrigger_irq
,
2775 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2777 struct irq_cfg
*cfg
;
2782 err
= assign_irq_vector(irq
, tmp
);
2784 struct ht_irq_msg msg
;
2788 cpus_and(tmp
, cfg
->domain
, tmp
);
2789 dest
= cpu_mask_to_apicid(tmp
);
2791 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2795 HT_IRQ_LOW_DEST_ID(dest
) |
2796 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2797 ((INT_DEST_MODE
== 0) ?
2798 HT_IRQ_LOW_DM_PHYSICAL
:
2799 HT_IRQ_LOW_DM_LOGICAL
) |
2800 HT_IRQ_LOW_RQEOI_EDGE
|
2801 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2802 HT_IRQ_LOW_MT_FIXED
:
2803 HT_IRQ_LOW_MT_ARBITRATED
) |
2804 HT_IRQ_LOW_IRQ_MASKED
;
2806 write_ht_irq_msg(irq
, &msg
);
2808 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2809 handle_edge_irq
, "edge");
2813 #endif /* CONFIG_HT_IRQ */
2815 /* --------------------------------------------------------------------------
2816 ACPI-based IOAPIC Configuration
2817 -------------------------------------------------------------------------- */
2821 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2823 union IO_APIC_reg_00 reg_00
;
2824 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2826 unsigned long flags
;
2830 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2831 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2832 * supports up to 16 on one shared APIC bus.
2834 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2835 * advantage of new APIC bus architecture.
2838 if (physids_empty(apic_id_map
))
2839 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2841 spin_lock_irqsave(&ioapic_lock
, flags
);
2842 reg_00
.raw
= io_apic_read(ioapic
, 0);
2843 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2845 if (apic_id
>= get_physical_broadcast()) {
2846 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2847 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2848 apic_id
= reg_00
.bits
.ID
;
2852 * Every APIC in a system must have a unique ID or we get lots of nice
2853 * 'stuck on smp_invalidate_needed IPI wait' messages.
2855 if (check_apicid_used(apic_id_map
, apic_id
)) {
2857 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2858 if (!check_apicid_used(apic_id_map
, i
))
2862 if (i
== get_physical_broadcast())
2863 panic("Max apic_id exceeded!\n");
2865 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2866 "trying %d\n", ioapic
, apic_id
, i
);
2871 tmp
= apicid_to_cpu_present(apic_id
);
2872 physids_or(apic_id_map
, apic_id_map
, tmp
);
2874 if (reg_00
.bits
.ID
!= apic_id
) {
2875 reg_00
.bits
.ID
= apic_id
;
2877 spin_lock_irqsave(&ioapic_lock
, flags
);
2878 io_apic_write(ioapic
, 0, reg_00
.raw
);
2879 reg_00
.raw
= io_apic_read(ioapic
, 0);
2880 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2883 if (reg_00
.bits
.ID
!= apic_id
) {
2884 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2889 apic_printk(APIC_VERBOSE
, KERN_INFO
2890 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2896 int __init
io_apic_get_version(int ioapic
)
2898 union IO_APIC_reg_01 reg_01
;
2899 unsigned long flags
;
2901 spin_lock_irqsave(&ioapic_lock
, flags
);
2902 reg_01
.raw
= io_apic_read(ioapic
, 1);
2903 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2905 return reg_01
.bits
.version
;
2909 int __init
io_apic_get_redir_entries(int ioapic
)
2911 union IO_APIC_reg_01 reg_01
;
2912 unsigned long flags
;
2914 spin_lock_irqsave(&ioapic_lock
, flags
);
2915 reg_01
.raw
= io_apic_read(ioapic
, 1);
2916 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2918 return reg_01
.bits
.entries
;
2922 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2924 if (!IO_APIC_IRQ(irq
)) {
2925 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2931 * IRQs < 16 are already in the irq_2_pin[] map
2934 add_pin_to_irq(irq
, ioapic
, pin
);
2936 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2941 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2945 if (skip_ioapic_setup
)
2948 for (i
= 0; i
< mp_irq_entries
; i
++)
2949 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2950 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2952 if (i
>= mp_irq_entries
)
2955 *trigger
= irq_trigger(i
);
2956 *polarity
= irq_polarity(i
);
2960 #endif /* CONFIG_ACPI */
2963 * This function currently is only a helper for the i386 smp boot process where
2964 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2965 * so mask in all cases should simply be TARGET_CPUS
2968 void __init
setup_ioapic_dest(void)
2970 int pin
, ioapic
, irq
, irq_entry
;
2971 struct irq_cfg
*cfg
;
2972 struct irq_desc
*desc
;
2974 if (skip_ioapic_setup
== 1)
2977 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2978 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2979 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2980 if (irq_entry
== -1)
2982 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2984 /* setup_IO_APIC_irqs could fail to get vector for some device
2985 * when you have too many devices, because at that time only boot
2990 setup_IO_APIC_irq(ioapic
, pin
, irq
,
2991 irq_trigger(irq_entry
),
2992 irq_polarity(irq_entry
));
2994 desc
= irq_to_desc(irq
);
2995 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3003 void __init
ioapic_init_mappings(void)
3005 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3008 for (i
= 0; i
< nr_ioapics
; i
++) {
3009 if (smp_found_config
) {
3010 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3013 "WARNING: bogus zero IO-APIC "
3014 "address found in MPTABLE, "
3015 "disabling IO/APIC support!\n");
3016 smp_found_config
= 0;
3017 skip_ioapic_setup
= 1;
3018 goto fake_ioapic_page
;
3022 ioapic_phys
= (unsigned long)
3023 alloc_bootmem_pages(PAGE_SIZE
);
3024 ioapic_phys
= __pa(ioapic_phys
);
3026 set_fixmap_nocache(idx
, ioapic_phys
);
3027 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
3028 __fix_to_virt(idx
), ioapic_phys
);