2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
49 #include <asm/proto.h>
52 #include <asm/timer.h>
53 #include <asm/i8259.h>
55 #include <asm/msidef.h>
56 #include <asm/hypertransport.h>
57 #include <asm/setup.h>
58 #include <asm/irq_remapping.h>
61 #include <mach_apic.h>
62 #include <mach_apicdef.h>
64 #define __apicdebuginit(type) static type __init
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
70 int sis_apic_bug
= -1;
72 static DEFINE_SPINLOCK(ioapic_lock
);
73 static DEFINE_SPINLOCK(vector_lock
);
77 * Rough estimation of how many shared IRQs there are, can
83 * # of IRQ routing registers
85 int nr_ioapic_registers
[MAX_IO_APICS
];
87 /* I/O APIC entries */
88 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
91 /* MP IRQ source entries */
92 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
94 /* # of MP IRQ source entries */
97 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
98 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
101 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
103 int skip_ioapic_setup
;
105 static int __init
parse_noapic(char *arg
)
107 /* disable IO-APIC */
108 disable_ioapic_setup();
111 early_param("noapic", parse_noapic
);
117 struct irq_cfg
*next
;
118 struct irq_pin_list
*irq_2_pin
;
120 cpumask_t old_domain
;
121 unsigned move_cleanup_count
;
123 u8 move_in_progress
: 1;
127 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
128 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
129 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
130 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
131 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
132 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
133 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
134 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
135 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
136 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
137 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
138 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
139 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
140 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
141 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
142 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
143 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
144 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
147 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
148 /* need to be biger than size of irq_cfg_legacy */
149 static int nr_irq_cfg
= 32;
151 static int __init
parse_nr_irq_cfg(char *arg
)
154 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
161 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
163 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
165 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
168 static struct irq_cfg
*irq_cfgx
;
169 static struct irq_cfg
*irq_cfgx_free
;
170 static void __init
init_work(void *data
)
172 struct dyn_array
*da
= data
;
179 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
181 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
182 for (i
= legacy_count
; i
< *da
->nr
; i
++)
183 init_one_irq_cfg(&cfg
[i
]);
185 for (i
= 1; i
< *da
->nr
; i
++)
186 cfg
[i
-1].next
= &cfg
[i
];
188 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
189 irq_cfgx
[legacy_count
- 1].next
= NULL
;
192 #define for_each_irq_cfg(cfg) \
193 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
195 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
197 static struct irq_cfg
*irq_cfg(unsigned int irq
)
212 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
214 struct irq_cfg
*cfg
, *cfg_pri
;
218 cfg_pri
= cfg
= irq_cfgx
;
228 if (!irq_cfgx_free
) {
230 unsigned long total_bytes
;
232 * we run out of pre-allocate ones, allocate more
234 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
236 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
238 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
240 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
243 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
246 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
248 for (i
= 0; i
< nr_irq_cfg
; i
++)
249 init_one_irq_cfg(&cfg
[i
]);
251 for (i
= 1; i
< nr_irq_cfg
; i
++)
252 cfg
[i
-1].next
= &cfg
[i
];
258 irq_cfgx_free
= irq_cfgx_free
->next
;
265 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
267 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
269 /* dump the results */
272 unsigned long bytes
= sizeof(struct irq_cfg
);
274 printk(KERN_DEBUG
"=========================== %d\n", irq
);
275 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
276 for_each_irq_cfg(cfg
) {
278 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
280 printk(KERN_DEBUG
"===========================\n");
287 * This is performance-critical, we want to do it O(1)
289 * the indexing order of this array favors 1:1 mappings
290 * between pins and IRQs.
293 struct irq_pin_list
{
295 struct irq_pin_list
*next
;
298 static struct irq_pin_list
*irq_2_pin_head
;
299 /* fill one page ? */
300 static int nr_irq_2_pin
= 0x100;
301 static struct irq_pin_list
*irq_2_pin_ptr
;
302 static void __init
irq_2_pin_init_work(void *data
)
304 struct dyn_array
*da
= data
;
305 struct irq_pin_list
*pin
;
310 for (i
= 1; i
< *da
->nr
; i
++)
311 pin
[i
-1].next
= &pin
[i
];
313 irq_2_pin_ptr
= &pin
[0];
315 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
317 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
319 struct irq_pin_list
*pin
;
325 irq_2_pin_ptr
= pin
->next
;
331 * we run out of pre-allocate ones, allocate more
333 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
336 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
339 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
340 nr_irq_2_pin
, PAGE_SIZE
, 0);
343 panic("can not get more irq_2_pin\n");
345 for (i
= 1; i
< nr_irq_2_pin
; i
++)
346 pin
[i
-1].next
= &pin
[i
];
348 irq_2_pin_ptr
= pin
->next
;
356 unsigned int unused
[3];
360 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
362 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
363 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
366 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
368 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
369 writel(reg
, &io_apic
->index
);
370 return readl(&io_apic
->data
);
373 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
375 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
376 writel(reg
, &io_apic
->index
);
377 writel(value
, &io_apic
->data
);
381 * Re-write a value: to be used for read-modify-write
382 * cycles where the read already set up the index register.
384 * Older SiS APIC requires we rewrite the index register
386 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
388 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
390 writel(reg
, &io_apic
->index
);
391 writel(value
, &io_apic
->data
);
395 struct { u32 w1
, w2
; };
396 struct IO_APIC_route_entry entry
;
399 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
401 union entry_union eu
;
403 spin_lock_irqsave(&ioapic_lock
, flags
);
404 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
405 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
406 spin_unlock_irqrestore(&ioapic_lock
, flags
);
411 * When we write a new IO APIC routing entry, we need to write the high
412 * word first! If the mask bit in the low word is clear, we will enable
413 * the interrupt, and we need to make sure the entry is fully populated
414 * before that happens.
417 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
419 union entry_union eu
;
421 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
422 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
425 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
428 spin_lock_irqsave(&ioapic_lock
, flags
);
429 __ioapic_write_entry(apic
, pin
, e
);
430 spin_unlock_irqrestore(&ioapic_lock
, flags
);
434 * When we mask an IO APIC routing entry, we need to write the low
435 * word first, in order to set the mask bit before we change the
438 static void ioapic_mask_entry(int apic
, int pin
)
441 union entry_union eu
= { .entry
.mask
= 1 };
443 spin_lock_irqsave(&ioapic_lock
, flags
);
444 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
445 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
446 spin_unlock_irqrestore(&ioapic_lock
, flags
);
450 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
454 struct irq_pin_list
*entry
;
457 entry
= cfg
->irq_2_pin
;
466 io_apic_write(apic
, 0x11 + pin
*2, dest
);
467 reg
= io_apic_read(apic
, 0x10 + pin
*2);
468 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
470 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
477 static int assign_irq_vector(int irq
, cpumask_t mask
);
479 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
488 cpus_and(tmp
, mask
, cpu_online_map
);
492 if (assign_irq_vector(irq
, mask
))
495 cpus_and(tmp
, cfg
->domain
, mask
);
497 dest
= cpu_mask_to_apicid(tmp
);
499 * Only the high 8 bits are valid.
501 dest
= SET_APIC_LOGICAL_ID(dest
);
503 spin_lock_irqsave(&ioapic_lock
, flags
);
504 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
505 irq_to_desc(irq
)->affinity
= mask
;
506 spin_unlock_irqrestore(&ioapic_lock
, flags
);
509 #endif /* CONFIG_SMP */
512 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
513 * shared ISA-space IRQs, so we have to support them. We are super
514 * fast in the common case, and fast for shared ISA-space IRQs.
516 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
519 struct irq_pin_list
*entry
;
521 /* first time to refer irq_cfg, so with new */
522 cfg
= irq_cfg_alloc(irq
);
523 entry
= cfg
->irq_2_pin
;
525 entry
= get_one_free_irq_2_pin();
526 cfg
->irq_2_pin
= entry
;
529 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
533 while (entry
->next
) {
534 /* not again, please */
535 if (entry
->apic
== apic
&& entry
->pin
== pin
)
541 entry
->next
= get_one_free_irq_2_pin();
545 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
549 * Reroute an IRQ to a different pin.
551 static void __init
replace_pin_at_irq(unsigned int irq
,
552 int oldapic
, int oldpin
,
553 int newapic
, int newpin
)
555 struct irq_cfg
*cfg
= irq_cfg(irq
);
556 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
560 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
561 entry
->apic
= newapic
;
564 /* every one is different, right? */
570 /* why? call replace before add? */
572 add_pin_to_irq(irq
, newapic
, newpin
);
575 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
578 struct irq_pin_list
*entry
;
579 unsigned int pin
, reg
;
582 entry
= cfg
->irq_2_pin
;
587 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
590 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
598 static void __mask_IO_APIC_irq(unsigned int irq
)
600 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
604 static void __unmask_IO_APIC_irq(unsigned int irq
)
606 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
609 /* mask = 1, trigger = 0 */
610 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
612 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
613 IO_APIC_REDIR_LEVEL_TRIGGER
);
616 /* mask = 0, trigger = 1 */
617 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
619 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
620 IO_APIC_REDIR_MASKED
);
623 static void mask_IO_APIC_irq(unsigned int irq
)
627 spin_lock_irqsave(&ioapic_lock
, flags
);
628 __mask_IO_APIC_irq(irq
);
629 spin_unlock_irqrestore(&ioapic_lock
, flags
);
632 static void unmask_IO_APIC_irq(unsigned int irq
)
636 spin_lock_irqsave(&ioapic_lock
, flags
);
637 __unmask_IO_APIC_irq(irq
);
638 spin_unlock_irqrestore(&ioapic_lock
, flags
);
641 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
643 struct IO_APIC_route_entry entry
;
645 /* Check delivery_mode to be sure we're not clearing an SMI pin */
646 entry
= ioapic_read_entry(apic
, pin
);
647 if (entry
.delivery_mode
== dest_SMI
)
651 * Disable it in the IO-APIC irq-routing table:
653 ioapic_mask_entry(apic
, pin
);
656 static void clear_IO_APIC(void)
660 for (apic
= 0; apic
< nr_ioapics
; apic
++)
661 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
662 clear_IO_APIC_pin(apic
, pin
);
666 void send_IPI_self(int vector
)
673 apic_wait_icr_idle();
674 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
676 * Send the IPI. The write to APIC_ICR fires this off.
678 apic_write(APIC_ICR
, cfg
);
680 #endif /* !CONFIG_SMP */
684 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
685 * specific CPU-side IRQs.
689 static int pirq_entries
[MAX_PIRQS
];
690 static int pirqs_enabled
;
692 static int __init
ioapic_pirq_setup(char *str
)
695 int ints
[MAX_PIRQS
+1];
697 get_options(str
, ARRAY_SIZE(ints
), ints
);
699 for (i
= 0; i
< MAX_PIRQS
; i
++)
700 pirq_entries
[i
] = -1;
703 apic_printk(APIC_VERBOSE
, KERN_INFO
704 "PIRQ redirection, working around broken MP-BIOS.\n");
706 if (ints
[0] < MAX_PIRQS
)
709 for (i
= 0; i
< max
; i
++) {
710 apic_printk(APIC_VERBOSE
, KERN_DEBUG
711 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
713 * PIRQs are mapped upside down, usually.
715 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
720 __setup("pirq=", ioapic_pirq_setup
);
723 * Find the IRQ entry number of a certain pin.
725 static int find_irq_entry(int apic
, int pin
, int type
)
729 for (i
= 0; i
< mp_irq_entries
; i
++)
730 if (mp_irqs
[i
].mp_irqtype
== type
&&
731 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
732 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
733 mp_irqs
[i
].mp_dstirq
== pin
)
740 * Find the pin to which IRQ[irq] (ISA) is connected
742 static int __init
find_isa_irq_pin(int irq
, int type
)
746 for (i
= 0; i
< mp_irq_entries
; i
++) {
747 int lbus
= mp_irqs
[i
].mp_srcbus
;
749 if (test_bit(lbus
, mp_bus_not_pci
) &&
750 (mp_irqs
[i
].mp_irqtype
== type
) &&
751 (mp_irqs
[i
].mp_srcbusirq
== irq
))
753 return mp_irqs
[i
].mp_dstirq
;
758 static int __init
find_isa_irq_apic(int irq
, int type
)
762 for (i
= 0; i
< mp_irq_entries
; i
++) {
763 int lbus
= mp_irqs
[i
].mp_srcbus
;
765 if (test_bit(lbus
, mp_bus_not_pci
) &&
766 (mp_irqs
[i
].mp_irqtype
== type
) &&
767 (mp_irqs
[i
].mp_srcbusirq
== irq
))
770 if (i
< mp_irq_entries
) {
772 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
773 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
782 * Find a specific PCI IRQ entry.
783 * Not an __init, possibly needed by modules
785 static int pin_2_irq(int idx
, int apic
, int pin
);
787 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
789 int apic
, i
, best_guess
= -1;
791 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
792 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
793 if (test_bit(bus
, mp_bus_not_pci
)) {
794 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
797 for (i
= 0; i
< mp_irq_entries
; i
++) {
798 int lbus
= mp_irqs
[i
].mp_srcbus
;
800 for (apic
= 0; apic
< nr_ioapics
; apic
++)
801 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
802 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
805 if (!test_bit(lbus
, mp_bus_not_pci
) &&
806 !mp_irqs
[i
].mp_irqtype
&&
808 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
809 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
811 if (!(apic
|| IO_APIC_IRQ(irq
)))
814 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
817 * Use the first all-but-pin matching entry as a
818 * best-guess fuzzy result for broken mptables.
826 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
828 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
830 * EISA Edge/Level control register, ELCR
832 static int EISA_ELCR(unsigned int irq
)
835 unsigned int port
= 0x4d0 + (irq
>> 3);
836 return (inb(port
) >> (irq
& 7)) & 1;
838 apic_printk(APIC_VERBOSE
, KERN_INFO
839 "Broken MPtable reports ISA irq %d\n", irq
);
844 /* ISA interrupts are always polarity zero edge triggered,
845 * when listed as conforming in the MP table. */
847 #define default_ISA_trigger(idx) (0)
848 #define default_ISA_polarity(idx) (0)
850 /* EISA interrupts are always polarity zero and can be edge or level
851 * trigger depending on the ELCR value. If an interrupt is listed as
852 * EISA conforming in the MP table, that means its trigger type must
853 * be read in from the ELCR */
855 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
856 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
858 /* PCI interrupts are always polarity one level triggered,
859 * when listed as conforming in the MP table. */
861 #define default_PCI_trigger(idx) (1)
862 #define default_PCI_polarity(idx) (1)
864 /* MCA interrupts are always polarity zero level triggered,
865 * when listed as conforming in the MP table. */
867 #define default_MCA_trigger(idx) (1)
868 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
870 static int MPBIOS_polarity(int idx
)
872 int bus
= mp_irqs
[idx
].mp_srcbus
;
876 * Determine IRQ line polarity (high active or low active):
878 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
879 case 0: /* conforms, ie. bus-type dependent polarity */
881 polarity
= test_bit(bus
, mp_bus_not_pci
)?
882 default_ISA_polarity(idx
):
883 default_PCI_polarity(idx
);
886 case 1: /* high active */
891 case 2: /* reserved */
893 printk(KERN_WARNING
"broken BIOS!!\n");
897 case 3: /* low active */
902 default: /* invalid */
904 printk(KERN_WARNING
"broken BIOS!!\n");
912 static int MPBIOS_trigger(int idx
)
914 int bus
= mp_irqs
[idx
].mp_srcbus
;
918 * Determine IRQ trigger mode (edge or level sensitive):
920 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
921 case 0: /* conforms, ie. bus-type dependent */
923 trigger
= test_bit(bus
, mp_bus_not_pci
)?
924 default_ISA_trigger(idx
):
925 default_PCI_trigger(idx
);
926 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
927 switch (mp_bus_id_to_type
[bus
]) {
928 case MP_BUS_ISA
: /* ISA pin */
930 /* set before the switch */
933 case MP_BUS_EISA
: /* EISA pin */
935 trigger
= default_EISA_trigger(idx
);
938 case MP_BUS_PCI
: /* PCI pin */
940 /* set before the switch */
943 case MP_BUS_MCA
: /* MCA pin */
945 trigger
= default_MCA_trigger(idx
);
950 printk(KERN_WARNING
"broken BIOS!!\n");
963 case 2: /* reserved */
965 printk(KERN_WARNING
"broken BIOS!!\n");
974 default: /* invalid */
976 printk(KERN_WARNING
"broken BIOS!!\n");
984 static inline int irq_polarity(int idx
)
986 return MPBIOS_polarity(idx
);
989 static inline int irq_trigger(int idx
)
991 return MPBIOS_trigger(idx
);
994 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
995 static int pin_2_irq(int idx
, int apic
, int pin
)
998 int bus
= mp_irqs
[idx
].mp_srcbus
;
1001 * Debugging check, we are in big trouble if this message pops up!
1003 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1004 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1006 if (test_bit(bus
, mp_bus_not_pci
))
1007 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1010 * PCI IRQs are mapped in order
1014 irq
+= nr_ioapic_registers
[i
++];
1018 * For MPS mode, so far only needed by ES7000 platform
1020 if (ioapic_renumber_irq
)
1021 irq
= ioapic_renumber_irq(apic
, irq
);
1025 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1027 if ((pin
>= 16) && (pin
<= 23)) {
1028 if (pirq_entries
[pin
-16] != -1) {
1029 if (!pirq_entries
[pin
-16]) {
1030 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1031 "disabling PIRQ%d\n", pin
-16);
1033 irq
= pirq_entries
[pin
-16];
1034 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1035 "using PIRQ%d -> IRQ %d\n",
1043 void lock_vector_lock(void)
1045 /* Used to the online set of cpus does not change
1046 * during assign_irq_vector.
1048 spin_lock(&vector_lock
);
1051 void unlock_vector_lock(void)
1053 spin_unlock(&vector_lock
);
1056 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1058 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1059 unsigned int old_vector
;
1061 struct irq_cfg
*cfg
;
1065 /* Only try and allocate irqs on cpus that are present */
1066 cpus_and(mask
, mask
, cpu_online_map
);
1068 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1071 old_vector
= cfg
->vector
;
1074 cpus_and(tmp
, cfg
->domain
, mask
);
1075 if (!cpus_empty(tmp
))
1079 for_each_cpu_mask_nr(cpu
, mask
) {
1080 cpumask_t domain
, new_mask
;
1084 domain
= vector_allocation_domain(cpu
);
1085 cpus_and(new_mask
, domain
, cpu_online_map
);
1087 vector
= current_vector
;
1088 offset
= current_offset
;
1091 if (vector
>= first_system_vector
) {
1092 /* If we run out of vectors on large boxen, must share them. */
1093 offset
= (offset
+ 1) % 8;
1094 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1096 if (unlikely(current_vector
== vector
))
1098 if (vector
== SYSCALL_VECTOR
)
1101 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1102 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1105 current_vector
= vector
;
1106 current_offset
= offset
;
1108 cfg
->move_in_progress
= 1;
1109 cfg
->old_domain
= cfg
->domain
;
1111 printk(KERN_DEBUG
"assign_irq_vector: irq %d vector %#x cpu ", irq
, vector
);
1112 for_each_cpu_mask_nr(new_cpu
, new_mask
) {
1113 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1114 printk(KERN_CONT
" %d ", new_cpu
);
1116 printk(KERN_CONT
"\n");
1117 cfg
->vector
= vector
;
1118 cfg
->domain
= domain
;
1124 static int assign_irq_vector(int irq
, cpumask_t mask
)
1127 unsigned long flags
;
1129 spin_lock_irqsave(&vector_lock
, flags
);
1130 err
= __assign_irq_vector(irq
, mask
);
1131 spin_unlock_irqrestore(&vector_lock
, flags
);
1136 static void __clear_irq_vector(int irq
)
1138 struct irq_cfg
*cfg
;
1143 BUG_ON(!cfg
->vector
);
1145 vector
= cfg
->vector
;
1146 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1147 for_each_cpu_mask_nr(cpu
, mask
)
1148 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1151 cpus_clear(cfg
->domain
);
1154 void __setup_vector_irq(int cpu
)
1156 /* Initialize vector_irq on a new cpu */
1157 /* This function must be called with vector_lock held */
1159 struct irq_cfg
*cfg
;
1161 /* Mark the inuse vectors */
1162 for_each_irq_cfg(cfg
) {
1163 if (!cpu_isset(cpu
, cfg
->domain
))
1165 vector
= cfg
->vector
;
1167 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1169 /* Mark the free vectors */
1170 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1171 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1176 if (!cpu_isset(cpu
, cfg
->domain
))
1177 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1181 static struct irq_chip ioapic_chip
;
1183 #define IOAPIC_AUTO -1
1184 #define IOAPIC_EDGE 0
1185 #define IOAPIC_LEVEL 1
1187 static inline int IO_APIC_irq_trigger(int irq
)
1191 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1192 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1193 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1194 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1195 return irq_trigger(idx
);
1199 * nonexistent IRQs are edge default
1204 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1206 struct irq_desc
*desc
;
1208 /* first time to use this irq_desc */
1210 desc
= irq_to_desc(irq
);
1212 desc
= irq_to_desc_alloc(irq
);
1214 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1215 trigger
== IOAPIC_LEVEL
) {
1216 desc
->status
|= IRQ_LEVEL
;
1217 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1218 handle_fasteoi_irq
, "fasteoi");
1220 desc
->status
&= ~IRQ_LEVEL
;
1221 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1222 handle_edge_irq
, "edge");
1226 static int setup_ioapic_entry(int apic
, int irq
,
1227 struct IO_APIC_route_entry
*entry
,
1228 unsigned int destination
, int trigger
,
1229 int polarity
, int vector
)
1232 * add it to the IO-APIC irq-routing table:
1234 memset(entry
,0,sizeof(*entry
));
1236 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1237 entry
->dest_mode
= INT_DEST_MODE
;
1238 entry
->dest
= destination
;
1240 entry
->mask
= 0; /* enable IRQ */
1241 entry
->trigger
= trigger
;
1242 entry
->polarity
= polarity
;
1243 entry
->vector
= vector
;
1245 /* Mask level triggered irqs.
1246 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1254 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1255 int trigger
, int polarity
)
1257 struct irq_cfg
*cfg
;
1258 struct IO_APIC_route_entry entry
;
1261 if (!IO_APIC_IRQ(irq
))
1267 if (assign_irq_vector(irq
, mask
))
1270 cpus_and(mask
, cfg
->domain
, mask
);
1272 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1273 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1274 "IRQ %d Mode:%i Active:%i)\n",
1275 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1276 irq
, trigger
, polarity
);
1279 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1280 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1282 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1283 mp_ioapics
[apic
].mp_apicid
, pin
);
1284 __clear_irq_vector(irq
);
1288 ioapic_register_intr(irq
, trigger
);
1290 disable_8259A_irq(irq
);
1292 ioapic_write_entry(apic
, pin
, entry
);
1295 static void __init
setup_IO_APIC_irqs(void)
1297 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1299 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1301 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1302 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1304 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1307 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1310 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1313 if (!first_notcon
) {
1314 apic_printk(APIC_VERBOSE
, " not connected.\n");
1318 irq
= pin_2_irq(idx
, apic
, pin
);
1320 if (multi_timer_check(apic
, irq
))
1323 add_pin_to_irq(irq
, apic
, pin
);
1325 setup_IO_APIC_irq(apic
, pin
, irq
,
1326 irq_trigger(idx
), irq_polarity(idx
));
1331 apic_printk(APIC_VERBOSE
, " not connected.\n");
1335 * Set up the timer pin, possibly with the 8259A-master behind.
1337 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1340 struct IO_APIC_route_entry entry
;
1342 memset(&entry
, 0, sizeof(entry
));
1345 * We use logical delivery to get the timer IRQ
1348 entry
.dest_mode
= INT_DEST_MODE
;
1349 entry
.mask
= 1; /* mask IRQ now */
1350 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1351 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1354 entry
.vector
= vector
;
1357 * The timer IRQ doesn't have to know that behind the
1358 * scene we may have a 8259A-master in AEOI mode ...
1360 ioapic_register_intr(0, IOAPIC_EDGE
);
1363 * Add it to the IO-APIC irq-routing table:
1365 ioapic_write_entry(apic
, pin
, entry
);
1369 __apicdebuginit(void) print_IO_APIC(void)
1372 union IO_APIC_reg_00 reg_00
;
1373 union IO_APIC_reg_01 reg_01
;
1374 union IO_APIC_reg_02 reg_02
;
1375 union IO_APIC_reg_03 reg_03
;
1376 unsigned long flags
;
1377 struct irq_cfg
*cfg
;
1379 if (apic_verbosity
== APIC_QUIET
)
1382 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1383 for (i
= 0; i
< nr_ioapics
; i
++)
1384 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1385 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1388 * We are a bit conservative about what we expect. We have to
1389 * know about every hardware change ASAP.
1391 printk(KERN_INFO
"testing the IO APIC.......................\n");
1393 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1395 spin_lock_irqsave(&ioapic_lock
, flags
);
1396 reg_00
.raw
= io_apic_read(apic
, 0);
1397 reg_01
.raw
= io_apic_read(apic
, 1);
1398 if (reg_01
.bits
.version
>= 0x10)
1399 reg_02
.raw
= io_apic_read(apic
, 2);
1400 if (reg_01
.bits
.version
>= 0x20)
1401 reg_03
.raw
= io_apic_read(apic
, 3);
1402 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1404 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1405 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1406 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1407 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1408 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1410 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1411 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1413 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1414 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1417 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1418 * but the value of reg_02 is read as the previous read register
1419 * value, so ignore it if reg_02 == reg_01.
1421 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1422 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1423 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1427 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1428 * or reg_03, but the value of reg_0[23] is read as the previous read
1429 * register value, so ignore it if reg_03 == reg_0[12].
1431 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1432 reg_03
.raw
!= reg_01
.raw
) {
1433 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1434 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1437 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1439 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1440 " Stat Dmod Deli Vect: \n");
1442 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1443 struct IO_APIC_route_entry entry
;
1445 entry
= ioapic_read_entry(apic
, i
);
1447 printk(KERN_DEBUG
" %02x %02X ", i
, entry
.dest
);
1449 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1454 entry
.delivery_status
,
1456 entry
.delivery_mode
,
1461 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1462 for_each_irq_cfg(cfg
) {
1463 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1466 printk(KERN_DEBUG
"IRQ%d ", i
);
1468 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1471 entry
= entry
->next
;
1476 printk(KERN_INFO
".................................... done.\n");
1481 __apicdebuginit(void) print_APIC_bitfield(int base
)
1486 if (apic_verbosity
== APIC_QUIET
)
1489 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1490 for (i
= 0; i
< 8; i
++) {
1491 v
= apic_read(base
+ i
*0x10);
1492 for (j
= 0; j
< 32; j
++) {
1502 __apicdebuginit(void) print_local_APIC(void *dummy
)
1504 unsigned int v
, ver
, maxlvt
;
1507 if (apic_verbosity
== APIC_QUIET
)
1510 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1511 smp_processor_id(), hard_smp_processor_id());
1512 v
= apic_read(APIC_ID
);
1513 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1515 v
= apic_read(APIC_LVR
);
1516 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1517 ver
= GET_APIC_VERSION(v
);
1518 maxlvt
= lapic_get_maxlvt();
1520 v
= apic_read(APIC_TASKPRI
);
1521 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1523 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1524 v
= apic_read(APIC_ARBPRI
);
1525 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1526 v
& APIC_ARBPRI_MASK
);
1527 v
= apic_read(APIC_PROCPRI
);
1528 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1531 v
= apic_read(APIC_EOI
);
1532 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1533 v
= apic_read(APIC_RRR
);
1534 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1535 v
= apic_read(APIC_LDR
);
1536 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1537 v
= apic_read(APIC_DFR
);
1538 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1539 v
= apic_read(APIC_SPIV
);
1540 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1542 printk(KERN_DEBUG
"... APIC ISR field:\n");
1543 print_APIC_bitfield(APIC_ISR
);
1544 printk(KERN_DEBUG
"... APIC TMR field:\n");
1545 print_APIC_bitfield(APIC_TMR
);
1546 printk(KERN_DEBUG
"... APIC IRR field:\n");
1547 print_APIC_bitfield(APIC_IRR
);
1549 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1550 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1551 apic_write(APIC_ESR
, 0);
1552 v
= apic_read(APIC_ESR
);
1553 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1556 icr
= apic_icr_read();
1557 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1558 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1560 v
= apic_read(APIC_LVTT
);
1561 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1563 if (maxlvt
> 3) { /* PC is LVT#4. */
1564 v
= apic_read(APIC_LVTPC
);
1565 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1567 v
= apic_read(APIC_LVT0
);
1568 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1569 v
= apic_read(APIC_LVT1
);
1570 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1572 if (maxlvt
> 2) { /* ERR is LVT#3. */
1573 v
= apic_read(APIC_LVTERR
);
1574 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1577 v
= apic_read(APIC_TMICT
);
1578 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1579 v
= apic_read(APIC_TMCCT
);
1580 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1581 v
= apic_read(APIC_TDCR
);
1582 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1586 __apicdebuginit(void) print_all_local_APICs(void)
1588 on_each_cpu(print_local_APIC
, NULL
, 1);
1591 __apicdebuginit(void) print_PIC(void)
1594 unsigned long flags
;
1596 if (apic_verbosity
== APIC_QUIET
)
1599 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1601 spin_lock_irqsave(&i8259A_lock
, flags
);
1603 v
= inb(0xa1) << 8 | inb(0x21);
1604 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1606 v
= inb(0xa0) << 8 | inb(0x20);
1607 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1611 v
= inb(0xa0) << 8 | inb(0x20);
1615 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1617 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1619 v
= inb(0x4d1) << 8 | inb(0x4d0);
1620 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1623 __apicdebuginit(int) print_all_ICs(void)
1626 print_all_local_APICs();
1632 fs_initcall(print_all_ICs
);
1635 /* Where if anywhere is the i8259 connect in external int mode */
1636 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1638 static void __init
enable_IO_APIC(void)
1640 union IO_APIC_reg_01 reg_01
;
1641 int i8259_apic
, i8259_pin
;
1643 unsigned long flags
;
1646 for (i
= 0; i
< MAX_PIRQS
; i
++)
1647 pirq_entries
[i
] = -1;
1650 * The number of IO-APIC IRQ registers (== #pins):
1652 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1653 spin_lock_irqsave(&ioapic_lock
, flags
);
1654 reg_01
.raw
= io_apic_read(apic
, 1);
1655 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1656 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1658 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1660 /* See if any of the pins is in ExtINT mode */
1661 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1662 struct IO_APIC_route_entry entry
;
1663 entry
= ioapic_read_entry(apic
, pin
);
1666 /* If the interrupt line is enabled and in ExtInt mode
1667 * I have found the pin where the i8259 is connected.
1669 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1670 ioapic_i8259
.apic
= apic
;
1671 ioapic_i8259
.pin
= pin
;
1677 /* Look to see what if the MP table has reported the ExtINT */
1678 /* If we could not find the appropriate pin by looking at the ioapic
1679 * the i8259 probably is not connected the ioapic but give the
1680 * mptable a chance anyway.
1682 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1683 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1684 /* Trust the MP table if nothing is setup in the hardware */
1685 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1686 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1687 ioapic_i8259
.pin
= i8259_pin
;
1688 ioapic_i8259
.apic
= i8259_apic
;
1690 /* Complain if the MP table and the hardware disagree */
1691 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1692 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1694 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1698 * Do not trust the IO-APIC being empty at bootup
1704 * Not an __init, needed by the reboot code
1706 void disable_IO_APIC(void)
1709 * Clear the IO-APIC before rebooting:
1714 * If the i8259 is routed through an IOAPIC
1715 * Put that IOAPIC in virtual wire mode
1716 * so legacy interrupts can be delivered.
1718 if (ioapic_i8259
.pin
!= -1) {
1719 struct IO_APIC_route_entry entry
;
1721 memset(&entry
, 0, sizeof(entry
));
1722 entry
.mask
= 0; /* Enabled */
1723 entry
.trigger
= 0; /* Edge */
1725 entry
.polarity
= 0; /* High */
1726 entry
.delivery_status
= 0;
1727 entry
.dest_mode
= 0; /* Physical */
1728 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1730 entry
.dest
= read_apic_id();
1733 * Add it to the IO-APIC irq-routing table:
1735 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1737 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1741 * function to set the IO-APIC physical IDs based on the
1742 * values stored in the MPC table.
1744 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1747 static void __init
setup_ioapic_ids_from_mpc(void)
1749 union IO_APIC_reg_00 reg_00
;
1750 physid_mask_t phys_id_present_map
;
1753 unsigned char old_id
;
1754 unsigned long flags
;
1756 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1760 * Don't check I/O APIC IDs for xAPIC systems. They have
1761 * no meaning without the serial APIC bus.
1763 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1764 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1767 * This is broken; anything with a real cpu count has to
1768 * circumvent this idiocy regardless.
1770 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1773 * Set the IOAPIC ID to the value stored in the MPC table.
1775 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1777 /* Read the register 0 value */
1778 spin_lock_irqsave(&ioapic_lock
, flags
);
1779 reg_00
.raw
= io_apic_read(apic
, 0);
1780 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1782 old_id
= mp_ioapics
[apic
].mp_apicid
;
1784 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1785 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1786 apic
, mp_ioapics
[apic
].mp_apicid
);
1787 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1789 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1793 * Sanity check, is the ID really free? Every APIC in a
1794 * system must have a unique ID or we get lots of nice
1795 * 'stuck on smp_invalidate_needed IPI wait' messages.
1797 if (check_apicid_used(phys_id_present_map
,
1798 mp_ioapics
[apic
].mp_apicid
)) {
1799 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1800 apic
, mp_ioapics
[apic
].mp_apicid
);
1801 for (i
= 0; i
< get_physical_broadcast(); i
++)
1802 if (!physid_isset(i
, phys_id_present_map
))
1804 if (i
>= get_physical_broadcast())
1805 panic("Max APIC ID exceeded!\n");
1806 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1808 physid_set(i
, phys_id_present_map
);
1809 mp_ioapics
[apic
].mp_apicid
= i
;
1812 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1813 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1814 "phys_id_present_map\n",
1815 mp_ioapics
[apic
].mp_apicid
);
1816 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1821 * We need to adjust the IRQ routing table
1822 * if the ID changed.
1824 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1825 for (i
= 0; i
< mp_irq_entries
; i
++)
1826 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1827 mp_irqs
[i
].mp_dstapic
1828 = mp_ioapics
[apic
].mp_apicid
;
1831 * Read the right value from the MPC table and
1832 * write it into the ID register.
1834 apic_printk(APIC_VERBOSE
, KERN_INFO
1835 "...changing IO-APIC physical APIC ID to %d ...",
1836 mp_ioapics
[apic
].mp_apicid
);
1838 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1839 spin_lock_irqsave(&ioapic_lock
, flags
);
1840 io_apic_write(apic
, 0, reg_00
.raw
);
1841 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1846 spin_lock_irqsave(&ioapic_lock
, flags
);
1847 reg_00
.raw
= io_apic_read(apic
, 0);
1848 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1849 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1850 printk("could not set ID!\n");
1852 apic_printk(APIC_VERBOSE
, " ok.\n");
1856 int no_timer_check __initdata
;
1858 static int __init
notimercheck(char *s
)
1863 __setup("no_timer_check", notimercheck
);
1866 * There is a nasty bug in some older SMP boards, their mptable lies
1867 * about the timer IRQ. We do the following to work around the situation:
1869 * - timer IRQ defaults to IO-APIC IRQ
1870 * - if this function detects that timer IRQs are defunct, then we fall
1871 * back to ISA timer IRQs
1873 static int __init
timer_irq_works(void)
1875 unsigned long t1
= jiffies
;
1876 unsigned long flags
;
1881 local_save_flags(flags
);
1883 /* Let ten ticks pass... */
1884 mdelay((10 * 1000) / HZ
);
1885 local_irq_restore(flags
);
1888 * Expect a few ticks at least, to be sure some possible
1889 * glue logic does not lock up after one or two first
1890 * ticks in a non-ExtINT mode. Also the local APIC
1891 * might have cached one ExtINT interrupt. Finally, at
1892 * least one tick may be lost due to delays.
1894 if (time_after(jiffies
, t1
+ 4))
1901 * In the SMP+IOAPIC case it might happen that there are an unspecified
1902 * number of pending IRQ events unhandled. These cases are very rare,
1903 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1904 * better to do it this way as thus we do not have to be aware of
1905 * 'pending' interrupts in the IRQ path, except at this point.
1908 * Edge triggered needs to resend any interrupt
1909 * that was delayed but this is now handled in the device
1916 * Starting up a edge-triggered IO-APIC interrupt is
1917 * nasty - we need to make sure that we get the edge.
1918 * If it is already asserted for some reason, we need
1919 * return 1 to indicate that is was pending.
1921 * This is not complete - we should be able to fake
1922 * an edge even if it isn't on the 8259A...
1924 * (We do this for level-triggered IRQs too - it cannot hurt.)
1926 static unsigned int startup_ioapic_irq(unsigned int irq
)
1928 int was_pending
= 0;
1929 unsigned long flags
;
1931 spin_lock_irqsave(&ioapic_lock
, flags
);
1933 disable_8259A_irq(irq
);
1934 if (i8259A_irq_pending(irq
))
1937 __unmask_IO_APIC_irq(irq
);
1938 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1943 static int ioapic_retrigger_irq(unsigned int irq
)
1945 send_IPI_self(irq_cfg(irq
)->vector
);
1951 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1953 unsigned vector
, me
;
1957 me
= smp_processor_id();
1958 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1960 struct irq_desc
*desc
;
1961 struct irq_cfg
*cfg
;
1962 irq
= __get_cpu_var(vector_irq
)[vector
];
1964 desc
= irq_to_desc(irq
);
1969 spin_lock(&desc
->lock
);
1970 if (!cfg
->move_cleanup_count
)
1973 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1976 __get_cpu_var(vector_irq
)[vector
] = -1;
1977 cfg
->move_cleanup_count
--;
1979 spin_unlock(&desc
->lock
);
1985 static void irq_complete_move(unsigned int irq
)
1987 struct irq_cfg
*cfg
= irq_cfg(irq
);
1988 unsigned vector
, me
;
1990 if (likely(!cfg
->move_in_progress
))
1993 vector
= ~get_irq_regs()->orig_ax
;
1994 me
= smp_processor_id();
1995 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1996 cpumask_t cleanup_mask
;
1998 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1999 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2000 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2001 cfg
->move_in_progress
= 0;
2005 static inline void irq_complete_move(unsigned int irq
) {}
2008 static void ack_apic_edge(unsigned int irq
)
2010 irq_complete_move(irq
);
2011 move_native_irq(irq
);
2015 atomic_t irq_mis_count
;
2016 static void ack_apic_level(unsigned int irq
)
2021 irq_complete_move(irq
);
2022 move_native_irq(irq
);
2024 * It appears there is an erratum which affects at least version 0x11
2025 * of I/O APIC (that's the 82093AA and cores integrated into various
2026 * chipsets). Under certain conditions a level-triggered interrupt is
2027 * erroneously delivered as edge-triggered one but the respective IRR
2028 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2029 * message but it will never arrive and further interrupts are blocked
2030 * from the source. The exact reason is so far unknown, but the
2031 * phenomenon was observed when two consecutive interrupt requests
2032 * from a given source get delivered to the same CPU and the source is
2033 * temporarily disabled in between.
2035 * A workaround is to simulate an EOI message manually. We achieve it
2036 * by setting the trigger mode to edge and then to level when the edge
2037 * trigger mode gets detected in the TMR of a local APIC for a
2038 * level-triggered interrupt. We mask the source for the time of the
2039 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2040 * The idea is from Manfred Spraul. --macro
2042 i
= irq_cfg(irq
)->vector
;
2044 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2048 if (!(v
& (1 << (i
& 0x1f)))) {
2049 atomic_inc(&irq_mis_count
);
2050 spin_lock(&ioapic_lock
);
2051 __mask_and_edge_IO_APIC_irq(irq
);
2052 __unmask_and_level_IO_APIC_irq(irq
);
2053 spin_unlock(&ioapic_lock
);
2057 static struct irq_chip ioapic_chip __read_mostly
= {
2059 .startup
= startup_ioapic_irq
,
2060 .mask
= mask_IO_APIC_irq
,
2061 .unmask
= unmask_IO_APIC_irq
,
2062 .ack
= ack_apic_edge
,
2063 .eoi
= ack_apic_level
,
2065 .set_affinity
= set_ioapic_affinity_irq
,
2067 .retrigger
= ioapic_retrigger_irq
,
2071 static inline void init_IO_APIC_traps(void)
2074 struct irq_desc
*desc
;
2075 struct irq_cfg
*cfg
;
2078 * NOTE! The local APIC isn't very good at handling
2079 * multiple interrupts at the same interrupt level.
2080 * As the interrupt level is determined by taking the
2081 * vector number and shifting that right by 4, we
2082 * want to spread these out a bit so that they don't
2083 * all fall in the same interrupt level.
2085 * Also, we've got to be careful not to trash gate
2086 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2088 for_each_irq_cfg(cfg
) {
2090 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2092 * Hmm.. We don't have an entry for this,
2093 * so default to an old-fashioned 8259
2094 * interrupt if we can..
2097 make_8259A_irq(irq
);
2099 desc
= irq_to_desc(irq
);
2100 /* Strange. Oh, well.. */
2101 desc
->chip
= &no_irq_chip
;
2108 * The local APIC irq-chip implementation:
2111 static void mask_lapic_irq(unsigned int irq
)
2115 v
= apic_read(APIC_LVT0
);
2116 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2119 static void unmask_lapic_irq(unsigned int irq
)
2123 v
= apic_read(APIC_LVT0
);
2124 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2127 static void ack_lapic_irq(unsigned int irq
)
2132 static struct irq_chip lapic_chip __read_mostly
= {
2133 .name
= "local-APIC",
2134 .mask
= mask_lapic_irq
,
2135 .unmask
= unmask_lapic_irq
,
2136 .ack
= ack_lapic_irq
,
2139 static void lapic_register_intr(int irq
)
2141 struct irq_desc
*desc
;
2143 desc
= irq_to_desc(irq
);
2144 desc
->status
&= ~IRQ_LEVEL
;
2145 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2149 static void __init
setup_nmi(void)
2152 * Dirty trick to enable the NMI watchdog ...
2153 * We put the 8259A master into AEOI mode and
2154 * unmask on all local APICs LVT0 as NMI.
2156 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2157 * is from Maciej W. Rozycki - so we do not have to EOI from
2158 * the NMI handler or the timer interrupt.
2160 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2162 enable_NMI_through_LVT0();
2164 apic_printk(APIC_VERBOSE
, " done.\n");
2168 * This looks a bit hackish but it's about the only one way of sending
2169 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2170 * not support the ExtINT mode, unfortunately. We need to send these
2171 * cycles as some i82489DX-based boards have glue logic that keeps the
2172 * 8259A interrupt line asserted until INTA. --macro
2174 static inline void __init
unlock_ExtINT_logic(void)
2177 struct IO_APIC_route_entry entry0
, entry1
;
2178 unsigned char save_control
, save_freq_select
;
2180 pin
= find_isa_irq_pin(8, mp_INT
);
2185 apic
= find_isa_irq_apic(8, mp_INT
);
2191 entry0
= ioapic_read_entry(apic
, pin
);
2192 clear_IO_APIC_pin(apic
, pin
);
2194 memset(&entry1
, 0, sizeof(entry1
));
2196 entry1
.dest_mode
= 0; /* physical delivery */
2197 entry1
.mask
= 0; /* unmask IRQ now */
2198 entry1
.dest
= hard_smp_processor_id();
2199 entry1
.delivery_mode
= dest_ExtINT
;
2200 entry1
.polarity
= entry0
.polarity
;
2204 ioapic_write_entry(apic
, pin
, entry1
);
2206 save_control
= CMOS_READ(RTC_CONTROL
);
2207 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2208 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2210 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2215 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2219 CMOS_WRITE(save_control
, RTC_CONTROL
);
2220 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2221 clear_IO_APIC_pin(apic
, pin
);
2223 ioapic_write_entry(apic
, pin
, entry0
);
2226 static int disable_timer_pin_1 __initdata
;
2228 static int __init
parse_disable_timer_pin_1(char *arg
)
2230 disable_timer_pin_1
= 1;
2233 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2235 int timer_through_8259 __initdata
;
2238 * This code may look a bit paranoid, but it's supposed to cooperate with
2239 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2240 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2241 * fanatically on his truly buggy board.
2243 static inline void __init
check_timer(void)
2245 struct irq_cfg
*cfg
= irq_cfg(0);
2246 int apic1
, pin1
, apic2
, pin2
;
2249 unsigned long flags
;
2251 local_irq_save(flags
);
2253 ver
= apic_read(APIC_LVR
);
2254 ver
= GET_APIC_VERSION(ver
);
2257 * get/set the timer IRQ vector:
2259 disable_8259A_irq(0);
2260 assign_irq_vector(0, TARGET_CPUS
);
2263 * As IRQ0 is to be enabled in the 8259A, the virtual
2264 * wire has to be disabled in the local APIC. Also
2265 * timer interrupts need to be acknowledged manually in
2266 * the 8259A for the i82489DX when using the NMI
2267 * watchdog as that APIC treats NMIs as level-triggered.
2268 * The AEOI mode will finish them in the 8259A
2271 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2273 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2275 pin1
= find_isa_irq_pin(0, mp_INT
);
2276 apic1
= find_isa_irq_apic(0, mp_INT
);
2277 pin2
= ioapic_i8259
.pin
;
2278 apic2
= ioapic_i8259
.apic
;
2280 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2281 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2282 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2285 * Some BIOS writers are clueless and report the ExtINTA
2286 * I/O APIC input from the cascaded 8259A as the timer
2287 * interrupt input. So just in case, if only one pin
2288 * was found above, try it both directly and through the
2295 } else if (pin2
== -1) {
2302 * Ok, does IRQ0 through the IOAPIC work?
2305 add_pin_to_irq(0, apic1
, pin1
);
2306 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2308 unmask_IO_APIC_irq(0);
2309 if (timer_irq_works()) {
2310 if (nmi_watchdog
== NMI_IO_APIC
) {
2312 enable_8259A_irq(0);
2314 if (disable_timer_pin_1
> 0)
2315 clear_IO_APIC_pin(0, pin1
);
2318 clear_IO_APIC_pin(apic1
, pin1
);
2320 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2321 "8254 timer not connected to IO-APIC\n");
2323 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2324 "(IRQ0) through the 8259A ...\n");
2325 apic_printk(APIC_QUIET
, KERN_INFO
2326 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2328 * legacy devices should be connected to IO APIC #0
2330 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2331 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2332 unmask_IO_APIC_irq(0);
2333 enable_8259A_irq(0);
2334 if (timer_irq_works()) {
2335 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2336 timer_through_8259
= 1;
2337 if (nmi_watchdog
== NMI_IO_APIC
) {
2338 disable_8259A_irq(0);
2340 enable_8259A_irq(0);
2345 * Cleanup, just in case ...
2347 disable_8259A_irq(0);
2348 clear_IO_APIC_pin(apic2
, pin2
);
2349 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2352 if (nmi_watchdog
== NMI_IO_APIC
) {
2353 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2354 "through the IO-APIC - disabling NMI Watchdog!\n");
2355 nmi_watchdog
= NMI_NONE
;
2359 apic_printk(APIC_QUIET
, KERN_INFO
2360 "...trying to set up timer as Virtual Wire IRQ...\n");
2362 lapic_register_intr(0);
2363 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2364 enable_8259A_irq(0);
2366 if (timer_irq_works()) {
2367 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2370 disable_8259A_irq(0);
2371 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2372 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2374 apic_printk(APIC_QUIET
, KERN_INFO
2375 "...trying to set up timer as ExtINT IRQ...\n");
2379 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2381 unlock_ExtINT_logic();
2383 if (timer_irq_works()) {
2384 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2387 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2388 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2389 "report. Then try booting with the 'noapic' option.\n");
2391 local_irq_restore(flags
);
2395 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2396 * to devices. However there may be an I/O APIC pin available for
2397 * this interrupt regardless. The pin may be left unconnected, but
2398 * typically it will be reused as an ExtINT cascade interrupt for
2399 * the master 8259A. In the MPS case such a pin will normally be
2400 * reported as an ExtINT interrupt in the MP table. With ACPI
2401 * there is no provision for ExtINT interrupts, and in the absence
2402 * of an override it would be treated as an ordinary ISA I/O APIC
2403 * interrupt, that is edge-triggered and unmasked by default. We
2404 * used to do this, but it caused problems on some systems because
2405 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2406 * the same ExtINT cascade interrupt to drive the local APIC of the
2407 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2408 * the I/O APIC in all cases now. No actual device should request
2409 * it anyway. --macro
2411 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2413 void __init
setup_IO_APIC(void)
2417 io_apic_irqs
= ~PIC_IRQS
;
2419 printk("ENABLING IO-APIC IRQs\n");
2422 * Set up IO-APIC IRQ routing.
2425 setup_ioapic_ids_from_mpc();
2427 setup_IO_APIC_irqs();
2428 init_IO_APIC_traps();
2433 * Called after all the initialization is done. If we didnt find any
2434 * APIC bugs then we can allow the modify fast path
2437 static int __init
io_apic_bug_finalize(void)
2439 if (sis_apic_bug
== -1)
2444 late_initcall(io_apic_bug_finalize
);
2446 struct sysfs_ioapic_data
{
2447 struct sys_device dev
;
2448 struct IO_APIC_route_entry entry
[0];
2450 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2452 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2454 struct IO_APIC_route_entry
*entry
;
2455 struct sysfs_ioapic_data
*data
;
2458 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2459 entry
= data
->entry
;
2460 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2461 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2466 static int ioapic_resume(struct sys_device
*dev
)
2468 struct IO_APIC_route_entry
*entry
;
2469 struct sysfs_ioapic_data
*data
;
2470 unsigned long flags
;
2471 union IO_APIC_reg_00 reg_00
;
2474 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2475 entry
= data
->entry
;
2477 spin_lock_irqsave(&ioapic_lock
, flags
);
2478 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2479 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2480 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2481 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2483 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2484 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2485 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2490 static struct sysdev_class ioapic_sysdev_class
= {
2492 .suspend
= ioapic_suspend
,
2493 .resume
= ioapic_resume
,
2496 static int __init
ioapic_init_sysfs(void)
2498 struct sys_device
*dev
;
2499 int i
, size
, error
= 0;
2501 error
= sysdev_class_register(&ioapic_sysdev_class
);
2505 for (i
= 0; i
< nr_ioapics
; i
++) {
2506 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2507 * sizeof(struct IO_APIC_route_entry
);
2508 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2509 if (!mp_ioapic_data
[i
]) {
2510 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2513 dev
= &mp_ioapic_data
[i
]->dev
;
2515 dev
->cls
= &ioapic_sysdev_class
;
2516 error
= sysdev_register(dev
);
2518 kfree(mp_ioapic_data
[i
]);
2519 mp_ioapic_data
[i
] = NULL
;
2520 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2528 device_initcall(ioapic_init_sysfs
);
2531 * Dynamic irq allocate and deallocation
2533 unsigned int create_irq_nr(unsigned int irq_want
)
2535 /* Allocate an unused irq */
2536 unsigned int irq
, new;
2537 unsigned long flags
;
2538 struct irq_cfg
*cfg_new
;
2540 #ifndef CONFIG_HAVE_SPARSE_IRQ
2541 /* only can use bus/dev/fn.. when per_cpu vector is used */
2542 irq_want
= nr_irqs
- 1;
2546 spin_lock_irqsave(&vector_lock
, flags
);
2547 for (new = (nr_irqs
- 1); new > 0; new--) {
2548 if (platform_legacy_irq(new))
2550 cfg_new
= irq_cfg(new);
2551 if (cfg_new
&& cfg_new
->vector
!= 0)
2554 cfg_new
= irq_cfg_alloc(new);
2555 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2559 spin_unlock_irqrestore(&vector_lock
, flags
);
2562 dynamic_irq_init(irq
);
2567 int create_irq(void)
2569 return create_irq_nr(nr_irqs
- 1);
2572 void destroy_irq(unsigned int irq
)
2574 unsigned long flags
;
2576 dynamic_irq_cleanup(irq
);
2578 spin_lock_irqsave(&vector_lock
, flags
);
2579 __clear_irq_vector(irq
);
2580 spin_unlock_irqrestore(&vector_lock
, flags
);
2584 * MSI message composition
2586 #ifdef CONFIG_PCI_MSI
2587 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2589 struct irq_cfg
*cfg
;
2595 err
= assign_irq_vector(irq
, tmp
);
2600 cpus_and(tmp
, cfg
->domain
, tmp
);
2601 dest
= cpu_mask_to_apicid(tmp
);
2603 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2606 ((INT_DEST_MODE
== 0) ?
2607 MSI_ADDR_DEST_MODE_PHYSICAL
:
2608 MSI_ADDR_DEST_MODE_LOGICAL
) |
2609 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2610 MSI_ADDR_REDIRECTION_CPU
:
2611 MSI_ADDR_REDIRECTION_LOWPRI
) |
2612 MSI_ADDR_DEST_ID(dest
);
2615 MSI_DATA_TRIGGER_EDGE
|
2616 MSI_DATA_LEVEL_ASSERT
|
2617 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2618 MSI_DATA_DELIVERY_FIXED
:
2619 MSI_DATA_DELIVERY_LOWPRI
) |
2620 MSI_DATA_VECTOR(cfg
->vector
);
2626 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2628 struct irq_cfg
*cfg
;
2633 cpus_and(tmp
, mask
, cpu_online_map
);
2634 if (cpus_empty(tmp
))
2637 if (assign_irq_vector(irq
, mask
))
2641 cpus_and(tmp
, cfg
->domain
, mask
);
2642 dest
= cpu_mask_to_apicid(tmp
);
2644 read_msi_msg(irq
, &msg
);
2646 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2647 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2648 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2649 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2651 write_msi_msg(irq
, &msg
);
2652 irq_to_desc(irq
)->affinity
= mask
;
2654 #endif /* CONFIG_SMP */
2657 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2658 * which implement the MSI or MSI-X Capability Structure.
2660 static struct irq_chip msi_chip
= {
2662 .unmask
= unmask_msi_irq
,
2663 .mask
= mask_msi_irq
,
2664 .ack
= ack_apic_edge
,
2666 .set_affinity
= set_msi_irq_affinity
,
2668 .retrigger
= ioapic_retrigger_irq
,
2672 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2677 ret
= msi_compose_msg(dev
, irq
, &msg
);
2681 set_irq_msi(irq
, desc
);
2682 write_msi_msg(irq
, &msg
);
2684 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2689 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
2693 irq
= dev
->bus
->number
;
2701 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2705 unsigned int irq_want
;
2707 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
2709 irq
= create_irq_nr(irq_want
);
2714 ret
= setup_msi_irq(dev
, desc
, irq
);
2723 void arch_teardown_msi_irq(unsigned int irq
)
2728 #endif /* CONFIG_PCI_MSI */
2731 * Hypertransport interrupt support
2733 #ifdef CONFIG_HT_IRQ
2737 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2739 struct ht_irq_msg msg
;
2740 fetch_ht_irq_msg(irq
, &msg
);
2742 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2743 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2745 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2746 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2748 write_ht_irq_msg(irq
, &msg
);
2751 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2753 struct irq_cfg
*cfg
;
2757 cpus_and(tmp
, mask
, cpu_online_map
);
2758 if (cpus_empty(tmp
))
2761 if (assign_irq_vector(irq
, mask
))
2765 cpus_and(tmp
, cfg
->domain
, mask
);
2766 dest
= cpu_mask_to_apicid(tmp
);
2768 target_ht_irq(irq
, dest
, cfg
->vector
);
2769 irq_to_desc(irq
)->affinity
= mask
;
2773 static struct irq_chip ht_irq_chip
= {
2775 .mask
= mask_ht_irq
,
2776 .unmask
= unmask_ht_irq
,
2777 .ack
= ack_apic_edge
,
2779 .set_affinity
= set_ht_irq_affinity
,
2781 .retrigger
= ioapic_retrigger_irq
,
2784 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2786 struct irq_cfg
*cfg
;
2791 err
= assign_irq_vector(irq
, tmp
);
2793 struct ht_irq_msg msg
;
2797 cpus_and(tmp
, cfg
->domain
, tmp
);
2798 dest
= cpu_mask_to_apicid(tmp
);
2800 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2804 HT_IRQ_LOW_DEST_ID(dest
) |
2805 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2806 ((INT_DEST_MODE
== 0) ?
2807 HT_IRQ_LOW_DM_PHYSICAL
:
2808 HT_IRQ_LOW_DM_LOGICAL
) |
2809 HT_IRQ_LOW_RQEOI_EDGE
|
2810 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2811 HT_IRQ_LOW_MT_FIXED
:
2812 HT_IRQ_LOW_MT_ARBITRATED
) |
2813 HT_IRQ_LOW_IRQ_MASKED
;
2815 write_ht_irq_msg(irq
, &msg
);
2817 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2818 handle_edge_irq
, "edge");
2822 #endif /* CONFIG_HT_IRQ */
2824 /* --------------------------------------------------------------------------
2825 ACPI-based IOAPIC Configuration
2826 -------------------------------------------------------------------------- */
2830 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2832 union IO_APIC_reg_00 reg_00
;
2833 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2835 unsigned long flags
;
2839 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2840 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2841 * supports up to 16 on one shared APIC bus.
2843 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2844 * advantage of new APIC bus architecture.
2847 if (physids_empty(apic_id_map
))
2848 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2850 spin_lock_irqsave(&ioapic_lock
, flags
);
2851 reg_00
.raw
= io_apic_read(ioapic
, 0);
2852 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2854 if (apic_id
>= get_physical_broadcast()) {
2855 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2856 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2857 apic_id
= reg_00
.bits
.ID
;
2861 * Every APIC in a system must have a unique ID or we get lots of nice
2862 * 'stuck on smp_invalidate_needed IPI wait' messages.
2864 if (check_apicid_used(apic_id_map
, apic_id
)) {
2866 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2867 if (!check_apicid_used(apic_id_map
, i
))
2871 if (i
== get_physical_broadcast())
2872 panic("Max apic_id exceeded!\n");
2874 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2875 "trying %d\n", ioapic
, apic_id
, i
);
2880 tmp
= apicid_to_cpu_present(apic_id
);
2881 physids_or(apic_id_map
, apic_id_map
, tmp
);
2883 if (reg_00
.bits
.ID
!= apic_id
) {
2884 reg_00
.bits
.ID
= apic_id
;
2886 spin_lock_irqsave(&ioapic_lock
, flags
);
2887 io_apic_write(ioapic
, 0, reg_00
.raw
);
2888 reg_00
.raw
= io_apic_read(ioapic
, 0);
2889 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2892 if (reg_00
.bits
.ID
!= apic_id
) {
2893 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2898 apic_printk(APIC_VERBOSE
, KERN_INFO
2899 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2905 int __init
io_apic_get_version(int ioapic
)
2907 union IO_APIC_reg_01 reg_01
;
2908 unsigned long flags
;
2910 spin_lock_irqsave(&ioapic_lock
, flags
);
2911 reg_01
.raw
= io_apic_read(ioapic
, 1);
2912 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2914 return reg_01
.bits
.version
;
2918 int __init
io_apic_get_redir_entries(int ioapic
)
2920 union IO_APIC_reg_01 reg_01
;
2921 unsigned long flags
;
2923 spin_lock_irqsave(&ioapic_lock
, flags
);
2924 reg_01
.raw
= io_apic_read(ioapic
, 1);
2925 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2927 return reg_01
.bits
.entries
;
2931 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2933 if (!IO_APIC_IRQ(irq
)) {
2934 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2940 * IRQs < 16 are already in the irq_2_pin[] map
2943 add_pin_to_irq(irq
, ioapic
, pin
);
2945 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2950 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2954 if (skip_ioapic_setup
)
2957 for (i
= 0; i
< mp_irq_entries
; i
++)
2958 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2959 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2961 if (i
>= mp_irq_entries
)
2964 *trigger
= irq_trigger(i
);
2965 *polarity
= irq_polarity(i
);
2969 #endif /* CONFIG_ACPI */
2972 * This function currently is only a helper for the i386 smp boot process where
2973 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2974 * so mask in all cases should simply be TARGET_CPUS
2977 void __init
setup_ioapic_dest(void)
2979 int pin
, ioapic
, irq
, irq_entry
;
2980 struct irq_cfg
*cfg
;
2981 struct irq_desc
*desc
;
2983 if (skip_ioapic_setup
== 1)
2986 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
2987 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
2988 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
2989 if (irq_entry
== -1)
2991 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
2993 /* setup_IO_APIC_irqs could fail to get vector for some device
2994 * when you have too many devices, because at that time only boot
2999 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3000 irq_trigger(irq_entry
),
3001 irq_polarity(irq_entry
));
3003 desc
= irq_to_desc(irq
);
3004 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3012 void __init
ioapic_init_mappings(void)
3014 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3017 for (i
= 0; i
< nr_ioapics
; i
++) {
3018 if (smp_found_config
) {
3019 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3022 "WARNING: bogus zero IO-APIC "
3023 "address found in MPTABLE, "
3024 "disabling IO/APIC support!\n");
3025 smp_found_config
= 0;
3026 skip_ioapic_setup
= 1;
3027 goto fake_ioapic_page
;
3031 ioapic_phys
= (unsigned long)
3032 alloc_bootmem_pages(PAGE_SIZE
);
3033 ioapic_phys
= __pa(ioapic_phys
);
3035 set_fixmap_nocache(idx
, ioapic_phys
);
3036 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
3037 __fix_to_virt(idx
), ioapic_phys
);