2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
54 #define __apicdebuginit(type) static type __init
56 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
57 atomic_t irq_mis_count
;
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
62 static DEFINE_SPINLOCK(ioapic_lock
);
63 DEFINE_SPINLOCK(vector_lock
);
65 int timer_through_8259 __initdata
;
68 * Is the SiS APIC rmw bug present ?
69 * -1 = don't know, 0 = no, 1 = yes
71 int sis_apic_bug
= -1;
75 * # of IRQ routing registers
77 int nr_ioapic_registers
[MAX_IO_APICS
];
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
86 /* # of MP IRQ source entries */
89 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
90 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
93 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
95 static int disable_timer_pin_1 __initdata
;
101 struct irq_cfg
*next
;
106 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
107 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
108 [0] = { .irq
= 0, .vector
= IRQ0_VECTOR
, },
109 [1] = { .irq
= 1, .vector
= IRQ1_VECTOR
, },
110 [2] = { .irq
= 2, .vector
= IRQ2_VECTOR
, },
111 [3] = { .irq
= 3, .vector
= IRQ3_VECTOR
, },
112 [4] = { .irq
= 4, .vector
= IRQ4_VECTOR
, },
113 [5] = { .irq
= 5, .vector
= IRQ5_VECTOR
, },
114 [6] = { .irq
= 6, .vector
= IRQ6_VECTOR
, },
115 [7] = { .irq
= 7, .vector
= IRQ7_VECTOR
, },
116 [8] = { .irq
= 8, .vector
= IRQ8_VECTOR
, },
117 [9] = { .irq
= 9, .vector
= IRQ9_VECTOR
, },
118 [10] = { .irq
= 10, .vector
= IRQ10_VECTOR
, },
119 [11] = { .irq
= 11, .vector
= IRQ11_VECTOR
, },
120 [12] = { .irq
= 12, .vector
= IRQ12_VECTOR
, },
121 [13] = { .irq
= 13, .vector
= IRQ13_VECTOR
, },
122 [14] = { .irq
= 14, .vector
= IRQ14_VECTOR
, },
123 [15] = { .irq
= 15, .vector
= IRQ15_VECTOR
, },
126 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
127 /* need to be biger than size of irq_cfg_legacy */
128 static int nr_irq_cfg
= 32;
130 static int __init
parse_nr_irq_cfg(char *arg
)
133 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
140 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
142 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
144 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
147 static struct irq_cfg
*irq_cfgx
;
148 static struct irq_cfg
*irq_cfgx_free
;
149 static void __init
init_work(void *data
)
151 struct dyn_array
*da
= data
;
158 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
160 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
161 for (i
= legacy_count
; i
< *da
->nr
; i
++)
162 init_one_irq_cfg(&cfg
[i
]);
164 for (i
= 1; i
< *da
->nr
; i
++)
165 cfg
[i
-1].next
= &cfg
[i
];
167 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
168 irq_cfgx
[legacy_count
- 1].next
= NULL
;
171 #define for_each_irq_cfg(cfg) \
172 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
174 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
176 static struct irq_cfg
*irq_cfg(unsigned int irq
)
191 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
193 struct irq_cfg
*cfg
, *cfg_pri
;
197 cfg_pri
= cfg
= irq_cfgx
;
207 if (!irq_cfgx_free
) {
209 unsigned long total_bytes
;
211 * we run out of pre-allocate ones, allocate more
213 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
215 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
217 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
219 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
222 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
225 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
227 for (i
= 0; i
< nr_irq_cfg
; i
++)
228 init_one_irq_cfg(&cfg
[i
]);
230 for (i
= 1; i
< nr_irq_cfg
; i
++)
231 cfg
[i
-1].next
= &cfg
[i
];
237 irq_cfgx_free
= irq_cfgx_free
->next
;
244 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
246 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
248 /* dump the results */
251 unsigned long bytes
= sizeof(struct irq_cfg
);
253 printk(KERN_DEBUG
"=========================== %d\n", irq
);
254 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
255 for_each_irq_cfg(cfg
) {
257 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
259 printk(KERN_DEBUG
"===========================\n");
266 * Rough estimation of how many shared IRQs there are, can
267 * be changed anytime.
272 * This is performance-critical, we want to do it O(1)
274 * the indexing order of this array favors 1:1 mappings
275 * between pins and IRQs.
278 static struct irq_pin_list
{
282 DEFINE_DYN_ARRAY(irq_2_pin
, sizeof(struct irq_pin_list
), pin_map_size
, 16, NULL
);
286 unsigned int unused
[3];
290 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
292 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
293 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
296 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
298 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
299 writel(reg
, &io_apic
->index
);
300 return readl(&io_apic
->data
);
303 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
305 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
306 writel(reg
, &io_apic
->index
);
307 writel(value
, &io_apic
->data
);
311 * Re-write a value: to be used for read-modify-write
312 * cycles where the read already set up the index register.
314 * Older SiS APIC requires we rewrite the index register
316 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
318 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
320 writel(reg
, &io_apic
->index
);
321 writel(value
, &io_apic
->data
);
325 struct { u32 w1
, w2
; };
326 struct IO_APIC_route_entry entry
;
329 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
331 union entry_union eu
;
333 spin_lock_irqsave(&ioapic_lock
, flags
);
334 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
335 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
336 spin_unlock_irqrestore(&ioapic_lock
, flags
);
341 * When we write a new IO APIC routing entry, we need to write the high
342 * word first! If the mask bit in the low word is clear, we will enable
343 * the interrupt, and we need to make sure the entry is fully populated
344 * before that happens.
347 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
349 union entry_union eu
;
351 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
352 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
355 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
358 spin_lock_irqsave(&ioapic_lock
, flags
);
359 __ioapic_write_entry(apic
, pin
, e
);
360 spin_unlock_irqrestore(&ioapic_lock
, flags
);
364 * When we mask an IO APIC routing entry, we need to write the low
365 * word first, in order to set the mask bit before we change the
368 static void ioapic_mask_entry(int apic
, int pin
)
371 union entry_union eu
= { .entry
.mask
= 1 };
373 spin_lock_irqsave(&ioapic_lock
, flags
);
374 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
375 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
376 spin_unlock_irqrestore(&ioapic_lock
, flags
);
380 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
381 * shared ISA-space IRQs, so we have to support them. We are super
382 * fast in the common case, and fast for shared ISA-space IRQs.
384 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
386 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
390 entry
= irq_2_pin
+ entry
->next
;
392 if (entry
->pin
!= -1) {
393 entry
->next
= first_free_entry
;
394 entry
= irq_2_pin
+ entry
->next
;
395 if (++first_free_entry
>= pin_map_size
)
396 panic("io_apic.c: whoops");
403 * Reroute an IRQ to a different pin.
405 static void __init
replace_pin_at_irq(unsigned int irq
,
406 int oldapic
, int oldpin
,
407 int newapic
, int newpin
)
409 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
412 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
413 entry
->apic
= newapic
;
418 entry
= irq_2_pin
+ entry
->next
;
422 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
424 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
425 unsigned int pin
, reg
;
431 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
434 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
437 entry
= irq_2_pin
+ entry
->next
;
442 static void __mask_IO_APIC_irq(unsigned int irq
)
444 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
448 static void __unmask_IO_APIC_irq(unsigned int irq
)
450 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
453 /* mask = 1, trigger = 0 */
454 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
456 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
457 IO_APIC_REDIR_LEVEL_TRIGGER
);
460 /* mask = 0, trigger = 1 */
461 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
463 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
464 IO_APIC_REDIR_MASKED
);
467 static void mask_IO_APIC_irq(unsigned int irq
)
471 spin_lock_irqsave(&ioapic_lock
, flags
);
472 __mask_IO_APIC_irq(irq
);
473 spin_unlock_irqrestore(&ioapic_lock
, flags
);
476 static void unmask_IO_APIC_irq(unsigned int irq
)
480 spin_lock_irqsave(&ioapic_lock
, flags
);
481 __unmask_IO_APIC_irq(irq
);
482 spin_unlock_irqrestore(&ioapic_lock
, flags
);
485 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
487 struct IO_APIC_route_entry entry
;
489 /* Check delivery_mode to be sure we're not clearing an SMI pin */
490 entry
= ioapic_read_entry(apic
, pin
);
491 if (entry
.delivery_mode
== dest_SMI
)
495 * Disable it in the IO-APIC irq-routing table:
497 ioapic_mask_entry(apic
, pin
);
500 static void clear_IO_APIC(void)
504 for (apic
= 0; apic
< nr_ioapics
; apic
++)
505 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
506 clear_IO_APIC_pin(apic
, pin
);
510 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
514 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
515 unsigned int apicid_value
;
517 struct irq_desc
*desc
;
519 cpus_and(tmp
, cpumask
, cpu_online_map
);
523 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
525 apicid_value
= cpu_mask_to_apicid(cpumask
);
526 /* Prepare to do the io_apic_write */
527 apicid_value
= apicid_value
<< 24;
528 spin_lock_irqsave(&ioapic_lock
, flags
);
533 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
536 entry
= irq_2_pin
+ entry
->next
;
538 desc
= irq_to_desc(irq
);
539 desc
->affinity
= cpumask
;
540 spin_unlock_irqrestore(&ioapic_lock
, flags
);
543 #endif /* CONFIG_SMP */
546 void send_IPI_self(int vector
)
553 apic_wait_icr_idle();
554 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
556 * Send the IPI. The write to APIC_ICR fires this off.
558 apic_write(APIC_ICR
, cfg
);
560 #endif /* !CONFIG_SMP */
564 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
565 * specific CPU-side IRQs.
569 static int pirq_entries
[MAX_PIRQS
];
570 static int pirqs_enabled
;
571 int skip_ioapic_setup
;
573 static int __init
ioapic_pirq_setup(char *str
)
576 int ints
[MAX_PIRQS
+1];
578 get_options(str
, ARRAY_SIZE(ints
), ints
);
580 for (i
= 0; i
< MAX_PIRQS
; i
++)
581 pirq_entries
[i
] = -1;
584 apic_printk(APIC_VERBOSE
, KERN_INFO
585 "PIRQ redirection, working around broken MP-BIOS.\n");
587 if (ints
[0] < MAX_PIRQS
)
590 for (i
= 0; i
< max
; i
++) {
591 apic_printk(APIC_VERBOSE
, KERN_DEBUG
592 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
594 * PIRQs are mapped upside down, usually.
596 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
601 __setup("pirq=", ioapic_pirq_setup
);
604 * Find the IRQ entry number of a certain pin.
606 static int find_irq_entry(int apic
, int pin
, int type
)
610 for (i
= 0; i
< mp_irq_entries
; i
++)
611 if (mp_irqs
[i
].mp_irqtype
== type
&&
612 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
613 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
614 mp_irqs
[i
].mp_dstirq
== pin
)
621 * Find the pin to which IRQ[irq] (ISA) is connected
623 static int __init
find_isa_irq_pin(int irq
, int type
)
627 for (i
= 0; i
< mp_irq_entries
; i
++) {
628 int lbus
= mp_irqs
[i
].mp_srcbus
;
630 if (test_bit(lbus
, mp_bus_not_pci
) &&
631 (mp_irqs
[i
].mp_irqtype
== type
) &&
632 (mp_irqs
[i
].mp_srcbusirq
== irq
))
634 return mp_irqs
[i
].mp_dstirq
;
639 static int __init
find_isa_irq_apic(int irq
, int type
)
643 for (i
= 0; i
< mp_irq_entries
; i
++) {
644 int lbus
= mp_irqs
[i
].mp_srcbus
;
646 if (test_bit(lbus
, mp_bus_not_pci
) &&
647 (mp_irqs
[i
].mp_irqtype
== type
) &&
648 (mp_irqs
[i
].mp_srcbusirq
== irq
))
651 if (i
< mp_irq_entries
) {
653 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
654 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
663 * Find a specific PCI IRQ entry.
664 * Not an __init, possibly needed by modules
666 static int pin_2_irq(int idx
, int apic
, int pin
);
668 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
670 int apic
, i
, best_guess
= -1;
672 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
673 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
674 if (test_bit(bus
, mp_bus_not_pci
)) {
675 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
678 for (i
= 0; i
< mp_irq_entries
; i
++) {
679 int lbus
= mp_irqs
[i
].mp_srcbus
;
681 for (apic
= 0; apic
< nr_ioapics
; apic
++)
682 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
683 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
686 if (!test_bit(lbus
, mp_bus_not_pci
) &&
687 !mp_irqs
[i
].mp_irqtype
&&
689 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
690 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
692 if (!(apic
|| IO_APIC_IRQ(irq
)))
695 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
698 * Use the first all-but-pin matching entry as a
699 * best-guess fuzzy result for broken mptables.
707 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
710 * This function currently is only a helper for the i386 smp boot process where
711 * we need to reprogram the ioredtbls to cater for the cpus which have come online
712 * so mask in all cases should simply be TARGET_CPUS
715 void __init
setup_ioapic_dest(void)
717 int pin
, ioapic
, irq
, irq_entry
;
719 if (skip_ioapic_setup
== 1)
722 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
723 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
724 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
727 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
728 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
735 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
737 * EISA Edge/Level control register, ELCR
739 static int EISA_ELCR(unsigned int irq
)
742 unsigned int port
= 0x4d0 + (irq
>> 3);
743 return (inb(port
) >> (irq
& 7)) & 1;
745 apic_printk(APIC_VERBOSE
, KERN_INFO
746 "Broken MPtable reports ISA irq %d\n", irq
);
751 /* ISA interrupts are always polarity zero edge triggered,
752 * when listed as conforming in the MP table. */
754 #define default_ISA_trigger(idx) (0)
755 #define default_ISA_polarity(idx) (0)
757 /* EISA interrupts are always polarity zero and can be edge or level
758 * trigger depending on the ELCR value. If an interrupt is listed as
759 * EISA conforming in the MP table, that means its trigger type must
760 * be read in from the ELCR */
762 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
763 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
765 /* PCI interrupts are always polarity one level triggered,
766 * when listed as conforming in the MP table. */
768 #define default_PCI_trigger(idx) (1)
769 #define default_PCI_polarity(idx) (1)
771 /* MCA interrupts are always polarity zero level triggered,
772 * when listed as conforming in the MP table. */
774 #define default_MCA_trigger(idx) (1)
775 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
777 static int MPBIOS_polarity(int idx
)
779 int bus
= mp_irqs
[idx
].mp_srcbus
;
783 * Determine IRQ line polarity (high active or low active):
785 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
786 case 0: /* conforms, ie. bus-type dependent polarity */
788 polarity
= test_bit(bus
, mp_bus_not_pci
)?
789 default_ISA_polarity(idx
):
790 default_PCI_polarity(idx
);
793 case 1: /* high active */
798 case 2: /* reserved */
800 printk(KERN_WARNING
"broken BIOS!!\n");
804 case 3: /* low active */
809 default: /* invalid */
811 printk(KERN_WARNING
"broken BIOS!!\n");
819 static int MPBIOS_trigger(int idx
)
821 int bus
= mp_irqs
[idx
].mp_srcbus
;
825 * Determine IRQ trigger mode (edge or level sensitive):
827 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
828 case 0: /* conforms, ie. bus-type dependent */
830 trigger
= test_bit(bus
, mp_bus_not_pci
)?
831 default_ISA_trigger(idx
):
832 default_PCI_trigger(idx
);
833 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
834 switch (mp_bus_id_to_type
[bus
]) {
835 case MP_BUS_ISA
: /* ISA pin */
837 /* set before the switch */
840 case MP_BUS_EISA
: /* EISA pin */
842 trigger
= default_EISA_trigger(idx
);
845 case MP_BUS_PCI
: /* PCI pin */
847 /* set before the switch */
850 case MP_BUS_MCA
: /* MCA pin */
852 trigger
= default_MCA_trigger(idx
);
857 printk(KERN_WARNING
"broken BIOS!!\n");
870 case 2: /* reserved */
872 printk(KERN_WARNING
"broken BIOS!!\n");
881 default: /* invalid */
883 printk(KERN_WARNING
"broken BIOS!!\n");
891 static inline int irq_polarity(int idx
)
893 return MPBIOS_polarity(idx
);
896 static inline int irq_trigger(int idx
)
898 return MPBIOS_trigger(idx
);
901 static int pin_2_irq(int idx
, int apic
, int pin
)
904 int bus
= mp_irqs
[idx
].mp_srcbus
;
907 * Debugging check, we are in big trouble if this message pops up!
909 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
910 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
912 if (test_bit(bus
, mp_bus_not_pci
))
913 irq
= mp_irqs
[idx
].mp_srcbusirq
;
916 * PCI IRQs are mapped in order
920 irq
+= nr_ioapic_registers
[i
++];
924 * For MPS mode, so far only needed by ES7000 platform
926 if (ioapic_renumber_irq
)
927 irq
= ioapic_renumber_irq(apic
, irq
);
931 * PCI IRQ command line redirection. Yes, limits are hardcoded.
933 if ((pin
>= 16) && (pin
<= 23)) {
934 if (pirq_entries
[pin
-16] != -1) {
935 if (!pirq_entries
[pin
-16]) {
936 apic_printk(APIC_VERBOSE
, KERN_DEBUG
937 "disabling PIRQ%d\n", pin
-16);
939 irq
= pirq_entries
[pin
-16];
940 apic_printk(APIC_VERBOSE
, KERN_DEBUG
941 "using PIRQ%d -> IRQ %d\n",
949 static inline int IO_APIC_irq_trigger(int irq
)
953 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
954 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
955 idx
= find_irq_entry(apic
, pin
, mp_INT
);
956 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
957 return irq_trigger(idx
);
961 * nonexistent IRQs are edge default
967 static int __assign_irq_vector(int irq
)
969 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
;
973 BUG_ON((unsigned)irq
>= nr_irqs
);
979 vector
= current_vector
;
980 offset
= current_offset
;
983 if (vector
>= first_system_vector
) {
984 offset
= (offset
+ 1) % 8;
985 vector
= FIRST_DEVICE_VECTOR
+ offset
;
987 if (vector
== current_vector
)
989 if (test_and_set_bit(vector
, used_vectors
))
992 current_vector
= vector
;
993 current_offset
= offset
;
994 cfg
->vector
= vector
;
999 static int assign_irq_vector(int irq
)
1001 unsigned long flags
;
1004 spin_lock_irqsave(&vector_lock
, flags
);
1005 vector
= __assign_irq_vector(irq
);
1006 spin_unlock_irqrestore(&vector_lock
, flags
);
1011 static struct irq_chip ioapic_chip
;
1013 #define IOAPIC_AUTO -1
1014 #define IOAPIC_EDGE 0
1015 #define IOAPIC_LEVEL 1
1017 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1019 struct irq_desc
*desc
;
1021 desc
= irq_to_desc(irq
);
1022 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1023 trigger
== IOAPIC_LEVEL
) {
1024 desc
->status
|= IRQ_LEVEL
;
1025 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1026 handle_fasteoi_irq
, "fasteoi");
1028 desc
->status
&= ~IRQ_LEVEL
;
1029 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1030 handle_edge_irq
, "edge");
1032 set_intr_gate(vector
, interrupt
[irq
]);
1035 static void __init
setup_IO_APIC_irqs(void)
1037 struct IO_APIC_route_entry entry
;
1038 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1040 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1042 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1043 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1046 * add it to the IO-APIC irq-routing table:
1048 memset(&entry
, 0, sizeof(entry
));
1050 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1051 entry
.dest_mode
= INT_DEST_MODE
;
1052 entry
.mask
= 0; /* enable IRQ */
1053 entry
.dest
.logical
.logical_dest
=
1054 cpu_mask_to_apicid(TARGET_CPUS
);
1056 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1059 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1060 " IO-APIC (apicid-pin) %d-%d",
1061 mp_ioapics
[apic
].mp_apicid
,
1065 apic_printk(APIC_VERBOSE
, ", %d-%d",
1066 mp_ioapics
[apic
].mp_apicid
, pin
);
1070 if (!first_notcon
) {
1071 apic_printk(APIC_VERBOSE
, " not connected.\n");
1075 entry
.trigger
= irq_trigger(idx
);
1076 entry
.polarity
= irq_polarity(idx
);
1078 if (irq_trigger(idx
)) {
1083 irq
= pin_2_irq(idx
, apic
, pin
);
1085 * skip adding the timer int on secondary nodes, which causes
1086 * a small but painful rift in the time-space continuum
1088 if (multi_timer_check(apic
, irq
))
1091 add_pin_to_irq(irq
, apic
, pin
);
1093 if (!apic
&& !IO_APIC_IRQ(irq
))
1096 if (IO_APIC_IRQ(irq
)) {
1097 vector
= assign_irq_vector(irq
);
1098 entry
.vector
= vector
;
1099 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1101 if (!apic
&& (irq
< 16))
1102 disable_8259A_irq(irq
);
1104 ioapic_write_entry(apic
, pin
, entry
);
1109 apic_printk(APIC_VERBOSE
, " not connected.\n");
1113 * Set up the timer pin, possibly with the 8259A-master behind.
1115 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1118 struct IO_APIC_route_entry entry
;
1120 memset(&entry
, 0, sizeof(entry
));
1123 * We use logical delivery to get the timer IRQ
1126 entry
.dest_mode
= INT_DEST_MODE
;
1127 entry
.mask
= 1; /* mask IRQ now */
1128 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1129 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1132 entry
.vector
= vector
;
1135 * The timer IRQ doesn't have to know that behind the
1136 * scene we may have a 8259A-master in AEOI mode ...
1138 ioapic_register_intr(0, vector
, IOAPIC_EDGE
);
1141 * Add it to the IO-APIC irq-routing table:
1143 ioapic_write_entry(apic
, pin
, entry
);
1147 __apicdebuginit(void) print_IO_APIC(void)
1150 union IO_APIC_reg_00 reg_00
;
1151 union IO_APIC_reg_01 reg_01
;
1152 union IO_APIC_reg_02 reg_02
;
1153 union IO_APIC_reg_03 reg_03
;
1154 unsigned long flags
;
1156 if (apic_verbosity
== APIC_QUIET
)
1159 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1160 for (i
= 0; i
< nr_ioapics
; i
++)
1161 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1162 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1165 * We are a bit conservative about what we expect. We have to
1166 * know about every hardware change ASAP.
1168 printk(KERN_INFO
"testing the IO APIC.......................\n");
1170 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1172 spin_lock_irqsave(&ioapic_lock
, flags
);
1173 reg_00
.raw
= io_apic_read(apic
, 0);
1174 reg_01
.raw
= io_apic_read(apic
, 1);
1175 if (reg_01
.bits
.version
>= 0x10)
1176 reg_02
.raw
= io_apic_read(apic
, 2);
1177 if (reg_01
.bits
.version
>= 0x20)
1178 reg_03
.raw
= io_apic_read(apic
, 3);
1179 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1181 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1182 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1183 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1184 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1185 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1187 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1188 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1190 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1191 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1194 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1195 * but the value of reg_02 is read as the previous read register
1196 * value, so ignore it if reg_02 == reg_01.
1198 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1199 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1200 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1204 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1205 * or reg_03, but the value of reg_0[23] is read as the previous read
1206 * register value, so ignore it if reg_03 == reg_0[12].
1208 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1209 reg_03
.raw
!= reg_01
.raw
) {
1210 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1211 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1214 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1216 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1217 " Stat Dest Deli Vect: \n");
1219 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1220 struct IO_APIC_route_entry entry
;
1222 entry
= ioapic_read_entry(apic
, i
);
1224 printk(KERN_DEBUG
" %02x %03X %02X ",
1226 entry
.dest
.logical
.logical_dest
,
1227 entry
.dest
.physical
.physical_dest
1230 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1235 entry
.delivery_status
,
1237 entry
.delivery_mode
,
1242 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1243 for (i
= 0; i
< nr_irqs
; i
++) {
1244 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1247 printk(KERN_DEBUG
"IRQ%d ", i
);
1249 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1252 entry
= irq_2_pin
+ entry
->next
;
1257 printk(KERN_INFO
".................................... done.\n");
1262 __apicdebuginit(void) print_APIC_bitfield(int base
)
1267 if (apic_verbosity
== APIC_QUIET
)
1270 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1271 for (i
= 0; i
< 8; i
++) {
1272 v
= apic_read(base
+ i
*0x10);
1273 for (j
= 0; j
< 32; j
++) {
1283 __apicdebuginit(void) print_local_APIC(void *dummy
)
1285 unsigned int v
, ver
, maxlvt
;
1288 if (apic_verbosity
== APIC_QUIET
)
1291 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1292 smp_processor_id(), hard_smp_processor_id());
1293 v
= apic_read(APIC_ID
);
1294 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1296 v
= apic_read(APIC_LVR
);
1297 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1298 ver
= GET_APIC_VERSION(v
);
1299 maxlvt
= lapic_get_maxlvt();
1301 v
= apic_read(APIC_TASKPRI
);
1302 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1304 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1305 v
= apic_read(APIC_ARBPRI
);
1306 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1307 v
& APIC_ARBPRI_MASK
);
1308 v
= apic_read(APIC_PROCPRI
);
1309 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1312 v
= apic_read(APIC_EOI
);
1313 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1314 v
= apic_read(APIC_RRR
);
1315 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1316 v
= apic_read(APIC_LDR
);
1317 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1318 v
= apic_read(APIC_DFR
);
1319 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1320 v
= apic_read(APIC_SPIV
);
1321 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1323 printk(KERN_DEBUG
"... APIC ISR field:\n");
1324 print_APIC_bitfield(APIC_ISR
);
1325 printk(KERN_DEBUG
"... APIC TMR field:\n");
1326 print_APIC_bitfield(APIC_TMR
);
1327 printk(KERN_DEBUG
"... APIC IRR field:\n");
1328 print_APIC_bitfield(APIC_IRR
);
1330 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1331 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1332 apic_write(APIC_ESR
, 0);
1333 v
= apic_read(APIC_ESR
);
1334 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1337 icr
= apic_icr_read();
1338 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1339 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1341 v
= apic_read(APIC_LVTT
);
1342 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1344 if (maxlvt
> 3) { /* PC is LVT#4. */
1345 v
= apic_read(APIC_LVTPC
);
1346 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1348 v
= apic_read(APIC_LVT0
);
1349 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1350 v
= apic_read(APIC_LVT1
);
1351 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1353 if (maxlvt
> 2) { /* ERR is LVT#3. */
1354 v
= apic_read(APIC_LVTERR
);
1355 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1358 v
= apic_read(APIC_TMICT
);
1359 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1360 v
= apic_read(APIC_TMCCT
);
1361 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1362 v
= apic_read(APIC_TDCR
);
1363 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1367 __apicdebuginit(void) print_all_local_APICs(void)
1369 on_each_cpu(print_local_APIC
, NULL
, 1);
1372 __apicdebuginit(void) print_PIC(void)
1375 unsigned long flags
;
1377 if (apic_verbosity
== APIC_QUIET
)
1380 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1382 spin_lock_irqsave(&i8259A_lock
, flags
);
1384 v
= inb(0xa1) << 8 | inb(0x21);
1385 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1387 v
= inb(0xa0) << 8 | inb(0x20);
1388 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1392 v
= inb(0xa0) << 8 | inb(0x20);
1396 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1398 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1400 v
= inb(0x4d1) << 8 | inb(0x4d0);
1401 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1404 __apicdebuginit(int) print_all_ICs(void)
1407 print_all_local_APICs();
1413 fs_initcall(print_all_ICs
);
1416 static void __init
enable_IO_APIC(void)
1418 union IO_APIC_reg_01 reg_01
;
1419 int i8259_apic
, i8259_pin
;
1421 unsigned long flags
;
1423 for (i
= 0; i
< pin_map_size
; i
++) {
1424 irq_2_pin
[i
].pin
= -1;
1425 irq_2_pin
[i
].next
= 0;
1428 for (i
= 0; i
< MAX_PIRQS
; i
++)
1429 pirq_entries
[i
] = -1;
1432 * The number of IO-APIC IRQ registers (== #pins):
1434 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1435 spin_lock_irqsave(&ioapic_lock
, flags
);
1436 reg_01
.raw
= io_apic_read(apic
, 1);
1437 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1438 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1440 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1442 /* See if any of the pins is in ExtINT mode */
1443 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1444 struct IO_APIC_route_entry entry
;
1445 entry
= ioapic_read_entry(apic
, pin
);
1448 /* If the interrupt line is enabled and in ExtInt mode
1449 * I have found the pin where the i8259 is connected.
1451 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1452 ioapic_i8259
.apic
= apic
;
1453 ioapic_i8259
.pin
= pin
;
1459 /* Look to see what if the MP table has reported the ExtINT */
1460 /* If we could not find the appropriate pin by looking at the ioapic
1461 * the i8259 probably is not connected the ioapic but give the
1462 * mptable a chance anyway.
1464 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1465 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1466 /* Trust the MP table if nothing is setup in the hardware */
1467 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1468 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1469 ioapic_i8259
.pin
= i8259_pin
;
1470 ioapic_i8259
.apic
= i8259_apic
;
1472 /* Complain if the MP table and the hardware disagree */
1473 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1474 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1476 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1480 * Do not trust the IO-APIC being empty at bootup
1486 * Not an __init, needed by the reboot code
1488 void disable_IO_APIC(void)
1491 * Clear the IO-APIC before rebooting:
1496 * If the i8259 is routed through an IOAPIC
1497 * Put that IOAPIC in virtual wire mode
1498 * so legacy interrupts can be delivered.
1500 if (ioapic_i8259
.pin
!= -1) {
1501 struct IO_APIC_route_entry entry
;
1503 memset(&entry
, 0, sizeof(entry
));
1504 entry
.mask
= 0; /* Enabled */
1505 entry
.trigger
= 0; /* Edge */
1507 entry
.polarity
= 0; /* High */
1508 entry
.delivery_status
= 0;
1509 entry
.dest_mode
= 0; /* Physical */
1510 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1512 entry
.dest
.physical
.physical_dest
= read_apic_id();
1515 * Add it to the IO-APIC irq-routing table:
1517 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1519 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1523 * function to set the IO-APIC physical IDs based on the
1524 * values stored in the MPC table.
1526 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1529 static void __init
setup_ioapic_ids_from_mpc(void)
1531 union IO_APIC_reg_00 reg_00
;
1532 physid_mask_t phys_id_present_map
;
1535 unsigned char old_id
;
1536 unsigned long flags
;
1538 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1542 * Don't check I/O APIC IDs for xAPIC systems. They have
1543 * no meaning without the serial APIC bus.
1545 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1546 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1549 * This is broken; anything with a real cpu count has to
1550 * circumvent this idiocy regardless.
1552 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1555 * Set the IOAPIC ID to the value stored in the MPC table.
1557 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1559 /* Read the register 0 value */
1560 spin_lock_irqsave(&ioapic_lock
, flags
);
1561 reg_00
.raw
= io_apic_read(apic
, 0);
1562 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1564 old_id
= mp_ioapics
[apic
].mp_apicid
;
1566 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1567 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1568 apic
, mp_ioapics
[apic
].mp_apicid
);
1569 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1571 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1575 * Sanity check, is the ID really free? Every APIC in a
1576 * system must have a unique ID or we get lots of nice
1577 * 'stuck on smp_invalidate_needed IPI wait' messages.
1579 if (check_apicid_used(phys_id_present_map
,
1580 mp_ioapics
[apic
].mp_apicid
)) {
1581 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1582 apic
, mp_ioapics
[apic
].mp_apicid
);
1583 for (i
= 0; i
< get_physical_broadcast(); i
++)
1584 if (!physid_isset(i
, phys_id_present_map
))
1586 if (i
>= get_physical_broadcast())
1587 panic("Max APIC ID exceeded!\n");
1588 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1590 physid_set(i
, phys_id_present_map
);
1591 mp_ioapics
[apic
].mp_apicid
= i
;
1594 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1595 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1596 "phys_id_present_map\n",
1597 mp_ioapics
[apic
].mp_apicid
);
1598 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1603 * We need to adjust the IRQ routing table
1604 * if the ID changed.
1606 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1607 for (i
= 0; i
< mp_irq_entries
; i
++)
1608 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1609 mp_irqs
[i
].mp_dstapic
1610 = mp_ioapics
[apic
].mp_apicid
;
1613 * Read the right value from the MPC table and
1614 * write it into the ID register.
1616 apic_printk(APIC_VERBOSE
, KERN_INFO
1617 "...changing IO-APIC physical APIC ID to %d ...",
1618 mp_ioapics
[apic
].mp_apicid
);
1620 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1621 spin_lock_irqsave(&ioapic_lock
, flags
);
1622 io_apic_write(apic
, 0, reg_00
.raw
);
1623 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1628 spin_lock_irqsave(&ioapic_lock
, flags
);
1629 reg_00
.raw
= io_apic_read(apic
, 0);
1630 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1631 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1632 printk("could not set ID!\n");
1634 apic_printk(APIC_VERBOSE
, " ok.\n");
1638 int no_timer_check __initdata
;
1640 static int __init
notimercheck(char *s
)
1645 __setup("no_timer_check", notimercheck
);
1648 * There is a nasty bug in some older SMP boards, their mptable lies
1649 * about the timer IRQ. We do the following to work around the situation:
1651 * - timer IRQ defaults to IO-APIC IRQ
1652 * - if this function detects that timer IRQs are defunct, then we fall
1653 * back to ISA timer IRQs
1655 static int __init
timer_irq_works(void)
1657 unsigned long t1
= jiffies
;
1658 unsigned long flags
;
1663 local_save_flags(flags
);
1665 /* Let ten ticks pass... */
1666 mdelay((10 * 1000) / HZ
);
1667 local_irq_restore(flags
);
1670 * Expect a few ticks at least, to be sure some possible
1671 * glue logic does not lock up after one or two first
1672 * ticks in a non-ExtINT mode. Also the local APIC
1673 * might have cached one ExtINT interrupt. Finally, at
1674 * least one tick may be lost due to delays.
1676 if (time_after(jiffies
, t1
+ 4))
1683 * In the SMP+IOAPIC case it might happen that there are an unspecified
1684 * number of pending IRQ events unhandled. These cases are very rare,
1685 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1686 * better to do it this way as thus we do not have to be aware of
1687 * 'pending' interrupts in the IRQ path, except at this point.
1690 * Edge triggered needs to resend any interrupt
1691 * that was delayed but this is now handled in the device
1698 * Starting up a edge-triggered IO-APIC interrupt is
1699 * nasty - we need to make sure that we get the edge.
1700 * If it is already asserted for some reason, we need
1701 * return 1 to indicate that is was pending.
1703 * This is not complete - we should be able to fake
1704 * an edge even if it isn't on the 8259A...
1706 * (We do this for level-triggered IRQs too - it cannot hurt.)
1708 static unsigned int startup_ioapic_irq(unsigned int irq
)
1710 int was_pending
= 0;
1711 unsigned long flags
;
1713 spin_lock_irqsave(&ioapic_lock
, flags
);
1715 disable_8259A_irq(irq
);
1716 if (i8259A_irq_pending(irq
))
1719 __unmask_IO_APIC_irq(irq
);
1720 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1725 static void ack_ioapic_irq(unsigned int irq
)
1727 move_native_irq(irq
);
1731 static void ack_ioapic_quirk_irq(unsigned int irq
)
1736 move_native_irq(irq
);
1738 * It appears there is an erratum which affects at least version 0x11
1739 * of I/O APIC (that's the 82093AA and cores integrated into various
1740 * chipsets). Under certain conditions a level-triggered interrupt is
1741 * erroneously delivered as edge-triggered one but the respective IRR
1742 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1743 * message but it will never arrive and further interrupts are blocked
1744 * from the source. The exact reason is so far unknown, but the
1745 * phenomenon was observed when two consecutive interrupt requests
1746 * from a given source get delivered to the same CPU and the source is
1747 * temporarily disabled in between.
1749 * A workaround is to simulate an EOI message manually. We achieve it
1750 * by setting the trigger mode to edge and then to level when the edge
1751 * trigger mode gets detected in the TMR of a local APIC for a
1752 * level-triggered interrupt. We mask the source for the time of the
1753 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1754 * The idea is from Manfred Spraul. --macro
1756 i
= irq_cfg(irq
)->vector
;
1758 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1762 if (!(v
& (1 << (i
& 0x1f)))) {
1763 atomic_inc(&irq_mis_count
);
1764 spin_lock(&ioapic_lock
);
1765 __mask_and_edge_IO_APIC_irq(irq
);
1766 __unmask_and_level_IO_APIC_irq(irq
);
1767 spin_unlock(&ioapic_lock
);
1771 static int ioapic_retrigger_irq(unsigned int irq
)
1773 send_IPI_self(irq_cfg(irq
)->vector
);
1778 static struct irq_chip ioapic_chip __read_mostly
= {
1780 .startup
= startup_ioapic_irq
,
1781 .mask
= mask_IO_APIC_irq
,
1782 .unmask
= unmask_IO_APIC_irq
,
1783 .ack
= ack_ioapic_irq
,
1784 .eoi
= ack_ioapic_quirk_irq
,
1786 .set_affinity
= set_ioapic_affinity_irq
,
1788 .retrigger
= ioapic_retrigger_irq
,
1792 static inline void init_IO_APIC_traps(void)
1795 struct irq_desc
*desc
;
1796 struct irq_cfg
*cfg
;
1799 * NOTE! The local APIC isn't very good at handling
1800 * multiple interrupts at the same interrupt level.
1801 * As the interrupt level is determined by taking the
1802 * vector number and shifting that right by 4, we
1803 * want to spread these out a bit so that they don't
1804 * all fall in the same interrupt level.
1806 * Also, we've got to be careful not to trash gate
1807 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1809 for_each_irq_cfg(cfg
) {
1811 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
1813 * Hmm.. We don't have an entry for this,
1814 * so default to an old-fashioned 8259
1815 * interrupt if we can..
1818 make_8259A_irq(irq
);
1820 desc
= irq_to_desc(irq
);
1821 /* Strange. Oh, well.. */
1822 desc
->chip
= &no_irq_chip
;
1829 * The local APIC irq-chip implementation:
1832 static void ack_lapic_irq(unsigned int irq
)
1837 static void mask_lapic_irq(unsigned int irq
)
1841 v
= apic_read(APIC_LVT0
);
1842 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1845 static void unmask_lapic_irq(unsigned int irq
)
1849 v
= apic_read(APIC_LVT0
);
1850 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1853 static struct irq_chip lapic_chip __read_mostly
= {
1854 .name
= "local-APIC",
1855 .mask
= mask_lapic_irq
,
1856 .unmask
= unmask_lapic_irq
,
1857 .ack
= ack_lapic_irq
,
1860 static void lapic_register_intr(int irq
, int vector
)
1862 struct irq_desc
*desc
;
1864 desc
= irq_to_desc(irq
);
1865 desc
->status
&= ~IRQ_LEVEL
;
1866 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
1868 set_intr_gate(vector
, interrupt
[irq
]);
1871 static void __init
setup_nmi(void)
1874 * Dirty trick to enable the NMI watchdog ...
1875 * We put the 8259A master into AEOI mode and
1876 * unmask on all local APICs LVT0 as NMI.
1878 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1879 * is from Maciej W. Rozycki - so we do not have to EOI from
1880 * the NMI handler or the timer interrupt.
1882 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
1884 enable_NMI_through_LVT0();
1886 apic_printk(APIC_VERBOSE
, " done.\n");
1890 * This looks a bit hackish but it's about the only one way of sending
1891 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1892 * not support the ExtINT mode, unfortunately. We need to send these
1893 * cycles as some i82489DX-based boards have glue logic that keeps the
1894 * 8259A interrupt line asserted until INTA. --macro
1896 static inline void __init
unlock_ExtINT_logic(void)
1899 struct IO_APIC_route_entry entry0
, entry1
;
1900 unsigned char save_control
, save_freq_select
;
1902 pin
= find_isa_irq_pin(8, mp_INT
);
1907 apic
= find_isa_irq_apic(8, mp_INT
);
1913 entry0
= ioapic_read_entry(apic
, pin
);
1914 clear_IO_APIC_pin(apic
, pin
);
1916 memset(&entry1
, 0, sizeof(entry1
));
1918 entry1
.dest_mode
= 0; /* physical delivery */
1919 entry1
.mask
= 0; /* unmask IRQ now */
1920 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
1921 entry1
.delivery_mode
= dest_ExtINT
;
1922 entry1
.polarity
= entry0
.polarity
;
1926 ioapic_write_entry(apic
, pin
, entry1
);
1928 save_control
= CMOS_READ(RTC_CONTROL
);
1929 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1930 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1932 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1937 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1941 CMOS_WRITE(save_control
, RTC_CONTROL
);
1942 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1943 clear_IO_APIC_pin(apic
, pin
);
1945 ioapic_write_entry(apic
, pin
, entry0
);
1949 * This code may look a bit paranoid, but it's supposed to cooperate with
1950 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1951 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1952 * fanatically on his truly buggy board.
1954 static inline void __init
check_timer(void)
1956 int apic1
, pin1
, apic2
, pin2
;
1960 unsigned long flags
;
1962 local_irq_save(flags
);
1964 ver
= apic_read(APIC_LVR
);
1965 ver
= GET_APIC_VERSION(ver
);
1968 * get/set the timer IRQ vector:
1970 disable_8259A_irq(0);
1971 vector
= assign_irq_vector(0);
1972 set_intr_gate(vector
, interrupt
[0]);
1975 * As IRQ0 is to be enabled in the 8259A, the virtual
1976 * wire has to be disabled in the local APIC. Also
1977 * timer interrupts need to be acknowledged manually in
1978 * the 8259A for the i82489DX when using the NMI
1979 * watchdog as that APIC treats NMIs as level-triggered.
1980 * The AEOI mode will finish them in the 8259A
1983 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1985 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
1987 pin1
= find_isa_irq_pin(0, mp_INT
);
1988 apic1
= find_isa_irq_apic(0, mp_INT
);
1989 pin2
= ioapic_i8259
.pin
;
1990 apic2
= ioapic_i8259
.apic
;
1992 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
1993 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
1994 vector
, apic1
, pin1
, apic2
, pin2
);
1997 * Some BIOS writers are clueless and report the ExtINTA
1998 * I/O APIC input from the cascaded 8259A as the timer
1999 * interrupt input. So just in case, if only one pin
2000 * was found above, try it both directly and through the
2007 } else if (pin2
== -1) {
2014 * Ok, does IRQ0 through the IOAPIC work?
2017 add_pin_to_irq(0, apic1
, pin1
);
2018 setup_timer_IRQ0_pin(apic1
, pin1
, vector
);
2020 unmask_IO_APIC_irq(0);
2021 if (timer_irq_works()) {
2022 if (nmi_watchdog
== NMI_IO_APIC
) {
2024 enable_8259A_irq(0);
2026 if (disable_timer_pin_1
> 0)
2027 clear_IO_APIC_pin(0, pin1
);
2030 clear_IO_APIC_pin(apic1
, pin1
);
2032 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2033 "8254 timer not connected to IO-APIC\n");
2035 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2036 "(IRQ0) through the 8259A ...\n");
2037 apic_printk(APIC_QUIET
, KERN_INFO
2038 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2040 * legacy devices should be connected to IO APIC #0
2042 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2043 setup_timer_IRQ0_pin(apic2
, pin2
, vector
);
2044 unmask_IO_APIC_irq(0);
2045 enable_8259A_irq(0);
2046 if (timer_irq_works()) {
2047 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2048 timer_through_8259
= 1;
2049 if (nmi_watchdog
== NMI_IO_APIC
) {
2050 disable_8259A_irq(0);
2052 enable_8259A_irq(0);
2057 * Cleanup, just in case ...
2059 disable_8259A_irq(0);
2060 clear_IO_APIC_pin(apic2
, pin2
);
2061 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2064 if (nmi_watchdog
== NMI_IO_APIC
) {
2065 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2066 "through the IO-APIC - disabling NMI Watchdog!\n");
2067 nmi_watchdog
= NMI_NONE
;
2071 apic_printk(APIC_QUIET
, KERN_INFO
2072 "...trying to set up timer as Virtual Wire IRQ...\n");
2074 lapic_register_intr(0, vector
);
2075 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2076 enable_8259A_irq(0);
2078 if (timer_irq_works()) {
2079 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2082 disable_8259A_irq(0);
2083 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2084 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2086 apic_printk(APIC_QUIET
, KERN_INFO
2087 "...trying to set up timer as ExtINT IRQ...\n");
2091 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2093 unlock_ExtINT_logic();
2095 if (timer_irq_works()) {
2096 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2099 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2100 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2101 "report. Then try booting with the 'noapic' option.\n");
2103 local_irq_restore(flags
);
2107 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2108 * to devices. However there may be an I/O APIC pin available for
2109 * this interrupt regardless. The pin may be left unconnected, but
2110 * typically it will be reused as an ExtINT cascade interrupt for
2111 * the master 8259A. In the MPS case such a pin will normally be
2112 * reported as an ExtINT interrupt in the MP table. With ACPI
2113 * there is no provision for ExtINT interrupts, and in the absence
2114 * of an override it would be treated as an ordinary ISA I/O APIC
2115 * interrupt, that is edge-triggered and unmasked by default. We
2116 * used to do this, but it caused problems on some systems because
2117 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2118 * the same ExtINT cascade interrupt to drive the local APIC of the
2119 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2120 * the I/O APIC in all cases now. No actual device should request
2121 * it anyway. --macro
2123 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2125 void __init
setup_IO_APIC(void)
2129 /* Reserve all the system vectors. */
2130 for (i
= first_system_vector
; i
< NR_VECTORS
; i
++)
2131 set_bit(i
, used_vectors
);
2135 io_apic_irqs
= ~PIC_IRQS
;
2137 printk("ENABLING IO-APIC IRQs\n");
2140 * Set up IO-APIC IRQ routing.
2143 setup_ioapic_ids_from_mpc();
2145 setup_IO_APIC_irqs();
2146 init_IO_APIC_traps();
2151 * Called after all the initialization is done. If we didnt find any
2152 * APIC bugs then we can allow the modify fast path
2155 static int __init
io_apic_bug_finalize(void)
2157 if (sis_apic_bug
== -1)
2162 late_initcall(io_apic_bug_finalize
);
2164 struct sysfs_ioapic_data
{
2165 struct sys_device dev
;
2166 struct IO_APIC_route_entry entry
[0];
2168 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2170 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2172 struct IO_APIC_route_entry
*entry
;
2173 struct sysfs_ioapic_data
*data
;
2176 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2177 entry
= data
->entry
;
2178 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2179 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2184 static int ioapic_resume(struct sys_device
*dev
)
2186 struct IO_APIC_route_entry
*entry
;
2187 struct sysfs_ioapic_data
*data
;
2188 unsigned long flags
;
2189 union IO_APIC_reg_00 reg_00
;
2192 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2193 entry
= data
->entry
;
2195 spin_lock_irqsave(&ioapic_lock
, flags
);
2196 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2197 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2198 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2199 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2201 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2202 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2203 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2208 static struct sysdev_class ioapic_sysdev_class
= {
2210 .suspend
= ioapic_suspend
,
2211 .resume
= ioapic_resume
,
2214 static int __init
ioapic_init_sysfs(void)
2216 struct sys_device
*dev
;
2217 int i
, size
, error
= 0;
2219 error
= sysdev_class_register(&ioapic_sysdev_class
);
2223 for (i
= 0; i
< nr_ioapics
; i
++) {
2224 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2225 * sizeof(struct IO_APIC_route_entry
);
2226 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2227 if (!mp_ioapic_data
[i
]) {
2228 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2231 dev
= &mp_ioapic_data
[i
]->dev
;
2233 dev
->cls
= &ioapic_sysdev_class
;
2234 error
= sysdev_register(dev
);
2236 kfree(mp_ioapic_data
[i
]);
2237 mp_ioapic_data
[i
] = NULL
;
2238 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2246 device_initcall(ioapic_init_sysfs
);
2249 * Dynamic irq allocate and deallocation
2251 int create_irq(void)
2253 /* Allocate an unused irq */
2254 int irq
, new, vector
= 0;
2255 unsigned long flags
;
2256 struct irq_cfg
*cfg_new
;
2259 spin_lock_irqsave(&vector_lock
, flags
);
2260 for (new = (nr_irqs
- 1); new >= 0; new--) {
2261 if (platform_legacy_irq(new))
2263 cfg_new
= irq_cfg(new);
2264 if (cfg_new
&& cfg_new
->vector
!= 0)
2267 cfg_new
= irq_cfg_alloc(new);
2268 vector
= __assign_irq_vector(new);
2269 if (likely(vector
> 0))
2273 spin_unlock_irqrestore(&vector_lock
, flags
);
2276 set_intr_gate(vector
, interrupt
[irq
]);
2277 dynamic_irq_init(irq
);
2282 void destroy_irq(unsigned int irq
)
2284 unsigned long flags
;
2286 dynamic_irq_cleanup(irq
);
2288 spin_lock_irqsave(&vector_lock
, flags
);
2289 clear_bit(irq_cfg(irq
)->vector
, used_vectors
);
2290 irq_cfg(irq
)->vector
= 0;
2291 spin_unlock_irqrestore(&vector_lock
, flags
);
2295 * MSI message composition
2297 #ifdef CONFIG_PCI_MSI
2298 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2303 vector
= assign_irq_vector(irq
);
2305 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2307 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2310 ((INT_DEST_MODE
== 0) ?
2311 MSI_ADDR_DEST_MODE_PHYSICAL
:
2312 MSI_ADDR_DEST_MODE_LOGICAL
) |
2313 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2314 MSI_ADDR_REDIRECTION_CPU
:
2315 MSI_ADDR_REDIRECTION_LOWPRI
) |
2316 MSI_ADDR_DEST_ID(dest
);
2319 MSI_DATA_TRIGGER_EDGE
|
2320 MSI_DATA_LEVEL_ASSERT
|
2321 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2322 MSI_DATA_DELIVERY_FIXED
:
2323 MSI_DATA_DELIVERY_LOWPRI
) |
2324 MSI_DATA_VECTOR(vector
);
2330 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2336 struct irq_desc
*desc
;
2338 cpus_and(tmp
, mask
, cpu_online_map
);
2339 if (cpus_empty(tmp
))
2342 vector
= assign_irq_vector(irq
);
2346 dest
= cpu_mask_to_apicid(mask
);
2348 read_msi_msg(irq
, &msg
);
2350 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2351 msg
.data
|= MSI_DATA_VECTOR(vector
);
2352 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2353 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2355 write_msi_msg(irq
, &msg
);
2356 desc
= irq_to_desc(irq
);
2357 desc
->affinity
= mask
;
2359 #endif /* CONFIG_SMP */
2362 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2363 * which implement the MSI or MSI-X Capability Structure.
2365 static struct irq_chip msi_chip
= {
2367 .unmask
= unmask_msi_irq
,
2368 .mask
= mask_msi_irq
,
2369 .ack
= ack_ioapic_irq
,
2371 .set_affinity
= set_msi_irq_affinity
,
2373 .retrigger
= ioapic_retrigger_irq
,
2376 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2384 ret
= msi_compose_msg(dev
, irq
, &msg
);
2390 set_irq_msi(irq
, desc
);
2391 write_msi_msg(irq
, &msg
);
2393 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2399 void arch_teardown_msi_irq(unsigned int irq
)
2404 #endif /* CONFIG_PCI_MSI */
2407 * Hypertransport interrupt support
2409 #ifdef CONFIG_HT_IRQ
2413 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2415 struct ht_irq_msg msg
;
2416 fetch_ht_irq_msg(irq
, &msg
);
2418 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2419 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2421 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2422 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2424 write_ht_irq_msg(irq
, &msg
);
2427 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2431 struct irq_desc
*desc
;
2433 cpus_and(tmp
, mask
, cpu_online_map
);
2434 if (cpus_empty(tmp
))
2437 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2439 dest
= cpu_mask_to_apicid(mask
);
2441 target_ht_irq(irq
, dest
);
2442 desc
= irq_to_desc(irq
);
2443 desc
->affinity
= mask
;
2447 static struct irq_chip ht_irq_chip
= {
2449 .mask
= mask_ht_irq
,
2450 .unmask
= unmask_ht_irq
,
2451 .ack
= ack_ioapic_irq
,
2453 .set_affinity
= set_ht_irq_affinity
,
2455 .retrigger
= ioapic_retrigger_irq
,
2458 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2462 vector
= assign_irq_vector(irq
);
2464 struct ht_irq_msg msg
;
2469 cpu_set(vector
>> 8, tmp
);
2470 dest
= cpu_mask_to_apicid(tmp
);
2472 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2476 HT_IRQ_LOW_DEST_ID(dest
) |
2477 HT_IRQ_LOW_VECTOR(vector
) |
2478 ((INT_DEST_MODE
== 0) ?
2479 HT_IRQ_LOW_DM_PHYSICAL
:
2480 HT_IRQ_LOW_DM_LOGICAL
) |
2481 HT_IRQ_LOW_RQEOI_EDGE
|
2482 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2483 HT_IRQ_LOW_MT_FIXED
:
2484 HT_IRQ_LOW_MT_ARBITRATED
) |
2485 HT_IRQ_LOW_IRQ_MASKED
;
2487 write_ht_irq_msg(irq
, &msg
);
2489 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2490 handle_edge_irq
, "edge");
2494 #endif /* CONFIG_HT_IRQ */
2496 /* --------------------------------------------------------------------------
2497 ACPI-based IOAPIC Configuration
2498 -------------------------------------------------------------------------- */
2502 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2504 union IO_APIC_reg_00 reg_00
;
2505 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2507 unsigned long flags
;
2511 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2512 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2513 * supports up to 16 on one shared APIC bus.
2515 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2516 * advantage of new APIC bus architecture.
2519 if (physids_empty(apic_id_map
))
2520 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2522 spin_lock_irqsave(&ioapic_lock
, flags
);
2523 reg_00
.raw
= io_apic_read(ioapic
, 0);
2524 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2526 if (apic_id
>= get_physical_broadcast()) {
2527 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2528 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2529 apic_id
= reg_00
.bits
.ID
;
2533 * Every APIC in a system must have a unique ID or we get lots of nice
2534 * 'stuck on smp_invalidate_needed IPI wait' messages.
2536 if (check_apicid_used(apic_id_map
, apic_id
)) {
2538 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2539 if (!check_apicid_used(apic_id_map
, i
))
2543 if (i
== get_physical_broadcast())
2544 panic("Max apic_id exceeded!\n");
2546 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2547 "trying %d\n", ioapic
, apic_id
, i
);
2552 tmp
= apicid_to_cpu_present(apic_id
);
2553 physids_or(apic_id_map
, apic_id_map
, tmp
);
2555 if (reg_00
.bits
.ID
!= apic_id
) {
2556 reg_00
.bits
.ID
= apic_id
;
2558 spin_lock_irqsave(&ioapic_lock
, flags
);
2559 io_apic_write(ioapic
, 0, reg_00
.raw
);
2560 reg_00
.raw
= io_apic_read(ioapic
, 0);
2561 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2564 if (reg_00
.bits
.ID
!= apic_id
) {
2565 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2570 apic_printk(APIC_VERBOSE
, KERN_INFO
2571 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2577 int __init
io_apic_get_version(int ioapic
)
2579 union IO_APIC_reg_01 reg_01
;
2580 unsigned long flags
;
2582 spin_lock_irqsave(&ioapic_lock
, flags
);
2583 reg_01
.raw
= io_apic_read(ioapic
, 1);
2584 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2586 return reg_01
.bits
.version
;
2590 int __init
io_apic_get_redir_entries(int ioapic
)
2592 union IO_APIC_reg_01 reg_01
;
2593 unsigned long flags
;
2595 spin_lock_irqsave(&ioapic_lock
, flags
);
2596 reg_01
.raw
= io_apic_read(ioapic
, 1);
2597 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2599 return reg_01
.bits
.entries
;
2603 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2605 struct IO_APIC_route_entry entry
;
2607 if (!IO_APIC_IRQ(irq
)) {
2608 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2614 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2615 * Note that we mask (disable) IRQs now -- these get enabled when the
2616 * corresponding device driver registers for this IRQ.
2619 memset(&entry
, 0, sizeof(entry
));
2621 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2622 entry
.dest_mode
= INT_DEST_MODE
;
2623 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2624 entry
.trigger
= edge_level
;
2625 entry
.polarity
= active_high_low
;
2629 * IRQs < 16 are already in the irq_2_pin[] map
2632 add_pin_to_irq(irq
, ioapic
, pin
);
2634 entry
.vector
= assign_irq_vector(irq
);
2636 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2637 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2638 mp_ioapics
[ioapic
].mp_apicid
, pin
, entry
.vector
, irq
,
2639 edge_level
, active_high_low
);
2641 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2643 if (!ioapic
&& (irq
< 16))
2644 disable_8259A_irq(irq
);
2646 ioapic_write_entry(ioapic
, pin
, entry
);
2651 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2655 if (skip_ioapic_setup
)
2658 for (i
= 0; i
< mp_irq_entries
; i
++)
2659 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2660 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2662 if (i
>= mp_irq_entries
)
2665 *trigger
= irq_trigger(i
);
2666 *polarity
= irq_polarity(i
);
2670 #endif /* CONFIG_ACPI */
2672 static int __init
parse_disable_timer_pin_1(char *arg
)
2674 disable_timer_pin_1
= 1;
2677 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2679 static int __init
parse_enable_timer_pin_1(char *arg
)
2681 disable_timer_pin_1
= -1;
2684 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2686 static int __init
parse_noapic(char *arg
)
2688 /* disable IO-APIC */
2689 disable_ioapic_setup();
2692 early_param("noapic", parse_noapic
);
2694 void __init
ioapic_init_mappings(void)
2696 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2699 for (i
= 0; i
< nr_ioapics
; i
++) {
2700 if (smp_found_config
) {
2701 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2704 "WARNING: bogus zero IO-APIC "
2705 "address found in MPTABLE, "
2706 "disabling IO/APIC support!\n");
2707 smp_found_config
= 0;
2708 skip_ioapic_setup
= 1;
2709 goto fake_ioapic_page
;
2713 ioapic_phys
= (unsigned long)
2714 alloc_bootmem_pages(PAGE_SIZE
);
2715 ioapic_phys
= __pa(ioapic_phys
);
2717 set_fixmap_nocache(idx
, ioapic_phys
);
2718 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
2719 __fix_to_virt(idx
), ioapic_phys
);