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x86: I/O APIC: fix the name of the through-8259A handler
[deliverable/linux.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39
40 #include <asm/io.h>
41 #include <asm/smp.h>
42 #include <asm/desc.h>
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
45 #include <asm/nmi.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
48
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
51
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
54
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
57
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
60
61 int timer_through_8259 __initdata;
62
63 /*
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
66 */
67 int sis_apic_bug = -1;
68
69 /*
70 * # of IRQ routing registers
71 */
72 int nr_ioapic_registers[MAX_IO_APICS];
73
74 /* I/O APIC entries */
75 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
76 int nr_ioapics;
77
78 /* MP IRQ source entries */
79 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
80
81 /* # of MP IRQ source entries */
82 int mp_irq_entries;
83
84 static int disable_timer_pin_1 __initdata;
85
86 /*
87 * Rough estimation of how many shared IRQs there are, can
88 * be changed anytime.
89 */
90 #define MAX_PLUS_SHARED_IRQS NR_IRQS
91 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
92
93 /*
94 * This is performance-critical, we want to do it O(1)
95 *
96 * the indexing order of this array favors 1:1 mappings
97 * between pins and IRQs.
98 */
99
100 static struct irq_pin_list {
101 int apic, pin, next;
102 } irq_2_pin[PIN_MAP_SIZE];
103
104 struct io_apic {
105 unsigned int index;
106 unsigned int unused[3];
107 unsigned int data;
108 };
109
110 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
111 {
112 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
113 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
114 }
115
116 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
117 {
118 struct io_apic __iomem *io_apic = io_apic_base(apic);
119 writel(reg, &io_apic->index);
120 return readl(&io_apic->data);
121 }
122
123 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
124 {
125 struct io_apic __iomem *io_apic = io_apic_base(apic);
126 writel(reg, &io_apic->index);
127 writel(value, &io_apic->data);
128 }
129
130 /*
131 * Re-write a value: to be used for read-modify-write
132 * cycles where the read already set up the index register.
133 *
134 * Older SiS APIC requires we rewrite the index register
135 */
136 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
137 {
138 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
139 if (sis_apic_bug)
140 writel(reg, &io_apic->index);
141 writel(value, &io_apic->data);
142 }
143
144 union entry_union {
145 struct { u32 w1, w2; };
146 struct IO_APIC_route_entry entry;
147 };
148
149 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
150 {
151 union entry_union eu;
152 unsigned long flags;
153 spin_lock_irqsave(&ioapic_lock, flags);
154 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
155 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
156 spin_unlock_irqrestore(&ioapic_lock, flags);
157 return eu.entry;
158 }
159
160 /*
161 * When we write a new IO APIC routing entry, we need to write the high
162 * word first! If the mask bit in the low word is clear, we will enable
163 * the interrupt, and we need to make sure the entry is fully populated
164 * before that happens.
165 */
166 static void
167 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
168 {
169 union entry_union eu;
170 eu.entry = e;
171 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
172 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
173 }
174
175 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
176 {
177 unsigned long flags;
178 spin_lock_irqsave(&ioapic_lock, flags);
179 __ioapic_write_entry(apic, pin, e);
180 spin_unlock_irqrestore(&ioapic_lock, flags);
181 }
182
183 /*
184 * When we mask an IO APIC routing entry, we need to write the low
185 * word first, in order to set the mask bit before we change the
186 * high bits!
187 */
188 static void ioapic_mask_entry(int apic, int pin)
189 {
190 unsigned long flags;
191 union entry_union eu = { .entry.mask = 1 };
192
193 spin_lock_irqsave(&ioapic_lock, flags);
194 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
195 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
196 spin_unlock_irqrestore(&ioapic_lock, flags);
197 }
198
199 /*
200 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
201 * shared ISA-space IRQs, so we have to support them. We are super
202 * fast in the common case, and fast for shared ISA-space IRQs.
203 */
204 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
205 {
206 static int first_free_entry = NR_IRQS;
207 struct irq_pin_list *entry = irq_2_pin + irq;
208
209 while (entry->next)
210 entry = irq_2_pin + entry->next;
211
212 if (entry->pin != -1) {
213 entry->next = first_free_entry;
214 entry = irq_2_pin + entry->next;
215 if (++first_free_entry >= PIN_MAP_SIZE)
216 panic("io_apic.c: whoops");
217 }
218 entry->apic = apic;
219 entry->pin = pin;
220 }
221
222 /*
223 * Reroute an IRQ to a different pin.
224 */
225 static void __init replace_pin_at_irq(unsigned int irq,
226 int oldapic, int oldpin,
227 int newapic, int newpin)
228 {
229 struct irq_pin_list *entry = irq_2_pin + irq;
230
231 while (1) {
232 if (entry->apic == oldapic && entry->pin == oldpin) {
233 entry->apic = newapic;
234 entry->pin = newpin;
235 }
236 if (!entry->next)
237 break;
238 entry = irq_2_pin + entry->next;
239 }
240 }
241
242 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
243 {
244 struct irq_pin_list *entry = irq_2_pin + irq;
245 unsigned int pin, reg;
246
247 for (;;) {
248 pin = entry->pin;
249 if (pin == -1)
250 break;
251 reg = io_apic_read(entry->apic, 0x10 + pin*2);
252 reg &= ~disable;
253 reg |= enable;
254 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
255 if (!entry->next)
256 break;
257 entry = irq_2_pin + entry->next;
258 }
259 }
260
261 /* mask = 1 */
262 static void __mask_IO_APIC_irq (unsigned int irq)
263 {
264 __modify_IO_APIC_irq(irq, 0x00010000, 0);
265 }
266
267 /* mask = 0 */
268 static void __unmask_IO_APIC_irq (unsigned int irq)
269 {
270 __modify_IO_APIC_irq(irq, 0, 0x00010000);
271 }
272
273 /* mask = 1, trigger = 0 */
274 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
275 {
276 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
277 }
278
279 /* mask = 0, trigger = 1 */
280 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
281 {
282 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
283 }
284
285 static void mask_IO_APIC_irq (unsigned int irq)
286 {
287 unsigned long flags;
288
289 spin_lock_irqsave(&ioapic_lock, flags);
290 __mask_IO_APIC_irq(irq);
291 spin_unlock_irqrestore(&ioapic_lock, flags);
292 }
293
294 static void unmask_IO_APIC_irq (unsigned int irq)
295 {
296 unsigned long flags;
297
298 spin_lock_irqsave(&ioapic_lock, flags);
299 __unmask_IO_APIC_irq(irq);
300 spin_unlock_irqrestore(&ioapic_lock, flags);
301 }
302
303 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
304 {
305 struct IO_APIC_route_entry entry;
306
307 /* Check delivery_mode to be sure we're not clearing an SMI pin */
308 entry = ioapic_read_entry(apic, pin);
309 if (entry.delivery_mode == dest_SMI)
310 return;
311
312 /*
313 * Disable it in the IO-APIC irq-routing table:
314 */
315 ioapic_mask_entry(apic, pin);
316 }
317
318 static void clear_IO_APIC (void)
319 {
320 int apic, pin;
321
322 for (apic = 0; apic < nr_ioapics; apic++)
323 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
324 clear_IO_APIC_pin(apic, pin);
325 }
326
327 #ifdef CONFIG_SMP
328 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
329 {
330 unsigned long flags;
331 int pin;
332 struct irq_pin_list *entry = irq_2_pin + irq;
333 unsigned int apicid_value;
334 cpumask_t tmp;
335
336 cpus_and(tmp, cpumask, cpu_online_map);
337 if (cpus_empty(tmp))
338 tmp = TARGET_CPUS;
339
340 cpus_and(cpumask, tmp, CPU_MASK_ALL);
341
342 apicid_value = cpu_mask_to_apicid(cpumask);
343 /* Prepare to do the io_apic_write */
344 apicid_value = apicid_value << 24;
345 spin_lock_irqsave(&ioapic_lock, flags);
346 for (;;) {
347 pin = entry->pin;
348 if (pin == -1)
349 break;
350 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
351 if (!entry->next)
352 break;
353 entry = irq_2_pin + entry->next;
354 }
355 irq_desc[irq].affinity = cpumask;
356 spin_unlock_irqrestore(&ioapic_lock, flags);
357 }
358
359 #if defined(CONFIG_IRQBALANCE)
360 # include <asm/processor.h> /* kernel_thread() */
361 # include <linux/kernel_stat.h> /* kstat */
362 # include <linux/slab.h> /* kmalloc() */
363 # include <linux/timer.h>
364
365 #define IRQBALANCE_CHECK_ARCH -999
366 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
367 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
368 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
369 #define BALANCED_IRQ_LESS_DELTA (HZ)
370
371 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
372 static int physical_balance __read_mostly;
373 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
374
375 static struct irq_cpu_info {
376 unsigned long * last_irq;
377 unsigned long * irq_delta;
378 unsigned long irq;
379 } irq_cpu_data[NR_CPUS];
380
381 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
382 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
383 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
384
385 #define IDLE_ENOUGH(cpu,now) \
386 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
387
388 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
389
390 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
391
392 static cpumask_t balance_irq_affinity[NR_IRQS] = {
393 [0 ... NR_IRQS-1] = CPU_MASK_ALL
394 };
395
396 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
397 {
398 balance_irq_affinity[irq] = mask;
399 }
400
401 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
402 unsigned long now, int direction)
403 {
404 int search_idle = 1;
405 int cpu = curr_cpu;
406
407 goto inside;
408
409 do {
410 if (unlikely(cpu == curr_cpu))
411 search_idle = 0;
412 inside:
413 if (direction == 1) {
414 cpu++;
415 if (cpu >= NR_CPUS)
416 cpu = 0;
417 } else {
418 cpu--;
419 if (cpu == -1)
420 cpu = NR_CPUS-1;
421 }
422 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
423 (search_idle && !IDLE_ENOUGH(cpu,now)));
424
425 return cpu;
426 }
427
428 static inline void balance_irq(int cpu, int irq)
429 {
430 unsigned long now = jiffies;
431 cpumask_t allowed_mask;
432 unsigned int new_cpu;
433
434 if (irqbalance_disabled)
435 return;
436
437 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
438 new_cpu = move(cpu, allowed_mask, now, 1);
439 if (cpu != new_cpu) {
440 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
441 }
442 }
443
444 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
445 {
446 int i, j;
447
448 for_each_online_cpu(i) {
449 for (j = 0; j < NR_IRQS; j++) {
450 if (!irq_desc[j].action)
451 continue;
452 /* Is it a significant load ? */
453 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
454 useful_load_threshold)
455 continue;
456 balance_irq(i, j);
457 }
458 }
459 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
460 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
461 return;
462 }
463
464 static void do_irq_balance(void)
465 {
466 int i, j;
467 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
468 unsigned long move_this_load = 0;
469 int max_loaded = 0, min_loaded = 0;
470 int load;
471 unsigned long useful_load_threshold = balanced_irq_interval + 10;
472 int selected_irq;
473 int tmp_loaded, first_attempt = 1;
474 unsigned long tmp_cpu_irq;
475 unsigned long imbalance = 0;
476 cpumask_t allowed_mask, target_cpu_mask, tmp;
477
478 for_each_possible_cpu(i) {
479 int package_index;
480 CPU_IRQ(i) = 0;
481 if (!cpu_online(i))
482 continue;
483 package_index = CPU_TO_PACKAGEINDEX(i);
484 for (j = 0; j < NR_IRQS; j++) {
485 unsigned long value_now, delta;
486 /* Is this an active IRQ or balancing disabled ? */
487 if (!irq_desc[j].action || irq_balancing_disabled(j))
488 continue;
489 if ( package_index == i )
490 IRQ_DELTA(package_index,j) = 0;
491 /* Determine the total count per processor per IRQ */
492 value_now = (unsigned long) kstat_cpu(i).irqs[j];
493
494 /* Determine the activity per processor per IRQ */
495 delta = value_now - LAST_CPU_IRQ(i,j);
496
497 /* Update last_cpu_irq[][] for the next time */
498 LAST_CPU_IRQ(i,j) = value_now;
499
500 /* Ignore IRQs whose rate is less than the clock */
501 if (delta < useful_load_threshold)
502 continue;
503 /* update the load for the processor or package total */
504 IRQ_DELTA(package_index,j) += delta;
505
506 /* Keep track of the higher numbered sibling as well */
507 if (i != package_index)
508 CPU_IRQ(i) += delta;
509 /*
510 * We have sibling A and sibling B in the package
511 *
512 * cpu_irq[A] = load for cpu A + load for cpu B
513 * cpu_irq[B] = load for cpu B
514 */
515 CPU_IRQ(package_index) += delta;
516 }
517 }
518 /* Find the least loaded processor package */
519 for_each_online_cpu(i) {
520 if (i != CPU_TO_PACKAGEINDEX(i))
521 continue;
522 if (min_cpu_irq > CPU_IRQ(i)) {
523 min_cpu_irq = CPU_IRQ(i);
524 min_loaded = i;
525 }
526 }
527 max_cpu_irq = ULONG_MAX;
528
529 tryanothercpu:
530 /* Look for heaviest loaded processor.
531 * We may come back to get the next heaviest loaded processor.
532 * Skip processors with trivial loads.
533 */
534 tmp_cpu_irq = 0;
535 tmp_loaded = -1;
536 for_each_online_cpu(i) {
537 if (i != CPU_TO_PACKAGEINDEX(i))
538 continue;
539 if (max_cpu_irq <= CPU_IRQ(i))
540 continue;
541 if (tmp_cpu_irq < CPU_IRQ(i)) {
542 tmp_cpu_irq = CPU_IRQ(i);
543 tmp_loaded = i;
544 }
545 }
546
547 if (tmp_loaded == -1) {
548 /* In the case of small number of heavy interrupt sources,
549 * loading some of the cpus too much. We use Ingo's original
550 * approach to rotate them around.
551 */
552 if (!first_attempt && imbalance >= useful_load_threshold) {
553 rotate_irqs_among_cpus(useful_load_threshold);
554 return;
555 }
556 goto not_worth_the_effort;
557 }
558
559 first_attempt = 0; /* heaviest search */
560 max_cpu_irq = tmp_cpu_irq; /* load */
561 max_loaded = tmp_loaded; /* processor */
562 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
563
564 /* if imbalance is less than approx 10% of max load, then
565 * observe diminishing returns action. - quit
566 */
567 if (imbalance < (max_cpu_irq >> 3))
568 goto not_worth_the_effort;
569
570 tryanotherirq:
571 /* if we select an IRQ to move that can't go where we want, then
572 * see if there is another one to try.
573 */
574 move_this_load = 0;
575 selected_irq = -1;
576 for (j = 0; j < NR_IRQS; j++) {
577 /* Is this an active IRQ? */
578 if (!irq_desc[j].action)
579 continue;
580 if (imbalance <= IRQ_DELTA(max_loaded,j))
581 continue;
582 /* Try to find the IRQ that is closest to the imbalance
583 * without going over.
584 */
585 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
586 move_this_load = IRQ_DELTA(max_loaded,j);
587 selected_irq = j;
588 }
589 }
590 if (selected_irq == -1) {
591 goto tryanothercpu;
592 }
593
594 imbalance = move_this_load;
595
596 /* For physical_balance case, we accumulated both load
597 * values in the one of the siblings cpu_irq[],
598 * to use the same code for physical and logical processors
599 * as much as possible.
600 *
601 * NOTE: the cpu_irq[] array holds the sum of the load for
602 * sibling A and sibling B in the slot for the lowest numbered
603 * sibling (A), _AND_ the load for sibling B in the slot for
604 * the higher numbered sibling.
605 *
606 * We seek the least loaded sibling by making the comparison
607 * (A+B)/2 vs B
608 */
609 load = CPU_IRQ(min_loaded) >> 1;
610 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
611 if (load > CPU_IRQ(j)) {
612 /* This won't change cpu_sibling_map[min_loaded] */
613 load = CPU_IRQ(j);
614 min_loaded = j;
615 }
616 }
617
618 cpus_and(allowed_mask,
619 cpu_online_map,
620 balance_irq_affinity[selected_irq]);
621 target_cpu_mask = cpumask_of_cpu(min_loaded);
622 cpus_and(tmp, target_cpu_mask, allowed_mask);
623
624 if (!cpus_empty(tmp)) {
625 /* mark for change destination */
626 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
627
628 /* Since we made a change, come back sooner to
629 * check for more variation.
630 */
631 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
632 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
633 return;
634 }
635 goto tryanotherirq;
636
637 not_worth_the_effort:
638 /*
639 * if we did not find an IRQ to move, then adjust the time interval
640 * upward
641 */
642 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
643 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
644 return;
645 }
646
647 static int balanced_irq(void *unused)
648 {
649 int i;
650 unsigned long prev_balance_time = jiffies;
651 long time_remaining = balanced_irq_interval;
652
653 /* push everything to CPU 0 to give us a starting point. */
654 for (i = 0 ; i < NR_IRQS ; i++) {
655 irq_desc[i].pending_mask = cpumask_of_cpu(0);
656 set_pending_irq(i, cpumask_of_cpu(0));
657 }
658
659 set_freezable();
660 for ( ; ; ) {
661 time_remaining = schedule_timeout_interruptible(time_remaining);
662 try_to_freeze();
663 if (time_after(jiffies,
664 prev_balance_time+balanced_irq_interval)) {
665 preempt_disable();
666 do_irq_balance();
667 prev_balance_time = jiffies;
668 time_remaining = balanced_irq_interval;
669 preempt_enable();
670 }
671 }
672 return 0;
673 }
674
675 static int __init balanced_irq_init(void)
676 {
677 int i;
678 struct cpuinfo_x86 *c;
679 cpumask_t tmp;
680
681 cpus_shift_right(tmp, cpu_online_map, 2);
682 c = &boot_cpu_data;
683 /* When not overwritten by the command line ask subarchitecture. */
684 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
685 irqbalance_disabled = NO_BALANCE_IRQ;
686 if (irqbalance_disabled)
687 return 0;
688
689 /* disable irqbalance completely if there is only one processor online */
690 if (num_online_cpus() < 2) {
691 irqbalance_disabled = 1;
692 return 0;
693 }
694 /*
695 * Enable physical balance only if more than 1 physical processor
696 * is present
697 */
698 if (smp_num_siblings > 1 && !cpus_empty(tmp))
699 physical_balance = 1;
700
701 for_each_online_cpu(i) {
702 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
703 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
704 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
705 printk(KERN_ERR "balanced_irq_init: out of memory");
706 goto failed;
707 }
708 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
709 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
710 }
711
712 printk(KERN_INFO "Starting balanced_irq\n");
713 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
714 return 0;
715 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
716 failed:
717 for_each_possible_cpu(i) {
718 kfree(irq_cpu_data[i].irq_delta);
719 irq_cpu_data[i].irq_delta = NULL;
720 kfree(irq_cpu_data[i].last_irq);
721 irq_cpu_data[i].last_irq = NULL;
722 }
723 return 0;
724 }
725
726 int __devinit irqbalance_disable(char *str)
727 {
728 irqbalance_disabled = 1;
729 return 1;
730 }
731
732 __setup("noirqbalance", irqbalance_disable);
733
734 late_initcall(balanced_irq_init);
735 #endif /* CONFIG_IRQBALANCE */
736 #endif /* CONFIG_SMP */
737
738 #ifndef CONFIG_SMP
739 void send_IPI_self(int vector)
740 {
741 unsigned int cfg;
742
743 /*
744 * Wait for idle.
745 */
746 apic_wait_icr_idle();
747 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
748 /*
749 * Send the IPI. The write to APIC_ICR fires this off.
750 */
751 apic_write_around(APIC_ICR, cfg);
752 }
753 #endif /* !CONFIG_SMP */
754
755
756 /*
757 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
758 * specific CPU-side IRQs.
759 */
760
761 #define MAX_PIRQS 8
762 static int pirq_entries [MAX_PIRQS];
763 static int pirqs_enabled;
764 int skip_ioapic_setup;
765
766 static int __init ioapic_pirq_setup(char *str)
767 {
768 int i, max;
769 int ints[MAX_PIRQS+1];
770
771 get_options(str, ARRAY_SIZE(ints), ints);
772
773 for (i = 0; i < MAX_PIRQS; i++)
774 pirq_entries[i] = -1;
775
776 pirqs_enabled = 1;
777 apic_printk(APIC_VERBOSE, KERN_INFO
778 "PIRQ redirection, working around broken MP-BIOS.\n");
779 max = MAX_PIRQS;
780 if (ints[0] < MAX_PIRQS)
781 max = ints[0];
782
783 for (i = 0; i < max; i++) {
784 apic_printk(APIC_VERBOSE, KERN_DEBUG
785 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
786 /*
787 * PIRQs are mapped upside down, usually.
788 */
789 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
790 }
791 return 1;
792 }
793
794 __setup("pirq=", ioapic_pirq_setup);
795
796 /*
797 * Find the IRQ entry number of a certain pin.
798 */
799 static int find_irq_entry(int apic, int pin, int type)
800 {
801 int i;
802
803 for (i = 0; i < mp_irq_entries; i++)
804 if (mp_irqs[i].mpc_irqtype == type &&
805 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
806 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
807 mp_irqs[i].mpc_dstirq == pin)
808 return i;
809
810 return -1;
811 }
812
813 /*
814 * Find the pin to which IRQ[irq] (ISA) is connected
815 */
816 static int __init find_isa_irq_pin(int irq, int type)
817 {
818 int i;
819
820 for (i = 0; i < mp_irq_entries; i++) {
821 int lbus = mp_irqs[i].mpc_srcbus;
822
823 if (test_bit(lbus, mp_bus_not_pci) &&
824 (mp_irqs[i].mpc_irqtype == type) &&
825 (mp_irqs[i].mpc_srcbusirq == irq))
826
827 return mp_irqs[i].mpc_dstirq;
828 }
829 return -1;
830 }
831
832 static int __init find_isa_irq_apic(int irq, int type)
833 {
834 int i;
835
836 for (i = 0; i < mp_irq_entries; i++) {
837 int lbus = mp_irqs[i].mpc_srcbus;
838
839 if (test_bit(lbus, mp_bus_not_pci) &&
840 (mp_irqs[i].mpc_irqtype == type) &&
841 (mp_irqs[i].mpc_srcbusirq == irq))
842 break;
843 }
844 if (i < mp_irq_entries) {
845 int apic;
846 for(apic = 0; apic < nr_ioapics; apic++) {
847 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
848 return apic;
849 }
850 }
851
852 return -1;
853 }
854
855 /*
856 * Find a specific PCI IRQ entry.
857 * Not an __init, possibly needed by modules
858 */
859 static int pin_2_irq(int idx, int apic, int pin);
860
861 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
862 {
863 int apic, i, best_guess = -1;
864
865 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
866 "slot:%d, pin:%d.\n", bus, slot, pin);
867 if (mp_bus_id_to_pci_bus[bus] == -1) {
868 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
869 return -1;
870 }
871 for (i = 0; i < mp_irq_entries; i++) {
872 int lbus = mp_irqs[i].mpc_srcbus;
873
874 for (apic = 0; apic < nr_ioapics; apic++)
875 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
876 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
877 break;
878
879 if (!test_bit(lbus, mp_bus_not_pci) &&
880 !mp_irqs[i].mpc_irqtype &&
881 (bus == lbus) &&
882 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
883 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
884
885 if (!(apic || IO_APIC_IRQ(irq)))
886 continue;
887
888 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
889 return irq;
890 /*
891 * Use the first all-but-pin matching entry as a
892 * best-guess fuzzy result for broken mptables.
893 */
894 if (best_guess < 0)
895 best_guess = irq;
896 }
897 }
898 return best_guess;
899 }
900 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
901
902 /*
903 * This function currently is only a helper for the i386 smp boot process where
904 * we need to reprogram the ioredtbls to cater for the cpus which have come online
905 * so mask in all cases should simply be TARGET_CPUS
906 */
907 #ifdef CONFIG_SMP
908 void __init setup_ioapic_dest(void)
909 {
910 int pin, ioapic, irq, irq_entry;
911
912 if (skip_ioapic_setup == 1)
913 return;
914
915 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
916 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
917 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
918 if (irq_entry == -1)
919 continue;
920 irq = pin_2_irq(irq_entry, ioapic, pin);
921 set_ioapic_affinity_irq(irq, TARGET_CPUS);
922 }
923
924 }
925 }
926 #endif
927
928 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
929 /*
930 * EISA Edge/Level control register, ELCR
931 */
932 static int EISA_ELCR(unsigned int irq)
933 {
934 if (irq < 16) {
935 unsigned int port = 0x4d0 + (irq >> 3);
936 return (inb(port) >> (irq & 7)) & 1;
937 }
938 apic_printk(APIC_VERBOSE, KERN_INFO
939 "Broken MPtable reports ISA irq %d\n", irq);
940 return 0;
941 }
942 #endif
943
944 /* ISA interrupts are always polarity zero edge triggered,
945 * when listed as conforming in the MP table. */
946
947 #define default_ISA_trigger(idx) (0)
948 #define default_ISA_polarity(idx) (0)
949
950 /* EISA interrupts are always polarity zero and can be edge or level
951 * trigger depending on the ELCR value. If an interrupt is listed as
952 * EISA conforming in the MP table, that means its trigger type must
953 * be read in from the ELCR */
954
955 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
956 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
957
958 /* PCI interrupts are always polarity one level triggered,
959 * when listed as conforming in the MP table. */
960
961 #define default_PCI_trigger(idx) (1)
962 #define default_PCI_polarity(idx) (1)
963
964 /* MCA interrupts are always polarity zero level triggered,
965 * when listed as conforming in the MP table. */
966
967 #define default_MCA_trigger(idx) (1)
968 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
969
970 static int MPBIOS_polarity(int idx)
971 {
972 int bus = mp_irqs[idx].mpc_srcbus;
973 int polarity;
974
975 /*
976 * Determine IRQ line polarity (high active or low active):
977 */
978 switch (mp_irqs[idx].mpc_irqflag & 3)
979 {
980 case 0: /* conforms, ie. bus-type dependent polarity */
981 {
982 polarity = test_bit(bus, mp_bus_not_pci)?
983 default_ISA_polarity(idx):
984 default_PCI_polarity(idx);
985 break;
986 }
987 case 1: /* high active */
988 {
989 polarity = 0;
990 break;
991 }
992 case 2: /* reserved */
993 {
994 printk(KERN_WARNING "broken BIOS!!\n");
995 polarity = 1;
996 break;
997 }
998 case 3: /* low active */
999 {
1000 polarity = 1;
1001 break;
1002 }
1003 default: /* invalid */
1004 {
1005 printk(KERN_WARNING "broken BIOS!!\n");
1006 polarity = 1;
1007 break;
1008 }
1009 }
1010 return polarity;
1011 }
1012
1013 static int MPBIOS_trigger(int idx)
1014 {
1015 int bus = mp_irqs[idx].mpc_srcbus;
1016 int trigger;
1017
1018 /*
1019 * Determine IRQ trigger mode (edge or level sensitive):
1020 */
1021 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1022 {
1023 case 0: /* conforms, ie. bus-type dependent */
1024 {
1025 trigger = test_bit(bus, mp_bus_not_pci)?
1026 default_ISA_trigger(idx):
1027 default_PCI_trigger(idx);
1028 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1029 switch (mp_bus_id_to_type[bus])
1030 {
1031 case MP_BUS_ISA: /* ISA pin */
1032 {
1033 /* set before the switch */
1034 break;
1035 }
1036 case MP_BUS_EISA: /* EISA pin */
1037 {
1038 trigger = default_EISA_trigger(idx);
1039 break;
1040 }
1041 case MP_BUS_PCI: /* PCI pin */
1042 {
1043 /* set before the switch */
1044 break;
1045 }
1046 case MP_BUS_MCA: /* MCA pin */
1047 {
1048 trigger = default_MCA_trigger(idx);
1049 break;
1050 }
1051 default:
1052 {
1053 printk(KERN_WARNING "broken BIOS!!\n");
1054 trigger = 1;
1055 break;
1056 }
1057 }
1058 #endif
1059 break;
1060 }
1061 case 1: /* edge */
1062 {
1063 trigger = 0;
1064 break;
1065 }
1066 case 2: /* reserved */
1067 {
1068 printk(KERN_WARNING "broken BIOS!!\n");
1069 trigger = 1;
1070 break;
1071 }
1072 case 3: /* level */
1073 {
1074 trigger = 1;
1075 break;
1076 }
1077 default: /* invalid */
1078 {
1079 printk(KERN_WARNING "broken BIOS!!\n");
1080 trigger = 0;
1081 break;
1082 }
1083 }
1084 return trigger;
1085 }
1086
1087 static inline int irq_polarity(int idx)
1088 {
1089 return MPBIOS_polarity(idx);
1090 }
1091
1092 static inline int irq_trigger(int idx)
1093 {
1094 return MPBIOS_trigger(idx);
1095 }
1096
1097 static int pin_2_irq(int idx, int apic, int pin)
1098 {
1099 int irq, i;
1100 int bus = mp_irqs[idx].mpc_srcbus;
1101
1102 /*
1103 * Debugging check, we are in big trouble if this message pops up!
1104 */
1105 if (mp_irqs[idx].mpc_dstirq != pin)
1106 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1107
1108 if (test_bit(bus, mp_bus_not_pci))
1109 irq = mp_irqs[idx].mpc_srcbusirq;
1110 else {
1111 /*
1112 * PCI IRQs are mapped in order
1113 */
1114 i = irq = 0;
1115 while (i < apic)
1116 irq += nr_ioapic_registers[i++];
1117 irq += pin;
1118
1119 /*
1120 * For MPS mode, so far only needed by ES7000 platform
1121 */
1122 if (ioapic_renumber_irq)
1123 irq = ioapic_renumber_irq(apic, irq);
1124 }
1125
1126 /*
1127 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1128 */
1129 if ((pin >= 16) && (pin <= 23)) {
1130 if (pirq_entries[pin-16] != -1) {
1131 if (!pirq_entries[pin-16]) {
1132 apic_printk(APIC_VERBOSE, KERN_DEBUG
1133 "disabling PIRQ%d\n", pin-16);
1134 } else {
1135 irq = pirq_entries[pin-16];
1136 apic_printk(APIC_VERBOSE, KERN_DEBUG
1137 "using PIRQ%d -> IRQ %d\n",
1138 pin-16, irq);
1139 }
1140 }
1141 }
1142 return irq;
1143 }
1144
1145 static inline int IO_APIC_irq_trigger(int irq)
1146 {
1147 int apic, idx, pin;
1148
1149 for (apic = 0; apic < nr_ioapics; apic++) {
1150 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1151 idx = find_irq_entry(apic,pin,mp_INT);
1152 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1153 return irq_trigger(idx);
1154 }
1155 }
1156 /*
1157 * nonexistent IRQs are edge default
1158 */
1159 return 0;
1160 }
1161
1162 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1163 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1164
1165 static int __assign_irq_vector(int irq)
1166 {
1167 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1168 int vector, offset;
1169
1170 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1171
1172 if (irq_vector[irq] > 0)
1173 return irq_vector[irq];
1174
1175 vector = current_vector;
1176 offset = current_offset;
1177 next:
1178 vector += 8;
1179 if (vector >= FIRST_SYSTEM_VECTOR) {
1180 offset = (offset + 1) % 8;
1181 vector = FIRST_DEVICE_VECTOR + offset;
1182 }
1183 if (vector == current_vector)
1184 return -ENOSPC;
1185 if (test_and_set_bit(vector, used_vectors))
1186 goto next;
1187
1188 current_vector = vector;
1189 current_offset = offset;
1190 irq_vector[irq] = vector;
1191
1192 return vector;
1193 }
1194
1195 static int assign_irq_vector(int irq)
1196 {
1197 unsigned long flags;
1198 int vector;
1199
1200 spin_lock_irqsave(&vector_lock, flags);
1201 vector = __assign_irq_vector(irq);
1202 spin_unlock_irqrestore(&vector_lock, flags);
1203
1204 return vector;
1205 }
1206 static struct irq_chip ioapic_chip;
1207
1208 #define IOAPIC_AUTO -1
1209 #define IOAPIC_EDGE 0
1210 #define IOAPIC_LEVEL 1
1211
1212 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1213 {
1214 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1215 trigger == IOAPIC_LEVEL) {
1216 irq_desc[irq].status |= IRQ_LEVEL;
1217 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1218 handle_fasteoi_irq, "fasteoi");
1219 } else {
1220 irq_desc[irq].status &= ~IRQ_LEVEL;
1221 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1222 handle_edge_irq, "edge");
1223 }
1224 set_intr_gate(vector, interrupt[irq]);
1225 }
1226
1227 static void __init setup_IO_APIC_irqs(void)
1228 {
1229 struct IO_APIC_route_entry entry;
1230 int apic, pin, idx, irq, first_notcon = 1, vector;
1231
1232 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1233
1234 for (apic = 0; apic < nr_ioapics; apic++) {
1235 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1236
1237 /*
1238 * add it to the IO-APIC irq-routing table:
1239 */
1240 memset(&entry,0,sizeof(entry));
1241
1242 entry.delivery_mode = INT_DELIVERY_MODE;
1243 entry.dest_mode = INT_DEST_MODE;
1244 entry.mask = 0; /* enable IRQ */
1245 entry.dest.logical.logical_dest =
1246 cpu_mask_to_apicid(TARGET_CPUS);
1247
1248 idx = find_irq_entry(apic,pin,mp_INT);
1249 if (idx == -1) {
1250 if (first_notcon) {
1251 apic_printk(APIC_VERBOSE, KERN_DEBUG
1252 " IO-APIC (apicid-pin) %d-%d",
1253 mp_ioapics[apic].mpc_apicid,
1254 pin);
1255 first_notcon = 0;
1256 } else
1257 apic_printk(APIC_VERBOSE, ", %d-%d",
1258 mp_ioapics[apic].mpc_apicid, pin);
1259 continue;
1260 }
1261
1262 if (!first_notcon) {
1263 apic_printk(APIC_VERBOSE, " not connected.\n");
1264 first_notcon = 1;
1265 }
1266
1267 entry.trigger = irq_trigger(idx);
1268 entry.polarity = irq_polarity(idx);
1269
1270 if (irq_trigger(idx)) {
1271 entry.trigger = 1;
1272 entry.mask = 1;
1273 }
1274
1275 irq = pin_2_irq(idx, apic, pin);
1276 /*
1277 * skip adding the timer int on secondary nodes, which causes
1278 * a small but painful rift in the time-space continuum
1279 */
1280 if (multi_timer_check(apic, irq))
1281 continue;
1282 else
1283 add_pin_to_irq(irq, apic, pin);
1284
1285 if (!apic && !IO_APIC_IRQ(irq))
1286 continue;
1287
1288 if (IO_APIC_IRQ(irq)) {
1289 vector = assign_irq_vector(irq);
1290 entry.vector = vector;
1291 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1292
1293 if (!apic && (irq < 16))
1294 disable_8259A_irq(irq);
1295 }
1296 ioapic_write_entry(apic, pin, entry);
1297 }
1298 }
1299
1300 if (!first_notcon)
1301 apic_printk(APIC_VERBOSE, " not connected.\n");
1302 }
1303
1304 /*
1305 * Set up the 8259A-master output pin:
1306 */
1307 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1308 {
1309 struct IO_APIC_route_entry entry;
1310
1311 memset(&entry,0,sizeof(entry));
1312
1313 disable_8259A_irq(0);
1314
1315 /* mask LVT0 */
1316 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1317
1318 /*
1319 * We use logical delivery to get the timer IRQ
1320 * to the first CPU.
1321 */
1322 entry.dest_mode = INT_DEST_MODE;
1323 entry.mask = 0; /* unmask IRQ now */
1324 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1325 entry.delivery_mode = INT_DELIVERY_MODE;
1326 entry.polarity = 0;
1327 entry.trigger = 0;
1328 entry.vector = vector;
1329
1330 /*
1331 * The timer IRQ doesn't have to know that behind the
1332 * scene we have a 8259A-master in AEOI mode ...
1333 */
1334 ioapic_register_intr(0, vector, IOAPIC_EDGE);
1335
1336 /*
1337 * Add it to the IO-APIC irq-routing table:
1338 */
1339 ioapic_write_entry(apic, pin, entry);
1340
1341 enable_8259A_irq(0);
1342 }
1343
1344 void __init print_IO_APIC(void)
1345 {
1346 int apic, i;
1347 union IO_APIC_reg_00 reg_00;
1348 union IO_APIC_reg_01 reg_01;
1349 union IO_APIC_reg_02 reg_02;
1350 union IO_APIC_reg_03 reg_03;
1351 unsigned long flags;
1352
1353 if (apic_verbosity == APIC_QUIET)
1354 return;
1355
1356 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1357 for (i = 0; i < nr_ioapics; i++)
1358 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1359 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1360
1361 /*
1362 * We are a bit conservative about what we expect. We have to
1363 * know about every hardware change ASAP.
1364 */
1365 printk(KERN_INFO "testing the IO APIC.......................\n");
1366
1367 for (apic = 0; apic < nr_ioapics; apic++) {
1368
1369 spin_lock_irqsave(&ioapic_lock, flags);
1370 reg_00.raw = io_apic_read(apic, 0);
1371 reg_01.raw = io_apic_read(apic, 1);
1372 if (reg_01.bits.version >= 0x10)
1373 reg_02.raw = io_apic_read(apic, 2);
1374 if (reg_01.bits.version >= 0x20)
1375 reg_03.raw = io_apic_read(apic, 3);
1376 spin_unlock_irqrestore(&ioapic_lock, flags);
1377
1378 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1379 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1380 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1381 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1382 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1383
1384 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1385 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1386
1387 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1388 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1389
1390 /*
1391 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1392 * but the value of reg_02 is read as the previous read register
1393 * value, so ignore it if reg_02 == reg_01.
1394 */
1395 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1396 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1397 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1398 }
1399
1400 /*
1401 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1402 * or reg_03, but the value of reg_0[23] is read as the previous read
1403 * register value, so ignore it if reg_03 == reg_0[12].
1404 */
1405 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1406 reg_03.raw != reg_01.raw) {
1407 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1408 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1409 }
1410
1411 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1412
1413 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1414 " Stat Dest Deli Vect: \n");
1415
1416 for (i = 0; i <= reg_01.bits.entries; i++) {
1417 struct IO_APIC_route_entry entry;
1418
1419 entry = ioapic_read_entry(apic, i);
1420
1421 printk(KERN_DEBUG " %02x %03X %02X ",
1422 i,
1423 entry.dest.logical.logical_dest,
1424 entry.dest.physical.physical_dest
1425 );
1426
1427 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1428 entry.mask,
1429 entry.trigger,
1430 entry.irr,
1431 entry.polarity,
1432 entry.delivery_status,
1433 entry.dest_mode,
1434 entry.delivery_mode,
1435 entry.vector
1436 );
1437 }
1438 }
1439 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1440 for (i = 0; i < NR_IRQS; i++) {
1441 struct irq_pin_list *entry = irq_2_pin + i;
1442 if (entry->pin < 0)
1443 continue;
1444 printk(KERN_DEBUG "IRQ%d ", i);
1445 for (;;) {
1446 printk("-> %d:%d", entry->apic, entry->pin);
1447 if (!entry->next)
1448 break;
1449 entry = irq_2_pin + entry->next;
1450 }
1451 printk("\n");
1452 }
1453
1454 printk(KERN_INFO ".................................... done.\n");
1455
1456 return;
1457 }
1458
1459 #if 0
1460
1461 static void print_APIC_bitfield (int base)
1462 {
1463 unsigned int v;
1464 int i, j;
1465
1466 if (apic_verbosity == APIC_QUIET)
1467 return;
1468
1469 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1470 for (i = 0; i < 8; i++) {
1471 v = apic_read(base + i*0x10);
1472 for (j = 0; j < 32; j++) {
1473 if (v & (1<<j))
1474 printk("1");
1475 else
1476 printk("0");
1477 }
1478 printk("\n");
1479 }
1480 }
1481
1482 void /*__init*/ print_local_APIC(void * dummy)
1483 {
1484 unsigned int v, ver, maxlvt;
1485
1486 if (apic_verbosity == APIC_QUIET)
1487 return;
1488
1489 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1490 smp_processor_id(), hard_smp_processor_id());
1491 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1492 GET_APIC_ID(read_apic_id()));
1493 v = apic_read(APIC_LVR);
1494 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1495 ver = GET_APIC_VERSION(v);
1496 maxlvt = lapic_get_maxlvt();
1497
1498 v = apic_read(APIC_TASKPRI);
1499 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1500
1501 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1502 v = apic_read(APIC_ARBPRI);
1503 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1504 v & APIC_ARBPRI_MASK);
1505 v = apic_read(APIC_PROCPRI);
1506 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1507 }
1508
1509 v = apic_read(APIC_EOI);
1510 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1511 v = apic_read(APIC_RRR);
1512 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1513 v = apic_read(APIC_LDR);
1514 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1515 v = apic_read(APIC_DFR);
1516 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1517 v = apic_read(APIC_SPIV);
1518 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1519
1520 printk(KERN_DEBUG "... APIC ISR field:\n");
1521 print_APIC_bitfield(APIC_ISR);
1522 printk(KERN_DEBUG "... APIC TMR field:\n");
1523 print_APIC_bitfield(APIC_TMR);
1524 printk(KERN_DEBUG "... APIC IRR field:\n");
1525 print_APIC_bitfield(APIC_IRR);
1526
1527 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1528 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1529 apic_write(APIC_ESR, 0);
1530 v = apic_read(APIC_ESR);
1531 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1532 }
1533
1534 v = apic_read(APIC_ICR);
1535 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1536 v = apic_read(APIC_ICR2);
1537 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1538
1539 v = apic_read(APIC_LVTT);
1540 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1541
1542 if (maxlvt > 3) { /* PC is LVT#4. */
1543 v = apic_read(APIC_LVTPC);
1544 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1545 }
1546 v = apic_read(APIC_LVT0);
1547 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1548 v = apic_read(APIC_LVT1);
1549 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1550
1551 if (maxlvt > 2) { /* ERR is LVT#3. */
1552 v = apic_read(APIC_LVTERR);
1553 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1554 }
1555
1556 v = apic_read(APIC_TMICT);
1557 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1558 v = apic_read(APIC_TMCCT);
1559 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1560 v = apic_read(APIC_TDCR);
1561 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1562 printk("\n");
1563 }
1564
1565 void print_all_local_APICs (void)
1566 {
1567 on_each_cpu(print_local_APIC, NULL, 1, 1);
1568 }
1569
1570 void /*__init*/ print_PIC(void)
1571 {
1572 unsigned int v;
1573 unsigned long flags;
1574
1575 if (apic_verbosity == APIC_QUIET)
1576 return;
1577
1578 printk(KERN_DEBUG "\nprinting PIC contents\n");
1579
1580 spin_lock_irqsave(&i8259A_lock, flags);
1581
1582 v = inb(0xa1) << 8 | inb(0x21);
1583 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1584
1585 v = inb(0xa0) << 8 | inb(0x20);
1586 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1587
1588 outb(0x0b,0xa0);
1589 outb(0x0b,0x20);
1590 v = inb(0xa0) << 8 | inb(0x20);
1591 outb(0x0a,0xa0);
1592 outb(0x0a,0x20);
1593
1594 spin_unlock_irqrestore(&i8259A_lock, flags);
1595
1596 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1597
1598 v = inb(0x4d1) << 8 | inb(0x4d0);
1599 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1600 }
1601
1602 #endif /* 0 */
1603
1604 static void __init enable_IO_APIC(void)
1605 {
1606 union IO_APIC_reg_01 reg_01;
1607 int i8259_apic, i8259_pin;
1608 int i, apic;
1609 unsigned long flags;
1610
1611 for (i = 0; i < PIN_MAP_SIZE; i++) {
1612 irq_2_pin[i].pin = -1;
1613 irq_2_pin[i].next = 0;
1614 }
1615 if (!pirqs_enabled)
1616 for (i = 0; i < MAX_PIRQS; i++)
1617 pirq_entries[i] = -1;
1618
1619 /*
1620 * The number of IO-APIC IRQ registers (== #pins):
1621 */
1622 for (apic = 0; apic < nr_ioapics; apic++) {
1623 spin_lock_irqsave(&ioapic_lock, flags);
1624 reg_01.raw = io_apic_read(apic, 1);
1625 spin_unlock_irqrestore(&ioapic_lock, flags);
1626 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1627 }
1628 for(apic = 0; apic < nr_ioapics; apic++) {
1629 int pin;
1630 /* See if any of the pins is in ExtINT mode */
1631 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1632 struct IO_APIC_route_entry entry;
1633 entry = ioapic_read_entry(apic, pin);
1634
1635
1636 /* If the interrupt line is enabled and in ExtInt mode
1637 * I have found the pin where the i8259 is connected.
1638 */
1639 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1640 ioapic_i8259.apic = apic;
1641 ioapic_i8259.pin = pin;
1642 goto found_i8259;
1643 }
1644 }
1645 }
1646 found_i8259:
1647 /* Look to see what if the MP table has reported the ExtINT */
1648 /* If we could not find the appropriate pin by looking at the ioapic
1649 * the i8259 probably is not connected the ioapic but give the
1650 * mptable a chance anyway.
1651 */
1652 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1653 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1654 /* Trust the MP table if nothing is setup in the hardware */
1655 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1656 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1657 ioapic_i8259.pin = i8259_pin;
1658 ioapic_i8259.apic = i8259_apic;
1659 }
1660 /* Complain if the MP table and the hardware disagree */
1661 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1662 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1663 {
1664 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1665 }
1666
1667 /*
1668 * Do not trust the IO-APIC being empty at bootup
1669 */
1670 clear_IO_APIC();
1671 }
1672
1673 /*
1674 * Not an __init, needed by the reboot code
1675 */
1676 void disable_IO_APIC(void)
1677 {
1678 /*
1679 * Clear the IO-APIC before rebooting:
1680 */
1681 clear_IO_APIC();
1682
1683 /*
1684 * If the i8259 is routed through an IOAPIC
1685 * Put that IOAPIC in virtual wire mode
1686 * so legacy interrupts can be delivered.
1687 */
1688 if (ioapic_i8259.pin != -1) {
1689 struct IO_APIC_route_entry entry;
1690
1691 memset(&entry, 0, sizeof(entry));
1692 entry.mask = 0; /* Enabled */
1693 entry.trigger = 0; /* Edge */
1694 entry.irr = 0;
1695 entry.polarity = 0; /* High */
1696 entry.delivery_status = 0;
1697 entry.dest_mode = 0; /* Physical */
1698 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1699 entry.vector = 0;
1700 entry.dest.physical.physical_dest =
1701 GET_APIC_ID(read_apic_id());
1702
1703 /*
1704 * Add it to the IO-APIC irq-routing table:
1705 */
1706 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1707 }
1708 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1709 }
1710
1711 /*
1712 * function to set the IO-APIC physical IDs based on the
1713 * values stored in the MPC table.
1714 *
1715 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1716 */
1717
1718 #ifndef CONFIG_X86_NUMAQ
1719 static void __init setup_ioapic_ids_from_mpc(void)
1720 {
1721 union IO_APIC_reg_00 reg_00;
1722 physid_mask_t phys_id_present_map;
1723 int apic;
1724 int i;
1725 unsigned char old_id;
1726 unsigned long flags;
1727
1728 /*
1729 * Don't check I/O APIC IDs for xAPIC systems. They have
1730 * no meaning without the serial APIC bus.
1731 */
1732 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1733 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1734 return;
1735 /*
1736 * This is broken; anything with a real cpu count has to
1737 * circumvent this idiocy regardless.
1738 */
1739 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1740
1741 /*
1742 * Set the IOAPIC ID to the value stored in the MPC table.
1743 */
1744 for (apic = 0; apic < nr_ioapics; apic++) {
1745
1746 /* Read the register 0 value */
1747 spin_lock_irqsave(&ioapic_lock, flags);
1748 reg_00.raw = io_apic_read(apic, 0);
1749 spin_unlock_irqrestore(&ioapic_lock, flags);
1750
1751 old_id = mp_ioapics[apic].mpc_apicid;
1752
1753 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1754 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1755 apic, mp_ioapics[apic].mpc_apicid);
1756 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1757 reg_00.bits.ID);
1758 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1759 }
1760
1761 /*
1762 * Sanity check, is the ID really free? Every APIC in a
1763 * system must have a unique ID or we get lots of nice
1764 * 'stuck on smp_invalidate_needed IPI wait' messages.
1765 */
1766 if (check_apicid_used(phys_id_present_map,
1767 mp_ioapics[apic].mpc_apicid)) {
1768 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1769 apic, mp_ioapics[apic].mpc_apicid);
1770 for (i = 0; i < get_physical_broadcast(); i++)
1771 if (!physid_isset(i, phys_id_present_map))
1772 break;
1773 if (i >= get_physical_broadcast())
1774 panic("Max APIC ID exceeded!\n");
1775 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1776 i);
1777 physid_set(i, phys_id_present_map);
1778 mp_ioapics[apic].mpc_apicid = i;
1779 } else {
1780 physid_mask_t tmp;
1781 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1782 apic_printk(APIC_VERBOSE, "Setting %d in the "
1783 "phys_id_present_map\n",
1784 mp_ioapics[apic].mpc_apicid);
1785 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1786 }
1787
1788
1789 /*
1790 * We need to adjust the IRQ routing table
1791 * if the ID changed.
1792 */
1793 if (old_id != mp_ioapics[apic].mpc_apicid)
1794 for (i = 0; i < mp_irq_entries; i++)
1795 if (mp_irqs[i].mpc_dstapic == old_id)
1796 mp_irqs[i].mpc_dstapic
1797 = mp_ioapics[apic].mpc_apicid;
1798
1799 /*
1800 * Read the right value from the MPC table and
1801 * write it into the ID register.
1802 */
1803 apic_printk(APIC_VERBOSE, KERN_INFO
1804 "...changing IO-APIC physical APIC ID to %d ...",
1805 mp_ioapics[apic].mpc_apicid);
1806
1807 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1808 spin_lock_irqsave(&ioapic_lock, flags);
1809 io_apic_write(apic, 0, reg_00.raw);
1810 spin_unlock_irqrestore(&ioapic_lock, flags);
1811
1812 /*
1813 * Sanity check
1814 */
1815 spin_lock_irqsave(&ioapic_lock, flags);
1816 reg_00.raw = io_apic_read(apic, 0);
1817 spin_unlock_irqrestore(&ioapic_lock, flags);
1818 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1819 printk("could not set ID!\n");
1820 else
1821 apic_printk(APIC_VERBOSE, " ok.\n");
1822 }
1823 }
1824 #else
1825 static void __init setup_ioapic_ids_from_mpc(void) { }
1826 #endif
1827
1828 int no_timer_check __initdata;
1829
1830 static int __init notimercheck(char *s)
1831 {
1832 no_timer_check = 1;
1833 return 1;
1834 }
1835 __setup("no_timer_check", notimercheck);
1836
1837 /*
1838 * There is a nasty bug in some older SMP boards, their mptable lies
1839 * about the timer IRQ. We do the following to work around the situation:
1840 *
1841 * - timer IRQ defaults to IO-APIC IRQ
1842 * - if this function detects that timer IRQs are defunct, then we fall
1843 * back to ISA timer IRQs
1844 */
1845 static int __init timer_irq_works(void)
1846 {
1847 unsigned long t1 = jiffies;
1848 unsigned long flags;
1849
1850 if (no_timer_check)
1851 return 1;
1852
1853 local_save_flags(flags);
1854 local_irq_enable();
1855 /* Let ten ticks pass... */
1856 mdelay((10 * 1000) / HZ);
1857 local_irq_restore(flags);
1858
1859 /*
1860 * Expect a few ticks at least, to be sure some possible
1861 * glue logic does not lock up after one or two first
1862 * ticks in a non-ExtINT mode. Also the local APIC
1863 * might have cached one ExtINT interrupt. Finally, at
1864 * least one tick may be lost due to delays.
1865 */
1866 if (time_after(jiffies, t1 + 4))
1867 return 1;
1868
1869 return 0;
1870 }
1871
1872 /*
1873 * In the SMP+IOAPIC case it might happen that there are an unspecified
1874 * number of pending IRQ events unhandled. These cases are very rare,
1875 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1876 * better to do it this way as thus we do not have to be aware of
1877 * 'pending' interrupts in the IRQ path, except at this point.
1878 */
1879 /*
1880 * Edge triggered needs to resend any interrupt
1881 * that was delayed but this is now handled in the device
1882 * independent code.
1883 */
1884
1885 /*
1886 * Startup quirk:
1887 *
1888 * Starting up a edge-triggered IO-APIC interrupt is
1889 * nasty - we need to make sure that we get the edge.
1890 * If it is already asserted for some reason, we need
1891 * return 1 to indicate that is was pending.
1892 *
1893 * This is not complete - we should be able to fake
1894 * an edge even if it isn't on the 8259A...
1895 *
1896 * (We do this for level-triggered IRQs too - it cannot hurt.)
1897 */
1898 static unsigned int startup_ioapic_irq(unsigned int irq)
1899 {
1900 int was_pending = 0;
1901 unsigned long flags;
1902
1903 spin_lock_irqsave(&ioapic_lock, flags);
1904 if (irq < 16) {
1905 disable_8259A_irq(irq);
1906 if (i8259A_irq_pending(irq))
1907 was_pending = 1;
1908 }
1909 __unmask_IO_APIC_irq(irq);
1910 spin_unlock_irqrestore(&ioapic_lock, flags);
1911
1912 return was_pending;
1913 }
1914
1915 static void ack_ioapic_irq(unsigned int irq)
1916 {
1917 move_native_irq(irq);
1918 ack_APIC_irq();
1919 }
1920
1921 static void ack_ioapic_quirk_irq(unsigned int irq)
1922 {
1923 unsigned long v;
1924 int i;
1925
1926 move_native_irq(irq);
1927 /*
1928 * It appears there is an erratum which affects at least version 0x11
1929 * of I/O APIC (that's the 82093AA and cores integrated into various
1930 * chipsets). Under certain conditions a level-triggered interrupt is
1931 * erroneously delivered as edge-triggered one but the respective IRR
1932 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1933 * message but it will never arrive and further interrupts are blocked
1934 * from the source. The exact reason is so far unknown, but the
1935 * phenomenon was observed when two consecutive interrupt requests
1936 * from a given source get delivered to the same CPU and the source is
1937 * temporarily disabled in between.
1938 *
1939 * A workaround is to simulate an EOI message manually. We achieve it
1940 * by setting the trigger mode to edge and then to level when the edge
1941 * trigger mode gets detected in the TMR of a local APIC for a
1942 * level-triggered interrupt. We mask the source for the time of the
1943 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1944 * The idea is from Manfred Spraul. --macro
1945 */
1946 i = irq_vector[irq];
1947
1948 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1949
1950 ack_APIC_irq();
1951
1952 if (!(v & (1 << (i & 0x1f)))) {
1953 atomic_inc(&irq_mis_count);
1954 spin_lock(&ioapic_lock);
1955 __mask_and_edge_IO_APIC_irq(irq);
1956 __unmask_and_level_IO_APIC_irq(irq);
1957 spin_unlock(&ioapic_lock);
1958 }
1959 }
1960
1961 static int ioapic_retrigger_irq(unsigned int irq)
1962 {
1963 send_IPI_self(irq_vector[irq]);
1964
1965 return 1;
1966 }
1967
1968 static struct irq_chip ioapic_chip __read_mostly = {
1969 .name = "IO-APIC",
1970 .startup = startup_ioapic_irq,
1971 .mask = mask_IO_APIC_irq,
1972 .unmask = unmask_IO_APIC_irq,
1973 .ack = ack_ioapic_irq,
1974 .eoi = ack_ioapic_quirk_irq,
1975 #ifdef CONFIG_SMP
1976 .set_affinity = set_ioapic_affinity_irq,
1977 #endif
1978 .retrigger = ioapic_retrigger_irq,
1979 };
1980
1981
1982 static inline void init_IO_APIC_traps(void)
1983 {
1984 int irq;
1985
1986 /*
1987 * NOTE! The local APIC isn't very good at handling
1988 * multiple interrupts at the same interrupt level.
1989 * As the interrupt level is determined by taking the
1990 * vector number and shifting that right by 4, we
1991 * want to spread these out a bit so that they don't
1992 * all fall in the same interrupt level.
1993 *
1994 * Also, we've got to be careful not to trash gate
1995 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1996 */
1997 for (irq = 0; irq < NR_IRQS ; irq++) {
1998 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
1999 /*
2000 * Hmm.. We don't have an entry for this,
2001 * so default to an old-fashioned 8259
2002 * interrupt if we can..
2003 */
2004 if (irq < 16)
2005 make_8259A_irq(irq);
2006 else
2007 /* Strange. Oh, well.. */
2008 irq_desc[irq].chip = &no_irq_chip;
2009 }
2010 }
2011 }
2012
2013 /*
2014 * The local APIC irq-chip implementation:
2015 */
2016
2017 static void ack_apic(unsigned int irq)
2018 {
2019 ack_APIC_irq();
2020 }
2021
2022 static void mask_lapic_irq (unsigned int irq)
2023 {
2024 unsigned long v;
2025
2026 v = apic_read(APIC_LVT0);
2027 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2028 }
2029
2030 static void unmask_lapic_irq (unsigned int irq)
2031 {
2032 unsigned long v;
2033
2034 v = apic_read(APIC_LVT0);
2035 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2036 }
2037
2038 static struct irq_chip lapic_chip __read_mostly = {
2039 .name = "local-APIC",
2040 .mask = mask_lapic_irq,
2041 .unmask = unmask_lapic_irq,
2042 .eoi = ack_apic,
2043 };
2044
2045 static void __init setup_nmi(void)
2046 {
2047 /*
2048 * Dirty trick to enable the NMI watchdog ...
2049 * We put the 8259A master into AEOI mode and
2050 * unmask on all local APICs LVT0 as NMI.
2051 *
2052 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2053 * is from Maciej W. Rozycki - so we do not have to EOI from
2054 * the NMI handler or the timer interrupt.
2055 */
2056 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2057
2058 enable_NMI_through_LVT0();
2059
2060 apic_printk(APIC_VERBOSE, " done.\n");
2061 }
2062
2063 /*
2064 * This looks a bit hackish but it's about the only one way of sending
2065 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2066 * not support the ExtINT mode, unfortunately. We need to send these
2067 * cycles as some i82489DX-based boards have glue logic that keeps the
2068 * 8259A interrupt line asserted until INTA. --macro
2069 */
2070 static inline void __init unlock_ExtINT_logic(void)
2071 {
2072 int apic, pin, i;
2073 struct IO_APIC_route_entry entry0, entry1;
2074 unsigned char save_control, save_freq_select;
2075
2076 pin = find_isa_irq_pin(8, mp_INT);
2077 if (pin == -1) {
2078 WARN_ON_ONCE(1);
2079 return;
2080 }
2081 apic = find_isa_irq_apic(8, mp_INT);
2082 if (apic == -1) {
2083 WARN_ON_ONCE(1);
2084 return;
2085 }
2086
2087 entry0 = ioapic_read_entry(apic, pin);
2088 clear_IO_APIC_pin(apic, pin);
2089
2090 memset(&entry1, 0, sizeof(entry1));
2091
2092 entry1.dest_mode = 0; /* physical delivery */
2093 entry1.mask = 0; /* unmask IRQ now */
2094 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2095 entry1.delivery_mode = dest_ExtINT;
2096 entry1.polarity = entry0.polarity;
2097 entry1.trigger = 0;
2098 entry1.vector = 0;
2099
2100 ioapic_write_entry(apic, pin, entry1);
2101
2102 save_control = CMOS_READ(RTC_CONTROL);
2103 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2104 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2105 RTC_FREQ_SELECT);
2106 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2107
2108 i = 100;
2109 while (i-- > 0) {
2110 mdelay(10);
2111 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2112 i -= 10;
2113 }
2114
2115 CMOS_WRITE(save_control, RTC_CONTROL);
2116 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2117 clear_IO_APIC_pin(apic, pin);
2118
2119 ioapic_write_entry(apic, pin, entry0);
2120 }
2121
2122 /*
2123 * This code may look a bit paranoid, but it's supposed to cooperate with
2124 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2125 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2126 * fanatically on his truly buggy board.
2127 */
2128 static inline void __init check_timer(void)
2129 {
2130 int apic1, pin1, apic2, pin2;
2131 int vector;
2132 unsigned int ver;
2133 unsigned long flags;
2134
2135 local_irq_save(flags);
2136
2137 ver = apic_read(APIC_LVR);
2138 ver = GET_APIC_VERSION(ver);
2139
2140 /*
2141 * get/set the timer IRQ vector:
2142 */
2143 disable_8259A_irq(0);
2144 vector = assign_irq_vector(0);
2145 set_intr_gate(vector, interrupt[0]);
2146
2147 /*
2148 * As IRQ0 is to be enabled in the 8259A, the virtual
2149 * wire has to be disabled in the local APIC. Also
2150 * timer interrupts need to be acknowledged manually in
2151 * the 8259A for the i82489DX when using the NMI
2152 * watchdog as that APIC treats NMIs as level-triggered.
2153 * The AEOI mode will finish them in the 8259A
2154 * automatically.
2155 */
2156 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2157 init_8259A(1);
2158 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2159
2160 pin1 = find_isa_irq_pin(0, mp_INT);
2161 apic1 = find_isa_irq_apic(0, mp_INT);
2162 pin2 = ioapic_i8259.pin;
2163 apic2 = ioapic_i8259.apic;
2164
2165 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2166 vector, apic1, pin1, apic2, pin2);
2167
2168 if (pin1 != -1) {
2169 /*
2170 * Ok, does IRQ0 through the IOAPIC work?
2171 */
2172 unmask_IO_APIC_irq(0);
2173 if (timer_irq_works()) {
2174 if (nmi_watchdog == NMI_IO_APIC) {
2175 setup_nmi();
2176 enable_8259A_irq(0);
2177 }
2178 if (disable_timer_pin_1 > 0)
2179 clear_IO_APIC_pin(0, pin1);
2180 goto out;
2181 }
2182 clear_IO_APIC_pin(apic1, pin1);
2183 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2184 "IO-APIC\n");
2185 }
2186
2187 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2188 if (pin2 != -1) {
2189 printk("\n..... (found pin %d) ...", pin2);
2190 /*
2191 * legacy devices should be connected to IO APIC #0
2192 */
2193 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2194 enable_8259A_irq(0);
2195 if (timer_irq_works()) {
2196 printk("works.\n");
2197 timer_through_8259 = 1;
2198 if (pin1 != -1)
2199 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2200 else
2201 add_pin_to_irq(0, apic2, pin2);
2202 if (nmi_watchdog == NMI_IO_APIC) {
2203 disable_8259A_irq(0);
2204 setup_nmi();
2205 enable_8259A_irq(0);
2206 }
2207 goto out;
2208 }
2209 /*
2210 * Cleanup, just in case ...
2211 */
2212 disable_8259A_irq(0);
2213 clear_IO_APIC_pin(apic2, pin2);
2214 }
2215 printk(" failed.\n");
2216
2217 if (nmi_watchdog == NMI_IO_APIC) {
2218 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2219 nmi_watchdog = 0;
2220 }
2221 timer_ack = 0;
2222
2223 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2224
2225 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2226 "fasteoi");
2227 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2228 enable_8259A_irq(0);
2229
2230 if (timer_irq_works()) {
2231 printk(" works.\n");
2232 goto out;
2233 }
2234 disable_8259A_irq(0);
2235 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2236 printk(" failed.\n");
2237
2238 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2239
2240 init_8259A(0);
2241 make_8259A_irq(0);
2242 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2243
2244 unlock_ExtINT_logic();
2245
2246 if (timer_irq_works()) {
2247 printk(" works.\n");
2248 goto out;
2249 }
2250 printk(" failed :(.\n");
2251 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2252 "report. Then try booting with the 'noapic' option");
2253 out:
2254 local_irq_restore(flags);
2255 }
2256
2257 /*
2258 *
2259 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2260 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2261 * Linux doesn't really care, as it's not actually used
2262 * for any interrupt handling anyway.
2263 */
2264 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2265
2266 void __init setup_IO_APIC(void)
2267 {
2268 int i;
2269
2270 /* Reserve all the system vectors. */
2271 for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++)
2272 set_bit(i, used_vectors);
2273
2274 enable_IO_APIC();
2275
2276 if (acpi_ioapic)
2277 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2278 else
2279 io_apic_irqs = ~PIC_IRQS;
2280
2281 printk("ENABLING IO-APIC IRQs\n");
2282
2283 /*
2284 * Set up IO-APIC IRQ routing.
2285 */
2286 if (!acpi_ioapic)
2287 setup_ioapic_ids_from_mpc();
2288 sync_Arb_IDs();
2289 setup_IO_APIC_irqs();
2290 init_IO_APIC_traps();
2291 check_timer();
2292 if (!acpi_ioapic)
2293 print_IO_APIC();
2294 }
2295
2296 /*
2297 * Called after all the initialization is done. If we didnt find any
2298 * APIC bugs then we can allow the modify fast path
2299 */
2300
2301 static int __init io_apic_bug_finalize(void)
2302 {
2303 if(sis_apic_bug == -1)
2304 sis_apic_bug = 0;
2305 return 0;
2306 }
2307
2308 late_initcall(io_apic_bug_finalize);
2309
2310 struct sysfs_ioapic_data {
2311 struct sys_device dev;
2312 struct IO_APIC_route_entry entry[0];
2313 };
2314 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2315
2316 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2317 {
2318 struct IO_APIC_route_entry *entry;
2319 struct sysfs_ioapic_data *data;
2320 int i;
2321
2322 data = container_of(dev, struct sysfs_ioapic_data, dev);
2323 entry = data->entry;
2324 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2325 entry[i] = ioapic_read_entry(dev->id, i);
2326
2327 return 0;
2328 }
2329
2330 static int ioapic_resume(struct sys_device *dev)
2331 {
2332 struct IO_APIC_route_entry *entry;
2333 struct sysfs_ioapic_data *data;
2334 unsigned long flags;
2335 union IO_APIC_reg_00 reg_00;
2336 int i;
2337
2338 data = container_of(dev, struct sysfs_ioapic_data, dev);
2339 entry = data->entry;
2340
2341 spin_lock_irqsave(&ioapic_lock, flags);
2342 reg_00.raw = io_apic_read(dev->id, 0);
2343 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2344 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2345 io_apic_write(dev->id, 0, reg_00.raw);
2346 }
2347 spin_unlock_irqrestore(&ioapic_lock, flags);
2348 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2349 ioapic_write_entry(dev->id, i, entry[i]);
2350
2351 return 0;
2352 }
2353
2354 static struct sysdev_class ioapic_sysdev_class = {
2355 .name = "ioapic",
2356 .suspend = ioapic_suspend,
2357 .resume = ioapic_resume,
2358 };
2359
2360 static int __init ioapic_init_sysfs(void)
2361 {
2362 struct sys_device * dev;
2363 int i, size, error = 0;
2364
2365 error = sysdev_class_register(&ioapic_sysdev_class);
2366 if (error)
2367 return error;
2368
2369 for (i = 0; i < nr_ioapics; i++ ) {
2370 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2371 * sizeof(struct IO_APIC_route_entry);
2372 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2373 if (!mp_ioapic_data[i]) {
2374 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2375 continue;
2376 }
2377 memset(mp_ioapic_data[i], 0, size);
2378 dev = &mp_ioapic_data[i]->dev;
2379 dev->id = i;
2380 dev->cls = &ioapic_sysdev_class;
2381 error = sysdev_register(dev);
2382 if (error) {
2383 kfree(mp_ioapic_data[i]);
2384 mp_ioapic_data[i] = NULL;
2385 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2386 continue;
2387 }
2388 }
2389
2390 return 0;
2391 }
2392
2393 device_initcall(ioapic_init_sysfs);
2394
2395 /*
2396 * Dynamic irq allocate and deallocation
2397 */
2398 int create_irq(void)
2399 {
2400 /* Allocate an unused irq */
2401 int irq, new, vector = 0;
2402 unsigned long flags;
2403
2404 irq = -ENOSPC;
2405 spin_lock_irqsave(&vector_lock, flags);
2406 for (new = (NR_IRQS - 1); new >= 0; new--) {
2407 if (platform_legacy_irq(new))
2408 continue;
2409 if (irq_vector[new] != 0)
2410 continue;
2411 vector = __assign_irq_vector(new);
2412 if (likely(vector > 0))
2413 irq = new;
2414 break;
2415 }
2416 spin_unlock_irqrestore(&vector_lock, flags);
2417
2418 if (irq >= 0) {
2419 set_intr_gate(vector, interrupt[irq]);
2420 dynamic_irq_init(irq);
2421 }
2422 return irq;
2423 }
2424
2425 void destroy_irq(unsigned int irq)
2426 {
2427 unsigned long flags;
2428
2429 dynamic_irq_cleanup(irq);
2430
2431 spin_lock_irqsave(&vector_lock, flags);
2432 clear_bit(irq_vector[irq], used_vectors);
2433 irq_vector[irq] = 0;
2434 spin_unlock_irqrestore(&vector_lock, flags);
2435 }
2436
2437 /*
2438 * MSI message composition
2439 */
2440 #ifdef CONFIG_PCI_MSI
2441 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2442 {
2443 int vector;
2444 unsigned dest;
2445
2446 vector = assign_irq_vector(irq);
2447 if (vector >= 0) {
2448 dest = cpu_mask_to_apicid(TARGET_CPUS);
2449
2450 msg->address_hi = MSI_ADDR_BASE_HI;
2451 msg->address_lo =
2452 MSI_ADDR_BASE_LO |
2453 ((INT_DEST_MODE == 0) ?
2454 MSI_ADDR_DEST_MODE_PHYSICAL:
2455 MSI_ADDR_DEST_MODE_LOGICAL) |
2456 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2457 MSI_ADDR_REDIRECTION_CPU:
2458 MSI_ADDR_REDIRECTION_LOWPRI) |
2459 MSI_ADDR_DEST_ID(dest);
2460
2461 msg->data =
2462 MSI_DATA_TRIGGER_EDGE |
2463 MSI_DATA_LEVEL_ASSERT |
2464 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2465 MSI_DATA_DELIVERY_FIXED:
2466 MSI_DATA_DELIVERY_LOWPRI) |
2467 MSI_DATA_VECTOR(vector);
2468 }
2469 return vector;
2470 }
2471
2472 #ifdef CONFIG_SMP
2473 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2474 {
2475 struct msi_msg msg;
2476 unsigned int dest;
2477 cpumask_t tmp;
2478 int vector;
2479
2480 cpus_and(tmp, mask, cpu_online_map);
2481 if (cpus_empty(tmp))
2482 tmp = TARGET_CPUS;
2483
2484 vector = assign_irq_vector(irq);
2485 if (vector < 0)
2486 return;
2487
2488 dest = cpu_mask_to_apicid(mask);
2489
2490 read_msi_msg(irq, &msg);
2491
2492 msg.data &= ~MSI_DATA_VECTOR_MASK;
2493 msg.data |= MSI_DATA_VECTOR(vector);
2494 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2495 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2496
2497 write_msi_msg(irq, &msg);
2498 irq_desc[irq].affinity = mask;
2499 }
2500 #endif /* CONFIG_SMP */
2501
2502 /*
2503 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2504 * which implement the MSI or MSI-X Capability Structure.
2505 */
2506 static struct irq_chip msi_chip = {
2507 .name = "PCI-MSI",
2508 .unmask = unmask_msi_irq,
2509 .mask = mask_msi_irq,
2510 .ack = ack_ioapic_irq,
2511 #ifdef CONFIG_SMP
2512 .set_affinity = set_msi_irq_affinity,
2513 #endif
2514 .retrigger = ioapic_retrigger_irq,
2515 };
2516
2517 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2518 {
2519 struct msi_msg msg;
2520 int irq, ret;
2521 irq = create_irq();
2522 if (irq < 0)
2523 return irq;
2524
2525 ret = msi_compose_msg(dev, irq, &msg);
2526 if (ret < 0) {
2527 destroy_irq(irq);
2528 return ret;
2529 }
2530
2531 set_irq_msi(irq, desc);
2532 write_msi_msg(irq, &msg);
2533
2534 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2535 "edge");
2536
2537 return 0;
2538 }
2539
2540 void arch_teardown_msi_irq(unsigned int irq)
2541 {
2542 destroy_irq(irq);
2543 }
2544
2545 #endif /* CONFIG_PCI_MSI */
2546
2547 /*
2548 * Hypertransport interrupt support
2549 */
2550 #ifdef CONFIG_HT_IRQ
2551
2552 #ifdef CONFIG_SMP
2553
2554 static void target_ht_irq(unsigned int irq, unsigned int dest)
2555 {
2556 struct ht_irq_msg msg;
2557 fetch_ht_irq_msg(irq, &msg);
2558
2559 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2560 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2561
2562 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2563 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2564
2565 write_ht_irq_msg(irq, &msg);
2566 }
2567
2568 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2569 {
2570 unsigned int dest;
2571 cpumask_t tmp;
2572
2573 cpus_and(tmp, mask, cpu_online_map);
2574 if (cpus_empty(tmp))
2575 tmp = TARGET_CPUS;
2576
2577 cpus_and(mask, tmp, CPU_MASK_ALL);
2578
2579 dest = cpu_mask_to_apicid(mask);
2580
2581 target_ht_irq(irq, dest);
2582 irq_desc[irq].affinity = mask;
2583 }
2584 #endif
2585
2586 static struct irq_chip ht_irq_chip = {
2587 .name = "PCI-HT",
2588 .mask = mask_ht_irq,
2589 .unmask = unmask_ht_irq,
2590 .ack = ack_ioapic_irq,
2591 #ifdef CONFIG_SMP
2592 .set_affinity = set_ht_irq_affinity,
2593 #endif
2594 .retrigger = ioapic_retrigger_irq,
2595 };
2596
2597 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2598 {
2599 int vector;
2600
2601 vector = assign_irq_vector(irq);
2602 if (vector >= 0) {
2603 struct ht_irq_msg msg;
2604 unsigned dest;
2605 cpumask_t tmp;
2606
2607 cpus_clear(tmp);
2608 cpu_set(vector >> 8, tmp);
2609 dest = cpu_mask_to_apicid(tmp);
2610
2611 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2612
2613 msg.address_lo =
2614 HT_IRQ_LOW_BASE |
2615 HT_IRQ_LOW_DEST_ID(dest) |
2616 HT_IRQ_LOW_VECTOR(vector) |
2617 ((INT_DEST_MODE == 0) ?
2618 HT_IRQ_LOW_DM_PHYSICAL :
2619 HT_IRQ_LOW_DM_LOGICAL) |
2620 HT_IRQ_LOW_RQEOI_EDGE |
2621 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2622 HT_IRQ_LOW_MT_FIXED :
2623 HT_IRQ_LOW_MT_ARBITRATED) |
2624 HT_IRQ_LOW_IRQ_MASKED;
2625
2626 write_ht_irq_msg(irq, &msg);
2627
2628 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2629 handle_edge_irq, "edge");
2630 }
2631 return vector;
2632 }
2633 #endif /* CONFIG_HT_IRQ */
2634
2635 /* --------------------------------------------------------------------------
2636 ACPI-based IOAPIC Configuration
2637 -------------------------------------------------------------------------- */
2638
2639 #ifdef CONFIG_ACPI
2640
2641 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2642 {
2643 union IO_APIC_reg_00 reg_00;
2644 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2645 physid_mask_t tmp;
2646 unsigned long flags;
2647 int i = 0;
2648
2649 /*
2650 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2651 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2652 * supports up to 16 on one shared APIC bus.
2653 *
2654 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2655 * advantage of new APIC bus architecture.
2656 */
2657
2658 if (physids_empty(apic_id_map))
2659 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2660
2661 spin_lock_irqsave(&ioapic_lock, flags);
2662 reg_00.raw = io_apic_read(ioapic, 0);
2663 spin_unlock_irqrestore(&ioapic_lock, flags);
2664
2665 if (apic_id >= get_physical_broadcast()) {
2666 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2667 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2668 apic_id = reg_00.bits.ID;
2669 }
2670
2671 /*
2672 * Every APIC in a system must have a unique ID or we get lots of nice
2673 * 'stuck on smp_invalidate_needed IPI wait' messages.
2674 */
2675 if (check_apicid_used(apic_id_map, apic_id)) {
2676
2677 for (i = 0; i < get_physical_broadcast(); i++) {
2678 if (!check_apicid_used(apic_id_map, i))
2679 break;
2680 }
2681
2682 if (i == get_physical_broadcast())
2683 panic("Max apic_id exceeded!\n");
2684
2685 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2686 "trying %d\n", ioapic, apic_id, i);
2687
2688 apic_id = i;
2689 }
2690
2691 tmp = apicid_to_cpu_present(apic_id);
2692 physids_or(apic_id_map, apic_id_map, tmp);
2693
2694 if (reg_00.bits.ID != apic_id) {
2695 reg_00.bits.ID = apic_id;
2696
2697 spin_lock_irqsave(&ioapic_lock, flags);
2698 io_apic_write(ioapic, 0, reg_00.raw);
2699 reg_00.raw = io_apic_read(ioapic, 0);
2700 spin_unlock_irqrestore(&ioapic_lock, flags);
2701
2702 /* Sanity check */
2703 if (reg_00.bits.ID != apic_id) {
2704 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2705 return -1;
2706 }
2707 }
2708
2709 apic_printk(APIC_VERBOSE, KERN_INFO
2710 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2711
2712 return apic_id;
2713 }
2714
2715
2716 int __init io_apic_get_version (int ioapic)
2717 {
2718 union IO_APIC_reg_01 reg_01;
2719 unsigned long flags;
2720
2721 spin_lock_irqsave(&ioapic_lock, flags);
2722 reg_01.raw = io_apic_read(ioapic, 1);
2723 spin_unlock_irqrestore(&ioapic_lock, flags);
2724
2725 return reg_01.bits.version;
2726 }
2727
2728
2729 int __init io_apic_get_redir_entries (int ioapic)
2730 {
2731 union IO_APIC_reg_01 reg_01;
2732 unsigned long flags;
2733
2734 spin_lock_irqsave(&ioapic_lock, flags);
2735 reg_01.raw = io_apic_read(ioapic, 1);
2736 spin_unlock_irqrestore(&ioapic_lock, flags);
2737
2738 return reg_01.bits.entries;
2739 }
2740
2741
2742 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2743 {
2744 struct IO_APIC_route_entry entry;
2745
2746 if (!IO_APIC_IRQ(irq)) {
2747 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2748 ioapic);
2749 return -EINVAL;
2750 }
2751
2752 /*
2753 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2754 * Note that we mask (disable) IRQs now -- these get enabled when the
2755 * corresponding device driver registers for this IRQ.
2756 */
2757
2758 memset(&entry,0,sizeof(entry));
2759
2760 entry.delivery_mode = INT_DELIVERY_MODE;
2761 entry.dest_mode = INT_DEST_MODE;
2762 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2763 entry.trigger = edge_level;
2764 entry.polarity = active_high_low;
2765 entry.mask = 1;
2766
2767 /*
2768 * IRQs < 16 are already in the irq_2_pin[] map
2769 */
2770 if (irq >= 16)
2771 add_pin_to_irq(irq, ioapic, pin);
2772
2773 entry.vector = assign_irq_vector(irq);
2774
2775 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2776 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2777 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2778 edge_level, active_high_low);
2779
2780 ioapic_register_intr(irq, entry.vector, edge_level);
2781
2782 if (!ioapic && (irq < 16))
2783 disable_8259A_irq(irq);
2784
2785 ioapic_write_entry(ioapic, pin, entry);
2786
2787 return 0;
2788 }
2789
2790 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2791 {
2792 int i;
2793
2794 if (skip_ioapic_setup)
2795 return -1;
2796
2797 for (i = 0; i < mp_irq_entries; i++)
2798 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2799 mp_irqs[i].mpc_srcbusirq == bus_irq)
2800 break;
2801 if (i >= mp_irq_entries)
2802 return -1;
2803
2804 *trigger = irq_trigger(i);
2805 *polarity = irq_polarity(i);
2806 return 0;
2807 }
2808
2809 #endif /* CONFIG_ACPI */
2810
2811 static int __init parse_disable_timer_pin_1(char *arg)
2812 {
2813 disable_timer_pin_1 = 1;
2814 return 0;
2815 }
2816 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2817
2818 static int __init parse_enable_timer_pin_1(char *arg)
2819 {
2820 disable_timer_pin_1 = -1;
2821 return 0;
2822 }
2823 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2824
2825 static int __init parse_noapic(char *arg)
2826 {
2827 /* disable IO-APIC */
2828 disable_ioapic_setup();
2829 return 0;
2830 }
2831 early_param("noapic", parse_noapic);
Linux kernel - Deliverables
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