2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
54 #define __apicdebuginit(type) static type __init
56 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
57 atomic_t irq_mis_count
;
59 /* Where if anywhere is the i8259 connect in external int mode */
60 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
62 static DEFINE_SPINLOCK(ioapic_lock
);
63 DEFINE_SPINLOCK(vector_lock
);
65 int timer_through_8259 __initdata
;
68 * Is the SiS APIC rmw bug present ?
69 * -1 = don't know, 0 = no, 1 = yes
71 int sis_apic_bug
= -1;
73 int first_free_entry
= NR_IRQS
;
75 * # of IRQ routing registers
77 int nr_ioapic_registers
[MAX_IO_APICS
];
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
86 /* # of MP IRQ source entries */
89 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
90 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
93 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
95 static int disable_timer_pin_1 __initdata
;
98 * Rough estimation of how many shared IRQs there are, can
101 #define MAX_PLUS_SHARED_IRQS NR_IRQS
102 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
104 int pin_map_size
= PIN_MAP_SIZE
;
107 * This is performance-critical, we want to do it O(1)
109 * the indexing order of this array favors 1:1 mappings
110 * between pins and IRQs.
113 static struct irq_pin_list
{
115 } irq_2_pin
[PIN_MAP_SIZE
];
119 unsigned int unused
[3];
123 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
125 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
126 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
129 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
131 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
132 writel(reg
, &io_apic
->index
);
133 return readl(&io_apic
->data
);
136 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
138 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
139 writel(reg
, &io_apic
->index
);
140 writel(value
, &io_apic
->data
);
144 * Re-write a value: to be used for read-modify-write
145 * cycles where the read already set up the index register.
147 * Older SiS APIC requires we rewrite the index register
149 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
151 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
153 writel(reg
, &io_apic
->index
);
154 writel(value
, &io_apic
->data
);
158 struct { u32 w1
, w2
; };
159 struct IO_APIC_route_entry entry
;
162 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
164 union entry_union eu
;
166 spin_lock_irqsave(&ioapic_lock
, flags
);
167 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
168 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
169 spin_unlock_irqrestore(&ioapic_lock
, flags
);
174 * When we write a new IO APIC routing entry, we need to write the high
175 * word first! If the mask bit in the low word is clear, we will enable
176 * the interrupt, and we need to make sure the entry is fully populated
177 * before that happens.
180 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
182 union entry_union eu
;
184 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
185 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
188 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
191 spin_lock_irqsave(&ioapic_lock
, flags
);
192 __ioapic_write_entry(apic
, pin
, e
);
193 spin_unlock_irqrestore(&ioapic_lock
, flags
);
197 * When we mask an IO APIC routing entry, we need to write the low
198 * word first, in order to set the mask bit before we change the
201 static void ioapic_mask_entry(int apic
, int pin
)
204 union entry_union eu
= { .entry
.mask
= 1 };
206 spin_lock_irqsave(&ioapic_lock
, flags
);
207 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
208 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
209 spin_unlock_irqrestore(&ioapic_lock
, flags
);
213 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
214 * shared ISA-space IRQs, so we have to support them. We are super
215 * fast in the common case, and fast for shared ISA-space IRQs.
217 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
219 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
222 entry
= irq_2_pin
+ entry
->next
;
224 if (entry
->pin
!= -1) {
225 entry
->next
= first_free_entry
;
226 entry
= irq_2_pin
+ entry
->next
;
227 if (++first_free_entry
>= pin_map_size
)
228 panic("io_apic.c: whoops");
235 * Reroute an IRQ to a different pin.
237 static void __init
replace_pin_at_irq(unsigned int irq
,
238 int oldapic
, int oldpin
,
239 int newapic
, int newpin
)
241 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
244 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
245 entry
->apic
= newapic
;
250 entry
= irq_2_pin
+ entry
->next
;
254 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
256 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
257 unsigned int pin
, reg
;
263 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
266 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
269 entry
= irq_2_pin
+ entry
->next
;
274 static void __mask_IO_APIC_irq(unsigned int irq
)
276 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
280 static void __unmask_IO_APIC_irq(unsigned int irq
)
282 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
285 /* mask = 1, trigger = 0 */
286 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
288 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
289 IO_APIC_REDIR_LEVEL_TRIGGER
);
292 /* mask = 0, trigger = 1 */
293 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
295 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
296 IO_APIC_REDIR_MASKED
);
299 static void mask_IO_APIC_irq(unsigned int irq
)
303 spin_lock_irqsave(&ioapic_lock
, flags
);
304 __mask_IO_APIC_irq(irq
);
305 spin_unlock_irqrestore(&ioapic_lock
, flags
);
308 static void unmask_IO_APIC_irq(unsigned int irq
)
312 spin_lock_irqsave(&ioapic_lock
, flags
);
313 __unmask_IO_APIC_irq(irq
);
314 spin_unlock_irqrestore(&ioapic_lock
, flags
);
317 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
319 struct IO_APIC_route_entry entry
;
321 /* Check delivery_mode to be sure we're not clearing an SMI pin */
322 entry
= ioapic_read_entry(apic
, pin
);
323 if (entry
.delivery_mode
== dest_SMI
)
327 * Disable it in the IO-APIC irq-routing table:
329 ioapic_mask_entry(apic
, pin
);
332 static void clear_IO_APIC(void)
336 for (apic
= 0; apic
< nr_ioapics
; apic
++)
337 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
338 clear_IO_APIC_pin(apic
, pin
);
342 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
346 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
347 unsigned int apicid_value
;
350 cpus_and(tmp
, cpumask
, cpu_online_map
);
354 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
356 apicid_value
= cpu_mask_to_apicid(cpumask
);
357 /* Prepare to do the io_apic_write */
358 apicid_value
= apicid_value
<< 24;
359 spin_lock_irqsave(&ioapic_lock
, flags
);
364 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
367 entry
= irq_2_pin
+ entry
->next
;
369 irq_desc
[irq
].affinity
= cpumask
;
370 spin_unlock_irqrestore(&ioapic_lock
, flags
);
373 #if defined(CONFIG_IRQBALANCE)
374 # include <asm/processor.h> /* kernel_thread() */
375 # include <linux/kernel_stat.h> /* kstat */
376 # include <linux/slab.h> /* kmalloc() */
377 # include <linux/timer.h>
379 #define IRQBALANCE_CHECK_ARCH -999
380 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
381 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
382 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
383 #define BALANCED_IRQ_LESS_DELTA (HZ)
385 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
386 static int physical_balance __read_mostly
;
387 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
389 static struct irq_cpu_info
{
390 unsigned long *last_irq
;
391 unsigned long *irq_delta
;
393 } irq_cpu_data
[NR_CPUS
];
395 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
396 #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
397 #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
399 #define IDLE_ENOUGH(cpu,now) \
400 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
402 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
404 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
406 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
407 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
410 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
412 balance_irq_affinity
[irq
] = mask
;
415 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
416 unsigned long now
, int direction
)
424 if (unlikely(cpu
== curr_cpu
))
427 if (direction
== 1) {
436 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
, allowed_mask
) ||
437 (search_idle
&& !IDLE_ENOUGH(cpu
, now
)));
442 static inline void balance_irq(int cpu
, int irq
)
444 unsigned long now
= jiffies
;
445 cpumask_t allowed_mask
;
446 unsigned int new_cpu
;
448 if (irqbalance_disabled
)
451 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
452 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
454 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
457 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
461 for_each_online_cpu(i
) {
462 for (j
= 0; j
< nr_irqs
; j
++) {
463 if (!irq_desc
[j
].action
)
465 /* Is it a significant load ? */
466 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
), j
) <
467 useful_load_threshold
)
472 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
473 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
477 static void do_irq_balance(void)
480 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
481 unsigned long move_this_load
= 0;
482 int max_loaded
= 0, min_loaded
= 0;
484 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
486 int tmp_loaded
, first_attempt
= 1;
487 unsigned long tmp_cpu_irq
;
488 unsigned long imbalance
= 0;
489 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
491 for_each_possible_cpu(i
) {
496 package_index
= CPU_TO_PACKAGEINDEX(i
);
497 for (j
= 0; j
< nr_irqs
; j
++) {
498 unsigned long value_now
, delta
;
499 /* Is this an active IRQ or balancing disabled ? */
500 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
502 if (package_index
== i
)
503 IRQ_DELTA(package_index
, j
) = 0;
504 /* Determine the total count per processor per IRQ */
505 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
507 /* Determine the activity per processor per IRQ */
508 delta
= value_now
- LAST_CPU_IRQ(i
, j
);
510 /* Update last_cpu_irq[][] for the next time */
511 LAST_CPU_IRQ(i
, j
) = value_now
;
513 /* Ignore IRQs whose rate is less than the clock */
514 if (delta
< useful_load_threshold
)
516 /* update the load for the processor or package total */
517 IRQ_DELTA(package_index
, j
) += delta
;
519 /* Keep track of the higher numbered sibling as well */
520 if (i
!= package_index
)
523 * We have sibling A and sibling B in the package
525 * cpu_irq[A] = load for cpu A + load for cpu B
526 * cpu_irq[B] = load for cpu B
528 CPU_IRQ(package_index
) += delta
;
531 /* Find the least loaded processor package */
532 for_each_online_cpu(i
) {
533 if (i
!= CPU_TO_PACKAGEINDEX(i
))
535 if (min_cpu_irq
> CPU_IRQ(i
)) {
536 min_cpu_irq
= CPU_IRQ(i
);
540 max_cpu_irq
= ULONG_MAX
;
544 * Look for heaviest loaded processor.
545 * We may come back to get the next heaviest loaded processor.
546 * Skip processors with trivial loads.
550 for_each_online_cpu(i
) {
551 if (i
!= CPU_TO_PACKAGEINDEX(i
))
553 if (max_cpu_irq
<= CPU_IRQ(i
))
555 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
556 tmp_cpu_irq
= CPU_IRQ(i
);
561 if (tmp_loaded
== -1) {
563 * In the case of small number of heavy interrupt sources,
564 * loading some of the cpus too much. We use Ingo's original
565 * approach to rotate them around.
567 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
568 rotate_irqs_among_cpus(useful_load_threshold
);
571 goto not_worth_the_effort
;
574 first_attempt
= 0; /* heaviest search */
575 max_cpu_irq
= tmp_cpu_irq
; /* load */
576 max_loaded
= tmp_loaded
; /* processor */
577 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
580 * if imbalance is less than approx 10% of max load, then
581 * observe diminishing returns action. - quit
583 if (imbalance
< (max_cpu_irq
>> 3))
584 goto not_worth_the_effort
;
587 /* if we select an IRQ to move that can't go where we want, then
588 * see if there is another one to try.
592 for (j
= 0; j
< nr_irqs
; j
++) {
593 /* Is this an active IRQ? */
594 if (!irq_desc
[j
].action
)
596 if (imbalance
<= IRQ_DELTA(max_loaded
, j
))
598 /* Try to find the IRQ that is closest to the imbalance
599 * without going over.
601 if (move_this_load
< IRQ_DELTA(max_loaded
, j
)) {
602 move_this_load
= IRQ_DELTA(max_loaded
, j
);
606 if (selected_irq
== -1)
609 imbalance
= move_this_load
;
611 /* For physical_balance case, we accumulated both load
612 * values in the one of the siblings cpu_irq[],
613 * to use the same code for physical and logical processors
614 * as much as possible.
616 * NOTE: the cpu_irq[] array holds the sum of the load for
617 * sibling A and sibling B in the slot for the lowest numbered
618 * sibling (A), _AND_ the load for sibling B in the slot for
619 * the higher numbered sibling.
621 * We seek the least loaded sibling by making the comparison
624 load
= CPU_IRQ(min_loaded
) >> 1;
625 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
626 if (load
> CPU_IRQ(j
)) {
627 /* This won't change cpu_sibling_map[min_loaded] */
633 cpus_and(allowed_mask
,
635 balance_irq_affinity
[selected_irq
]);
636 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
637 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
639 if (!cpus_empty(tmp
)) {
640 /* mark for change destination */
641 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
643 /* Since we made a change, come back sooner to
644 * check for more variation.
646 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
647 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
652 not_worth_the_effort
:
654 * if we did not find an IRQ to move, then adjust the time interval
657 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
658 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
662 static int balanced_irq(void *unused
)
665 unsigned long prev_balance_time
= jiffies
;
666 long time_remaining
= balanced_irq_interval
;
668 /* push everything to CPU 0 to give us a starting point. */
669 for (i
= 0 ; i
< nr_irqs
; i
++) {
670 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
671 set_pending_irq(i
, cpumask_of_cpu(0));
676 time_remaining
= schedule_timeout_interruptible(time_remaining
);
678 if (time_after(jiffies
,
679 prev_balance_time
+balanced_irq_interval
)) {
682 prev_balance_time
= jiffies
;
683 time_remaining
= balanced_irq_interval
;
690 static int __init
balanced_irq_init(void)
693 struct cpuinfo_x86
*c
;
696 cpus_shift_right(tmp
, cpu_online_map
, 2);
698 /* When not overwritten by the command line ask subarchitecture. */
699 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
700 irqbalance_disabled
= NO_BALANCE_IRQ
;
701 if (irqbalance_disabled
)
704 /* disable irqbalance completely if there is only one processor online */
705 if (num_online_cpus() < 2) {
706 irqbalance_disabled
= 1;
710 * Enable physical balance only if more than 1 physical processor
713 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
714 physical_balance
= 1;
716 for_each_online_cpu(i
) {
717 irq_cpu_data
[i
].irq_delta
= kzalloc(sizeof(unsigned long) * nr_irqs
, GFP_KERNEL
);
718 irq_cpu_data
[i
].last_irq
= kzalloc(sizeof(unsigned long) * nr_irqs
, GFP_KERNEL
);
719 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
720 printk(KERN_ERR
"balanced_irq_init: out of memory");
725 printk(KERN_INFO
"Starting balanced_irq\n");
726 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
728 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
730 for_each_possible_cpu(i
) {
731 kfree(irq_cpu_data
[i
].irq_delta
);
732 irq_cpu_data
[i
].irq_delta
= NULL
;
733 kfree(irq_cpu_data
[i
].last_irq
);
734 irq_cpu_data
[i
].last_irq
= NULL
;
739 int __devinit
irqbalance_disable(char *str
)
741 irqbalance_disabled
= 1;
745 __setup("noirqbalance", irqbalance_disable
);
747 late_initcall(balanced_irq_init
);
748 #endif /* CONFIG_IRQBALANCE */
749 #endif /* CONFIG_SMP */
752 void send_IPI_self(int vector
)
759 apic_wait_icr_idle();
760 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
762 * Send the IPI. The write to APIC_ICR fires this off.
764 apic_write(APIC_ICR
, cfg
);
766 #endif /* !CONFIG_SMP */
770 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
771 * specific CPU-side IRQs.
775 static int pirq_entries
[MAX_PIRQS
];
776 static int pirqs_enabled
;
777 int skip_ioapic_setup
;
779 static int __init
ioapic_pirq_setup(char *str
)
782 int ints
[MAX_PIRQS
+1];
784 get_options(str
, ARRAY_SIZE(ints
), ints
);
786 for (i
= 0; i
< MAX_PIRQS
; i
++)
787 pirq_entries
[i
] = -1;
790 apic_printk(APIC_VERBOSE
, KERN_INFO
791 "PIRQ redirection, working around broken MP-BIOS.\n");
793 if (ints
[0] < MAX_PIRQS
)
796 for (i
= 0; i
< max
; i
++) {
797 apic_printk(APIC_VERBOSE
, KERN_DEBUG
798 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
800 * PIRQs are mapped upside down, usually.
802 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
807 __setup("pirq=", ioapic_pirq_setup
);
810 * Find the IRQ entry number of a certain pin.
812 static int find_irq_entry(int apic
, int pin
, int type
)
816 for (i
= 0; i
< mp_irq_entries
; i
++)
817 if (mp_irqs
[i
].mp_irqtype
== type
&&
818 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
819 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
820 mp_irqs
[i
].mp_dstirq
== pin
)
827 * Find the pin to which IRQ[irq] (ISA) is connected
829 static int __init
find_isa_irq_pin(int irq
, int type
)
833 for (i
= 0; i
< mp_irq_entries
; i
++) {
834 int lbus
= mp_irqs
[i
].mp_srcbus
;
836 if (test_bit(lbus
, mp_bus_not_pci
) &&
837 (mp_irqs
[i
].mp_irqtype
== type
) &&
838 (mp_irqs
[i
].mp_srcbusirq
== irq
))
840 return mp_irqs
[i
].mp_dstirq
;
845 static int __init
find_isa_irq_apic(int irq
, int type
)
849 for (i
= 0; i
< mp_irq_entries
; i
++) {
850 int lbus
= mp_irqs
[i
].mp_srcbus
;
852 if (test_bit(lbus
, mp_bus_not_pci
) &&
853 (mp_irqs
[i
].mp_irqtype
== type
) &&
854 (mp_irqs
[i
].mp_srcbusirq
== irq
))
857 if (i
< mp_irq_entries
) {
859 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
860 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
869 * Find a specific PCI IRQ entry.
870 * Not an __init, possibly needed by modules
872 static int pin_2_irq(int idx
, int apic
, int pin
);
874 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
876 int apic
, i
, best_guess
= -1;
878 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
879 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
880 if (test_bit(bus
, mp_bus_not_pci
)) {
881 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
884 for (i
= 0; i
< mp_irq_entries
; i
++) {
885 int lbus
= mp_irqs
[i
].mp_srcbus
;
887 for (apic
= 0; apic
< nr_ioapics
; apic
++)
888 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
889 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
892 if (!test_bit(lbus
, mp_bus_not_pci
) &&
893 !mp_irqs
[i
].mp_irqtype
&&
895 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
896 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
898 if (!(apic
|| IO_APIC_IRQ(irq
)))
901 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
904 * Use the first all-but-pin matching entry as a
905 * best-guess fuzzy result for broken mptables.
913 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
916 * This function currently is only a helper for the i386 smp boot process where
917 * we need to reprogram the ioredtbls to cater for the cpus which have come online
918 * so mask in all cases should simply be TARGET_CPUS
921 void __init
setup_ioapic_dest(void)
923 int pin
, ioapic
, irq
, irq_entry
;
925 if (skip_ioapic_setup
== 1)
928 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
929 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
930 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
933 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
934 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
941 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
943 * EISA Edge/Level control register, ELCR
945 static int EISA_ELCR(unsigned int irq
)
948 unsigned int port
= 0x4d0 + (irq
>> 3);
949 return (inb(port
) >> (irq
& 7)) & 1;
951 apic_printk(APIC_VERBOSE
, KERN_INFO
952 "Broken MPtable reports ISA irq %d\n", irq
);
957 /* ISA interrupts are always polarity zero edge triggered,
958 * when listed as conforming in the MP table. */
960 #define default_ISA_trigger(idx) (0)
961 #define default_ISA_polarity(idx) (0)
963 /* EISA interrupts are always polarity zero and can be edge or level
964 * trigger depending on the ELCR value. If an interrupt is listed as
965 * EISA conforming in the MP table, that means its trigger type must
966 * be read in from the ELCR */
968 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
969 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
971 /* PCI interrupts are always polarity one level triggered,
972 * when listed as conforming in the MP table. */
974 #define default_PCI_trigger(idx) (1)
975 #define default_PCI_polarity(idx) (1)
977 /* MCA interrupts are always polarity zero level triggered,
978 * when listed as conforming in the MP table. */
980 #define default_MCA_trigger(idx) (1)
981 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
983 static int MPBIOS_polarity(int idx
)
985 int bus
= mp_irqs
[idx
].mp_srcbus
;
989 * Determine IRQ line polarity (high active or low active):
991 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
992 case 0: /* conforms, ie. bus-type dependent polarity */
994 polarity
= test_bit(bus
, mp_bus_not_pci
)?
995 default_ISA_polarity(idx
):
996 default_PCI_polarity(idx
);
999 case 1: /* high active */
1004 case 2: /* reserved */
1006 printk(KERN_WARNING
"broken BIOS!!\n");
1010 case 3: /* low active */
1015 default: /* invalid */
1017 printk(KERN_WARNING
"broken BIOS!!\n");
1025 static int MPBIOS_trigger(int idx
)
1027 int bus
= mp_irqs
[idx
].mp_srcbus
;
1031 * Determine IRQ trigger mode (edge or level sensitive):
1033 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
1034 case 0: /* conforms, ie. bus-type dependent */
1036 trigger
= test_bit(bus
, mp_bus_not_pci
)?
1037 default_ISA_trigger(idx
):
1038 default_PCI_trigger(idx
);
1039 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1040 switch (mp_bus_id_to_type
[bus
]) {
1041 case MP_BUS_ISA
: /* ISA pin */
1043 /* set before the switch */
1046 case MP_BUS_EISA
: /* EISA pin */
1048 trigger
= default_EISA_trigger(idx
);
1051 case MP_BUS_PCI
: /* PCI pin */
1053 /* set before the switch */
1056 case MP_BUS_MCA
: /* MCA pin */
1058 trigger
= default_MCA_trigger(idx
);
1063 printk(KERN_WARNING
"broken BIOS!!\n");
1076 case 2: /* reserved */
1078 printk(KERN_WARNING
"broken BIOS!!\n");
1087 default: /* invalid */
1089 printk(KERN_WARNING
"broken BIOS!!\n");
1097 static inline int irq_polarity(int idx
)
1099 return MPBIOS_polarity(idx
);
1102 static inline int irq_trigger(int idx
)
1104 return MPBIOS_trigger(idx
);
1107 static int pin_2_irq(int idx
, int apic
, int pin
)
1110 int bus
= mp_irqs
[idx
].mp_srcbus
;
1113 * Debugging check, we are in big trouble if this message pops up!
1115 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1116 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1118 if (test_bit(bus
, mp_bus_not_pci
))
1119 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1122 * PCI IRQs are mapped in order
1126 irq
+= nr_ioapic_registers
[i
++];
1130 * For MPS mode, so far only needed by ES7000 platform
1132 if (ioapic_renumber_irq
)
1133 irq
= ioapic_renumber_irq(apic
, irq
);
1137 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1139 if ((pin
>= 16) && (pin
<= 23)) {
1140 if (pirq_entries
[pin
-16] != -1) {
1141 if (!pirq_entries
[pin
-16]) {
1142 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1143 "disabling PIRQ%d\n", pin
-16);
1145 irq
= pirq_entries
[pin
-16];
1146 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1147 "using PIRQ%d -> IRQ %d\n",
1155 static inline int IO_APIC_irq_trigger(int irq
)
1159 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1160 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1161 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1162 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1163 return irq_trigger(idx
);
1167 * nonexistent IRQs are edge default
1172 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1173 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1175 static int __assign_irq_vector(int irq
)
1177 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
;
1180 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1182 if (irq_vector
[irq
] > 0)
1183 return irq_vector
[irq
];
1185 vector
= current_vector
;
1186 offset
= current_offset
;
1189 if (vector
>= first_system_vector
) {
1190 offset
= (offset
+ 1) % 8;
1191 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1193 if (vector
== current_vector
)
1195 if (test_and_set_bit(vector
, used_vectors
))
1198 current_vector
= vector
;
1199 current_offset
= offset
;
1200 irq_vector
[irq
] = vector
;
1205 static int assign_irq_vector(int irq
)
1207 unsigned long flags
;
1210 spin_lock_irqsave(&vector_lock
, flags
);
1211 vector
= __assign_irq_vector(irq
);
1212 spin_unlock_irqrestore(&vector_lock
, flags
);
1217 static struct irq_chip ioapic_chip
;
1219 #define IOAPIC_AUTO -1
1220 #define IOAPIC_EDGE 0
1221 #define IOAPIC_LEVEL 1
1223 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1225 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1226 trigger
== IOAPIC_LEVEL
) {
1227 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1228 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1229 handle_fasteoi_irq
, "fasteoi");
1231 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1232 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1233 handle_edge_irq
, "edge");
1235 set_intr_gate(vector
, interrupt
[irq
]);
1238 static void __init
setup_IO_APIC_irqs(void)
1240 struct IO_APIC_route_entry entry
;
1241 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1243 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1245 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1246 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1249 * add it to the IO-APIC irq-routing table:
1251 memset(&entry
, 0, sizeof(entry
));
1253 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1254 entry
.dest_mode
= INT_DEST_MODE
;
1255 entry
.mask
= 0; /* enable IRQ */
1256 entry
.dest
.logical
.logical_dest
=
1257 cpu_mask_to_apicid(TARGET_CPUS
);
1259 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1262 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1263 " IO-APIC (apicid-pin) %d-%d",
1264 mp_ioapics
[apic
].mp_apicid
,
1268 apic_printk(APIC_VERBOSE
, ", %d-%d",
1269 mp_ioapics
[apic
].mp_apicid
, pin
);
1273 if (!first_notcon
) {
1274 apic_printk(APIC_VERBOSE
, " not connected.\n");
1278 entry
.trigger
= irq_trigger(idx
);
1279 entry
.polarity
= irq_polarity(idx
);
1281 if (irq_trigger(idx
)) {
1286 irq
= pin_2_irq(idx
, apic
, pin
);
1288 * skip adding the timer int on secondary nodes, which causes
1289 * a small but painful rift in the time-space continuum
1291 if (multi_timer_check(apic
, irq
))
1294 add_pin_to_irq(irq
, apic
, pin
);
1296 if (!apic
&& !IO_APIC_IRQ(irq
))
1299 if (IO_APIC_IRQ(irq
)) {
1300 vector
= assign_irq_vector(irq
);
1301 entry
.vector
= vector
;
1302 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1304 if (!apic
&& (irq
< 16))
1305 disable_8259A_irq(irq
);
1307 ioapic_write_entry(apic
, pin
, entry
);
1312 apic_printk(APIC_VERBOSE
, " not connected.\n");
1316 * Set up the timer pin, possibly with the 8259A-master behind.
1318 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1321 struct IO_APIC_route_entry entry
;
1323 memset(&entry
, 0, sizeof(entry
));
1326 * We use logical delivery to get the timer IRQ
1329 entry
.dest_mode
= INT_DEST_MODE
;
1330 entry
.mask
= 1; /* mask IRQ now */
1331 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1332 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1335 entry
.vector
= vector
;
1338 * The timer IRQ doesn't have to know that behind the
1339 * scene we may have a 8259A-master in AEOI mode ...
1341 ioapic_register_intr(0, vector
, IOAPIC_EDGE
);
1344 * Add it to the IO-APIC irq-routing table:
1346 ioapic_write_entry(apic
, pin
, entry
);
1350 __apicdebuginit(void) print_IO_APIC(void)
1353 union IO_APIC_reg_00 reg_00
;
1354 union IO_APIC_reg_01 reg_01
;
1355 union IO_APIC_reg_02 reg_02
;
1356 union IO_APIC_reg_03 reg_03
;
1357 unsigned long flags
;
1359 if (apic_verbosity
== APIC_QUIET
)
1362 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1363 for (i
= 0; i
< nr_ioapics
; i
++)
1364 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1365 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1368 * We are a bit conservative about what we expect. We have to
1369 * know about every hardware change ASAP.
1371 printk(KERN_INFO
"testing the IO APIC.......................\n");
1373 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1375 spin_lock_irqsave(&ioapic_lock
, flags
);
1376 reg_00
.raw
= io_apic_read(apic
, 0);
1377 reg_01
.raw
= io_apic_read(apic
, 1);
1378 if (reg_01
.bits
.version
>= 0x10)
1379 reg_02
.raw
= io_apic_read(apic
, 2);
1380 if (reg_01
.bits
.version
>= 0x20)
1381 reg_03
.raw
= io_apic_read(apic
, 3);
1382 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1384 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1385 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1386 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1387 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1388 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1390 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1391 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1393 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1394 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1397 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1398 * but the value of reg_02 is read as the previous read register
1399 * value, so ignore it if reg_02 == reg_01.
1401 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1402 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1403 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1407 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1408 * or reg_03, but the value of reg_0[23] is read as the previous read
1409 * register value, so ignore it if reg_03 == reg_0[12].
1411 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1412 reg_03
.raw
!= reg_01
.raw
) {
1413 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1414 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1417 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1419 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1420 " Stat Dest Deli Vect: \n");
1422 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1423 struct IO_APIC_route_entry entry
;
1425 entry
= ioapic_read_entry(apic
, i
);
1427 printk(KERN_DEBUG
" %02x %03X %02X ",
1429 entry
.dest
.logical
.logical_dest
,
1430 entry
.dest
.physical
.physical_dest
1433 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1438 entry
.delivery_status
,
1440 entry
.delivery_mode
,
1445 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1446 for (i
= 0; i
< nr_irqs
; i
++) {
1447 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1450 printk(KERN_DEBUG
"IRQ%d ", i
);
1452 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1455 entry
= irq_2_pin
+ entry
->next
;
1460 printk(KERN_INFO
".................................... done.\n");
1465 __apicdebuginit(void) print_APIC_bitfield(int base
)
1470 if (apic_verbosity
== APIC_QUIET
)
1473 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1474 for (i
= 0; i
< 8; i
++) {
1475 v
= apic_read(base
+ i
*0x10);
1476 for (j
= 0; j
< 32; j
++) {
1486 __apicdebuginit(void) print_local_APIC(void *dummy
)
1488 unsigned int v
, ver
, maxlvt
;
1491 if (apic_verbosity
== APIC_QUIET
)
1494 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1495 smp_processor_id(), hard_smp_processor_id());
1496 v
= apic_read(APIC_ID
);
1497 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1499 v
= apic_read(APIC_LVR
);
1500 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1501 ver
= GET_APIC_VERSION(v
);
1502 maxlvt
= lapic_get_maxlvt();
1504 v
= apic_read(APIC_TASKPRI
);
1505 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1507 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1508 v
= apic_read(APIC_ARBPRI
);
1509 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1510 v
& APIC_ARBPRI_MASK
);
1511 v
= apic_read(APIC_PROCPRI
);
1512 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1515 v
= apic_read(APIC_EOI
);
1516 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1517 v
= apic_read(APIC_RRR
);
1518 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1519 v
= apic_read(APIC_LDR
);
1520 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1521 v
= apic_read(APIC_DFR
);
1522 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1523 v
= apic_read(APIC_SPIV
);
1524 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1526 printk(KERN_DEBUG
"... APIC ISR field:\n");
1527 print_APIC_bitfield(APIC_ISR
);
1528 printk(KERN_DEBUG
"... APIC TMR field:\n");
1529 print_APIC_bitfield(APIC_TMR
);
1530 printk(KERN_DEBUG
"... APIC IRR field:\n");
1531 print_APIC_bitfield(APIC_IRR
);
1533 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1534 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1535 apic_write(APIC_ESR
, 0);
1536 v
= apic_read(APIC_ESR
);
1537 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1540 icr
= apic_icr_read();
1541 printk(KERN_DEBUG
"... APIC ICR: %08x\n", icr
);
1542 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", icr
>> 32);
1544 v
= apic_read(APIC_LVTT
);
1545 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1547 if (maxlvt
> 3) { /* PC is LVT#4. */
1548 v
= apic_read(APIC_LVTPC
);
1549 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1551 v
= apic_read(APIC_LVT0
);
1552 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1553 v
= apic_read(APIC_LVT1
);
1554 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1556 if (maxlvt
> 2) { /* ERR is LVT#3. */
1557 v
= apic_read(APIC_LVTERR
);
1558 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1561 v
= apic_read(APIC_TMICT
);
1562 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1563 v
= apic_read(APIC_TMCCT
);
1564 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1565 v
= apic_read(APIC_TDCR
);
1566 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1570 __apicdebuginit(void) print_all_local_APICs(void)
1572 on_each_cpu(print_local_APIC
, NULL
, 1);
1575 __apicdebuginit(void) print_PIC(void)
1578 unsigned long flags
;
1580 if (apic_verbosity
== APIC_QUIET
)
1583 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1585 spin_lock_irqsave(&i8259A_lock
, flags
);
1587 v
= inb(0xa1) << 8 | inb(0x21);
1588 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1590 v
= inb(0xa0) << 8 | inb(0x20);
1591 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1595 v
= inb(0xa0) << 8 | inb(0x20);
1599 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1601 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1603 v
= inb(0x4d1) << 8 | inb(0x4d0);
1604 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1607 __apicdebuginit(int) print_all_ICs(void)
1610 print_all_local_APICs();
1616 fs_initcall(print_all_ICs
);
1619 static void __init
enable_IO_APIC(void)
1621 union IO_APIC_reg_01 reg_01
;
1622 int i8259_apic
, i8259_pin
;
1624 unsigned long flags
;
1626 for (i
= 0; i
< pin_map_size
; i
++) {
1627 irq_2_pin
[i
].pin
= -1;
1628 irq_2_pin
[i
].next
= 0;
1631 for (i
= 0; i
< MAX_PIRQS
; i
++)
1632 pirq_entries
[i
] = -1;
1635 * The number of IO-APIC IRQ registers (== #pins):
1637 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1638 spin_lock_irqsave(&ioapic_lock
, flags
);
1639 reg_01
.raw
= io_apic_read(apic
, 1);
1640 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1641 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1643 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1645 /* See if any of the pins is in ExtINT mode */
1646 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1647 struct IO_APIC_route_entry entry
;
1648 entry
= ioapic_read_entry(apic
, pin
);
1651 /* If the interrupt line is enabled and in ExtInt mode
1652 * I have found the pin where the i8259 is connected.
1654 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1655 ioapic_i8259
.apic
= apic
;
1656 ioapic_i8259
.pin
= pin
;
1662 /* Look to see what if the MP table has reported the ExtINT */
1663 /* If we could not find the appropriate pin by looking at the ioapic
1664 * the i8259 probably is not connected the ioapic but give the
1665 * mptable a chance anyway.
1667 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1668 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1669 /* Trust the MP table if nothing is setup in the hardware */
1670 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1671 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1672 ioapic_i8259
.pin
= i8259_pin
;
1673 ioapic_i8259
.apic
= i8259_apic
;
1675 /* Complain if the MP table and the hardware disagree */
1676 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1677 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1679 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1683 * Do not trust the IO-APIC being empty at bootup
1689 * Not an __init, needed by the reboot code
1691 void disable_IO_APIC(void)
1694 * Clear the IO-APIC before rebooting:
1699 * If the i8259 is routed through an IOAPIC
1700 * Put that IOAPIC in virtual wire mode
1701 * so legacy interrupts can be delivered.
1703 if (ioapic_i8259
.pin
!= -1) {
1704 struct IO_APIC_route_entry entry
;
1706 memset(&entry
, 0, sizeof(entry
));
1707 entry
.mask
= 0; /* Enabled */
1708 entry
.trigger
= 0; /* Edge */
1710 entry
.polarity
= 0; /* High */
1711 entry
.delivery_status
= 0;
1712 entry
.dest_mode
= 0; /* Physical */
1713 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1715 entry
.dest
.physical
.physical_dest
= read_apic_id();
1718 * Add it to the IO-APIC irq-routing table:
1720 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1722 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1726 * function to set the IO-APIC physical IDs based on the
1727 * values stored in the MPC table.
1729 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1732 static void __init
setup_ioapic_ids_from_mpc(void)
1734 union IO_APIC_reg_00 reg_00
;
1735 physid_mask_t phys_id_present_map
;
1738 unsigned char old_id
;
1739 unsigned long flags
;
1741 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1745 * Don't check I/O APIC IDs for xAPIC systems. They have
1746 * no meaning without the serial APIC bus.
1748 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1749 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1752 * This is broken; anything with a real cpu count has to
1753 * circumvent this idiocy regardless.
1755 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1758 * Set the IOAPIC ID to the value stored in the MPC table.
1760 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1762 /* Read the register 0 value */
1763 spin_lock_irqsave(&ioapic_lock
, flags
);
1764 reg_00
.raw
= io_apic_read(apic
, 0);
1765 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1767 old_id
= mp_ioapics
[apic
].mp_apicid
;
1769 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1770 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1771 apic
, mp_ioapics
[apic
].mp_apicid
);
1772 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1774 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1778 * Sanity check, is the ID really free? Every APIC in a
1779 * system must have a unique ID or we get lots of nice
1780 * 'stuck on smp_invalidate_needed IPI wait' messages.
1782 if (check_apicid_used(phys_id_present_map
,
1783 mp_ioapics
[apic
].mp_apicid
)) {
1784 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1785 apic
, mp_ioapics
[apic
].mp_apicid
);
1786 for (i
= 0; i
< get_physical_broadcast(); i
++)
1787 if (!physid_isset(i
, phys_id_present_map
))
1789 if (i
>= get_physical_broadcast())
1790 panic("Max APIC ID exceeded!\n");
1791 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1793 physid_set(i
, phys_id_present_map
);
1794 mp_ioapics
[apic
].mp_apicid
= i
;
1797 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1798 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1799 "phys_id_present_map\n",
1800 mp_ioapics
[apic
].mp_apicid
);
1801 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1806 * We need to adjust the IRQ routing table
1807 * if the ID changed.
1809 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1810 for (i
= 0; i
< mp_irq_entries
; i
++)
1811 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1812 mp_irqs
[i
].mp_dstapic
1813 = mp_ioapics
[apic
].mp_apicid
;
1816 * Read the right value from the MPC table and
1817 * write it into the ID register.
1819 apic_printk(APIC_VERBOSE
, KERN_INFO
1820 "...changing IO-APIC physical APIC ID to %d ...",
1821 mp_ioapics
[apic
].mp_apicid
);
1823 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1824 spin_lock_irqsave(&ioapic_lock
, flags
);
1825 io_apic_write(apic
, 0, reg_00
.raw
);
1826 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1831 spin_lock_irqsave(&ioapic_lock
, flags
);
1832 reg_00
.raw
= io_apic_read(apic
, 0);
1833 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1834 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1835 printk("could not set ID!\n");
1837 apic_printk(APIC_VERBOSE
, " ok.\n");
1841 int no_timer_check __initdata
;
1843 static int __init
notimercheck(char *s
)
1848 __setup("no_timer_check", notimercheck
);
1851 * There is a nasty bug in some older SMP boards, their mptable lies
1852 * about the timer IRQ. We do the following to work around the situation:
1854 * - timer IRQ defaults to IO-APIC IRQ
1855 * - if this function detects that timer IRQs are defunct, then we fall
1856 * back to ISA timer IRQs
1858 static int __init
timer_irq_works(void)
1860 unsigned long t1
= jiffies
;
1861 unsigned long flags
;
1866 local_save_flags(flags
);
1868 /* Let ten ticks pass... */
1869 mdelay((10 * 1000) / HZ
);
1870 local_irq_restore(flags
);
1873 * Expect a few ticks at least, to be sure some possible
1874 * glue logic does not lock up after one or two first
1875 * ticks in a non-ExtINT mode. Also the local APIC
1876 * might have cached one ExtINT interrupt. Finally, at
1877 * least one tick may be lost due to delays.
1879 if (time_after(jiffies
, t1
+ 4))
1886 * In the SMP+IOAPIC case it might happen that there are an unspecified
1887 * number of pending IRQ events unhandled. These cases are very rare,
1888 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1889 * better to do it this way as thus we do not have to be aware of
1890 * 'pending' interrupts in the IRQ path, except at this point.
1893 * Edge triggered needs to resend any interrupt
1894 * that was delayed but this is now handled in the device
1901 * Starting up a edge-triggered IO-APIC interrupt is
1902 * nasty - we need to make sure that we get the edge.
1903 * If it is already asserted for some reason, we need
1904 * return 1 to indicate that is was pending.
1906 * This is not complete - we should be able to fake
1907 * an edge even if it isn't on the 8259A...
1909 * (We do this for level-triggered IRQs too - it cannot hurt.)
1911 static unsigned int startup_ioapic_irq(unsigned int irq
)
1913 int was_pending
= 0;
1914 unsigned long flags
;
1916 spin_lock_irqsave(&ioapic_lock
, flags
);
1918 disable_8259A_irq(irq
);
1919 if (i8259A_irq_pending(irq
))
1922 __unmask_IO_APIC_irq(irq
);
1923 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1928 static void ack_ioapic_irq(unsigned int irq
)
1930 move_native_irq(irq
);
1934 static void ack_ioapic_quirk_irq(unsigned int irq
)
1939 move_native_irq(irq
);
1941 * It appears there is an erratum which affects at least version 0x11
1942 * of I/O APIC (that's the 82093AA and cores integrated into various
1943 * chipsets). Under certain conditions a level-triggered interrupt is
1944 * erroneously delivered as edge-triggered one but the respective IRR
1945 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1946 * message but it will never arrive and further interrupts are blocked
1947 * from the source. The exact reason is so far unknown, but the
1948 * phenomenon was observed when two consecutive interrupt requests
1949 * from a given source get delivered to the same CPU and the source is
1950 * temporarily disabled in between.
1952 * A workaround is to simulate an EOI message manually. We achieve it
1953 * by setting the trigger mode to edge and then to level when the edge
1954 * trigger mode gets detected in the TMR of a local APIC for a
1955 * level-triggered interrupt. We mask the source for the time of the
1956 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1957 * The idea is from Manfred Spraul. --macro
1959 i
= irq_vector
[irq
];
1961 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1965 if (!(v
& (1 << (i
& 0x1f)))) {
1966 atomic_inc(&irq_mis_count
);
1967 spin_lock(&ioapic_lock
);
1968 __mask_and_edge_IO_APIC_irq(irq
);
1969 __unmask_and_level_IO_APIC_irq(irq
);
1970 spin_unlock(&ioapic_lock
);
1974 static int ioapic_retrigger_irq(unsigned int irq
)
1976 send_IPI_self(irq_vector
[irq
]);
1981 static struct irq_chip ioapic_chip __read_mostly
= {
1983 .startup
= startup_ioapic_irq
,
1984 .mask
= mask_IO_APIC_irq
,
1985 .unmask
= unmask_IO_APIC_irq
,
1986 .ack
= ack_ioapic_irq
,
1987 .eoi
= ack_ioapic_quirk_irq
,
1989 .set_affinity
= set_ioapic_affinity_irq
,
1991 .retrigger
= ioapic_retrigger_irq
,
1995 static inline void init_IO_APIC_traps(void)
2000 * NOTE! The local APIC isn't very good at handling
2001 * multiple interrupts at the same interrupt level.
2002 * As the interrupt level is determined by taking the
2003 * vector number and shifting that right by 4, we
2004 * want to spread these out a bit so that they don't
2005 * all fall in the same interrupt level.
2007 * Also, we've got to be careful not to trash gate
2008 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2010 for (irq
= 0; irq
< nr_irqs
; irq
++) {
2011 if (IO_APIC_IRQ(irq
) && !irq_vector
[irq
]) {
2013 * Hmm.. We don't have an entry for this,
2014 * so default to an old-fashioned 8259
2015 * interrupt if we can..
2018 make_8259A_irq(irq
);
2020 /* Strange. Oh, well.. */
2021 irq_desc
[irq
].chip
= &no_irq_chip
;
2027 * The local APIC irq-chip implementation:
2030 static void ack_lapic_irq(unsigned int irq
)
2035 static void mask_lapic_irq(unsigned int irq
)
2039 v
= apic_read(APIC_LVT0
);
2040 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2043 static void unmask_lapic_irq(unsigned int irq
)
2047 v
= apic_read(APIC_LVT0
);
2048 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2051 static struct irq_chip lapic_chip __read_mostly
= {
2052 .name
= "local-APIC",
2053 .mask
= mask_lapic_irq
,
2054 .unmask
= unmask_lapic_irq
,
2055 .ack
= ack_lapic_irq
,
2058 static void lapic_register_intr(int irq
, int vector
)
2060 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
2061 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2063 set_intr_gate(vector
, interrupt
[irq
]);
2066 static void __init
setup_nmi(void)
2069 * Dirty trick to enable the NMI watchdog ...
2070 * We put the 8259A master into AEOI mode and
2071 * unmask on all local APICs LVT0 as NMI.
2073 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2074 * is from Maciej W. Rozycki - so we do not have to EOI from
2075 * the NMI handler or the timer interrupt.
2077 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2079 enable_NMI_through_LVT0();
2081 apic_printk(APIC_VERBOSE
, " done.\n");
2085 * This looks a bit hackish but it's about the only one way of sending
2086 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2087 * not support the ExtINT mode, unfortunately. We need to send these
2088 * cycles as some i82489DX-based boards have glue logic that keeps the
2089 * 8259A interrupt line asserted until INTA. --macro
2091 static inline void __init
unlock_ExtINT_logic(void)
2094 struct IO_APIC_route_entry entry0
, entry1
;
2095 unsigned char save_control
, save_freq_select
;
2097 pin
= find_isa_irq_pin(8, mp_INT
);
2102 apic
= find_isa_irq_apic(8, mp_INT
);
2108 entry0
= ioapic_read_entry(apic
, pin
);
2109 clear_IO_APIC_pin(apic
, pin
);
2111 memset(&entry1
, 0, sizeof(entry1
));
2113 entry1
.dest_mode
= 0; /* physical delivery */
2114 entry1
.mask
= 0; /* unmask IRQ now */
2115 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2116 entry1
.delivery_mode
= dest_ExtINT
;
2117 entry1
.polarity
= entry0
.polarity
;
2121 ioapic_write_entry(apic
, pin
, entry1
);
2123 save_control
= CMOS_READ(RTC_CONTROL
);
2124 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2125 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2127 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2132 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2136 CMOS_WRITE(save_control
, RTC_CONTROL
);
2137 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2138 clear_IO_APIC_pin(apic
, pin
);
2140 ioapic_write_entry(apic
, pin
, entry0
);
2144 * This code may look a bit paranoid, but it's supposed to cooperate with
2145 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2146 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2147 * fanatically on his truly buggy board.
2149 static inline void __init
check_timer(void)
2151 int apic1
, pin1
, apic2
, pin2
;
2155 unsigned long flags
;
2157 local_irq_save(flags
);
2159 ver
= apic_read(APIC_LVR
);
2160 ver
= GET_APIC_VERSION(ver
);
2163 * get/set the timer IRQ vector:
2165 disable_8259A_irq(0);
2166 vector
= assign_irq_vector(0);
2167 set_intr_gate(vector
, interrupt
[0]);
2170 * As IRQ0 is to be enabled in the 8259A, the virtual
2171 * wire has to be disabled in the local APIC. Also
2172 * timer interrupts need to be acknowledged manually in
2173 * the 8259A for the i82489DX when using the NMI
2174 * watchdog as that APIC treats NMIs as level-triggered.
2175 * The AEOI mode will finish them in the 8259A
2178 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2180 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2182 pin1
= find_isa_irq_pin(0, mp_INT
);
2183 apic1
= find_isa_irq_apic(0, mp_INT
);
2184 pin2
= ioapic_i8259
.pin
;
2185 apic2
= ioapic_i8259
.apic
;
2187 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2188 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2189 vector
, apic1
, pin1
, apic2
, pin2
);
2192 * Some BIOS writers are clueless and report the ExtINTA
2193 * I/O APIC input from the cascaded 8259A as the timer
2194 * interrupt input. So just in case, if only one pin
2195 * was found above, try it both directly and through the
2202 } else if (pin2
== -1) {
2209 * Ok, does IRQ0 through the IOAPIC work?
2212 add_pin_to_irq(0, apic1
, pin1
);
2213 setup_timer_IRQ0_pin(apic1
, pin1
, vector
);
2215 unmask_IO_APIC_irq(0);
2216 if (timer_irq_works()) {
2217 if (nmi_watchdog
== NMI_IO_APIC
) {
2219 enable_8259A_irq(0);
2221 if (disable_timer_pin_1
> 0)
2222 clear_IO_APIC_pin(0, pin1
);
2225 clear_IO_APIC_pin(apic1
, pin1
);
2227 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2228 "8254 timer not connected to IO-APIC\n");
2230 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2231 "(IRQ0) through the 8259A ...\n");
2232 apic_printk(APIC_QUIET
, KERN_INFO
2233 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2235 * legacy devices should be connected to IO APIC #0
2237 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2238 setup_timer_IRQ0_pin(apic2
, pin2
, vector
);
2239 unmask_IO_APIC_irq(0);
2240 enable_8259A_irq(0);
2241 if (timer_irq_works()) {
2242 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2243 timer_through_8259
= 1;
2244 if (nmi_watchdog
== NMI_IO_APIC
) {
2245 disable_8259A_irq(0);
2247 enable_8259A_irq(0);
2252 * Cleanup, just in case ...
2254 disable_8259A_irq(0);
2255 clear_IO_APIC_pin(apic2
, pin2
);
2256 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2259 if (nmi_watchdog
== NMI_IO_APIC
) {
2260 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2261 "through the IO-APIC - disabling NMI Watchdog!\n");
2262 nmi_watchdog
= NMI_NONE
;
2266 apic_printk(APIC_QUIET
, KERN_INFO
2267 "...trying to set up timer as Virtual Wire IRQ...\n");
2269 lapic_register_intr(0, vector
);
2270 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2271 enable_8259A_irq(0);
2273 if (timer_irq_works()) {
2274 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2277 disable_8259A_irq(0);
2278 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2279 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2281 apic_printk(APIC_QUIET
, KERN_INFO
2282 "...trying to set up timer as ExtINT IRQ...\n");
2286 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2288 unlock_ExtINT_logic();
2290 if (timer_irq_works()) {
2291 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2294 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2295 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2296 "report. Then try booting with the 'noapic' option.\n");
2298 local_irq_restore(flags
);
2302 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2303 * to devices. However there may be an I/O APIC pin available for
2304 * this interrupt regardless. The pin may be left unconnected, but
2305 * typically it will be reused as an ExtINT cascade interrupt for
2306 * the master 8259A. In the MPS case such a pin will normally be
2307 * reported as an ExtINT interrupt in the MP table. With ACPI
2308 * there is no provision for ExtINT interrupts, and in the absence
2309 * of an override it would be treated as an ordinary ISA I/O APIC
2310 * interrupt, that is edge-triggered and unmasked by default. We
2311 * used to do this, but it caused problems on some systems because
2312 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2313 * the same ExtINT cascade interrupt to drive the local APIC of the
2314 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2315 * the I/O APIC in all cases now. No actual device should request
2316 * it anyway. --macro
2318 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2320 void __init
setup_IO_APIC(void)
2324 /* Reserve all the system vectors. */
2325 for (i
= first_system_vector
; i
< NR_VECTORS
; i
++)
2326 set_bit(i
, used_vectors
);
2330 io_apic_irqs
= ~PIC_IRQS
;
2332 printk("ENABLING IO-APIC IRQs\n");
2335 * Set up IO-APIC IRQ routing.
2338 setup_ioapic_ids_from_mpc();
2340 setup_IO_APIC_irqs();
2341 init_IO_APIC_traps();
2346 * Called after all the initialization is done. If we didnt find any
2347 * APIC bugs then we can allow the modify fast path
2350 static int __init
io_apic_bug_finalize(void)
2352 if (sis_apic_bug
== -1)
2357 late_initcall(io_apic_bug_finalize
);
2359 struct sysfs_ioapic_data
{
2360 struct sys_device dev
;
2361 struct IO_APIC_route_entry entry
[0];
2363 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2365 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2367 struct IO_APIC_route_entry
*entry
;
2368 struct sysfs_ioapic_data
*data
;
2371 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2372 entry
= data
->entry
;
2373 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2374 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2379 static int ioapic_resume(struct sys_device
*dev
)
2381 struct IO_APIC_route_entry
*entry
;
2382 struct sysfs_ioapic_data
*data
;
2383 unsigned long flags
;
2384 union IO_APIC_reg_00 reg_00
;
2387 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2388 entry
= data
->entry
;
2390 spin_lock_irqsave(&ioapic_lock
, flags
);
2391 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2392 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2393 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2394 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2396 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2397 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2398 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2403 static struct sysdev_class ioapic_sysdev_class
= {
2405 .suspend
= ioapic_suspend
,
2406 .resume
= ioapic_resume
,
2409 static int __init
ioapic_init_sysfs(void)
2411 struct sys_device
*dev
;
2412 int i
, size
, error
= 0;
2414 error
= sysdev_class_register(&ioapic_sysdev_class
);
2418 for (i
= 0; i
< nr_ioapics
; i
++) {
2419 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2420 * sizeof(struct IO_APIC_route_entry
);
2421 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2422 if (!mp_ioapic_data
[i
]) {
2423 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2426 dev
= &mp_ioapic_data
[i
]->dev
;
2428 dev
->cls
= &ioapic_sysdev_class
;
2429 error
= sysdev_register(dev
);
2431 kfree(mp_ioapic_data
[i
]);
2432 mp_ioapic_data
[i
] = NULL
;
2433 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2441 device_initcall(ioapic_init_sysfs
);
2444 * Dynamic irq allocate and deallocation
2446 int create_irq(void)
2448 /* Allocate an unused irq */
2449 int irq
, new, vector
= 0;
2450 unsigned long flags
;
2453 spin_lock_irqsave(&vector_lock
, flags
);
2454 for (new = (nr_irqs
- 1); new >= 0; new--) {
2455 if (platform_legacy_irq(new))
2457 if (irq_vector
[new] != 0)
2459 vector
= __assign_irq_vector(new);
2460 if (likely(vector
> 0))
2464 spin_unlock_irqrestore(&vector_lock
, flags
);
2467 set_intr_gate(vector
, interrupt
[irq
]);
2468 dynamic_irq_init(irq
);
2473 void destroy_irq(unsigned int irq
)
2475 unsigned long flags
;
2477 dynamic_irq_cleanup(irq
);
2479 spin_lock_irqsave(&vector_lock
, flags
);
2480 clear_bit(irq_vector
[irq
], used_vectors
);
2481 irq_vector
[irq
] = 0;
2482 spin_unlock_irqrestore(&vector_lock
, flags
);
2486 * MSI message composition
2488 #ifdef CONFIG_PCI_MSI
2489 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2494 vector
= assign_irq_vector(irq
);
2496 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2498 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2501 ((INT_DEST_MODE
== 0) ?
2502 MSI_ADDR_DEST_MODE_PHYSICAL
:
2503 MSI_ADDR_DEST_MODE_LOGICAL
) |
2504 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2505 MSI_ADDR_REDIRECTION_CPU
:
2506 MSI_ADDR_REDIRECTION_LOWPRI
) |
2507 MSI_ADDR_DEST_ID(dest
);
2510 MSI_DATA_TRIGGER_EDGE
|
2511 MSI_DATA_LEVEL_ASSERT
|
2512 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2513 MSI_DATA_DELIVERY_FIXED
:
2514 MSI_DATA_DELIVERY_LOWPRI
) |
2515 MSI_DATA_VECTOR(vector
);
2521 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2528 cpus_and(tmp
, mask
, cpu_online_map
);
2529 if (cpus_empty(tmp
))
2532 vector
= assign_irq_vector(irq
);
2536 dest
= cpu_mask_to_apicid(mask
);
2538 read_msi_msg(irq
, &msg
);
2540 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2541 msg
.data
|= MSI_DATA_VECTOR(vector
);
2542 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2543 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2545 write_msi_msg(irq
, &msg
);
2546 irq_desc
[irq
].affinity
= mask
;
2548 #endif /* CONFIG_SMP */
2551 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2552 * which implement the MSI or MSI-X Capability Structure.
2554 static struct irq_chip msi_chip
= {
2556 .unmask
= unmask_msi_irq
,
2557 .mask
= mask_msi_irq
,
2558 .ack
= ack_ioapic_irq
,
2560 .set_affinity
= set_msi_irq_affinity
,
2562 .retrigger
= ioapic_retrigger_irq
,
2565 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2573 ret
= msi_compose_msg(dev
, irq
, &msg
);
2579 set_irq_msi(irq
, desc
);
2580 write_msi_msg(irq
, &msg
);
2582 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2588 void arch_teardown_msi_irq(unsigned int irq
)
2593 #endif /* CONFIG_PCI_MSI */
2596 * Hypertransport interrupt support
2598 #ifdef CONFIG_HT_IRQ
2602 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2604 struct ht_irq_msg msg
;
2605 fetch_ht_irq_msg(irq
, &msg
);
2607 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2608 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2610 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2611 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2613 write_ht_irq_msg(irq
, &msg
);
2616 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2621 cpus_and(tmp
, mask
, cpu_online_map
);
2622 if (cpus_empty(tmp
))
2625 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2627 dest
= cpu_mask_to_apicid(mask
);
2629 target_ht_irq(irq
, dest
);
2630 irq_desc
[irq
].affinity
= mask
;
2634 static struct irq_chip ht_irq_chip
= {
2636 .mask
= mask_ht_irq
,
2637 .unmask
= unmask_ht_irq
,
2638 .ack
= ack_ioapic_irq
,
2640 .set_affinity
= set_ht_irq_affinity
,
2642 .retrigger
= ioapic_retrigger_irq
,
2645 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2649 vector
= assign_irq_vector(irq
);
2651 struct ht_irq_msg msg
;
2656 cpu_set(vector
>> 8, tmp
);
2657 dest
= cpu_mask_to_apicid(tmp
);
2659 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2663 HT_IRQ_LOW_DEST_ID(dest
) |
2664 HT_IRQ_LOW_VECTOR(vector
) |
2665 ((INT_DEST_MODE
== 0) ?
2666 HT_IRQ_LOW_DM_PHYSICAL
:
2667 HT_IRQ_LOW_DM_LOGICAL
) |
2668 HT_IRQ_LOW_RQEOI_EDGE
|
2669 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2670 HT_IRQ_LOW_MT_FIXED
:
2671 HT_IRQ_LOW_MT_ARBITRATED
) |
2672 HT_IRQ_LOW_IRQ_MASKED
;
2674 write_ht_irq_msg(irq
, &msg
);
2676 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2677 handle_edge_irq
, "edge");
2681 #endif /* CONFIG_HT_IRQ */
2683 /* --------------------------------------------------------------------------
2684 ACPI-based IOAPIC Configuration
2685 -------------------------------------------------------------------------- */
2689 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2691 union IO_APIC_reg_00 reg_00
;
2692 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2694 unsigned long flags
;
2698 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2699 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2700 * supports up to 16 on one shared APIC bus.
2702 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2703 * advantage of new APIC bus architecture.
2706 if (physids_empty(apic_id_map
))
2707 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2709 spin_lock_irqsave(&ioapic_lock
, flags
);
2710 reg_00
.raw
= io_apic_read(ioapic
, 0);
2711 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2713 if (apic_id
>= get_physical_broadcast()) {
2714 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2715 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2716 apic_id
= reg_00
.bits
.ID
;
2720 * Every APIC in a system must have a unique ID or we get lots of nice
2721 * 'stuck on smp_invalidate_needed IPI wait' messages.
2723 if (check_apicid_used(apic_id_map
, apic_id
)) {
2725 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2726 if (!check_apicid_used(apic_id_map
, i
))
2730 if (i
== get_physical_broadcast())
2731 panic("Max apic_id exceeded!\n");
2733 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2734 "trying %d\n", ioapic
, apic_id
, i
);
2739 tmp
= apicid_to_cpu_present(apic_id
);
2740 physids_or(apic_id_map
, apic_id_map
, tmp
);
2742 if (reg_00
.bits
.ID
!= apic_id
) {
2743 reg_00
.bits
.ID
= apic_id
;
2745 spin_lock_irqsave(&ioapic_lock
, flags
);
2746 io_apic_write(ioapic
, 0, reg_00
.raw
);
2747 reg_00
.raw
= io_apic_read(ioapic
, 0);
2748 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2751 if (reg_00
.bits
.ID
!= apic_id
) {
2752 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2757 apic_printk(APIC_VERBOSE
, KERN_INFO
2758 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2764 int __init
io_apic_get_version(int ioapic
)
2766 union IO_APIC_reg_01 reg_01
;
2767 unsigned long flags
;
2769 spin_lock_irqsave(&ioapic_lock
, flags
);
2770 reg_01
.raw
= io_apic_read(ioapic
, 1);
2771 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2773 return reg_01
.bits
.version
;
2777 int __init
io_apic_get_redir_entries(int ioapic
)
2779 union IO_APIC_reg_01 reg_01
;
2780 unsigned long flags
;
2782 spin_lock_irqsave(&ioapic_lock
, flags
);
2783 reg_01
.raw
= io_apic_read(ioapic
, 1);
2784 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2786 return reg_01
.bits
.entries
;
2790 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2792 struct IO_APIC_route_entry entry
;
2794 if (!IO_APIC_IRQ(irq
)) {
2795 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2801 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2802 * Note that we mask (disable) IRQs now -- these get enabled when the
2803 * corresponding device driver registers for this IRQ.
2806 memset(&entry
, 0, sizeof(entry
));
2808 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2809 entry
.dest_mode
= INT_DEST_MODE
;
2810 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2811 entry
.trigger
= edge_level
;
2812 entry
.polarity
= active_high_low
;
2816 * IRQs < 16 are already in the irq_2_pin[] map
2819 add_pin_to_irq(irq
, ioapic
, pin
);
2821 entry
.vector
= assign_irq_vector(irq
);
2823 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2824 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2825 mp_ioapics
[ioapic
].mp_apicid
, pin
, entry
.vector
, irq
,
2826 edge_level
, active_high_low
);
2828 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2830 if (!ioapic
&& (irq
< 16))
2831 disable_8259A_irq(irq
);
2833 ioapic_write_entry(ioapic
, pin
, entry
);
2838 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2842 if (skip_ioapic_setup
)
2845 for (i
= 0; i
< mp_irq_entries
; i
++)
2846 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2847 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2849 if (i
>= mp_irq_entries
)
2852 *trigger
= irq_trigger(i
);
2853 *polarity
= irq_polarity(i
);
2857 #endif /* CONFIG_ACPI */
2859 static int __init
parse_disable_timer_pin_1(char *arg
)
2861 disable_timer_pin_1
= 1;
2864 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2866 static int __init
parse_enable_timer_pin_1(char *arg
)
2868 disable_timer_pin_1
= -1;
2871 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2873 static int __init
parse_noapic(char *arg
)
2875 /* disable IO-APIC */
2876 disable_ioapic_setup();
2879 early_param("noapic", parse_noapic
);
2881 void __init
ioapic_init_mappings(void)
2883 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2886 for (i
= 0; i
< nr_ioapics
; i
++) {
2887 if (smp_found_config
) {
2888 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2891 "WARNING: bogus zero IO-APIC "
2892 "address found in MPTABLE, "
2893 "disabling IO/APIC support!\n");
2894 smp_found_config
= 0;
2895 skip_ioapic_setup
= 1;
2896 goto fake_ioapic_page
;
2900 ioapic_phys
= (unsigned long)
2901 alloc_bootmem_pages(PAGE_SIZE
);
2902 ioapic_phys
= __pa(ioapic_phys
);
2904 set_fixmap_nocache(idx
, ioapic_phys
);
2905 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
2906 __fix_to_virt(idx
), ioapic_phys
);