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[deliverable/linux.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
40
41 #include <asm/io.h>
42 #include <asm/smp.h>
43 #include <asm/desc.h>
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
46 #include <asm/nmi.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
50
51 #include <mach_ipi.h>
52 #include <mach_apic.h>
53 #include <mach_apicdef.h>
54
55 #define __apicdebuginit(type) static type __init
56
57 int (*ioapic_renumber_irq)(int ioapic, int irq);
58 atomic_t irq_mis_count;
59
60 /* Where if anywhere is the i8259 connect in external int mode */
61 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
62
63 static DEFINE_SPINLOCK(ioapic_lock);
64 static DEFINE_SPINLOCK(vector_lock);
65
66 int timer_through_8259 __initdata;
67
68 /*
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
71 */
72 int sis_apic_bug = -1;
73
74 int first_free_entry;
75 /*
76 * # of IRQ routing registers
77 */
78 int nr_ioapic_registers[MAX_IO_APICS];
79
80 /* I/O APIC entries */
81 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
82 int nr_ioapics;
83
84 /* MP IRQ source entries */
85 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
86
87 /* # of MP IRQ source entries */
88 int mp_irq_entries;
89
90 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
91 int mp_bus_id_to_type[MAX_MP_BUSSES];
92 #endif
93
94 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
95
96 static int disable_timer_pin_1 __initdata;
97
98 struct irq_cfg;
99 struct irq_pin_list;
100 struct irq_cfg {
101 unsigned int irq;
102 struct irq_cfg *next;
103 struct irq_pin_list *irq_2_pin;
104 cpumask_t domain;
105 cpumask_t old_domain;
106 unsigned move_cleanup_count;
107 u8 vector;
108 u8 move_in_progress : 1;
109 };
110
111
112 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
113 static struct irq_cfg irq_cfg_legacy[] __initdata = {
114 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
115 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
116 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
117 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
118 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
119 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
120 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
121 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
122 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
123 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
124 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
125 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
126 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
127 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
128 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
129 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
130 };
131
132 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
133 /* need to be biger than size of irq_cfg_legacy */
134 static int nr_irq_cfg = 32;
135
136 static int __init parse_nr_irq_cfg(char *arg)
137 {
138 if (arg) {
139 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
140 if (nr_irq_cfg < 32)
141 nr_irq_cfg = 32;
142 }
143 return 0;
144 }
145
146 early_param("nr_irq_cfg", parse_nr_irq_cfg);
147
148 static void init_one_irq_cfg(struct irq_cfg *cfg)
149 {
150 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
151 }
152
153 static struct irq_cfg *irq_cfgx;
154 static struct irq_cfg *irq_cfgx_free;
155 static void __init init_work(void *data)
156 {
157 struct dyn_array *da = data;
158 struct irq_cfg *cfg;
159 int legacy_count;
160 int i;
161
162 cfg = *da->name;
163
164 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
165
166 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
167 for (i = legacy_count; i < *da->nr; i++)
168 init_one_irq_cfg(&cfg[i]);
169
170 for (i = 1; i < *da->nr; i++)
171 cfg[i-1].next = &cfg[i];
172
173 irq_cfgx_free = &irq_cfgx[legacy_count];
174 irq_cfgx[legacy_count - 1].next = NULL;
175 }
176
177 #define for_each_irq_cfg(cfg) \
178 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
179
180 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
181
182 static struct irq_cfg *irq_cfg(unsigned int irq)
183 {
184 struct irq_cfg *cfg;
185
186 cfg = irq_cfgx;
187 while (cfg) {
188 if (cfg->irq == irq)
189 return cfg;
190
191 cfg = cfg->next;
192 }
193
194 return NULL;
195 }
196
197 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
198 {
199 struct irq_cfg *cfg, *cfg_pri;
200 int i;
201 int count = 0;
202
203 cfg_pri = cfg = irq_cfgx;
204 while (cfg) {
205 if (cfg->irq == irq)
206 return cfg;
207
208 cfg_pri = cfg;
209 cfg = cfg->next;
210 count++;
211 }
212
213 if (!irq_cfgx_free) {
214 unsigned long phys;
215 unsigned long total_bytes;
216 /*
217 * we run out of pre-allocate ones, allocate more
218 */
219 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
220
221 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
222 if (after_bootmem)
223 cfg = kzalloc(total_bytes, GFP_ATOMIC);
224 else
225 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
226
227 if (!cfg)
228 panic("please boot with nr_irq_cfg= %d\n", count * 2);
229
230 phys = __pa(cfg);
231 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
232
233 for (i = 0; i < nr_irq_cfg; i++)
234 init_one_irq_cfg(&cfg[i]);
235
236 for (i = 1; i < nr_irq_cfg; i++)
237 cfg[i-1].next = &cfg[i];
238
239 irq_cfgx_free = cfg;
240 }
241
242 cfg = irq_cfgx_free;
243 irq_cfgx_free = irq_cfgx_free->next;
244 cfg->next = NULL;
245 if (cfg_pri)
246 cfg_pri->next = cfg;
247 else
248 irq_cfgx = cfg;
249 cfg->irq = irq;
250 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
251
252 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
253 {
254 /* dump the results */
255 struct irq_cfg *cfg;
256 unsigned long phys;
257 unsigned long bytes = sizeof(struct irq_cfg);
258
259 printk(KERN_DEBUG "=========================== %d\n", irq);
260 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
261 for_each_irq_cfg(cfg) {
262 phys = __pa(cfg);
263 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
264 }
265 printk(KERN_DEBUG "===========================\n");
266 }
267 #endif
268 return cfg;
269 }
270
271 static int assign_irq_vector(int irq, cpumask_t mask);
272 /*
273 * Rough estimation of how many shared IRQs there are, can
274 * be changed anytime.
275 */
276 int pin_map_size;
277
278 /*
279 * This is performance-critical, we want to do it O(1)
280 *
281 * the indexing order of this array favors 1:1 mappings
282 * between pins and IRQs.
283 */
284
285 struct irq_pin_list {
286 int apic, pin;
287 struct irq_pin_list *next;
288 };
289
290 static struct irq_pin_list *irq_2_pin_head;
291 /* fill one page ? */
292 static int nr_irq_2_pin = 0x100;
293 static struct irq_pin_list *irq_2_pin_ptr;
294 static void __init irq_2_pin_init_work(void *data)
295 {
296 struct dyn_array *da = data;
297 struct irq_pin_list *pin;
298 int i;
299
300 pin = *da->name;
301
302 for (i = 1; i < *da->nr; i++)
303 pin[i-1].next = &pin[i];
304
305 irq_2_pin_ptr = &pin[0];
306 }
307 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
308
309 static struct irq_pin_list *get_one_free_irq_2_pin(void)
310 {
311 struct irq_pin_list *pin;
312 int i;
313
314 pin = irq_2_pin_ptr;
315
316 if (pin) {
317 irq_2_pin_ptr = pin->next;
318 pin->next = NULL;
319 return pin;
320 }
321
322 /*
323 * we run out of pre-allocate ones, allocate more
324 */
325 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
326
327 if (after_bootmem)
328 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
329 GFP_ATOMIC);
330 else
331 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
332 nr_irq_2_pin, PAGE_SIZE, 0);
333
334 if (!pin)
335 panic("can not get more irq_2_pin\n");
336
337 for (i = 1; i < nr_irq_2_pin; i++)
338 pin[i-1].next = &pin[i];
339
340 irq_2_pin_ptr = pin->next;
341 pin->next = NULL;
342
343 return pin;
344 }
345
346 struct io_apic {
347 unsigned int index;
348 unsigned int unused[3];
349 unsigned int data;
350 };
351
352 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
353 {
354 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
355 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
356 }
357
358 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
359 {
360 struct io_apic __iomem *io_apic = io_apic_base(apic);
361 writel(reg, &io_apic->index);
362 return readl(&io_apic->data);
363 }
364
365 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
366 {
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 writel(value, &io_apic->data);
370 }
371
372 /*
373 * Re-write a value: to be used for read-modify-write
374 * cycles where the read already set up the index register.
375 *
376 * Older SiS APIC requires we rewrite the index register
377 */
378 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
379 {
380 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
381 if (sis_apic_bug)
382 writel(reg, &io_apic->index);
383 writel(value, &io_apic->data);
384 }
385
386 union entry_union {
387 struct { u32 w1, w2; };
388 struct IO_APIC_route_entry entry;
389 };
390
391 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
392 {
393 union entry_union eu;
394 unsigned long flags;
395 spin_lock_irqsave(&ioapic_lock, flags);
396 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
397 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
398 spin_unlock_irqrestore(&ioapic_lock, flags);
399 return eu.entry;
400 }
401
402 /*
403 * When we write a new IO APIC routing entry, we need to write the high
404 * word first! If the mask bit in the low word is clear, we will enable
405 * the interrupt, and we need to make sure the entry is fully populated
406 * before that happens.
407 */
408 static void
409 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
410 {
411 union entry_union eu;
412 eu.entry = e;
413 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
414 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
415 }
416
417 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
418 {
419 unsigned long flags;
420 spin_lock_irqsave(&ioapic_lock, flags);
421 __ioapic_write_entry(apic, pin, e);
422 spin_unlock_irqrestore(&ioapic_lock, flags);
423 }
424
425 /*
426 * When we mask an IO APIC routing entry, we need to write the low
427 * word first, in order to set the mask bit before we change the
428 * high bits!
429 */
430 static void ioapic_mask_entry(int apic, int pin)
431 {
432 unsigned long flags;
433 union entry_union eu = { .entry.mask = 1 };
434
435 spin_lock_irqsave(&ioapic_lock, flags);
436 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
437 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
438 spin_unlock_irqrestore(&ioapic_lock, flags);
439 }
440
441 #ifdef CONFIG_SMP
442 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
443 {
444 int apic, pin;
445 struct irq_cfg *cfg;
446 struct irq_pin_list *entry;
447
448 cfg = irq_cfg(irq);
449 entry = cfg->irq_2_pin;
450 for (;;) {
451 unsigned int reg;
452
453 if (!entry)
454 break;
455
456 apic = entry->apic;
457 pin = entry->pin;
458 io_apic_write(apic, 0x11 + pin*2, dest);
459 reg = io_apic_read(apic, 0x10 + pin*2);
460 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
461 reg |= vector;
462 io_apic_modify(apic, 0x10 + pin *2, reg);
463 if (!entry->next)
464 break;
465 entry = entry->next;
466 }
467 }
468 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
469 {
470 struct irq_cfg *cfg;
471 unsigned long flags;
472 unsigned int dest;
473 cpumask_t tmp;
474
475 cfg = irq_cfg(irq);
476
477 cpus_and(tmp, mask, cpu_online_map);
478 if (cpus_empty(tmp))
479 return;
480
481 if (assign_irq_vector(irq, mask))
482 return;
483
484 cpus_and(tmp, cfg->domain, mask);
485
486 dest = cpu_mask_to_apicid(tmp);
487 /*
488 * Only the high 8 bits are valid.
489 */
490 dest = SET_APIC_LOGICAL_ID(dest);
491
492 spin_lock_irqsave(&ioapic_lock, flags);
493 __target_IO_APIC_irq(irq, dest, cfg->vector);
494 irq_to_desc(irq)->affinity = mask;
495 spin_unlock_irqrestore(&ioapic_lock, flags);
496 }
497
498 #endif /* CONFIG_SMP */
499
500 /*
501 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
502 * shared ISA-space IRQs, so we have to support them. We are super
503 * fast in the common case, and fast for shared ISA-space IRQs.
504 */
505 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
506 {
507 struct irq_cfg *cfg;
508 struct irq_pin_list *entry;
509
510 /* first time to refer irq_cfg, so with new */
511 cfg = irq_cfg_alloc(irq);
512 entry = cfg->irq_2_pin;
513 if (!entry) {
514 entry = get_one_free_irq_2_pin();
515 cfg->irq_2_pin = entry;
516 entry->apic = apic;
517 entry->pin = pin;
518 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
519 return;
520 }
521
522 while (entry->next) {
523 /* not again, please */
524 if (entry->apic == apic && entry->pin == pin)
525 return;
526
527 entry = entry->next;
528 }
529
530 entry->next = get_one_free_irq_2_pin();
531 entry = entry->next;
532 entry->apic = apic;
533 entry->pin = pin;
534 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
535 }
536
537 /*
538 * Reroute an IRQ to a different pin.
539 */
540 static void __init replace_pin_at_irq(unsigned int irq,
541 int oldapic, int oldpin,
542 int newapic, int newpin)
543 {
544 struct irq_cfg *cfg = irq_cfg(irq);
545 struct irq_pin_list *entry = cfg->irq_2_pin;
546 int replaced = 0;
547
548 while (entry) {
549 if (entry->apic == oldapic && entry->pin == oldpin) {
550 entry->apic = newapic;
551 entry->pin = newpin;
552 replaced = 1;
553 /* every one is different, right? */
554 break;
555 }
556 entry = entry->next;
557 }
558
559 /* why? call replace before add? */
560 if (!replaced)
561 add_pin_to_irq(irq, newapic, newpin);
562 }
563
564 static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
565 {
566 struct irq_cfg *cfg;
567 struct irq_pin_list *entry;
568 unsigned int pin, reg;
569
570 cfg = irq_cfg(irq);
571 entry = cfg->irq_2_pin;
572 for (;;) {
573 if (!entry)
574 break;
575 pin = entry->pin;
576 reg = io_apic_read(entry->apic, 0x10 + pin*2);
577 reg &= ~disable;
578 reg |= enable;
579 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
580 if (!entry->next)
581 break;
582 entry = entry->next;
583 }
584 }
585
586 /* mask = 1 */
587 static void __mask_IO_APIC_irq(unsigned int irq)
588 {
589 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
590 }
591
592 /* mask = 0 */
593 static void __unmask_IO_APIC_irq(unsigned int irq)
594 {
595 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
596 }
597
598 /* mask = 1, trigger = 0 */
599 static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
600 {
601 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
602 IO_APIC_REDIR_LEVEL_TRIGGER);
603 }
604
605 /* mask = 0, trigger = 1 */
606 static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
607 {
608 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
609 IO_APIC_REDIR_MASKED);
610 }
611
612 static void mask_IO_APIC_irq(unsigned int irq)
613 {
614 unsigned long flags;
615
616 spin_lock_irqsave(&ioapic_lock, flags);
617 __mask_IO_APIC_irq(irq);
618 spin_unlock_irqrestore(&ioapic_lock, flags);
619 }
620
621 static void unmask_IO_APIC_irq(unsigned int irq)
622 {
623 unsigned long flags;
624
625 spin_lock_irqsave(&ioapic_lock, flags);
626 __unmask_IO_APIC_irq(irq);
627 spin_unlock_irqrestore(&ioapic_lock, flags);
628 }
629
630 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
631 {
632 struct IO_APIC_route_entry entry;
633
634 /* Check delivery_mode to be sure we're not clearing an SMI pin */
635 entry = ioapic_read_entry(apic, pin);
636 if (entry.delivery_mode == dest_SMI)
637 return;
638
639 /*
640 * Disable it in the IO-APIC irq-routing table:
641 */
642 ioapic_mask_entry(apic, pin);
643 }
644
645 static void clear_IO_APIC(void)
646 {
647 int apic, pin;
648
649 for (apic = 0; apic < nr_ioapics; apic++)
650 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
651 clear_IO_APIC_pin(apic, pin);
652 }
653
654 #ifndef CONFIG_SMP
655 void send_IPI_self(int vector)
656 {
657 unsigned int cfg;
658
659 /*
660 * Wait for idle.
661 */
662 apic_wait_icr_idle();
663 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
664 /*
665 * Send the IPI. The write to APIC_ICR fires this off.
666 */
667 apic_write(APIC_ICR, cfg);
668 }
669 #endif /* !CONFIG_SMP */
670
671
672 /*
673 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
674 * specific CPU-side IRQs.
675 */
676
677 #define MAX_PIRQS 8
678 static int pirq_entries [MAX_PIRQS];
679 static int pirqs_enabled;
680 int skip_ioapic_setup;
681
682 static int __init ioapic_pirq_setup(char *str)
683 {
684 int i, max;
685 int ints[MAX_PIRQS+1];
686
687 get_options(str, ARRAY_SIZE(ints), ints);
688
689 for (i = 0; i < MAX_PIRQS; i++)
690 pirq_entries[i] = -1;
691
692 pirqs_enabled = 1;
693 apic_printk(APIC_VERBOSE, KERN_INFO
694 "PIRQ redirection, working around broken MP-BIOS.\n");
695 max = MAX_PIRQS;
696 if (ints[0] < MAX_PIRQS)
697 max = ints[0];
698
699 for (i = 0; i < max; i++) {
700 apic_printk(APIC_VERBOSE, KERN_DEBUG
701 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
702 /*
703 * PIRQs are mapped upside down, usually.
704 */
705 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
706 }
707 return 1;
708 }
709
710 __setup("pirq=", ioapic_pirq_setup);
711
712 /*
713 * Find the IRQ entry number of a certain pin.
714 */
715 static int find_irq_entry(int apic, int pin, int type)
716 {
717 int i;
718
719 for (i = 0; i < mp_irq_entries; i++)
720 if (mp_irqs[i].mp_irqtype == type &&
721 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
722 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
723 mp_irqs[i].mp_dstirq == pin)
724 return i;
725
726 return -1;
727 }
728
729 /*
730 * Find the pin to which IRQ[irq] (ISA) is connected
731 */
732 static int __init find_isa_irq_pin(int irq, int type)
733 {
734 int i;
735
736 for (i = 0; i < mp_irq_entries; i++) {
737 int lbus = mp_irqs[i].mp_srcbus;
738
739 if (test_bit(lbus, mp_bus_not_pci) &&
740 (mp_irqs[i].mp_irqtype == type) &&
741 (mp_irqs[i].mp_srcbusirq == irq))
742
743 return mp_irqs[i].mp_dstirq;
744 }
745 return -1;
746 }
747
748 static int __init find_isa_irq_apic(int irq, int type)
749 {
750 int i;
751
752 for (i = 0; i < mp_irq_entries; i++) {
753 int lbus = mp_irqs[i].mp_srcbus;
754
755 if (test_bit(lbus, mp_bus_not_pci) &&
756 (mp_irqs[i].mp_irqtype == type) &&
757 (mp_irqs[i].mp_srcbusirq == irq))
758 break;
759 }
760 if (i < mp_irq_entries) {
761 int apic;
762 for (apic = 0; apic < nr_ioapics; apic++) {
763 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
764 return apic;
765 }
766 }
767
768 return -1;
769 }
770
771 /*
772 * Find a specific PCI IRQ entry.
773 * Not an __init, possibly needed by modules
774 */
775 static int pin_2_irq(int idx, int apic, int pin);
776
777 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
778 {
779 int apic, i, best_guess = -1;
780
781 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
782 "slot:%d, pin:%d.\n", bus, slot, pin);
783 if (test_bit(bus, mp_bus_not_pci)) {
784 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
785 return -1;
786 }
787 for (i = 0; i < mp_irq_entries; i++) {
788 int lbus = mp_irqs[i].mp_srcbus;
789
790 for (apic = 0; apic < nr_ioapics; apic++)
791 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
792 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
793 break;
794
795 if (!test_bit(lbus, mp_bus_not_pci) &&
796 !mp_irqs[i].mp_irqtype &&
797 (bus == lbus) &&
798 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
799 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
800
801 if (!(apic || IO_APIC_IRQ(irq)))
802 continue;
803
804 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
805 return irq;
806 /*
807 * Use the first all-but-pin matching entry as a
808 * best-guess fuzzy result for broken mptables.
809 */
810 if (best_guess < 0)
811 best_guess = irq;
812 }
813 }
814 return best_guess;
815 }
816 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
817
818 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
819 /*
820 * EISA Edge/Level control register, ELCR
821 */
822 static int EISA_ELCR(unsigned int irq)
823 {
824 if (irq < 16) {
825 unsigned int port = 0x4d0 + (irq >> 3);
826 return (inb(port) >> (irq & 7)) & 1;
827 }
828 apic_printk(APIC_VERBOSE, KERN_INFO
829 "Broken MPtable reports ISA irq %d\n", irq);
830 return 0;
831 }
832 #endif
833
834 /* ISA interrupts are always polarity zero edge triggered,
835 * when listed as conforming in the MP table. */
836
837 #define default_ISA_trigger(idx) (0)
838 #define default_ISA_polarity(idx) (0)
839
840 /* EISA interrupts are always polarity zero and can be edge or level
841 * trigger depending on the ELCR value. If an interrupt is listed as
842 * EISA conforming in the MP table, that means its trigger type must
843 * be read in from the ELCR */
844
845 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
846 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
847
848 /* PCI interrupts are always polarity one level triggered,
849 * when listed as conforming in the MP table. */
850
851 #define default_PCI_trigger(idx) (1)
852 #define default_PCI_polarity(idx) (1)
853
854 /* MCA interrupts are always polarity zero level triggered,
855 * when listed as conforming in the MP table. */
856
857 #define default_MCA_trigger(idx) (1)
858 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
859
860 static int MPBIOS_polarity(int idx)
861 {
862 int bus = mp_irqs[idx].mp_srcbus;
863 int polarity;
864
865 /*
866 * Determine IRQ line polarity (high active or low active):
867 */
868 switch (mp_irqs[idx].mp_irqflag & 3) {
869 case 0: /* conforms, ie. bus-type dependent polarity */
870 {
871 polarity = test_bit(bus, mp_bus_not_pci)?
872 default_ISA_polarity(idx):
873 default_PCI_polarity(idx);
874 break;
875 }
876 case 1: /* high active */
877 {
878 polarity = 0;
879 break;
880 }
881 case 2: /* reserved */
882 {
883 printk(KERN_WARNING "broken BIOS!!\n");
884 polarity = 1;
885 break;
886 }
887 case 3: /* low active */
888 {
889 polarity = 1;
890 break;
891 }
892 default: /* invalid */
893 {
894 printk(KERN_WARNING "broken BIOS!!\n");
895 polarity = 1;
896 break;
897 }
898 }
899 return polarity;
900 }
901
902 static int MPBIOS_trigger(int idx)
903 {
904 int bus = mp_irqs[idx].mp_srcbus;
905 int trigger;
906
907 /*
908 * Determine IRQ trigger mode (edge or level sensitive):
909 */
910 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
911 case 0: /* conforms, ie. bus-type dependent */
912 {
913 trigger = test_bit(bus, mp_bus_not_pci)?
914 default_ISA_trigger(idx):
915 default_PCI_trigger(idx);
916 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
917 switch (mp_bus_id_to_type[bus]) {
918 case MP_BUS_ISA: /* ISA pin */
919 {
920 /* set before the switch */
921 break;
922 }
923 case MP_BUS_EISA: /* EISA pin */
924 {
925 trigger = default_EISA_trigger(idx);
926 break;
927 }
928 case MP_BUS_PCI: /* PCI pin */
929 {
930 /* set before the switch */
931 break;
932 }
933 case MP_BUS_MCA: /* MCA pin */
934 {
935 trigger = default_MCA_trigger(idx);
936 break;
937 }
938 default:
939 {
940 printk(KERN_WARNING "broken BIOS!!\n");
941 trigger = 1;
942 break;
943 }
944 }
945 #endif
946 break;
947 }
948 case 1: /* edge */
949 {
950 trigger = 0;
951 break;
952 }
953 case 2: /* reserved */
954 {
955 printk(KERN_WARNING "broken BIOS!!\n");
956 trigger = 1;
957 break;
958 }
959 case 3: /* level */
960 {
961 trigger = 1;
962 break;
963 }
964 default: /* invalid */
965 {
966 printk(KERN_WARNING "broken BIOS!!\n");
967 trigger = 0;
968 break;
969 }
970 }
971 return trigger;
972 }
973
974 static inline int irq_polarity(int idx)
975 {
976 return MPBIOS_polarity(idx);
977 }
978
979 static inline int irq_trigger(int idx)
980 {
981 return MPBIOS_trigger(idx);
982 }
983
984 static int pin_2_irq(int idx, int apic, int pin)
985 {
986 int irq, i;
987 int bus = mp_irqs[idx].mp_srcbus;
988
989 /*
990 * Debugging check, we are in big trouble if this message pops up!
991 */
992 if (mp_irqs[idx].mp_dstirq != pin)
993 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
994
995 if (test_bit(bus, mp_bus_not_pci))
996 irq = mp_irqs[idx].mp_srcbusirq;
997 else {
998 /*
999 * PCI IRQs are mapped in order
1000 */
1001 i = irq = 0;
1002 while (i < apic)
1003 irq += nr_ioapic_registers[i++];
1004 irq += pin;
1005
1006 /*
1007 * For MPS mode, so far only needed by ES7000 platform
1008 */
1009 if (ioapic_renumber_irq)
1010 irq = ioapic_renumber_irq(apic, irq);
1011 }
1012
1013 /*
1014 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1015 */
1016 if ((pin >= 16) && (pin <= 23)) {
1017 if (pirq_entries[pin-16] != -1) {
1018 if (!pirq_entries[pin-16]) {
1019 apic_printk(APIC_VERBOSE, KERN_DEBUG
1020 "disabling PIRQ%d\n", pin-16);
1021 } else {
1022 irq = pirq_entries[pin-16];
1023 apic_printk(APIC_VERBOSE, KERN_DEBUG
1024 "using PIRQ%d -> IRQ %d\n",
1025 pin-16, irq);
1026 }
1027 }
1028 }
1029 return irq;
1030 }
1031
1032 static inline int IO_APIC_irq_trigger(int irq)
1033 {
1034 int apic, idx, pin;
1035
1036 for (apic = 0; apic < nr_ioapics; apic++) {
1037 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1038 idx = find_irq_entry(apic, pin, mp_INT);
1039 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1040 return irq_trigger(idx);
1041 }
1042 }
1043 /*
1044 * nonexistent IRQs are edge default
1045 */
1046 return 0;
1047 }
1048
1049 void lock_vector_lock(void)
1050 {
1051 /* Used to the online set of cpus does not change
1052 * during assign_irq_vector.
1053 */
1054 spin_lock(&vector_lock);
1055 }
1056
1057 void unlock_vector_lock(void)
1058 {
1059 spin_unlock(&vector_lock);
1060 }
1061
1062 static int __assign_irq_vector(int irq, cpumask_t mask)
1063 {
1064 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1065 unsigned int old_vector;
1066 int cpu;
1067 struct irq_cfg *cfg;
1068
1069 cfg = irq_cfg(irq);
1070
1071 /* Only try and allocate irqs on cpus that are present */
1072 cpus_and(mask, mask, cpu_online_map);
1073
1074 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1075 return -EBUSY;
1076
1077 old_vector = cfg->vector;
1078 if (old_vector) {
1079 cpumask_t tmp;
1080 cpus_and(tmp, cfg->domain, mask);
1081 if (!cpus_empty(tmp))
1082 return 0;
1083 }
1084
1085 for_each_cpu_mask_nr(cpu, mask) {
1086 cpumask_t domain, new_mask;
1087 int new_cpu;
1088 int vector, offset;
1089
1090 domain = vector_allocation_domain(cpu);
1091 cpus_and(new_mask, domain, cpu_online_map);
1092
1093 vector = current_vector;
1094 offset = current_offset;
1095 next:
1096 vector += 8;
1097 if (vector >= first_system_vector) {
1098 /* If we run out of vectors on large boxen, must share them. */
1099 offset = (offset + 1) % 8;
1100 vector = FIRST_DEVICE_VECTOR + offset;
1101 }
1102 if (unlikely(current_vector == vector))
1103 continue;
1104 if (vector == SYSCALL_VECTOR)
1105 goto next;
1106
1107 for_each_cpu_mask_nr(new_cpu, new_mask)
1108 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1109 goto next;
1110 /* Found one! */
1111 current_vector = vector;
1112 current_offset = offset;
1113 if (old_vector) {
1114 cfg->move_in_progress = 1;
1115 cfg->old_domain = cfg->domain;
1116 }
1117 for_each_cpu_mask_nr(new_cpu, new_mask)
1118 per_cpu(vector_irq, new_cpu)[vector] = irq;
1119 cfg->vector = vector;
1120 cfg->domain = domain;
1121 return 0;
1122 }
1123 return -ENOSPC;
1124 }
1125
1126 static int assign_irq_vector(int irq, cpumask_t mask)
1127 {
1128 int err;
1129 unsigned long flags;
1130
1131 spin_lock_irqsave(&vector_lock, flags);
1132 err = __assign_irq_vector(irq, mask);
1133 spin_unlock_irqrestore(&vector_lock, flags);
1134
1135 return err;
1136 }
1137
1138 static void __clear_irq_vector(int irq)
1139 {
1140 struct irq_cfg *cfg;
1141 cpumask_t mask;
1142 int cpu, vector;
1143
1144 cfg = irq_cfg(irq);
1145 BUG_ON(!cfg->vector);
1146
1147 vector = cfg->vector;
1148 cpus_and(mask, cfg->domain, cpu_online_map);
1149 for_each_cpu_mask_nr(cpu, mask)
1150 per_cpu(vector_irq, cpu)[vector] = -1;
1151
1152 cfg->vector = 0;
1153 cpus_clear(cfg->domain);
1154 }
1155
1156 void __setup_vector_irq(int cpu)
1157 {
1158 /* Initialize vector_irq on a new cpu */
1159 /* This function must be called with vector_lock held */
1160 int irq, vector;
1161 struct irq_cfg *cfg;
1162
1163 /* Mark the inuse vectors */
1164 for_each_irq_cfg(cfg) {
1165 if (!cpu_isset(cpu, cfg->domain))
1166 continue;
1167 vector = cfg->vector;
1168 irq = cfg->irq;
1169 per_cpu(vector_irq, cpu)[vector] = irq;
1170 }
1171 /* Mark the free vectors */
1172 for (vector = 0; vector < NR_VECTORS; ++vector) {
1173 irq = per_cpu(vector_irq, cpu)[vector];
1174 if (irq < 0)
1175 continue;
1176
1177 cfg = irq_cfg(irq);
1178 if (!cpu_isset(cpu, cfg->domain))
1179 per_cpu(vector_irq, cpu)[vector] = -1;
1180 }
1181 }
1182
1183 static struct irq_chip ioapic_chip;
1184
1185 #define IOAPIC_AUTO -1
1186 #define IOAPIC_EDGE 0
1187 #define IOAPIC_LEVEL 1
1188
1189 static void ioapic_register_intr(int irq, unsigned long trigger)
1190 {
1191 struct irq_desc *desc;
1192
1193 /* first time to use this irq_desc */
1194 if (irq < 16)
1195 desc = irq_to_desc(irq);
1196 else
1197 desc = irq_to_desc_alloc(irq);
1198
1199 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1200 trigger == IOAPIC_LEVEL) {
1201 desc->status |= IRQ_LEVEL;
1202 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1203 handle_fasteoi_irq, "fasteoi");
1204 } else {
1205 desc->status &= ~IRQ_LEVEL;
1206 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1207 handle_edge_irq, "edge");
1208 }
1209 }
1210
1211 static int setup_ioapic_entry(int apic, int irq,
1212 struct IO_APIC_route_entry *entry,
1213 unsigned int destination, int trigger,
1214 int polarity, int vector)
1215 {
1216 /*
1217 * add it to the IO-APIC irq-routing table:
1218 */
1219 memset(entry,0,sizeof(*entry));
1220
1221 entry->delivery_mode = INT_DELIVERY_MODE;
1222 entry->dest_mode = INT_DEST_MODE;
1223 entry->dest.logical.logical_dest = destination;
1224
1225 entry->mask = 0; /* enable IRQ */
1226 entry->trigger = trigger;
1227 entry->polarity = polarity;
1228 entry->vector = vector;
1229
1230 /* Mask level triggered irqs.
1231 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1232 */
1233 if (trigger)
1234 entry->mask = 1;
1235
1236 return 0;
1237 }
1238
1239 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1240 int trigger, int polarity)
1241 {
1242 struct irq_cfg *cfg;
1243 struct IO_APIC_route_entry entry;
1244 cpumask_t mask;
1245
1246 if (!IO_APIC_IRQ(irq))
1247 return;
1248
1249 cfg = irq_cfg(irq);
1250
1251 mask = TARGET_CPUS;
1252 if (assign_irq_vector(irq, mask))
1253 return;
1254
1255 cpus_and(mask, cfg->domain, mask);
1256
1257 apic_printk(APIC_VERBOSE,KERN_DEBUG
1258 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1259 "IRQ %d Mode:%i Active:%i)\n",
1260 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1261 irq, trigger, polarity);
1262
1263
1264 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1265 cpu_mask_to_apicid(mask), trigger, polarity,
1266 cfg->vector)) {
1267 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1268 mp_ioapics[apic].mp_apicid, pin);
1269 __clear_irq_vector(irq);
1270 return;
1271 }
1272
1273 ioapic_register_intr(irq, trigger);
1274 if (irq < 16)
1275 disable_8259A_irq(irq);
1276
1277 ioapic_write_entry(apic, pin, entry);
1278 }
1279
1280 static void __init setup_IO_APIC_irqs(void)
1281 {
1282 int apic, pin, idx, irq, first_notcon = 1;
1283
1284 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1285
1286 for (apic = 0; apic < nr_ioapics; apic++) {
1287 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1288
1289 idx = find_irq_entry(apic,pin,mp_INT);
1290 if (idx == -1) {
1291 if (first_notcon) {
1292 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1293 first_notcon = 0;
1294 } else
1295 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1296 continue;
1297 }
1298 if (!first_notcon) {
1299 apic_printk(APIC_VERBOSE, " not connected.\n");
1300 first_notcon = 1;
1301 }
1302
1303 irq = pin_2_irq(idx, apic, pin);
1304
1305 if (multi_timer_check(apic, irq))
1306 continue;
1307
1308 add_pin_to_irq(irq, apic, pin);
1309
1310 setup_IO_APIC_irq(apic, pin, irq,
1311 irq_trigger(idx), irq_polarity(idx));
1312 }
1313 }
1314
1315 if (!first_notcon)
1316 apic_printk(APIC_VERBOSE, " not connected.\n");
1317 }
1318
1319 /*
1320 * Set up the timer pin, possibly with the 8259A-master behind.
1321 */
1322 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1323 int vector)
1324 {
1325 struct IO_APIC_route_entry entry;
1326
1327 memset(&entry, 0, sizeof(entry));
1328
1329 /*
1330 * We use logical delivery to get the timer IRQ
1331 * to the first CPU.
1332 */
1333 entry.dest_mode = INT_DEST_MODE;
1334 entry.mask = 1; /* mask IRQ now */
1335 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1336 entry.delivery_mode = INT_DELIVERY_MODE;
1337 entry.polarity = 0;
1338 entry.trigger = 0;
1339 entry.vector = vector;
1340
1341 /*
1342 * The timer IRQ doesn't have to know that behind the
1343 * scene we may have a 8259A-master in AEOI mode ...
1344 */
1345 ioapic_register_intr(0, IOAPIC_EDGE);
1346
1347 /*
1348 * Add it to the IO-APIC irq-routing table:
1349 */
1350 ioapic_write_entry(apic, pin, entry);
1351 }
1352
1353
1354 __apicdebuginit(void) print_IO_APIC(void)
1355 {
1356 int apic, i;
1357 union IO_APIC_reg_00 reg_00;
1358 union IO_APIC_reg_01 reg_01;
1359 union IO_APIC_reg_02 reg_02;
1360 union IO_APIC_reg_03 reg_03;
1361 unsigned long flags;
1362 struct irq_cfg *cfg;
1363
1364 if (apic_verbosity == APIC_QUIET)
1365 return;
1366
1367 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1368 for (i = 0; i < nr_ioapics; i++)
1369 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1370 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1371
1372 /*
1373 * We are a bit conservative about what we expect. We have to
1374 * know about every hardware change ASAP.
1375 */
1376 printk(KERN_INFO "testing the IO APIC.......................\n");
1377
1378 for (apic = 0; apic < nr_ioapics; apic++) {
1379
1380 spin_lock_irqsave(&ioapic_lock, flags);
1381 reg_00.raw = io_apic_read(apic, 0);
1382 reg_01.raw = io_apic_read(apic, 1);
1383 if (reg_01.bits.version >= 0x10)
1384 reg_02.raw = io_apic_read(apic, 2);
1385 if (reg_01.bits.version >= 0x20)
1386 reg_03.raw = io_apic_read(apic, 3);
1387 spin_unlock_irqrestore(&ioapic_lock, flags);
1388
1389 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1390 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1391 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1392 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1393 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1394
1395 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1396 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1397
1398 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1399 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1400
1401 /*
1402 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1403 * but the value of reg_02 is read as the previous read register
1404 * value, so ignore it if reg_02 == reg_01.
1405 */
1406 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1407 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1408 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1409 }
1410
1411 /*
1412 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1413 * or reg_03, but the value of reg_0[23] is read as the previous read
1414 * register value, so ignore it if reg_03 == reg_0[12].
1415 */
1416 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1417 reg_03.raw != reg_01.raw) {
1418 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1419 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1420 }
1421
1422 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1423
1424 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1425 " Stat Dest Deli Vect: \n");
1426
1427 for (i = 0; i <= reg_01.bits.entries; i++) {
1428 struct IO_APIC_route_entry entry;
1429
1430 entry = ioapic_read_entry(apic, i);
1431
1432 printk(KERN_DEBUG " %02x %03X %02X ",
1433 i,
1434 entry.dest.logical.logical_dest,
1435 entry.dest.physical.physical_dest
1436 );
1437
1438 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1439 entry.mask,
1440 entry.trigger,
1441 entry.irr,
1442 entry.polarity,
1443 entry.delivery_status,
1444 entry.dest_mode,
1445 entry.delivery_mode,
1446 entry.vector
1447 );
1448 }
1449 }
1450 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1451 for_each_irq_cfg(cfg) {
1452 struct irq_pin_list *entry = cfg->irq_2_pin;
1453 if (!entry)
1454 continue;
1455 printk(KERN_DEBUG "IRQ%d ", i);
1456 for (;;) {
1457 printk("-> %d:%d", entry->apic, entry->pin);
1458 if (!entry->next)
1459 break;
1460 entry = entry->next;
1461 }
1462 printk("\n");
1463 }
1464
1465 printk(KERN_INFO ".................................... done.\n");
1466
1467 return;
1468 }
1469
1470 __apicdebuginit(void) print_APIC_bitfield(int base)
1471 {
1472 unsigned int v;
1473 int i, j;
1474
1475 if (apic_verbosity == APIC_QUIET)
1476 return;
1477
1478 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1479 for (i = 0; i < 8; i++) {
1480 v = apic_read(base + i*0x10);
1481 for (j = 0; j < 32; j++) {
1482 if (v & (1<<j))
1483 printk("1");
1484 else
1485 printk("0");
1486 }
1487 printk("\n");
1488 }
1489 }
1490
1491 __apicdebuginit(void) print_local_APIC(void *dummy)
1492 {
1493 unsigned int v, ver, maxlvt;
1494 u64 icr;
1495
1496 if (apic_verbosity == APIC_QUIET)
1497 return;
1498
1499 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1500 smp_processor_id(), hard_smp_processor_id());
1501 v = apic_read(APIC_ID);
1502 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1503 GET_APIC_ID(v));
1504 v = apic_read(APIC_LVR);
1505 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1506 ver = GET_APIC_VERSION(v);
1507 maxlvt = lapic_get_maxlvt();
1508
1509 v = apic_read(APIC_TASKPRI);
1510 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1511
1512 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1513 v = apic_read(APIC_ARBPRI);
1514 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1515 v & APIC_ARBPRI_MASK);
1516 v = apic_read(APIC_PROCPRI);
1517 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1518 }
1519
1520 v = apic_read(APIC_EOI);
1521 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1522 v = apic_read(APIC_RRR);
1523 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1524 v = apic_read(APIC_LDR);
1525 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1526 v = apic_read(APIC_DFR);
1527 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1528 v = apic_read(APIC_SPIV);
1529 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1530
1531 printk(KERN_DEBUG "... APIC ISR field:\n");
1532 print_APIC_bitfield(APIC_ISR);
1533 printk(KERN_DEBUG "... APIC TMR field:\n");
1534 print_APIC_bitfield(APIC_TMR);
1535 printk(KERN_DEBUG "... APIC IRR field:\n");
1536 print_APIC_bitfield(APIC_IRR);
1537
1538 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1539 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1540 apic_write(APIC_ESR, 0);
1541 v = apic_read(APIC_ESR);
1542 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1543 }
1544
1545 icr = apic_icr_read();
1546 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1547 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1548
1549 v = apic_read(APIC_LVTT);
1550 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1551
1552 if (maxlvt > 3) { /* PC is LVT#4. */
1553 v = apic_read(APIC_LVTPC);
1554 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1555 }
1556 v = apic_read(APIC_LVT0);
1557 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1558 v = apic_read(APIC_LVT1);
1559 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1560
1561 if (maxlvt > 2) { /* ERR is LVT#3. */
1562 v = apic_read(APIC_LVTERR);
1563 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1564 }
1565
1566 v = apic_read(APIC_TMICT);
1567 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1568 v = apic_read(APIC_TMCCT);
1569 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1570 v = apic_read(APIC_TDCR);
1571 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1572 printk("\n");
1573 }
1574
1575 __apicdebuginit(void) print_all_local_APICs(void)
1576 {
1577 on_each_cpu(print_local_APIC, NULL, 1);
1578 }
1579
1580 __apicdebuginit(void) print_PIC(void)
1581 {
1582 unsigned int v;
1583 unsigned long flags;
1584
1585 if (apic_verbosity == APIC_QUIET)
1586 return;
1587
1588 printk(KERN_DEBUG "\nprinting PIC contents\n");
1589
1590 spin_lock_irqsave(&i8259A_lock, flags);
1591
1592 v = inb(0xa1) << 8 | inb(0x21);
1593 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1594
1595 v = inb(0xa0) << 8 | inb(0x20);
1596 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1597
1598 outb(0x0b, 0xa0);
1599 outb(0x0b, 0x20);
1600 v = inb(0xa0) << 8 | inb(0x20);
1601 outb(0x0a, 0xa0);
1602 outb(0x0a, 0x20);
1603
1604 spin_unlock_irqrestore(&i8259A_lock, flags);
1605
1606 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1607
1608 v = inb(0x4d1) << 8 | inb(0x4d0);
1609 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1610 }
1611
1612 __apicdebuginit(int) print_all_ICs(void)
1613 {
1614 print_PIC();
1615 print_all_local_APICs();
1616 print_IO_APIC();
1617
1618 return 0;
1619 }
1620
1621 fs_initcall(print_all_ICs);
1622
1623
1624 static void __init enable_IO_APIC(void)
1625 {
1626 union IO_APIC_reg_01 reg_01;
1627 int i8259_apic, i8259_pin;
1628 int i, apic;
1629 unsigned long flags;
1630
1631 if (!pirqs_enabled)
1632 for (i = 0; i < MAX_PIRQS; i++)
1633 pirq_entries[i] = -1;
1634
1635 /*
1636 * The number of IO-APIC IRQ registers (== #pins):
1637 */
1638 for (apic = 0; apic < nr_ioapics; apic++) {
1639 spin_lock_irqsave(&ioapic_lock, flags);
1640 reg_01.raw = io_apic_read(apic, 1);
1641 spin_unlock_irqrestore(&ioapic_lock, flags);
1642 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1643 }
1644 for (apic = 0; apic < nr_ioapics; apic++) {
1645 int pin;
1646 /* See if any of the pins is in ExtINT mode */
1647 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1648 struct IO_APIC_route_entry entry;
1649 entry = ioapic_read_entry(apic, pin);
1650
1651
1652 /* If the interrupt line is enabled and in ExtInt mode
1653 * I have found the pin where the i8259 is connected.
1654 */
1655 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1656 ioapic_i8259.apic = apic;
1657 ioapic_i8259.pin = pin;
1658 goto found_i8259;
1659 }
1660 }
1661 }
1662 found_i8259:
1663 /* Look to see what if the MP table has reported the ExtINT */
1664 /* If we could not find the appropriate pin by looking at the ioapic
1665 * the i8259 probably is not connected the ioapic but give the
1666 * mptable a chance anyway.
1667 */
1668 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1669 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1670 /* Trust the MP table if nothing is setup in the hardware */
1671 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1672 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1673 ioapic_i8259.pin = i8259_pin;
1674 ioapic_i8259.apic = i8259_apic;
1675 }
1676 /* Complain if the MP table and the hardware disagree */
1677 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1678 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1679 {
1680 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1681 }
1682
1683 /*
1684 * Do not trust the IO-APIC being empty at bootup
1685 */
1686 clear_IO_APIC();
1687 }
1688
1689 /*
1690 * Not an __init, needed by the reboot code
1691 */
1692 void disable_IO_APIC(void)
1693 {
1694 /*
1695 * Clear the IO-APIC before rebooting:
1696 */
1697 clear_IO_APIC();
1698
1699 /*
1700 * If the i8259 is routed through an IOAPIC
1701 * Put that IOAPIC in virtual wire mode
1702 * so legacy interrupts can be delivered.
1703 */
1704 if (ioapic_i8259.pin != -1) {
1705 struct IO_APIC_route_entry entry;
1706
1707 memset(&entry, 0, sizeof(entry));
1708 entry.mask = 0; /* Enabled */
1709 entry.trigger = 0; /* Edge */
1710 entry.irr = 0;
1711 entry.polarity = 0; /* High */
1712 entry.delivery_status = 0;
1713 entry.dest_mode = 0; /* Physical */
1714 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1715 entry.vector = 0;
1716 entry.dest.physical.physical_dest = read_apic_id();
1717
1718 /*
1719 * Add it to the IO-APIC irq-routing table:
1720 */
1721 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1722 }
1723 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1724 }
1725
1726 /*
1727 * function to set the IO-APIC physical IDs based on the
1728 * values stored in the MPC table.
1729 *
1730 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1731 */
1732
1733 static void __init setup_ioapic_ids_from_mpc(void)
1734 {
1735 union IO_APIC_reg_00 reg_00;
1736 physid_mask_t phys_id_present_map;
1737 int apic;
1738 int i;
1739 unsigned char old_id;
1740 unsigned long flags;
1741
1742 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1743 return;
1744
1745 /*
1746 * Don't check I/O APIC IDs for xAPIC systems. They have
1747 * no meaning without the serial APIC bus.
1748 */
1749 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1750 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1751 return;
1752 /*
1753 * This is broken; anything with a real cpu count has to
1754 * circumvent this idiocy regardless.
1755 */
1756 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1757
1758 /*
1759 * Set the IOAPIC ID to the value stored in the MPC table.
1760 */
1761 for (apic = 0; apic < nr_ioapics; apic++) {
1762
1763 /* Read the register 0 value */
1764 spin_lock_irqsave(&ioapic_lock, flags);
1765 reg_00.raw = io_apic_read(apic, 0);
1766 spin_unlock_irqrestore(&ioapic_lock, flags);
1767
1768 old_id = mp_ioapics[apic].mp_apicid;
1769
1770 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1771 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1772 apic, mp_ioapics[apic].mp_apicid);
1773 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1774 reg_00.bits.ID);
1775 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1776 }
1777
1778 /*
1779 * Sanity check, is the ID really free? Every APIC in a
1780 * system must have a unique ID or we get lots of nice
1781 * 'stuck on smp_invalidate_needed IPI wait' messages.
1782 */
1783 if (check_apicid_used(phys_id_present_map,
1784 mp_ioapics[apic].mp_apicid)) {
1785 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1786 apic, mp_ioapics[apic].mp_apicid);
1787 for (i = 0; i < get_physical_broadcast(); i++)
1788 if (!physid_isset(i, phys_id_present_map))
1789 break;
1790 if (i >= get_physical_broadcast())
1791 panic("Max APIC ID exceeded!\n");
1792 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1793 i);
1794 physid_set(i, phys_id_present_map);
1795 mp_ioapics[apic].mp_apicid = i;
1796 } else {
1797 physid_mask_t tmp;
1798 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1799 apic_printk(APIC_VERBOSE, "Setting %d in the "
1800 "phys_id_present_map\n",
1801 mp_ioapics[apic].mp_apicid);
1802 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1803 }
1804
1805
1806 /*
1807 * We need to adjust the IRQ routing table
1808 * if the ID changed.
1809 */
1810 if (old_id != mp_ioapics[apic].mp_apicid)
1811 for (i = 0; i < mp_irq_entries; i++)
1812 if (mp_irqs[i].mp_dstapic == old_id)
1813 mp_irqs[i].mp_dstapic
1814 = mp_ioapics[apic].mp_apicid;
1815
1816 /*
1817 * Read the right value from the MPC table and
1818 * write it into the ID register.
1819 */
1820 apic_printk(APIC_VERBOSE, KERN_INFO
1821 "...changing IO-APIC physical APIC ID to %d ...",
1822 mp_ioapics[apic].mp_apicid);
1823
1824 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1825 spin_lock_irqsave(&ioapic_lock, flags);
1826 io_apic_write(apic, 0, reg_00.raw);
1827 spin_unlock_irqrestore(&ioapic_lock, flags);
1828
1829 /*
1830 * Sanity check
1831 */
1832 spin_lock_irqsave(&ioapic_lock, flags);
1833 reg_00.raw = io_apic_read(apic, 0);
1834 spin_unlock_irqrestore(&ioapic_lock, flags);
1835 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1836 printk("could not set ID!\n");
1837 else
1838 apic_printk(APIC_VERBOSE, " ok.\n");
1839 }
1840 }
1841
1842 int no_timer_check __initdata;
1843
1844 static int __init notimercheck(char *s)
1845 {
1846 no_timer_check = 1;
1847 return 1;
1848 }
1849 __setup("no_timer_check", notimercheck);
1850
1851 /*
1852 * There is a nasty bug in some older SMP boards, their mptable lies
1853 * about the timer IRQ. We do the following to work around the situation:
1854 *
1855 * - timer IRQ defaults to IO-APIC IRQ
1856 * - if this function detects that timer IRQs are defunct, then we fall
1857 * back to ISA timer IRQs
1858 */
1859 static int __init timer_irq_works(void)
1860 {
1861 unsigned long t1 = jiffies;
1862 unsigned long flags;
1863
1864 if (no_timer_check)
1865 return 1;
1866
1867 local_save_flags(flags);
1868 local_irq_enable();
1869 /* Let ten ticks pass... */
1870 mdelay((10 * 1000) / HZ);
1871 local_irq_restore(flags);
1872
1873 /*
1874 * Expect a few ticks at least, to be sure some possible
1875 * glue logic does not lock up after one or two first
1876 * ticks in a non-ExtINT mode. Also the local APIC
1877 * might have cached one ExtINT interrupt. Finally, at
1878 * least one tick may be lost due to delays.
1879 */
1880 if (time_after(jiffies, t1 + 4))
1881 return 1;
1882
1883 return 0;
1884 }
1885
1886 /*
1887 * In the SMP+IOAPIC case it might happen that there are an unspecified
1888 * number of pending IRQ events unhandled. These cases are very rare,
1889 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1890 * better to do it this way as thus we do not have to be aware of
1891 * 'pending' interrupts in the IRQ path, except at this point.
1892 */
1893 /*
1894 * Edge triggered needs to resend any interrupt
1895 * that was delayed but this is now handled in the device
1896 * independent code.
1897 */
1898
1899 /*
1900 * Startup quirk:
1901 *
1902 * Starting up a edge-triggered IO-APIC interrupt is
1903 * nasty - we need to make sure that we get the edge.
1904 * If it is already asserted for some reason, we need
1905 * return 1 to indicate that is was pending.
1906 *
1907 * This is not complete - we should be able to fake
1908 * an edge even if it isn't on the 8259A...
1909 *
1910 * (We do this for level-triggered IRQs too - it cannot hurt.)
1911 */
1912 static unsigned int startup_ioapic_irq(unsigned int irq)
1913 {
1914 int was_pending = 0;
1915 unsigned long flags;
1916
1917 spin_lock_irqsave(&ioapic_lock, flags);
1918 if (irq < 16) {
1919 disable_8259A_irq(irq);
1920 if (i8259A_irq_pending(irq))
1921 was_pending = 1;
1922 }
1923 __unmask_IO_APIC_irq(irq);
1924 spin_unlock_irqrestore(&ioapic_lock, flags);
1925
1926 return was_pending;
1927 }
1928
1929 static void irq_complete_move(unsigned int irq);
1930 static void ack_ioapic_irq(unsigned int irq)
1931 {
1932 irq_complete_move(irq);
1933 move_native_irq(irq);
1934 ack_APIC_irq();
1935 }
1936
1937 static void ack_ioapic_quirk_irq(unsigned int irq)
1938 {
1939 unsigned long v;
1940 int i;
1941
1942 irq_complete_move(irq);
1943 move_native_irq(irq);
1944 /*
1945 * It appears there is an erratum which affects at least version 0x11
1946 * of I/O APIC (that's the 82093AA and cores integrated into various
1947 * chipsets). Under certain conditions a level-triggered interrupt is
1948 * erroneously delivered as edge-triggered one but the respective IRR
1949 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1950 * message but it will never arrive and further interrupts are blocked
1951 * from the source. The exact reason is so far unknown, but the
1952 * phenomenon was observed when two consecutive interrupt requests
1953 * from a given source get delivered to the same CPU and the source is
1954 * temporarily disabled in between.
1955 *
1956 * A workaround is to simulate an EOI message manually. We achieve it
1957 * by setting the trigger mode to edge and then to level when the edge
1958 * trigger mode gets detected in the TMR of a local APIC for a
1959 * level-triggered interrupt. We mask the source for the time of the
1960 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1961 * The idea is from Manfred Spraul. --macro
1962 */
1963 i = irq_cfg(irq)->vector;
1964
1965 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1966
1967 ack_APIC_irq();
1968
1969 if (!(v & (1 << (i & 0x1f)))) {
1970 atomic_inc(&irq_mis_count);
1971 spin_lock(&ioapic_lock);
1972 __mask_and_edge_IO_APIC_irq(irq);
1973 __unmask_and_level_IO_APIC_irq(irq);
1974 spin_unlock(&ioapic_lock);
1975 }
1976 }
1977
1978 static int ioapic_retrigger_irq(unsigned int irq)
1979 {
1980 send_IPI_self(irq_cfg(irq)->vector);
1981
1982 return 1;
1983 }
1984
1985 #ifdef CONFIG_SMP
1986 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1987 {
1988 unsigned vector, me;
1989 ack_APIC_irq();
1990 irq_enter();
1991
1992 me = smp_processor_id();
1993 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1994 unsigned int irq;
1995 struct irq_desc *desc;
1996 struct irq_cfg *cfg;
1997 irq = __get_cpu_var(vector_irq)[vector];
1998
1999 desc = irq_to_desc(irq);
2000 if (!desc)
2001 continue;
2002
2003 cfg = irq_cfg(irq);
2004 spin_lock(&desc->lock);
2005 if (!cfg->move_cleanup_count)
2006 goto unlock;
2007
2008 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2009 goto unlock;
2010
2011 __get_cpu_var(vector_irq)[vector] = -1;
2012 cfg->move_cleanup_count--;
2013 unlock:
2014 spin_unlock(&desc->lock);
2015 }
2016
2017 irq_exit();
2018 }
2019
2020 static void irq_complete_move(unsigned int irq)
2021 {
2022 struct irq_cfg *cfg = irq_cfg(irq);
2023 unsigned vector, me;
2024
2025 if (likely(!cfg->move_in_progress))
2026 return;
2027
2028 vector = ~get_irq_regs()->orig_ax;
2029 me = smp_processor_id();
2030 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2031 cpumask_t cleanup_mask;
2032
2033 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2034 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2035 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2036 cfg->move_in_progress = 0;
2037 }
2038 }
2039 #else
2040 static inline void irq_complete_move(unsigned int irq) {}
2041 #endif
2042
2043 static struct irq_chip ioapic_chip __read_mostly = {
2044 .name = "IO-APIC",
2045 .startup = startup_ioapic_irq,
2046 .mask = mask_IO_APIC_irq,
2047 .unmask = unmask_IO_APIC_irq,
2048 .ack = ack_ioapic_irq,
2049 .eoi = ack_ioapic_quirk_irq,
2050 #ifdef CONFIG_SMP
2051 .set_affinity = set_ioapic_affinity_irq,
2052 #endif
2053 .retrigger = ioapic_retrigger_irq,
2054 };
2055
2056
2057 static inline void init_IO_APIC_traps(void)
2058 {
2059 int irq;
2060 struct irq_desc *desc;
2061 struct irq_cfg *cfg;
2062
2063 /*
2064 * NOTE! The local APIC isn't very good at handling
2065 * multiple interrupts at the same interrupt level.
2066 * As the interrupt level is determined by taking the
2067 * vector number and shifting that right by 4, we
2068 * want to spread these out a bit so that they don't
2069 * all fall in the same interrupt level.
2070 *
2071 * Also, we've got to be careful not to trash gate
2072 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2073 */
2074 for_each_irq_cfg(cfg) {
2075 irq = cfg->irq;
2076 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2077 /*
2078 * Hmm.. We don't have an entry for this,
2079 * so default to an old-fashioned 8259
2080 * interrupt if we can..
2081 */
2082 if (irq < 16)
2083 make_8259A_irq(irq);
2084 else {
2085 desc = irq_to_desc(irq);
2086 /* Strange. Oh, well.. */
2087 desc->chip = &no_irq_chip;
2088 }
2089 }
2090 }
2091 }
2092
2093 /*
2094 * The local APIC irq-chip implementation:
2095 */
2096
2097 static void ack_lapic_irq(unsigned int irq)
2098 {
2099 ack_APIC_irq();
2100 }
2101
2102 static void mask_lapic_irq(unsigned int irq)
2103 {
2104 unsigned long v;
2105
2106 v = apic_read(APIC_LVT0);
2107 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2108 }
2109
2110 static void unmask_lapic_irq(unsigned int irq)
2111 {
2112 unsigned long v;
2113
2114 v = apic_read(APIC_LVT0);
2115 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2116 }
2117
2118 static struct irq_chip lapic_chip __read_mostly = {
2119 .name = "local-APIC",
2120 .mask = mask_lapic_irq,
2121 .unmask = unmask_lapic_irq,
2122 .ack = ack_lapic_irq,
2123 };
2124
2125 static void lapic_register_intr(int irq)
2126 {
2127 struct irq_desc *desc;
2128
2129 desc = irq_to_desc(irq);
2130 desc->status &= ~IRQ_LEVEL;
2131 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2132 "edge");
2133 }
2134
2135 static void __init setup_nmi(void)
2136 {
2137 /*
2138 * Dirty trick to enable the NMI watchdog ...
2139 * We put the 8259A master into AEOI mode and
2140 * unmask on all local APICs LVT0 as NMI.
2141 *
2142 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2143 * is from Maciej W. Rozycki - so we do not have to EOI from
2144 * the NMI handler or the timer interrupt.
2145 */
2146 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2147
2148 enable_NMI_through_LVT0();
2149
2150 apic_printk(APIC_VERBOSE, " done.\n");
2151 }
2152
2153 /*
2154 * This looks a bit hackish but it's about the only one way of sending
2155 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2156 * not support the ExtINT mode, unfortunately. We need to send these
2157 * cycles as some i82489DX-based boards have glue logic that keeps the
2158 * 8259A interrupt line asserted until INTA. --macro
2159 */
2160 static inline void __init unlock_ExtINT_logic(void)
2161 {
2162 int apic, pin, i;
2163 struct IO_APIC_route_entry entry0, entry1;
2164 unsigned char save_control, save_freq_select;
2165
2166 pin = find_isa_irq_pin(8, mp_INT);
2167 if (pin == -1) {
2168 WARN_ON_ONCE(1);
2169 return;
2170 }
2171 apic = find_isa_irq_apic(8, mp_INT);
2172 if (apic == -1) {
2173 WARN_ON_ONCE(1);
2174 return;
2175 }
2176
2177 entry0 = ioapic_read_entry(apic, pin);
2178 clear_IO_APIC_pin(apic, pin);
2179
2180 memset(&entry1, 0, sizeof(entry1));
2181
2182 entry1.dest_mode = 0; /* physical delivery */
2183 entry1.mask = 0; /* unmask IRQ now */
2184 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2185 entry1.delivery_mode = dest_ExtINT;
2186 entry1.polarity = entry0.polarity;
2187 entry1.trigger = 0;
2188 entry1.vector = 0;
2189
2190 ioapic_write_entry(apic, pin, entry1);
2191
2192 save_control = CMOS_READ(RTC_CONTROL);
2193 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2194 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2195 RTC_FREQ_SELECT);
2196 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2197
2198 i = 100;
2199 while (i-- > 0) {
2200 mdelay(10);
2201 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2202 i -= 10;
2203 }
2204
2205 CMOS_WRITE(save_control, RTC_CONTROL);
2206 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2207 clear_IO_APIC_pin(apic, pin);
2208
2209 ioapic_write_entry(apic, pin, entry0);
2210 }
2211
2212 /*
2213 * This code may look a bit paranoid, but it's supposed to cooperate with
2214 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2215 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2216 * fanatically on his truly buggy board.
2217 */
2218 static inline void __init check_timer(void)
2219 {
2220 struct irq_cfg *cfg = irq_cfg(0);
2221 int apic1, pin1, apic2, pin2;
2222 int no_pin1 = 0;
2223 unsigned int ver;
2224 unsigned long flags;
2225
2226 local_irq_save(flags);
2227
2228 ver = apic_read(APIC_LVR);
2229 ver = GET_APIC_VERSION(ver);
2230
2231 /*
2232 * get/set the timer IRQ vector:
2233 */
2234 disable_8259A_irq(0);
2235 assign_irq_vector(0, TARGET_CPUS);
2236
2237 /*
2238 * As IRQ0 is to be enabled in the 8259A, the virtual
2239 * wire has to be disabled in the local APIC. Also
2240 * timer interrupts need to be acknowledged manually in
2241 * the 8259A for the i82489DX when using the NMI
2242 * watchdog as that APIC treats NMIs as level-triggered.
2243 * The AEOI mode will finish them in the 8259A
2244 * automatically.
2245 */
2246 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2247 init_8259A(1);
2248 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2249
2250 pin1 = find_isa_irq_pin(0, mp_INT);
2251 apic1 = find_isa_irq_apic(0, mp_INT);
2252 pin2 = ioapic_i8259.pin;
2253 apic2 = ioapic_i8259.apic;
2254
2255 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2256 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2257 cfg->vector, apic1, pin1, apic2, pin2);
2258
2259 /*
2260 * Some BIOS writers are clueless and report the ExtINTA
2261 * I/O APIC input from the cascaded 8259A as the timer
2262 * interrupt input. So just in case, if only one pin
2263 * was found above, try it both directly and through the
2264 * 8259A.
2265 */
2266 if (pin1 == -1) {
2267 pin1 = pin2;
2268 apic1 = apic2;
2269 no_pin1 = 1;
2270 } else if (pin2 == -1) {
2271 pin2 = pin1;
2272 apic2 = apic1;
2273 }
2274
2275 if (pin1 != -1) {
2276 /*
2277 * Ok, does IRQ0 through the IOAPIC work?
2278 */
2279 if (no_pin1) {
2280 add_pin_to_irq(0, apic1, pin1);
2281 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2282 }
2283 unmask_IO_APIC_irq(0);
2284 if (timer_irq_works()) {
2285 if (nmi_watchdog == NMI_IO_APIC) {
2286 setup_nmi();
2287 enable_8259A_irq(0);
2288 }
2289 if (disable_timer_pin_1 > 0)
2290 clear_IO_APIC_pin(0, pin1);
2291 goto out;
2292 }
2293 clear_IO_APIC_pin(apic1, pin1);
2294 if (!no_pin1)
2295 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2296 "8254 timer not connected to IO-APIC\n");
2297
2298 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2299 "(IRQ0) through the 8259A ...\n");
2300 apic_printk(APIC_QUIET, KERN_INFO
2301 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2302 /*
2303 * legacy devices should be connected to IO APIC #0
2304 */
2305 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2306 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2307 unmask_IO_APIC_irq(0);
2308 enable_8259A_irq(0);
2309 if (timer_irq_works()) {
2310 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2311 timer_through_8259 = 1;
2312 if (nmi_watchdog == NMI_IO_APIC) {
2313 disable_8259A_irq(0);
2314 setup_nmi();
2315 enable_8259A_irq(0);
2316 }
2317 goto out;
2318 }
2319 /*
2320 * Cleanup, just in case ...
2321 */
2322 disable_8259A_irq(0);
2323 clear_IO_APIC_pin(apic2, pin2);
2324 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2325 }
2326
2327 if (nmi_watchdog == NMI_IO_APIC) {
2328 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2329 "through the IO-APIC - disabling NMI Watchdog!\n");
2330 nmi_watchdog = NMI_NONE;
2331 }
2332 timer_ack = 0;
2333
2334 apic_printk(APIC_QUIET, KERN_INFO
2335 "...trying to set up timer as Virtual Wire IRQ...\n");
2336
2337 lapic_register_intr(0);
2338 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2339 enable_8259A_irq(0);
2340
2341 if (timer_irq_works()) {
2342 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2343 goto out;
2344 }
2345 disable_8259A_irq(0);
2346 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2347 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2348
2349 apic_printk(APIC_QUIET, KERN_INFO
2350 "...trying to set up timer as ExtINT IRQ...\n");
2351
2352 init_8259A(0);
2353 make_8259A_irq(0);
2354 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2355
2356 unlock_ExtINT_logic();
2357
2358 if (timer_irq_works()) {
2359 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2360 goto out;
2361 }
2362 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2363 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2364 "report. Then try booting with the 'noapic' option.\n");
2365 out:
2366 local_irq_restore(flags);
2367 }
2368
2369 /*
2370 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2371 * to devices. However there may be an I/O APIC pin available for
2372 * this interrupt regardless. The pin may be left unconnected, but
2373 * typically it will be reused as an ExtINT cascade interrupt for
2374 * the master 8259A. In the MPS case such a pin will normally be
2375 * reported as an ExtINT interrupt in the MP table. With ACPI
2376 * there is no provision for ExtINT interrupts, and in the absence
2377 * of an override it would be treated as an ordinary ISA I/O APIC
2378 * interrupt, that is edge-triggered and unmasked by default. We
2379 * used to do this, but it caused problems on some systems because
2380 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2381 * the same ExtINT cascade interrupt to drive the local APIC of the
2382 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2383 * the I/O APIC in all cases now. No actual device should request
2384 * it anyway. --macro
2385 */
2386 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2387
2388 void __init setup_IO_APIC(void)
2389 {
2390 enable_IO_APIC();
2391
2392 io_apic_irqs = ~PIC_IRQS;
2393
2394 printk("ENABLING IO-APIC IRQs\n");
2395
2396 /*
2397 * Set up IO-APIC IRQ routing.
2398 */
2399 if (!acpi_ioapic)
2400 setup_ioapic_ids_from_mpc();
2401 sync_Arb_IDs();
2402 setup_IO_APIC_irqs();
2403 init_IO_APIC_traps();
2404 check_timer();
2405 }
2406
2407 /*
2408 * Called after all the initialization is done. If we didnt find any
2409 * APIC bugs then we can allow the modify fast path
2410 */
2411
2412 static int __init io_apic_bug_finalize(void)
2413 {
2414 if (sis_apic_bug == -1)
2415 sis_apic_bug = 0;
2416 return 0;
2417 }
2418
2419 late_initcall(io_apic_bug_finalize);
2420
2421 struct sysfs_ioapic_data {
2422 struct sys_device dev;
2423 struct IO_APIC_route_entry entry[0];
2424 };
2425 static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2426
2427 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2428 {
2429 struct IO_APIC_route_entry *entry;
2430 struct sysfs_ioapic_data *data;
2431 int i;
2432
2433 data = container_of(dev, struct sysfs_ioapic_data, dev);
2434 entry = data->entry;
2435 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2436 entry[i] = ioapic_read_entry(dev->id, i);
2437
2438 return 0;
2439 }
2440
2441 static int ioapic_resume(struct sys_device *dev)
2442 {
2443 struct IO_APIC_route_entry *entry;
2444 struct sysfs_ioapic_data *data;
2445 unsigned long flags;
2446 union IO_APIC_reg_00 reg_00;
2447 int i;
2448
2449 data = container_of(dev, struct sysfs_ioapic_data, dev);
2450 entry = data->entry;
2451
2452 spin_lock_irqsave(&ioapic_lock, flags);
2453 reg_00.raw = io_apic_read(dev->id, 0);
2454 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2455 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2456 io_apic_write(dev->id, 0, reg_00.raw);
2457 }
2458 spin_unlock_irqrestore(&ioapic_lock, flags);
2459 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2460 ioapic_write_entry(dev->id, i, entry[i]);
2461
2462 return 0;
2463 }
2464
2465 static struct sysdev_class ioapic_sysdev_class = {
2466 .name = "ioapic",
2467 .suspend = ioapic_suspend,
2468 .resume = ioapic_resume,
2469 };
2470
2471 static int __init ioapic_init_sysfs(void)
2472 {
2473 struct sys_device *dev;
2474 int i, size, error = 0;
2475
2476 error = sysdev_class_register(&ioapic_sysdev_class);
2477 if (error)
2478 return error;
2479
2480 for (i = 0; i < nr_ioapics; i++) {
2481 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2482 * sizeof(struct IO_APIC_route_entry);
2483 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2484 if (!mp_ioapic_data[i]) {
2485 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2486 continue;
2487 }
2488 dev = &mp_ioapic_data[i]->dev;
2489 dev->id = i;
2490 dev->cls = &ioapic_sysdev_class;
2491 error = sysdev_register(dev);
2492 if (error) {
2493 kfree(mp_ioapic_data[i]);
2494 mp_ioapic_data[i] = NULL;
2495 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2496 continue;
2497 }
2498 }
2499
2500 return 0;
2501 }
2502
2503 device_initcall(ioapic_init_sysfs);
2504
2505 /*
2506 * Dynamic irq allocate and deallocation
2507 */
2508 unsigned int create_irq_nr(unsigned int irq_want)
2509 {
2510 /* Allocate an unused irq */
2511 unsigned int irq, new;
2512 unsigned long flags;
2513 struct irq_cfg *cfg_new;
2514
2515 #ifndef CONFIG_HAVE_SPARSE_IRQ
2516 /* only can use bus/dev/fn.. when per_cpu vector is used */
2517 irq_want = nr_irqs - 1;
2518 #endif
2519
2520 irq = 0;
2521 spin_lock_irqsave(&vector_lock, flags);
2522 for (new = (nr_irqs - 1); new > 0; new--) {
2523 if (platform_legacy_irq(new))
2524 continue;
2525 cfg_new = irq_cfg(new);
2526 if (cfg_new && cfg_new->vector != 0)
2527 continue;
2528 if (!cfg_new)
2529 cfg_new = irq_cfg_alloc(new);
2530 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2531 irq = new;
2532 break;
2533 }
2534 spin_unlock_irqrestore(&vector_lock, flags);
2535
2536 if (irq > 0) {
2537 dynamic_irq_init(irq);
2538 }
2539 return irq;
2540 }
2541
2542 int create_irq(void)
2543 {
2544 return create_irq_nr(nr_irqs - 1);
2545 }
2546
2547 void destroy_irq(unsigned int irq)
2548 {
2549 unsigned long flags;
2550
2551 dynamic_irq_cleanup(irq);
2552
2553 spin_lock_irqsave(&vector_lock, flags);
2554 __clear_irq_vector(irq);
2555 spin_unlock_irqrestore(&vector_lock, flags);
2556 }
2557
2558 /*
2559 * MSI message composition
2560 */
2561 #ifdef CONFIG_PCI_MSI
2562 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2563 {
2564 struct irq_cfg *cfg;
2565 int err;
2566 unsigned dest;
2567 cpumask_t tmp;
2568
2569 tmp = TARGET_CPUS;
2570 err = assign_irq_vector(irq, tmp);
2571 if (err)
2572 return err;
2573
2574 cfg = irq_cfg(irq);
2575 cpus_and(tmp, cfg->domain, tmp);
2576 dest = cpu_mask_to_apicid(tmp);
2577
2578 msg->address_hi = MSI_ADDR_BASE_HI;
2579 msg->address_lo =
2580 MSI_ADDR_BASE_LO |
2581 ((INT_DEST_MODE == 0) ?
2582 MSI_ADDR_DEST_MODE_PHYSICAL:
2583 MSI_ADDR_DEST_MODE_LOGICAL) |
2584 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2585 MSI_ADDR_REDIRECTION_CPU:
2586 MSI_ADDR_REDIRECTION_LOWPRI) |
2587 MSI_ADDR_DEST_ID(dest);
2588
2589 msg->data =
2590 MSI_DATA_TRIGGER_EDGE |
2591 MSI_DATA_LEVEL_ASSERT |
2592 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2593 MSI_DATA_DELIVERY_FIXED:
2594 MSI_DATA_DELIVERY_LOWPRI) |
2595 MSI_DATA_VECTOR(cfg->vector);
2596
2597 return err;
2598 }
2599
2600 #ifdef CONFIG_SMP
2601 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2602 {
2603 struct irq_cfg *cfg;
2604 struct msi_msg msg;
2605 unsigned int dest;
2606 cpumask_t tmp;
2607
2608 cpus_and(tmp, mask, cpu_online_map);
2609 if (cpus_empty(tmp))
2610 return;
2611
2612 if (assign_irq_vector(irq, mask))
2613 return;
2614
2615 cfg = irq_cfg(irq);
2616 cpus_and(tmp, cfg->domain, mask);
2617 dest = cpu_mask_to_apicid(tmp);
2618
2619 read_msi_msg(irq, &msg);
2620
2621 msg.data &= ~MSI_DATA_VECTOR_MASK;
2622 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2623 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2624 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2625
2626 write_msi_msg(irq, &msg);
2627 irq_to_desc(irq)->affinity = mask;
2628 }
2629 #endif /* CONFIG_SMP */
2630
2631 /*
2632 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2633 * which implement the MSI or MSI-X Capability Structure.
2634 */
2635 static struct irq_chip msi_chip = {
2636 .name = "PCI-MSI",
2637 .unmask = unmask_msi_irq,
2638 .mask = mask_msi_irq,
2639 .ack = ack_ioapic_irq,
2640 #ifdef CONFIG_SMP
2641 .set_affinity = set_msi_irq_affinity,
2642 #endif
2643 .retrigger = ioapic_retrigger_irq,
2644 };
2645
2646 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2647 {
2648 unsigned int irq;
2649
2650 irq = dev->bus->number;
2651 irq <<= 8;
2652 irq |= dev->devfn;
2653 irq <<= 12;
2654
2655 return irq;
2656 }
2657
2658 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2659 {
2660 struct msi_msg msg;
2661 int irq, ret;
2662
2663 unsigned int irq_want;
2664
2665 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2666
2667 irq = create_irq_nr(irq_want);
2668
2669 if (irq == 0)
2670 return -1;
2671
2672 ret = msi_compose_msg(dev, irq, &msg);
2673 if (ret < 0) {
2674 destroy_irq(irq);
2675 return ret;
2676 }
2677
2678 set_irq_msi(irq, desc);
2679 write_msi_msg(irq, &msg);
2680
2681 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2682 "edge");
2683
2684 return 0;
2685 }
2686
2687 void arch_teardown_msi_irq(unsigned int irq)
2688 {
2689 destroy_irq(irq);
2690 }
2691
2692 #endif /* CONFIG_PCI_MSI */
2693
2694 /*
2695 * Hypertransport interrupt support
2696 */
2697 #ifdef CONFIG_HT_IRQ
2698
2699 #ifdef CONFIG_SMP
2700
2701 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2702 {
2703 struct ht_irq_msg msg;
2704 fetch_ht_irq_msg(irq, &msg);
2705
2706 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2707 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2708
2709 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2710 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2711
2712 write_ht_irq_msg(irq, &msg);
2713 }
2714
2715 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2716 {
2717 struct irq_cfg *cfg;
2718 unsigned int dest;
2719 cpumask_t tmp;
2720
2721 cpus_and(tmp, mask, cpu_online_map);
2722 if (cpus_empty(tmp))
2723 return;
2724
2725 if (assign_irq_vector(irq, mask))
2726 return;
2727
2728 cfg = irq_cfg(irq);
2729 cpus_and(tmp, cfg->domain, mask);
2730 dest = cpu_mask_to_apicid(tmp);
2731
2732 target_ht_irq(irq, dest, cfg->vector);
2733 irq_to_desc(irq)->affinity = mask;
2734 }
2735 #endif
2736
2737 static struct irq_chip ht_irq_chip = {
2738 .name = "PCI-HT",
2739 .mask = mask_ht_irq,
2740 .unmask = unmask_ht_irq,
2741 .ack = ack_ioapic_irq,
2742 #ifdef CONFIG_SMP
2743 .set_affinity = set_ht_irq_affinity,
2744 #endif
2745 .retrigger = ioapic_retrigger_irq,
2746 };
2747
2748 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2749 {
2750 struct irq_cfg *cfg;
2751 int err;
2752 cpumask_t tmp;
2753
2754 tmp = TARGET_CPUS;
2755 err = assign_irq_vector(irq, tmp);
2756 if ( !err) {
2757 struct ht_irq_msg msg;
2758 unsigned dest;
2759
2760 cfg = irq_cfg(irq);
2761 cpus_and(tmp, cfg->domain, tmp);
2762 dest = cpu_mask_to_apicid(tmp);
2763
2764 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2765
2766 msg.address_lo =
2767 HT_IRQ_LOW_BASE |
2768 HT_IRQ_LOW_DEST_ID(dest) |
2769 HT_IRQ_LOW_VECTOR(cfg->vector) |
2770 ((INT_DEST_MODE == 0) ?
2771 HT_IRQ_LOW_DM_PHYSICAL :
2772 HT_IRQ_LOW_DM_LOGICAL) |
2773 HT_IRQ_LOW_RQEOI_EDGE |
2774 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2775 HT_IRQ_LOW_MT_FIXED :
2776 HT_IRQ_LOW_MT_ARBITRATED) |
2777 HT_IRQ_LOW_IRQ_MASKED;
2778
2779 write_ht_irq_msg(irq, &msg);
2780
2781 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2782 handle_edge_irq, "edge");
2783 }
2784 return err;
2785 }
2786 #endif /* CONFIG_HT_IRQ */
2787
2788 /* --------------------------------------------------------------------------
2789 ACPI-based IOAPIC Configuration
2790 -------------------------------------------------------------------------- */
2791
2792 #ifdef CONFIG_ACPI
2793
2794 int __init io_apic_get_unique_id(int ioapic, int apic_id)
2795 {
2796 union IO_APIC_reg_00 reg_00;
2797 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2798 physid_mask_t tmp;
2799 unsigned long flags;
2800 int i = 0;
2801
2802 /*
2803 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2804 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2805 * supports up to 16 on one shared APIC bus.
2806 *
2807 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2808 * advantage of new APIC bus architecture.
2809 */
2810
2811 if (physids_empty(apic_id_map))
2812 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2813
2814 spin_lock_irqsave(&ioapic_lock, flags);
2815 reg_00.raw = io_apic_read(ioapic, 0);
2816 spin_unlock_irqrestore(&ioapic_lock, flags);
2817
2818 if (apic_id >= get_physical_broadcast()) {
2819 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2820 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2821 apic_id = reg_00.bits.ID;
2822 }
2823
2824 /*
2825 * Every APIC in a system must have a unique ID or we get lots of nice
2826 * 'stuck on smp_invalidate_needed IPI wait' messages.
2827 */
2828 if (check_apicid_used(apic_id_map, apic_id)) {
2829
2830 for (i = 0; i < get_physical_broadcast(); i++) {
2831 if (!check_apicid_used(apic_id_map, i))
2832 break;
2833 }
2834
2835 if (i == get_physical_broadcast())
2836 panic("Max apic_id exceeded!\n");
2837
2838 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2839 "trying %d\n", ioapic, apic_id, i);
2840
2841 apic_id = i;
2842 }
2843
2844 tmp = apicid_to_cpu_present(apic_id);
2845 physids_or(apic_id_map, apic_id_map, tmp);
2846
2847 if (reg_00.bits.ID != apic_id) {
2848 reg_00.bits.ID = apic_id;
2849
2850 spin_lock_irqsave(&ioapic_lock, flags);
2851 io_apic_write(ioapic, 0, reg_00.raw);
2852 reg_00.raw = io_apic_read(ioapic, 0);
2853 spin_unlock_irqrestore(&ioapic_lock, flags);
2854
2855 /* Sanity check */
2856 if (reg_00.bits.ID != apic_id) {
2857 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2858 return -1;
2859 }
2860 }
2861
2862 apic_printk(APIC_VERBOSE, KERN_INFO
2863 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2864
2865 return apic_id;
2866 }
2867
2868
2869 int __init io_apic_get_version(int ioapic)
2870 {
2871 union IO_APIC_reg_01 reg_01;
2872 unsigned long flags;
2873
2874 spin_lock_irqsave(&ioapic_lock, flags);
2875 reg_01.raw = io_apic_read(ioapic, 1);
2876 spin_unlock_irqrestore(&ioapic_lock, flags);
2877
2878 return reg_01.bits.version;
2879 }
2880
2881
2882 int __init io_apic_get_redir_entries(int ioapic)
2883 {
2884 union IO_APIC_reg_01 reg_01;
2885 unsigned long flags;
2886
2887 spin_lock_irqsave(&ioapic_lock, flags);
2888 reg_01.raw = io_apic_read(ioapic, 1);
2889 spin_unlock_irqrestore(&ioapic_lock, flags);
2890
2891 return reg_01.bits.entries;
2892 }
2893
2894
2895 int io_apic_set_pci_routing(int ioapic, int pin, int irq, int triggering, int polarity)
2896 {
2897 if (!IO_APIC_IRQ(irq)) {
2898 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2899 ioapic);
2900 return -EINVAL;
2901 }
2902
2903 /*
2904 * IRQs < 16 are already in the irq_2_pin[] map
2905 */
2906 if (irq >= 16)
2907 add_pin_to_irq(irq, ioapic, pin);
2908
2909 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2910
2911 return 0;
2912 }
2913
2914 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2915 {
2916 int i;
2917
2918 if (skip_ioapic_setup)
2919 return -1;
2920
2921 for (i = 0; i < mp_irq_entries; i++)
2922 if (mp_irqs[i].mp_irqtype == mp_INT &&
2923 mp_irqs[i].mp_srcbusirq == bus_irq)
2924 break;
2925 if (i >= mp_irq_entries)
2926 return -1;
2927
2928 *trigger = irq_trigger(i);
2929 *polarity = irq_polarity(i);
2930 return 0;
2931 }
2932
2933 #endif /* CONFIG_ACPI */
2934
2935 /*
2936 * This function currently is only a helper for the i386 smp boot process where
2937 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2938 * so mask in all cases should simply be TARGET_CPUS
2939 */
2940 #ifdef CONFIG_SMP
2941 void __init setup_ioapic_dest(void)
2942 {
2943 int pin, ioapic, irq, irq_entry;
2944 struct irq_cfg *cfg;
2945 struct irq_desc *desc;
2946
2947 if (skip_ioapic_setup == 1)
2948 return;
2949
2950 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2951 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2952 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2953 if (irq_entry == -1)
2954 continue;
2955 irq = pin_2_irq(irq_entry, ioapic, pin);
2956
2957 /* setup_IO_APIC_irqs could fail to get vector for some device
2958 * when you have too many devices, because at that time only boot
2959 * cpu is online.
2960 */
2961 cfg = irq_cfg(irq);
2962 if (!cfg->vector)
2963 setup_IO_APIC_irq(ioapic, pin, irq,
2964 irq_trigger(irq_entry),
2965 irq_polarity(irq_entry));
2966 else {
2967 desc = irq_to_desc(irq);
2968 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2969 }
2970 }
2971
2972 }
2973 }
2974 #endif
2975
2976 static int __init parse_disable_timer_pin_1(char *arg)
2977 {
2978 disable_timer_pin_1 = 1;
2979 return 0;
2980 }
2981 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2982
2983 static int __init parse_enable_timer_pin_1(char *arg)
2984 {
2985 disable_timer_pin_1 = -1;
2986 return 0;
2987 }
2988 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2989
2990 static int __init parse_noapic(char *arg)
2991 {
2992 /* disable IO-APIC */
2993 disable_ioapic_setup();
2994 return 0;
2995 }
2996 early_param("noapic", parse_noapic);
2997
2998 void __init ioapic_init_mappings(void)
2999 {
3000 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3001 int i;
3002
3003 for (i = 0; i < nr_ioapics; i++) {
3004 if (smp_found_config) {
3005 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3006 if (!ioapic_phys) {
3007 printk(KERN_ERR
3008 "WARNING: bogus zero IO-APIC "
3009 "address found in MPTABLE, "
3010 "disabling IO/APIC support!\n");
3011 smp_found_config = 0;
3012 skip_ioapic_setup = 1;
3013 goto fake_ioapic_page;
3014 }
3015 } else {
3016 fake_ioapic_page:
3017 ioapic_phys = (unsigned long)
3018 alloc_bootmem_pages(PAGE_SIZE);
3019 ioapic_phys = __pa(ioapic_phys);
3020 }
3021 set_fixmap_nocache(idx, ioapic_phys);
3022 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
3023 __fix_to_virt(idx), ioapic_phys);
3024 idx++;
3025 }
3026 }
3027
Linux kernel - Deliverables
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