2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
42 #include <asm/timer.h>
43 #include <asm/i8259.h>
45 #include <asm/msidef.h>
46 #include <asm/hypertransport.h>
48 #include <mach_apic.h>
49 #include <mach_apicdef.h>
53 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
54 atomic_t irq_mis_count
;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
59 static DEFINE_SPINLOCK(ioapic_lock
);
60 static DEFINE_SPINLOCK(vector_lock
);
62 int timer_over_8254 __initdata
= 1;
65 * Is the SiS APIC rmw bug present ?
66 * -1 = don't know, 0 = no, 1 = yes
68 int sis_apic_bug
= -1;
71 * # of IRQ routing registers
73 int nr_ioapic_registers
[MAX_IO_APICS
];
75 static int disable_timer_pin_1 __initdata
;
78 * Rough estimation of how many shared IRQs there are, can
81 #define MAX_PLUS_SHARED_IRQS NR_IRQS
82 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
85 * This is performance-critical, we want to do it O(1)
87 * the indexing order of this array favors 1:1 mappings
88 * between pins and IRQs.
91 static struct irq_pin_list
{
93 } irq_2_pin
[PIN_MAP_SIZE
];
97 unsigned int unused
[3];
101 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
103 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
104 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
107 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
109 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
110 writel(reg
, &io_apic
->index
);
111 return readl(&io_apic
->data
);
114 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
116 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
117 writel(reg
, &io_apic
->index
);
118 writel(value
, &io_apic
->data
);
122 * Re-write a value: to be used for read-modify-write
123 * cycles where the read already set up the index register.
125 * Older SiS APIC requires we rewrite the index register
127 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
129 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
131 writel(reg
, &io_apic
->index
);
132 writel(value
, &io_apic
->data
);
136 struct { u32 w1
, w2
; };
137 struct IO_APIC_route_entry entry
;
140 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
142 union entry_union eu
;
144 spin_lock_irqsave(&ioapic_lock
, flags
);
145 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
146 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
147 spin_unlock_irqrestore(&ioapic_lock
, flags
);
152 * When we write a new IO APIC routing entry, we need to write the high
153 * word first! If the mask bit in the low word is clear, we will enable
154 * the interrupt, and we need to make sure the entry is fully populated
155 * before that happens.
158 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
160 union entry_union eu
;
162 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
163 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
166 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
169 spin_lock_irqsave(&ioapic_lock
, flags
);
170 __ioapic_write_entry(apic
, pin
, e
);
171 spin_unlock_irqrestore(&ioapic_lock
, flags
);
175 * When we mask an IO APIC routing entry, we need to write the low
176 * word first, in order to set the mask bit before we change the
179 static void ioapic_mask_entry(int apic
, int pin
)
182 union entry_union eu
= { .entry
.mask
= 1 };
184 spin_lock_irqsave(&ioapic_lock
, flags
);
185 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
186 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
187 spin_unlock_irqrestore(&ioapic_lock
, flags
);
191 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
192 * shared ISA-space IRQs, so we have to support them. We are super
193 * fast in the common case, and fast for shared ISA-space IRQs.
195 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
197 static int first_free_entry
= NR_IRQS
;
198 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
201 entry
= irq_2_pin
+ entry
->next
;
203 if (entry
->pin
!= -1) {
204 entry
->next
= first_free_entry
;
205 entry
= irq_2_pin
+ entry
->next
;
206 if (++first_free_entry
>= PIN_MAP_SIZE
)
207 panic("io_apic.c: whoops");
214 * Reroute an IRQ to a different pin.
216 static void __init
replace_pin_at_irq(unsigned int irq
,
217 int oldapic
, int oldpin
,
218 int newapic
, int newpin
)
220 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
223 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
224 entry
->apic
= newapic
;
229 entry
= irq_2_pin
+ entry
->next
;
233 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
235 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
236 unsigned int pin
, reg
;
242 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
245 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
248 entry
= irq_2_pin
+ entry
->next
;
253 static void __mask_IO_APIC_irq (unsigned int irq
)
255 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
259 static void __unmask_IO_APIC_irq (unsigned int irq
)
261 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
264 /* mask = 1, trigger = 0 */
265 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
267 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
270 /* mask = 0, trigger = 1 */
271 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
273 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
276 static void mask_IO_APIC_irq (unsigned int irq
)
280 spin_lock_irqsave(&ioapic_lock
, flags
);
281 __mask_IO_APIC_irq(irq
);
282 spin_unlock_irqrestore(&ioapic_lock
, flags
);
285 static void unmask_IO_APIC_irq (unsigned int irq
)
289 spin_lock_irqsave(&ioapic_lock
, flags
);
290 __unmask_IO_APIC_irq(irq
);
291 spin_unlock_irqrestore(&ioapic_lock
, flags
);
294 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
296 struct IO_APIC_route_entry entry
;
298 /* Check delivery_mode to be sure we're not clearing an SMI pin */
299 entry
= ioapic_read_entry(apic
, pin
);
300 if (entry
.delivery_mode
== dest_SMI
)
304 * Disable it in the IO-APIC irq-routing table:
306 ioapic_mask_entry(apic
, pin
);
309 static void clear_IO_APIC (void)
313 for (apic
= 0; apic
< nr_ioapics
; apic
++)
314 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
315 clear_IO_APIC_pin(apic
, pin
);
319 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
323 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
324 unsigned int apicid_value
;
327 cpus_and(tmp
, cpumask
, cpu_online_map
);
331 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
333 apicid_value
= cpu_mask_to_apicid(cpumask
);
334 /* Prepare to do the io_apic_write */
335 apicid_value
= apicid_value
<< 24;
336 spin_lock_irqsave(&ioapic_lock
, flags
);
341 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
344 entry
= irq_2_pin
+ entry
->next
;
346 irq_desc
[irq
].affinity
= cpumask
;
347 spin_unlock_irqrestore(&ioapic_lock
, flags
);
350 #if defined(CONFIG_IRQBALANCE)
351 # include <asm/processor.h> /* kernel_thread() */
352 # include <linux/kernel_stat.h> /* kstat */
353 # include <linux/slab.h> /* kmalloc() */
354 # include <linux/timer.h> /* time_after() */
356 #define IRQBALANCE_CHECK_ARCH -999
357 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
358 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
359 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
360 #define BALANCED_IRQ_LESS_DELTA (HZ)
362 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
363 static int physical_balance __read_mostly
;
364 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
366 static struct irq_cpu_info
{
367 unsigned long * last_irq
;
368 unsigned long * irq_delta
;
370 } irq_cpu_data
[NR_CPUS
];
372 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
373 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
374 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
376 #define IDLE_ENOUGH(cpu,now) \
377 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
379 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
381 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
383 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
384 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
387 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
389 balance_irq_affinity
[irq
] = mask
;
392 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
393 unsigned long now
, int direction
)
401 if (unlikely(cpu
== curr_cpu
))
404 if (direction
== 1) {
413 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
414 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
419 static inline void balance_irq(int cpu
, int irq
)
421 unsigned long now
= jiffies
;
422 cpumask_t allowed_mask
;
423 unsigned int new_cpu
;
425 if (irqbalance_disabled
)
428 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
429 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
430 if (cpu
!= new_cpu
) {
431 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
435 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
439 for_each_online_cpu(i
) {
440 for (j
= 0; j
< NR_IRQS
; j
++) {
441 if (!irq_desc
[j
].action
)
443 /* Is it a significant load ? */
444 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
445 useful_load_threshold
)
450 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
451 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
455 static void do_irq_balance(void)
458 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
459 unsigned long move_this_load
= 0;
460 int max_loaded
= 0, min_loaded
= 0;
462 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
464 int tmp_loaded
, first_attempt
= 1;
465 unsigned long tmp_cpu_irq
;
466 unsigned long imbalance
= 0;
467 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
469 for_each_possible_cpu(i
) {
474 package_index
= CPU_TO_PACKAGEINDEX(i
);
475 for (j
= 0; j
< NR_IRQS
; j
++) {
476 unsigned long value_now
, delta
;
477 /* Is this an active IRQ or balancing disabled ? */
478 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
480 if ( package_index
== i
)
481 IRQ_DELTA(package_index
,j
) = 0;
482 /* Determine the total count per processor per IRQ */
483 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
485 /* Determine the activity per processor per IRQ */
486 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
488 /* Update last_cpu_irq[][] for the next time */
489 LAST_CPU_IRQ(i
,j
) = value_now
;
491 /* Ignore IRQs whose rate is less than the clock */
492 if (delta
< useful_load_threshold
)
494 /* update the load for the processor or package total */
495 IRQ_DELTA(package_index
,j
) += delta
;
497 /* Keep track of the higher numbered sibling as well */
498 if (i
!= package_index
)
501 * We have sibling A and sibling B in the package
503 * cpu_irq[A] = load for cpu A + load for cpu B
504 * cpu_irq[B] = load for cpu B
506 CPU_IRQ(package_index
) += delta
;
509 /* Find the least loaded processor package */
510 for_each_online_cpu(i
) {
511 if (i
!= CPU_TO_PACKAGEINDEX(i
))
513 if (min_cpu_irq
> CPU_IRQ(i
)) {
514 min_cpu_irq
= CPU_IRQ(i
);
518 max_cpu_irq
= ULONG_MAX
;
521 /* Look for heaviest loaded processor.
522 * We may come back to get the next heaviest loaded processor.
523 * Skip processors with trivial loads.
527 for_each_online_cpu(i
) {
528 if (i
!= CPU_TO_PACKAGEINDEX(i
))
530 if (max_cpu_irq
<= CPU_IRQ(i
))
532 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
533 tmp_cpu_irq
= CPU_IRQ(i
);
538 if (tmp_loaded
== -1) {
539 /* In the case of small number of heavy interrupt sources,
540 * loading some of the cpus too much. We use Ingo's original
541 * approach to rotate them around.
543 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
544 rotate_irqs_among_cpus(useful_load_threshold
);
547 goto not_worth_the_effort
;
550 first_attempt
= 0; /* heaviest search */
551 max_cpu_irq
= tmp_cpu_irq
; /* load */
552 max_loaded
= tmp_loaded
; /* processor */
553 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
555 /* if imbalance is less than approx 10% of max load, then
556 * observe diminishing returns action. - quit
558 if (imbalance
< (max_cpu_irq
>> 3))
559 goto not_worth_the_effort
;
562 /* if we select an IRQ to move that can't go where we want, then
563 * see if there is another one to try.
567 for (j
= 0; j
< NR_IRQS
; j
++) {
568 /* Is this an active IRQ? */
569 if (!irq_desc
[j
].action
)
571 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
573 /* Try to find the IRQ that is closest to the imbalance
574 * without going over.
576 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
577 move_this_load
= IRQ_DELTA(max_loaded
,j
);
581 if (selected_irq
== -1) {
585 imbalance
= move_this_load
;
587 /* For physical_balance case, we accumlated both load
588 * values in the one of the siblings cpu_irq[],
589 * to use the same code for physical and logical processors
590 * as much as possible.
592 * NOTE: the cpu_irq[] array holds the sum of the load for
593 * sibling A and sibling B in the slot for the lowest numbered
594 * sibling (A), _AND_ the load for sibling B in the slot for
595 * the higher numbered sibling.
597 * We seek the least loaded sibling by making the comparison
600 load
= CPU_IRQ(min_loaded
) >> 1;
601 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
602 if (load
> CPU_IRQ(j
)) {
603 /* This won't change cpu_sibling_map[min_loaded] */
609 cpus_and(allowed_mask
,
611 balance_irq_affinity
[selected_irq
]);
612 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
613 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
615 if (!cpus_empty(tmp
)) {
616 /* mark for change destination */
617 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
619 /* Since we made a change, come back sooner to
620 * check for more variation.
622 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
623 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
628 not_worth_the_effort
:
630 * if we did not find an IRQ to move, then adjust the time interval
633 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
634 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
638 static int balanced_irq(void *unused
)
641 unsigned long prev_balance_time
= jiffies
;
642 long time_remaining
= balanced_irq_interval
;
644 /* push everything to CPU 0 to give us a starting point. */
645 for (i
= 0 ; i
< NR_IRQS
; i
++) {
646 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
647 set_pending_irq(i
, cpumask_of_cpu(0));
652 time_remaining
= schedule_timeout_interruptible(time_remaining
);
654 if (time_after(jiffies
,
655 prev_balance_time
+balanced_irq_interval
)) {
658 prev_balance_time
= jiffies
;
659 time_remaining
= balanced_irq_interval
;
666 static int __init
balanced_irq_init(void)
669 struct cpuinfo_x86
*c
;
672 cpus_shift_right(tmp
, cpu_online_map
, 2);
674 /* When not overwritten by the command line ask subarchitecture. */
675 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
676 irqbalance_disabled
= NO_BALANCE_IRQ
;
677 if (irqbalance_disabled
)
680 /* disable irqbalance completely if there is only one processor online */
681 if (num_online_cpus() < 2) {
682 irqbalance_disabled
= 1;
686 * Enable physical balance only if more than 1 physical processor
689 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
690 physical_balance
= 1;
692 for_each_online_cpu(i
) {
693 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
694 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
695 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
696 printk(KERN_ERR
"balanced_irq_init: out of memory");
699 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
700 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
703 printk(KERN_INFO
"Starting balanced_irq\n");
704 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
706 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
708 for_each_possible_cpu(i
) {
709 kfree(irq_cpu_data
[i
].irq_delta
);
710 irq_cpu_data
[i
].irq_delta
= NULL
;
711 kfree(irq_cpu_data
[i
].last_irq
);
712 irq_cpu_data
[i
].last_irq
= NULL
;
717 int __devinit
irqbalance_disable(char *str
)
719 irqbalance_disabled
= 1;
723 __setup("noirqbalance", irqbalance_disable
);
725 late_initcall(balanced_irq_init
);
726 #endif /* CONFIG_IRQBALANCE */
727 #endif /* CONFIG_SMP */
730 void fastcall
send_IPI_self(int vector
)
737 apic_wait_icr_idle();
738 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
740 * Send the IPI. The write to APIC_ICR fires this off.
742 apic_write_around(APIC_ICR
, cfg
);
744 #endif /* !CONFIG_SMP */
748 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
749 * specific CPU-side IRQs.
753 static int pirq_entries
[MAX_PIRQS
];
754 static int pirqs_enabled
;
755 int skip_ioapic_setup
;
757 static int __init
ioapic_pirq_setup(char *str
)
760 int ints
[MAX_PIRQS
+1];
762 get_options(str
, ARRAY_SIZE(ints
), ints
);
764 for (i
= 0; i
< MAX_PIRQS
; i
++)
765 pirq_entries
[i
] = -1;
768 apic_printk(APIC_VERBOSE
, KERN_INFO
769 "PIRQ redirection, working around broken MP-BIOS.\n");
771 if (ints
[0] < MAX_PIRQS
)
774 for (i
= 0; i
< max
; i
++) {
775 apic_printk(APIC_VERBOSE
, KERN_DEBUG
776 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
778 * PIRQs are mapped upside down, usually.
780 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
785 __setup("pirq=", ioapic_pirq_setup
);
788 * Find the IRQ entry number of a certain pin.
790 static int find_irq_entry(int apic
, int pin
, int type
)
794 for (i
= 0; i
< mp_irq_entries
; i
++)
795 if (mp_irqs
[i
].mpc_irqtype
== type
&&
796 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
797 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
798 mp_irqs
[i
].mpc_dstirq
== pin
)
805 * Find the pin to which IRQ[irq] (ISA) is connected
807 static int __init
find_isa_irq_pin(int irq
, int type
)
811 for (i
= 0; i
< mp_irq_entries
; i
++) {
812 int lbus
= mp_irqs
[i
].mpc_srcbus
;
814 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
815 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
816 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
818 (mp_irqs
[i
].mpc_irqtype
== type
) &&
819 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
821 return mp_irqs
[i
].mpc_dstirq
;
826 static int __init
find_isa_irq_apic(int irq
, int type
)
830 for (i
= 0; i
< mp_irq_entries
; i
++) {
831 int lbus
= mp_irqs
[i
].mpc_srcbus
;
833 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
834 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
835 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
837 (mp_irqs
[i
].mpc_irqtype
== type
) &&
838 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
841 if (i
< mp_irq_entries
) {
843 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
844 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
853 * Find a specific PCI IRQ entry.
854 * Not an __init, possibly needed by modules
856 static int pin_2_irq(int idx
, int apic
, int pin
);
858 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
860 int apic
, i
, best_guess
= -1;
862 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
863 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
864 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
865 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
868 for (i
= 0; i
< mp_irq_entries
; i
++) {
869 int lbus
= mp_irqs
[i
].mpc_srcbus
;
871 for (apic
= 0; apic
< nr_ioapics
; apic
++)
872 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
873 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
876 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
877 !mp_irqs
[i
].mpc_irqtype
&&
879 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
880 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
882 if (!(apic
|| IO_APIC_IRQ(irq
)))
885 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
888 * Use the first all-but-pin matching entry as a
889 * best-guess fuzzy result for broken mptables.
897 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
900 * This function currently is only a helper for the i386 smp boot process where
901 * we need to reprogram the ioredtbls to cater for the cpus which have come online
902 * so mask in all cases should simply be TARGET_CPUS
905 void __init
setup_ioapic_dest(void)
907 int pin
, ioapic
, irq
, irq_entry
;
909 if (skip_ioapic_setup
== 1)
912 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
913 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
914 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
917 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
918 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
926 * EISA Edge/Level control register, ELCR
928 static int EISA_ELCR(unsigned int irq
)
931 unsigned int port
= 0x4d0 + (irq
>> 3);
932 return (inb(port
) >> (irq
& 7)) & 1;
934 apic_printk(APIC_VERBOSE
, KERN_INFO
935 "Broken MPtable reports ISA irq %d\n", irq
);
939 /* EISA interrupts are always polarity zero and can be edge or level
940 * trigger depending on the ELCR value. If an interrupt is listed as
941 * EISA conforming in the MP table, that means its trigger type must
942 * be read in from the ELCR */
944 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
945 #define default_EISA_polarity(idx) (0)
947 /* ISA interrupts are always polarity zero edge triggered,
948 * when listed as conforming in the MP table. */
950 #define default_ISA_trigger(idx) (0)
951 #define default_ISA_polarity(idx) (0)
953 /* PCI interrupts are always polarity one level triggered,
954 * when listed as conforming in the MP table. */
956 #define default_PCI_trigger(idx) (1)
957 #define default_PCI_polarity(idx) (1)
959 /* MCA interrupts are always polarity zero level triggered,
960 * when listed as conforming in the MP table. */
962 #define default_MCA_trigger(idx) (1)
963 #define default_MCA_polarity(idx) (0)
965 static int __init
MPBIOS_polarity(int idx
)
967 int bus
= mp_irqs
[idx
].mpc_srcbus
;
971 * Determine IRQ line polarity (high active or low active):
973 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
975 case 0: /* conforms, ie. bus-type dependent polarity */
977 switch (mp_bus_id_to_type
[bus
])
979 case MP_BUS_ISA
: /* ISA pin */
981 polarity
= default_ISA_polarity(idx
);
984 case MP_BUS_EISA
: /* EISA pin */
986 polarity
= default_EISA_polarity(idx
);
989 case MP_BUS_PCI
: /* PCI pin */
991 polarity
= default_PCI_polarity(idx
);
994 case MP_BUS_MCA
: /* MCA pin */
996 polarity
= default_MCA_polarity(idx
);
1001 printk(KERN_WARNING
"broken BIOS!!\n");
1008 case 1: /* high active */
1013 case 2: /* reserved */
1015 printk(KERN_WARNING
"broken BIOS!!\n");
1019 case 3: /* low active */
1024 default: /* invalid */
1026 printk(KERN_WARNING
"broken BIOS!!\n");
1034 static int MPBIOS_trigger(int idx
)
1036 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1040 * Determine IRQ trigger mode (edge or level sensitive):
1042 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1044 case 0: /* conforms, ie. bus-type dependent */
1046 switch (mp_bus_id_to_type
[bus
])
1048 case MP_BUS_ISA
: /* ISA pin */
1050 trigger
= default_ISA_trigger(idx
);
1053 case MP_BUS_EISA
: /* EISA pin */
1055 trigger
= default_EISA_trigger(idx
);
1058 case MP_BUS_PCI
: /* PCI pin */
1060 trigger
= default_PCI_trigger(idx
);
1063 case MP_BUS_MCA
: /* MCA pin */
1065 trigger
= default_MCA_trigger(idx
);
1070 printk(KERN_WARNING
"broken BIOS!!\n");
1082 case 2: /* reserved */
1084 printk(KERN_WARNING
"broken BIOS!!\n");
1093 default: /* invalid */
1095 printk(KERN_WARNING
"broken BIOS!!\n");
1103 static inline int irq_polarity(int idx
)
1105 return MPBIOS_polarity(idx
);
1108 static inline int irq_trigger(int idx
)
1110 return MPBIOS_trigger(idx
);
1113 static int pin_2_irq(int idx
, int apic
, int pin
)
1116 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1119 * Debugging check, we are in big trouble if this message pops up!
1121 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1122 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1124 switch (mp_bus_id_to_type
[bus
])
1126 case MP_BUS_ISA
: /* ISA pin */
1130 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1133 case MP_BUS_PCI
: /* PCI pin */
1136 * PCI IRQs are mapped in order
1140 irq
+= nr_ioapic_registers
[i
++];
1144 * For MPS mode, so far only needed by ES7000 platform
1146 if (ioapic_renumber_irq
)
1147 irq
= ioapic_renumber_irq(apic
, irq
);
1153 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
1160 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1162 if ((pin
>= 16) && (pin
<= 23)) {
1163 if (pirq_entries
[pin
-16] != -1) {
1164 if (!pirq_entries
[pin
-16]) {
1165 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1166 "disabling PIRQ%d\n", pin
-16);
1168 irq
= pirq_entries
[pin
-16];
1169 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1170 "using PIRQ%d -> IRQ %d\n",
1178 static inline int IO_APIC_irq_trigger(int irq
)
1182 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1183 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1184 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1185 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1186 return irq_trigger(idx
);
1190 * nonexistent IRQs are edge default
1195 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1196 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1198 static int __assign_irq_vector(int irq
)
1200 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1201 int vector
, offset
, i
;
1203 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1205 if (irq_vector
[irq
] > 0)
1206 return irq_vector
[irq
];
1208 vector
= current_vector
;
1209 offset
= current_offset
;
1212 if (vector
>= FIRST_SYSTEM_VECTOR
) {
1213 offset
= (offset
+ 1) % 8;
1214 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1216 if (vector
== current_vector
)
1218 if (vector
== SYSCALL_VECTOR
)
1220 for (i
= 0; i
< NR_IRQ_VECTORS
; i
++)
1221 if (irq_vector
[i
] == vector
)
1224 current_vector
= vector
;
1225 current_offset
= offset
;
1226 irq_vector
[irq
] = vector
;
1231 static int assign_irq_vector(int irq
)
1233 unsigned long flags
;
1236 spin_lock_irqsave(&vector_lock
, flags
);
1237 vector
= __assign_irq_vector(irq
);
1238 spin_unlock_irqrestore(&vector_lock
, flags
);
1242 static struct irq_chip ioapic_chip
;
1244 #define IOAPIC_AUTO -1
1245 #define IOAPIC_EDGE 0
1246 #define IOAPIC_LEVEL 1
1248 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1250 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1251 trigger
== IOAPIC_LEVEL
) {
1252 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1253 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1254 handle_fasteoi_irq
, "fasteoi");
1256 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1257 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1258 handle_edge_irq
, "edge");
1260 set_intr_gate(vector
, interrupt
[irq
]);
1263 static void __init
setup_IO_APIC_irqs(void)
1265 struct IO_APIC_route_entry entry
;
1266 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1267 unsigned long flags
;
1269 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1271 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1272 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1275 * add it to the IO-APIC irq-routing table:
1277 memset(&entry
,0,sizeof(entry
));
1279 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1280 entry
.dest_mode
= INT_DEST_MODE
;
1281 entry
.mask
= 0; /* enable IRQ */
1282 entry
.dest
.logical
.logical_dest
=
1283 cpu_mask_to_apicid(TARGET_CPUS
);
1285 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1288 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1289 " IO-APIC (apicid-pin) %d-%d",
1290 mp_ioapics
[apic
].mpc_apicid
,
1294 apic_printk(APIC_VERBOSE
, ", %d-%d",
1295 mp_ioapics
[apic
].mpc_apicid
, pin
);
1299 if (!first_notcon
) {
1300 apic_printk(APIC_VERBOSE
, " not connected.\n");
1304 entry
.trigger
= irq_trigger(idx
);
1305 entry
.polarity
= irq_polarity(idx
);
1307 if (irq_trigger(idx
)) {
1312 irq
= pin_2_irq(idx
, apic
, pin
);
1314 * skip adding the timer int on secondary nodes, which causes
1315 * a small but painful rift in the time-space continuum
1317 if (multi_timer_check(apic
, irq
))
1320 add_pin_to_irq(irq
, apic
, pin
);
1322 if (!apic
&& !IO_APIC_IRQ(irq
))
1325 if (IO_APIC_IRQ(irq
)) {
1326 vector
= assign_irq_vector(irq
);
1327 entry
.vector
= vector
;
1328 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1330 if (!apic
&& (irq
< 16))
1331 disable_8259A_irq(irq
);
1333 spin_lock_irqsave(&ioapic_lock
, flags
);
1334 __ioapic_write_entry(apic
, pin
, entry
);
1335 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1340 apic_printk(APIC_VERBOSE
, " not connected.\n");
1344 * Set up the 8259A-master output pin:
1346 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1348 struct IO_APIC_route_entry entry
;
1350 memset(&entry
,0,sizeof(entry
));
1352 disable_8259A_irq(0);
1355 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1358 * We use logical delivery to get the timer IRQ
1361 entry
.dest_mode
= INT_DEST_MODE
;
1362 entry
.mask
= 0; /* unmask IRQ now */
1363 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1364 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1367 entry
.vector
= vector
;
1370 * The timer IRQ doesn't have to know that behind the
1371 * scene we have a 8259A-master in AEOI mode ...
1373 irq_desc
[0].chip
= &ioapic_chip
;
1374 set_irq_handler(0, handle_edge_irq
);
1377 * Add it to the IO-APIC irq-routing table:
1379 ioapic_write_entry(apic
, pin
, entry
);
1381 enable_8259A_irq(0);
1384 void __init
print_IO_APIC(void)
1387 union IO_APIC_reg_00 reg_00
;
1388 union IO_APIC_reg_01 reg_01
;
1389 union IO_APIC_reg_02 reg_02
;
1390 union IO_APIC_reg_03 reg_03
;
1391 unsigned long flags
;
1393 if (apic_verbosity
== APIC_QUIET
)
1396 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1397 for (i
= 0; i
< nr_ioapics
; i
++)
1398 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1399 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1402 * We are a bit conservative about what we expect. We have to
1403 * know about every hardware change ASAP.
1405 printk(KERN_INFO
"testing the IO APIC.......................\n");
1407 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1409 spin_lock_irqsave(&ioapic_lock
, flags
);
1410 reg_00
.raw
= io_apic_read(apic
, 0);
1411 reg_01
.raw
= io_apic_read(apic
, 1);
1412 if (reg_01
.bits
.version
>= 0x10)
1413 reg_02
.raw
= io_apic_read(apic
, 2);
1414 if (reg_01
.bits
.version
>= 0x20)
1415 reg_03
.raw
= io_apic_read(apic
, 3);
1416 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1418 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1419 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1420 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1421 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1422 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1424 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1425 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1427 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1428 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1431 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1432 * but the value of reg_02 is read as the previous read register
1433 * value, so ignore it if reg_02 == reg_01.
1435 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1436 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1437 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1441 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1442 * or reg_03, but the value of reg_0[23] is read as the previous read
1443 * register value, so ignore it if reg_03 == reg_0[12].
1445 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1446 reg_03
.raw
!= reg_01
.raw
) {
1447 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1448 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1451 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1453 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1454 " Stat Dest Deli Vect: \n");
1456 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1457 struct IO_APIC_route_entry entry
;
1459 entry
= ioapic_read_entry(apic
, i
);
1461 printk(KERN_DEBUG
" %02x %03X %02X ",
1463 entry
.dest
.logical
.logical_dest
,
1464 entry
.dest
.physical
.physical_dest
1467 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1472 entry
.delivery_status
,
1474 entry
.delivery_mode
,
1479 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1480 for (i
= 0; i
< NR_IRQS
; i
++) {
1481 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1484 printk(KERN_DEBUG
"IRQ%d ", i
);
1486 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1489 entry
= irq_2_pin
+ entry
->next
;
1494 printk(KERN_INFO
".................................... done.\n");
1501 static void print_APIC_bitfield (int base
)
1506 if (apic_verbosity
== APIC_QUIET
)
1509 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1510 for (i
= 0; i
< 8; i
++) {
1511 v
= apic_read(base
+ i
*0x10);
1512 for (j
= 0; j
< 32; j
++) {
1522 void /*__init*/ print_local_APIC(void * dummy
)
1524 unsigned int v
, ver
, maxlvt
;
1526 if (apic_verbosity
== APIC_QUIET
)
1529 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1530 smp_processor_id(), hard_smp_processor_id());
1531 v
= apic_read(APIC_ID
);
1532 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1533 v
= apic_read(APIC_LVR
);
1534 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1535 ver
= GET_APIC_VERSION(v
);
1536 maxlvt
= lapic_get_maxlvt();
1538 v
= apic_read(APIC_TASKPRI
);
1539 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1541 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1542 v
= apic_read(APIC_ARBPRI
);
1543 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1544 v
& APIC_ARBPRI_MASK
);
1545 v
= apic_read(APIC_PROCPRI
);
1546 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1549 v
= apic_read(APIC_EOI
);
1550 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1551 v
= apic_read(APIC_RRR
);
1552 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1553 v
= apic_read(APIC_LDR
);
1554 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1555 v
= apic_read(APIC_DFR
);
1556 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1557 v
= apic_read(APIC_SPIV
);
1558 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1560 printk(KERN_DEBUG
"... APIC ISR field:\n");
1561 print_APIC_bitfield(APIC_ISR
);
1562 printk(KERN_DEBUG
"... APIC TMR field:\n");
1563 print_APIC_bitfield(APIC_TMR
);
1564 printk(KERN_DEBUG
"... APIC IRR field:\n");
1565 print_APIC_bitfield(APIC_IRR
);
1567 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1568 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1569 apic_write(APIC_ESR
, 0);
1570 v
= apic_read(APIC_ESR
);
1571 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1574 v
= apic_read(APIC_ICR
);
1575 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1576 v
= apic_read(APIC_ICR2
);
1577 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1579 v
= apic_read(APIC_LVTT
);
1580 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1582 if (maxlvt
> 3) { /* PC is LVT#4. */
1583 v
= apic_read(APIC_LVTPC
);
1584 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1586 v
= apic_read(APIC_LVT0
);
1587 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1588 v
= apic_read(APIC_LVT1
);
1589 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1591 if (maxlvt
> 2) { /* ERR is LVT#3. */
1592 v
= apic_read(APIC_LVTERR
);
1593 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1596 v
= apic_read(APIC_TMICT
);
1597 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1598 v
= apic_read(APIC_TMCCT
);
1599 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1600 v
= apic_read(APIC_TDCR
);
1601 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1605 void print_all_local_APICs (void)
1607 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1610 void /*__init*/ print_PIC(void)
1613 unsigned long flags
;
1615 if (apic_verbosity
== APIC_QUIET
)
1618 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1620 spin_lock_irqsave(&i8259A_lock
, flags
);
1622 v
= inb(0xa1) << 8 | inb(0x21);
1623 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1625 v
= inb(0xa0) << 8 | inb(0x20);
1626 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1630 v
= inb(0xa0) << 8 | inb(0x20);
1634 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1636 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1638 v
= inb(0x4d1) << 8 | inb(0x4d0);
1639 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1644 static void __init
enable_IO_APIC(void)
1646 union IO_APIC_reg_01 reg_01
;
1647 int i8259_apic
, i8259_pin
;
1649 unsigned long flags
;
1651 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1652 irq_2_pin
[i
].pin
= -1;
1653 irq_2_pin
[i
].next
= 0;
1656 for (i
= 0; i
< MAX_PIRQS
; i
++)
1657 pirq_entries
[i
] = -1;
1660 * The number of IO-APIC IRQ registers (== #pins):
1662 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1663 spin_lock_irqsave(&ioapic_lock
, flags
);
1664 reg_01
.raw
= io_apic_read(apic
, 1);
1665 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1666 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1668 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1670 /* See if any of the pins is in ExtINT mode */
1671 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1672 struct IO_APIC_route_entry entry
;
1673 entry
= ioapic_read_entry(apic
, pin
);
1676 /* If the interrupt line is enabled and in ExtInt mode
1677 * I have found the pin where the i8259 is connected.
1679 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1680 ioapic_i8259
.apic
= apic
;
1681 ioapic_i8259
.pin
= pin
;
1687 /* Look to see what if the MP table has reported the ExtINT */
1688 /* If we could not find the appropriate pin by looking at the ioapic
1689 * the i8259 probably is not connected the ioapic but give the
1690 * mptable a chance anyway.
1692 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1693 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1694 /* Trust the MP table if nothing is setup in the hardware */
1695 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1696 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1697 ioapic_i8259
.pin
= i8259_pin
;
1698 ioapic_i8259
.apic
= i8259_apic
;
1700 /* Complain if the MP table and the hardware disagree */
1701 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1702 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1704 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1708 * Do not trust the IO-APIC being empty at bootup
1714 * Not an __init, needed by the reboot code
1716 void disable_IO_APIC(void)
1719 * Clear the IO-APIC before rebooting:
1724 * If the i8259 is routed through an IOAPIC
1725 * Put that IOAPIC in virtual wire mode
1726 * so legacy interrupts can be delivered.
1728 if (ioapic_i8259
.pin
!= -1) {
1729 struct IO_APIC_route_entry entry
;
1731 memset(&entry
, 0, sizeof(entry
));
1732 entry
.mask
= 0; /* Enabled */
1733 entry
.trigger
= 0; /* Edge */
1735 entry
.polarity
= 0; /* High */
1736 entry
.delivery_status
= 0;
1737 entry
.dest_mode
= 0; /* Physical */
1738 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1740 entry
.dest
.physical
.physical_dest
=
1741 GET_APIC_ID(apic_read(APIC_ID
));
1744 * Add it to the IO-APIC irq-routing table:
1746 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1748 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1752 * function to set the IO-APIC physical IDs based on the
1753 * values stored in the MPC table.
1755 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1758 #ifndef CONFIG_X86_NUMAQ
1759 static void __init
setup_ioapic_ids_from_mpc(void)
1761 union IO_APIC_reg_00 reg_00
;
1762 physid_mask_t phys_id_present_map
;
1765 unsigned char old_id
;
1766 unsigned long flags
;
1769 * Don't check I/O APIC IDs for xAPIC systems. They have
1770 * no meaning without the serial APIC bus.
1772 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1773 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1776 * This is broken; anything with a real cpu count has to
1777 * circumvent this idiocy regardless.
1779 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1782 * Set the IOAPIC ID to the value stored in the MPC table.
1784 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1786 /* Read the register 0 value */
1787 spin_lock_irqsave(&ioapic_lock
, flags
);
1788 reg_00
.raw
= io_apic_read(apic
, 0);
1789 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1791 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1793 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1794 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1795 apic
, mp_ioapics
[apic
].mpc_apicid
);
1796 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1798 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1802 * Sanity check, is the ID really free? Every APIC in a
1803 * system must have a unique ID or we get lots of nice
1804 * 'stuck on smp_invalidate_needed IPI wait' messages.
1806 if (check_apicid_used(phys_id_present_map
,
1807 mp_ioapics
[apic
].mpc_apicid
)) {
1808 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1809 apic
, mp_ioapics
[apic
].mpc_apicid
);
1810 for (i
= 0; i
< get_physical_broadcast(); i
++)
1811 if (!physid_isset(i
, phys_id_present_map
))
1813 if (i
>= get_physical_broadcast())
1814 panic("Max APIC ID exceeded!\n");
1815 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1817 physid_set(i
, phys_id_present_map
);
1818 mp_ioapics
[apic
].mpc_apicid
= i
;
1821 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1822 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1823 "phys_id_present_map\n",
1824 mp_ioapics
[apic
].mpc_apicid
);
1825 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1830 * We need to adjust the IRQ routing table
1831 * if the ID changed.
1833 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1834 for (i
= 0; i
< mp_irq_entries
; i
++)
1835 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1836 mp_irqs
[i
].mpc_dstapic
1837 = mp_ioapics
[apic
].mpc_apicid
;
1840 * Read the right value from the MPC table and
1841 * write it into the ID register.
1843 apic_printk(APIC_VERBOSE
, KERN_INFO
1844 "...changing IO-APIC physical APIC ID to %d ...",
1845 mp_ioapics
[apic
].mpc_apicid
);
1847 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1848 spin_lock_irqsave(&ioapic_lock
, flags
);
1849 io_apic_write(apic
, 0, reg_00
.raw
);
1850 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1855 spin_lock_irqsave(&ioapic_lock
, flags
);
1856 reg_00
.raw
= io_apic_read(apic
, 0);
1857 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1858 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1859 printk("could not set ID!\n");
1861 apic_printk(APIC_VERBOSE
, " ok.\n");
1865 static void __init
setup_ioapic_ids_from_mpc(void) { }
1868 int no_timer_check __initdata
;
1870 static int __init
notimercheck(char *s
)
1875 __setup("no_timer_check", notimercheck
);
1878 * There is a nasty bug in some older SMP boards, their mptable lies
1879 * about the timer IRQ. We do the following to work around the situation:
1881 * - timer IRQ defaults to IO-APIC IRQ
1882 * - if this function detects that timer IRQs are defunct, then we fall
1883 * back to ISA timer IRQs
1885 static int __init
timer_irq_works(void)
1887 unsigned long t1
= jiffies
;
1893 /* Let ten ticks pass... */
1894 mdelay((10 * 1000) / HZ
);
1897 * Expect a few ticks at least, to be sure some possible
1898 * glue logic does not lock up after one or two first
1899 * ticks in a non-ExtINT mode. Also the local APIC
1900 * might have cached one ExtINT interrupt. Finally, at
1901 * least one tick may be lost due to delays.
1903 if (jiffies
- t1
> 4)
1910 * In the SMP+IOAPIC case it might happen that there are an unspecified
1911 * number of pending IRQ events unhandled. These cases are very rare,
1912 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1913 * better to do it this way as thus we do not have to be aware of
1914 * 'pending' interrupts in the IRQ path, except at this point.
1917 * Edge triggered needs to resend any interrupt
1918 * that was delayed but this is now handled in the device
1925 * Starting up a edge-triggered IO-APIC interrupt is
1926 * nasty - we need to make sure that we get the edge.
1927 * If it is already asserted for some reason, we need
1928 * return 1 to indicate that is was pending.
1930 * This is not complete - we should be able to fake
1931 * an edge even if it isn't on the 8259A...
1933 * (We do this for level-triggered IRQs too - it cannot hurt.)
1935 static unsigned int startup_ioapic_irq(unsigned int irq
)
1937 int was_pending
= 0;
1938 unsigned long flags
;
1940 spin_lock_irqsave(&ioapic_lock
, flags
);
1942 disable_8259A_irq(irq
);
1943 if (i8259A_irq_pending(irq
))
1946 __unmask_IO_APIC_irq(irq
);
1947 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1952 static void ack_ioapic_irq(unsigned int irq
)
1954 move_native_irq(irq
);
1958 static void ack_ioapic_quirk_irq(unsigned int irq
)
1963 move_native_irq(irq
);
1965 * It appears there is an erratum which affects at least version 0x11
1966 * of I/O APIC (that's the 82093AA and cores integrated into various
1967 * chipsets). Under certain conditions a level-triggered interrupt is
1968 * erroneously delivered as edge-triggered one but the respective IRR
1969 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1970 * message but it will never arrive and further interrupts are blocked
1971 * from the source. The exact reason is so far unknown, but the
1972 * phenomenon was observed when two consecutive interrupt requests
1973 * from a given source get delivered to the same CPU and the source is
1974 * temporarily disabled in between.
1976 * A workaround is to simulate an EOI message manually. We achieve it
1977 * by setting the trigger mode to edge and then to level when the edge
1978 * trigger mode gets detected in the TMR of a local APIC for a
1979 * level-triggered interrupt. We mask the source for the time of the
1980 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1981 * The idea is from Manfred Spraul. --macro
1983 i
= irq_vector
[irq
];
1985 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1989 if (!(v
& (1 << (i
& 0x1f)))) {
1990 atomic_inc(&irq_mis_count
);
1991 spin_lock(&ioapic_lock
);
1992 __mask_and_edge_IO_APIC_irq(irq
);
1993 __unmask_and_level_IO_APIC_irq(irq
);
1994 spin_unlock(&ioapic_lock
);
1998 static int ioapic_retrigger_irq(unsigned int irq
)
2000 send_IPI_self(irq_vector
[irq
]);
2005 static struct irq_chip ioapic_chip __read_mostly
= {
2007 .startup
= startup_ioapic_irq
,
2008 .mask
= mask_IO_APIC_irq
,
2009 .unmask
= unmask_IO_APIC_irq
,
2010 .ack
= ack_ioapic_irq
,
2011 .eoi
= ack_ioapic_quirk_irq
,
2013 .set_affinity
= set_ioapic_affinity_irq
,
2015 .retrigger
= ioapic_retrigger_irq
,
2019 static inline void init_IO_APIC_traps(void)
2024 * NOTE! The local APIC isn't very good at handling
2025 * multiple interrupts at the same interrupt level.
2026 * As the interrupt level is determined by taking the
2027 * vector number and shifting that right by 4, we
2028 * want to spread these out a bit so that they don't
2029 * all fall in the same interrupt level.
2031 * Also, we've got to be careful not to trash gate
2032 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2034 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2036 if (IO_APIC_IRQ(tmp
) && !irq_vector
[tmp
]) {
2038 * Hmm.. We don't have an entry for this,
2039 * so default to an old-fashioned 8259
2040 * interrupt if we can..
2043 make_8259A_irq(irq
);
2045 /* Strange. Oh, well.. */
2046 irq_desc
[irq
].chip
= &no_irq_chip
;
2052 * The local APIC irq-chip implementation:
2055 static void ack_apic(unsigned int irq
)
2060 static void mask_lapic_irq (unsigned int irq
)
2064 v
= apic_read(APIC_LVT0
);
2065 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2068 static void unmask_lapic_irq (unsigned int irq
)
2072 v
= apic_read(APIC_LVT0
);
2073 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2076 static struct irq_chip lapic_chip __read_mostly
= {
2077 .name
= "local-APIC-edge",
2078 .mask
= mask_lapic_irq
,
2079 .unmask
= unmask_lapic_irq
,
2083 static void setup_nmi (void)
2086 * Dirty trick to enable the NMI watchdog ...
2087 * We put the 8259A master into AEOI mode and
2088 * unmask on all local APICs LVT0 as NMI.
2090 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2091 * is from Maciej W. Rozycki - so we do not have to EOI from
2092 * the NMI handler or the timer interrupt.
2094 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2096 on_each_cpu(enable_NMI_through_LVT0
, NULL
, 1, 1);
2098 apic_printk(APIC_VERBOSE
, " done.\n");
2102 * This looks a bit hackish but it's about the only one way of sending
2103 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2104 * not support the ExtINT mode, unfortunately. We need to send these
2105 * cycles as some i82489DX-based boards have glue logic that keeps the
2106 * 8259A interrupt line asserted until INTA. --macro
2108 static inline void unlock_ExtINT_logic(void)
2111 struct IO_APIC_route_entry entry0
, entry1
;
2112 unsigned char save_control
, save_freq_select
;
2114 pin
= find_isa_irq_pin(8, mp_INT
);
2119 apic
= find_isa_irq_apic(8, mp_INT
);
2125 entry0
= ioapic_read_entry(apic
, pin
);
2126 clear_IO_APIC_pin(apic
, pin
);
2128 memset(&entry1
, 0, sizeof(entry1
));
2130 entry1
.dest_mode
= 0; /* physical delivery */
2131 entry1
.mask
= 0; /* unmask IRQ now */
2132 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2133 entry1
.delivery_mode
= dest_ExtINT
;
2134 entry1
.polarity
= entry0
.polarity
;
2138 ioapic_write_entry(apic
, pin
, entry1
);
2140 save_control
= CMOS_READ(RTC_CONTROL
);
2141 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2142 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2144 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2149 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2153 CMOS_WRITE(save_control
, RTC_CONTROL
);
2154 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2155 clear_IO_APIC_pin(apic
, pin
);
2157 ioapic_write_entry(apic
, pin
, entry0
);
2160 int timer_uses_ioapic_pin_0
;
2163 * This code may look a bit paranoid, but it's supposed to cooperate with
2164 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2165 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2166 * fanatically on his truly buggy board.
2168 static inline void __init
check_timer(void)
2170 int apic1
, pin1
, apic2
, pin2
;
2174 * get/set the timer IRQ vector:
2176 disable_8259A_irq(0);
2177 vector
= assign_irq_vector(0);
2178 set_intr_gate(vector
, interrupt
[0]);
2181 * Subtle, code in do_timer_interrupt() expects an AEOI
2182 * mode for the 8259A whenever interrupts are routed
2183 * through I/O APICs. Also IRQ0 has to be enabled in
2184 * the 8259A which implies the virtual wire has to be
2185 * disabled in the local APIC.
2187 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2190 if (timer_over_8254
> 0)
2191 enable_8259A_irq(0);
2193 pin1
= find_isa_irq_pin(0, mp_INT
);
2194 apic1
= find_isa_irq_apic(0, mp_INT
);
2195 pin2
= ioapic_i8259
.pin
;
2196 apic2
= ioapic_i8259
.apic
;
2199 timer_uses_ioapic_pin_0
= 1;
2201 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2202 vector
, apic1
, pin1
, apic2
, pin2
);
2206 * Ok, does IRQ0 through the IOAPIC work?
2208 unmask_IO_APIC_irq(0);
2209 if (timer_irq_works()) {
2210 if (nmi_watchdog
== NMI_IO_APIC
) {
2211 disable_8259A_irq(0);
2213 enable_8259A_irq(0);
2215 if (disable_timer_pin_1
> 0)
2216 clear_IO_APIC_pin(0, pin1
);
2219 clear_IO_APIC_pin(apic1
, pin1
);
2220 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2224 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2226 printk("\n..... (found pin %d) ...", pin2
);
2228 * legacy devices should be connected to IO APIC #0
2230 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2231 if (timer_irq_works()) {
2234 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2236 add_pin_to_irq(0, apic2
, pin2
);
2237 if (nmi_watchdog
== NMI_IO_APIC
) {
2243 * Cleanup, just in case ...
2245 clear_IO_APIC_pin(apic2
, pin2
);
2247 printk(" failed.\n");
2249 if (nmi_watchdog
== NMI_IO_APIC
) {
2250 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2254 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2256 disable_8259A_irq(0);
2257 set_irq_chip_and_handler_name(0, &lapic_chip
, handle_fasteoi_irq
,
2259 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2260 enable_8259A_irq(0);
2262 if (timer_irq_works()) {
2263 printk(" works.\n");
2266 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2267 printk(" failed.\n");
2269 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2274 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2276 unlock_ExtINT_logic();
2278 if (timer_irq_works()) {
2279 printk(" works.\n");
2282 printk(" failed :(.\n");
2283 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2284 "report. Then try booting with the 'noapic' option");
2289 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2290 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2291 * Linux doesn't really care, as it's not actually used
2292 * for any interrupt handling anyway.
2294 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2296 void __init
setup_IO_APIC(void)
2301 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2303 io_apic_irqs
= ~PIC_IRQS
;
2305 printk("ENABLING IO-APIC IRQs\n");
2308 * Set up IO-APIC IRQ routing.
2311 setup_ioapic_ids_from_mpc();
2313 setup_IO_APIC_irqs();
2314 init_IO_APIC_traps();
2320 static int __init
setup_disable_8254_timer(char *s
)
2322 timer_over_8254
= -1;
2325 static int __init
setup_enable_8254_timer(char *s
)
2327 timer_over_8254
= 2;
2331 __setup("disable_8254_timer", setup_disable_8254_timer
);
2332 __setup("enable_8254_timer", setup_enable_8254_timer
);
2335 * Called after all the initialization is done. If we didnt find any
2336 * APIC bugs then we can allow the modify fast path
2339 static int __init
io_apic_bug_finalize(void)
2341 if(sis_apic_bug
== -1)
2346 late_initcall(io_apic_bug_finalize
);
2348 struct sysfs_ioapic_data
{
2349 struct sys_device dev
;
2350 struct IO_APIC_route_entry entry
[0];
2352 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2354 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2356 struct IO_APIC_route_entry
*entry
;
2357 struct sysfs_ioapic_data
*data
;
2360 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2361 entry
= data
->entry
;
2362 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2363 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2368 static int ioapic_resume(struct sys_device
*dev
)
2370 struct IO_APIC_route_entry
*entry
;
2371 struct sysfs_ioapic_data
*data
;
2372 unsigned long flags
;
2373 union IO_APIC_reg_00 reg_00
;
2376 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2377 entry
= data
->entry
;
2379 spin_lock_irqsave(&ioapic_lock
, flags
);
2380 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2381 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2382 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2383 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2385 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2386 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2387 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2392 static struct sysdev_class ioapic_sysdev_class
= {
2393 set_kset_name("ioapic"),
2394 .suspend
= ioapic_suspend
,
2395 .resume
= ioapic_resume
,
2398 static int __init
ioapic_init_sysfs(void)
2400 struct sys_device
* dev
;
2401 int i
, size
, error
= 0;
2403 error
= sysdev_class_register(&ioapic_sysdev_class
);
2407 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2408 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2409 * sizeof(struct IO_APIC_route_entry
);
2410 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2411 if (!mp_ioapic_data
[i
]) {
2412 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2415 memset(mp_ioapic_data
[i
], 0, size
);
2416 dev
= &mp_ioapic_data
[i
]->dev
;
2418 dev
->cls
= &ioapic_sysdev_class
;
2419 error
= sysdev_register(dev
);
2421 kfree(mp_ioapic_data
[i
]);
2422 mp_ioapic_data
[i
] = NULL
;
2423 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2431 device_initcall(ioapic_init_sysfs
);
2434 * Dynamic irq allocate and deallocation
2436 int create_irq(void)
2438 /* Allocate an unused irq */
2439 int irq
, new, vector
= 0;
2440 unsigned long flags
;
2443 spin_lock_irqsave(&vector_lock
, flags
);
2444 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2445 if (platform_legacy_irq(new))
2447 if (irq_vector
[new] != 0)
2449 vector
= __assign_irq_vector(new);
2450 if (likely(vector
> 0))
2454 spin_unlock_irqrestore(&vector_lock
, flags
);
2457 set_intr_gate(vector
, interrupt
[irq
]);
2458 dynamic_irq_init(irq
);
2463 void destroy_irq(unsigned int irq
)
2465 unsigned long flags
;
2467 dynamic_irq_cleanup(irq
);
2469 spin_lock_irqsave(&vector_lock
, flags
);
2470 irq_vector
[irq
] = 0;
2471 spin_unlock_irqrestore(&vector_lock
, flags
);
2475 * MSI mesage composition
2477 #ifdef CONFIG_PCI_MSI
2478 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2483 vector
= assign_irq_vector(irq
);
2485 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2487 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2490 ((INT_DEST_MODE
== 0) ?
2491 MSI_ADDR_DEST_MODE_PHYSICAL
:
2492 MSI_ADDR_DEST_MODE_LOGICAL
) |
2493 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2494 MSI_ADDR_REDIRECTION_CPU
:
2495 MSI_ADDR_REDIRECTION_LOWPRI
) |
2496 MSI_ADDR_DEST_ID(dest
);
2499 MSI_DATA_TRIGGER_EDGE
|
2500 MSI_DATA_LEVEL_ASSERT
|
2501 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2502 MSI_DATA_DELIVERY_FIXED
:
2503 MSI_DATA_DELIVERY_LOWPRI
) |
2504 MSI_DATA_VECTOR(vector
);
2510 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2517 cpus_and(tmp
, mask
, cpu_online_map
);
2518 if (cpus_empty(tmp
))
2521 vector
= assign_irq_vector(irq
);
2525 dest
= cpu_mask_to_apicid(mask
);
2527 read_msi_msg(irq
, &msg
);
2529 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2530 msg
.data
|= MSI_DATA_VECTOR(vector
);
2531 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2532 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2534 write_msi_msg(irq
, &msg
);
2535 irq_desc
[irq
].affinity
= mask
;
2537 #endif /* CONFIG_SMP */
2540 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2541 * which implement the MSI or MSI-X Capability Structure.
2543 static struct irq_chip msi_chip
= {
2545 .unmask
= unmask_msi_irq
,
2546 .mask
= mask_msi_irq
,
2547 .ack
= ack_ioapic_irq
,
2549 .set_affinity
= set_msi_irq_affinity
,
2551 .retrigger
= ioapic_retrigger_irq
,
2554 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2562 ret
= msi_compose_msg(dev
, irq
, &msg
);
2568 set_irq_msi(irq
, desc
);
2569 write_msi_msg(irq
, &msg
);
2571 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2577 void arch_teardown_msi_irq(unsigned int irq
)
2582 #endif /* CONFIG_PCI_MSI */
2585 * Hypertransport interrupt support
2587 #ifdef CONFIG_HT_IRQ
2591 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2593 struct ht_irq_msg msg
;
2594 fetch_ht_irq_msg(irq
, &msg
);
2596 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2597 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2599 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2600 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2602 write_ht_irq_msg(irq
, &msg
);
2605 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2610 cpus_and(tmp
, mask
, cpu_online_map
);
2611 if (cpus_empty(tmp
))
2614 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2616 dest
= cpu_mask_to_apicid(mask
);
2618 target_ht_irq(irq
, dest
);
2619 irq_desc
[irq
].affinity
= mask
;
2623 static struct irq_chip ht_irq_chip
= {
2625 .mask
= mask_ht_irq
,
2626 .unmask
= unmask_ht_irq
,
2627 .ack
= ack_ioapic_irq
,
2629 .set_affinity
= set_ht_irq_affinity
,
2631 .retrigger
= ioapic_retrigger_irq
,
2634 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2638 vector
= assign_irq_vector(irq
);
2640 struct ht_irq_msg msg
;
2645 cpu_set(vector
>> 8, tmp
);
2646 dest
= cpu_mask_to_apicid(tmp
);
2648 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2652 HT_IRQ_LOW_DEST_ID(dest
) |
2653 HT_IRQ_LOW_VECTOR(vector
) |
2654 ((INT_DEST_MODE
== 0) ?
2655 HT_IRQ_LOW_DM_PHYSICAL
:
2656 HT_IRQ_LOW_DM_LOGICAL
) |
2657 HT_IRQ_LOW_RQEOI_EDGE
|
2658 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2659 HT_IRQ_LOW_MT_FIXED
:
2660 HT_IRQ_LOW_MT_ARBITRATED
) |
2661 HT_IRQ_LOW_IRQ_MASKED
;
2663 write_ht_irq_msg(irq
, &msg
);
2665 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2666 handle_edge_irq
, "edge");
2670 #endif /* CONFIG_HT_IRQ */
2672 /* --------------------------------------------------------------------------
2673 ACPI-based IOAPIC Configuration
2674 -------------------------------------------------------------------------- */
2678 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2680 union IO_APIC_reg_00 reg_00
;
2681 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2683 unsigned long flags
;
2687 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2688 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2689 * supports up to 16 on one shared APIC bus.
2691 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2692 * advantage of new APIC bus architecture.
2695 if (physids_empty(apic_id_map
))
2696 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2698 spin_lock_irqsave(&ioapic_lock
, flags
);
2699 reg_00
.raw
= io_apic_read(ioapic
, 0);
2700 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2702 if (apic_id
>= get_physical_broadcast()) {
2703 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2704 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2705 apic_id
= reg_00
.bits
.ID
;
2709 * Every APIC in a system must have a unique ID or we get lots of nice
2710 * 'stuck on smp_invalidate_needed IPI wait' messages.
2712 if (check_apicid_used(apic_id_map
, apic_id
)) {
2714 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2715 if (!check_apicid_used(apic_id_map
, i
))
2719 if (i
== get_physical_broadcast())
2720 panic("Max apic_id exceeded!\n");
2722 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2723 "trying %d\n", ioapic
, apic_id
, i
);
2728 tmp
= apicid_to_cpu_present(apic_id
);
2729 physids_or(apic_id_map
, apic_id_map
, tmp
);
2731 if (reg_00
.bits
.ID
!= apic_id
) {
2732 reg_00
.bits
.ID
= apic_id
;
2734 spin_lock_irqsave(&ioapic_lock
, flags
);
2735 io_apic_write(ioapic
, 0, reg_00
.raw
);
2736 reg_00
.raw
= io_apic_read(ioapic
, 0);
2737 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2740 if (reg_00
.bits
.ID
!= apic_id
) {
2741 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2746 apic_printk(APIC_VERBOSE
, KERN_INFO
2747 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2753 int __init
io_apic_get_version (int ioapic
)
2755 union IO_APIC_reg_01 reg_01
;
2756 unsigned long flags
;
2758 spin_lock_irqsave(&ioapic_lock
, flags
);
2759 reg_01
.raw
= io_apic_read(ioapic
, 1);
2760 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2762 return reg_01
.bits
.version
;
2766 int __init
io_apic_get_redir_entries (int ioapic
)
2768 union IO_APIC_reg_01 reg_01
;
2769 unsigned long flags
;
2771 spin_lock_irqsave(&ioapic_lock
, flags
);
2772 reg_01
.raw
= io_apic_read(ioapic
, 1);
2773 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2775 return reg_01
.bits
.entries
;
2779 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2781 struct IO_APIC_route_entry entry
;
2782 unsigned long flags
;
2784 if (!IO_APIC_IRQ(irq
)) {
2785 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2791 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2792 * Note that we mask (disable) IRQs now -- these get enabled when the
2793 * corresponding device driver registers for this IRQ.
2796 memset(&entry
,0,sizeof(entry
));
2798 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2799 entry
.dest_mode
= INT_DEST_MODE
;
2800 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2801 entry
.trigger
= edge_level
;
2802 entry
.polarity
= active_high_low
;
2806 * IRQs < 16 are already in the irq_2_pin[] map
2809 add_pin_to_irq(irq
, ioapic
, pin
);
2811 entry
.vector
= assign_irq_vector(irq
);
2813 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2814 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2815 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2816 edge_level
, active_high_low
);
2818 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2820 if (!ioapic
&& (irq
< 16))
2821 disable_8259A_irq(irq
);
2823 spin_lock_irqsave(&ioapic_lock
, flags
);
2824 __ioapic_write_entry(ioapic
, pin
, entry
);
2825 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2830 #endif /* CONFIG_ACPI */
2832 static int __init
parse_disable_timer_pin_1(char *arg
)
2834 disable_timer_pin_1
= 1;
2837 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2839 static int __init
parse_enable_timer_pin_1(char *arg
)
2841 disable_timer_pin_1
= -1;
2844 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2846 static int __init
parse_noapic(char *arg
)
2848 /* disable IO-APIC */
2849 disable_ioapic_setup();
2852 early_param("noapic", parse_noapic
);