2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
53 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
54 atomic_t irq_mis_count
;
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
59 static DEFINE_SPINLOCK(ioapic_lock
);
60 static DEFINE_SPINLOCK(vector_lock
);
62 int timer_through_8259 __initdata
;
65 * Is the SiS APIC rmw bug present ?
66 * -1 = don't know, 0 = no, 1 = yes
68 int sis_apic_bug
= -1;
71 * # of IRQ routing registers
73 int nr_ioapic_registers
[MAX_IO_APICS
];
75 /* I/O APIC entries */
76 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
79 /* MP IRQ source entries */
80 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
82 /* # of MP IRQ source entries */
85 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
86 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
89 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
91 static int disable_timer_pin_1 __initdata
;
94 * Rough estimation of how many shared IRQs there are, can
97 #define MAX_PLUS_SHARED_IRQS NR_IRQS
98 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
101 * This is performance-critical, we want to do it O(1)
103 * the indexing order of this array favors 1:1 mappings
104 * between pins and IRQs.
107 static struct irq_pin_list
{
109 } irq_2_pin
[PIN_MAP_SIZE
];
113 unsigned int unused
[3];
117 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
119 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
120 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
123 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
125 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
126 writel(reg
, &io_apic
->index
);
127 return readl(&io_apic
->data
);
130 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
132 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
133 writel(reg
, &io_apic
->index
);
134 writel(value
, &io_apic
->data
);
138 * Re-write a value: to be used for read-modify-write
139 * cycles where the read already set up the index register.
141 * Older SiS APIC requires we rewrite the index register
143 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
145 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
147 writel(reg
, &io_apic
->index
);
148 writel(value
, &io_apic
->data
);
152 struct { u32 w1
, w2
; };
153 struct IO_APIC_route_entry entry
;
156 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
158 union entry_union eu
;
160 spin_lock_irqsave(&ioapic_lock
, flags
);
161 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
162 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
163 spin_unlock_irqrestore(&ioapic_lock
, flags
);
168 * When we write a new IO APIC routing entry, we need to write the high
169 * word first! If the mask bit in the low word is clear, we will enable
170 * the interrupt, and we need to make sure the entry is fully populated
171 * before that happens.
174 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
176 union entry_union eu
;
178 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
179 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
182 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
185 spin_lock_irqsave(&ioapic_lock
, flags
);
186 __ioapic_write_entry(apic
, pin
, e
);
187 spin_unlock_irqrestore(&ioapic_lock
, flags
);
191 * When we mask an IO APIC routing entry, we need to write the low
192 * word first, in order to set the mask bit before we change the
195 static void ioapic_mask_entry(int apic
, int pin
)
198 union entry_union eu
= { .entry
.mask
= 1 };
200 spin_lock_irqsave(&ioapic_lock
, flags
);
201 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
202 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
203 spin_unlock_irqrestore(&ioapic_lock
, flags
);
207 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
208 * shared ISA-space IRQs, so we have to support them. We are super
209 * fast in the common case, and fast for shared ISA-space IRQs.
211 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
213 static int first_free_entry
= NR_IRQS
;
214 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
217 entry
= irq_2_pin
+ entry
->next
;
219 if (entry
->pin
!= -1) {
220 entry
->next
= first_free_entry
;
221 entry
= irq_2_pin
+ entry
->next
;
222 if (++first_free_entry
>= PIN_MAP_SIZE
)
223 panic("io_apic.c: whoops");
230 * Reroute an IRQ to a different pin.
232 static void __init
replace_pin_at_irq(unsigned int irq
,
233 int oldapic
, int oldpin
,
234 int newapic
, int newpin
)
236 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
239 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
240 entry
->apic
= newapic
;
245 entry
= irq_2_pin
+ entry
->next
;
249 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
251 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
252 unsigned int pin
, reg
;
258 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
261 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
264 entry
= irq_2_pin
+ entry
->next
;
269 static void __mask_IO_APIC_irq(unsigned int irq
)
271 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
275 static void __unmask_IO_APIC_irq(unsigned int irq
)
277 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
280 /* mask = 1, trigger = 0 */
281 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
283 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
284 IO_APIC_REDIR_LEVEL_TRIGGER
);
287 /* mask = 0, trigger = 1 */
288 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
290 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
291 IO_APIC_REDIR_MASKED
);
294 static void mask_IO_APIC_irq(unsigned int irq
)
298 spin_lock_irqsave(&ioapic_lock
, flags
);
299 __mask_IO_APIC_irq(irq
);
300 spin_unlock_irqrestore(&ioapic_lock
, flags
);
303 static void unmask_IO_APIC_irq(unsigned int irq
)
307 spin_lock_irqsave(&ioapic_lock
, flags
);
308 __unmask_IO_APIC_irq(irq
);
309 spin_unlock_irqrestore(&ioapic_lock
, flags
);
312 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
314 struct IO_APIC_route_entry entry
;
316 /* Check delivery_mode to be sure we're not clearing an SMI pin */
317 entry
= ioapic_read_entry(apic
, pin
);
318 if (entry
.delivery_mode
== dest_SMI
)
322 * Disable it in the IO-APIC irq-routing table:
324 ioapic_mask_entry(apic
, pin
);
327 static void clear_IO_APIC(void)
331 for (apic
= 0; apic
< nr_ioapics
; apic
++)
332 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
333 clear_IO_APIC_pin(apic
, pin
);
337 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
341 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
342 unsigned int apicid_value
;
345 cpus_and(tmp
, cpumask
, cpu_online_map
);
349 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
351 apicid_value
= cpu_mask_to_apicid(cpumask
);
352 /* Prepare to do the io_apic_write */
353 apicid_value
= apicid_value
<< 24;
354 spin_lock_irqsave(&ioapic_lock
, flags
);
359 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
362 entry
= irq_2_pin
+ entry
->next
;
364 irq_desc
[irq
].affinity
= cpumask
;
365 spin_unlock_irqrestore(&ioapic_lock
, flags
);
368 #if defined(CONFIG_IRQBALANCE)
369 # include <asm/processor.h> /* kernel_thread() */
370 # include <linux/kernel_stat.h> /* kstat */
371 # include <linux/slab.h> /* kmalloc() */
372 # include <linux/timer.h>
374 #define IRQBALANCE_CHECK_ARCH -999
375 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
376 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
377 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
378 #define BALANCED_IRQ_LESS_DELTA (HZ)
380 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
381 static int physical_balance __read_mostly
;
382 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
384 static struct irq_cpu_info
{
385 unsigned long *last_irq
;
386 unsigned long *irq_delta
;
388 } irq_cpu_data
[NR_CPUS
];
390 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
391 #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
392 #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
394 #define IDLE_ENOUGH(cpu,now) \
395 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
397 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
399 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
401 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
402 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
405 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
407 balance_irq_affinity
[irq
] = mask
;
410 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
411 unsigned long now
, int direction
)
419 if (unlikely(cpu
== curr_cpu
))
422 if (direction
== 1) {
431 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
, allowed_mask
) ||
432 (search_idle
&& !IDLE_ENOUGH(cpu
, now
)));
437 static inline void balance_irq(int cpu
, int irq
)
439 unsigned long now
= jiffies
;
440 cpumask_t allowed_mask
;
441 unsigned int new_cpu
;
443 if (irqbalance_disabled
)
446 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
447 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
449 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
452 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
456 for_each_online_cpu(i
) {
457 for (j
= 0; j
< NR_IRQS
; j
++) {
458 if (!irq_desc
[j
].action
)
460 /* Is it a significant load ? */
461 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
), j
) <
462 useful_load_threshold
)
467 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
468 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
472 static void do_irq_balance(void)
475 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
476 unsigned long move_this_load
= 0;
477 int max_loaded
= 0, min_loaded
= 0;
479 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
481 int tmp_loaded
, first_attempt
= 1;
482 unsigned long tmp_cpu_irq
;
483 unsigned long imbalance
= 0;
484 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
486 for_each_possible_cpu(i
) {
491 package_index
= CPU_TO_PACKAGEINDEX(i
);
492 for (j
= 0; j
< NR_IRQS
; j
++) {
493 unsigned long value_now
, delta
;
494 /* Is this an active IRQ or balancing disabled ? */
495 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
497 if (package_index
== i
)
498 IRQ_DELTA(package_index
, j
) = 0;
499 /* Determine the total count per processor per IRQ */
500 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
502 /* Determine the activity per processor per IRQ */
503 delta
= value_now
- LAST_CPU_IRQ(i
, j
);
505 /* Update last_cpu_irq[][] for the next time */
506 LAST_CPU_IRQ(i
, j
) = value_now
;
508 /* Ignore IRQs whose rate is less than the clock */
509 if (delta
< useful_load_threshold
)
511 /* update the load for the processor or package total */
512 IRQ_DELTA(package_index
, j
) += delta
;
514 /* Keep track of the higher numbered sibling as well */
515 if (i
!= package_index
)
518 * We have sibling A and sibling B in the package
520 * cpu_irq[A] = load for cpu A + load for cpu B
521 * cpu_irq[B] = load for cpu B
523 CPU_IRQ(package_index
) += delta
;
526 /* Find the least loaded processor package */
527 for_each_online_cpu(i
) {
528 if (i
!= CPU_TO_PACKAGEINDEX(i
))
530 if (min_cpu_irq
> CPU_IRQ(i
)) {
531 min_cpu_irq
= CPU_IRQ(i
);
535 max_cpu_irq
= ULONG_MAX
;
539 * Look for heaviest loaded processor.
540 * We may come back to get the next heaviest loaded processor.
541 * Skip processors with trivial loads.
545 for_each_online_cpu(i
) {
546 if (i
!= CPU_TO_PACKAGEINDEX(i
))
548 if (max_cpu_irq
<= CPU_IRQ(i
))
550 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
551 tmp_cpu_irq
= CPU_IRQ(i
);
556 if (tmp_loaded
== -1) {
558 * In the case of small number of heavy interrupt sources,
559 * loading some of the cpus too much. We use Ingo's original
560 * approach to rotate them around.
562 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
563 rotate_irqs_among_cpus(useful_load_threshold
);
566 goto not_worth_the_effort
;
569 first_attempt
= 0; /* heaviest search */
570 max_cpu_irq
= tmp_cpu_irq
; /* load */
571 max_loaded
= tmp_loaded
; /* processor */
572 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
575 * if imbalance is less than approx 10% of max load, then
576 * observe diminishing returns action. - quit
578 if (imbalance
< (max_cpu_irq
>> 3))
579 goto not_worth_the_effort
;
582 /* if we select an IRQ to move that can't go where we want, then
583 * see if there is another one to try.
587 for (j
= 0; j
< NR_IRQS
; j
++) {
588 /* Is this an active IRQ? */
589 if (!irq_desc
[j
].action
)
591 if (imbalance
<= IRQ_DELTA(max_loaded
, j
))
593 /* Try to find the IRQ that is closest to the imbalance
594 * without going over.
596 if (move_this_load
< IRQ_DELTA(max_loaded
, j
)) {
597 move_this_load
= IRQ_DELTA(max_loaded
, j
);
601 if (selected_irq
== -1)
604 imbalance
= move_this_load
;
606 /* For physical_balance case, we accumulated both load
607 * values in the one of the siblings cpu_irq[],
608 * to use the same code for physical and logical processors
609 * as much as possible.
611 * NOTE: the cpu_irq[] array holds the sum of the load for
612 * sibling A and sibling B in the slot for the lowest numbered
613 * sibling (A), _AND_ the load for sibling B in the slot for
614 * the higher numbered sibling.
616 * We seek the least loaded sibling by making the comparison
619 load
= CPU_IRQ(min_loaded
) >> 1;
620 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
621 if (load
> CPU_IRQ(j
)) {
622 /* This won't change cpu_sibling_map[min_loaded] */
628 cpus_and(allowed_mask
,
630 balance_irq_affinity
[selected_irq
]);
631 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
632 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
634 if (!cpus_empty(tmp
)) {
635 /* mark for change destination */
636 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
638 /* Since we made a change, come back sooner to
639 * check for more variation.
641 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
642 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
647 not_worth_the_effort
:
649 * if we did not find an IRQ to move, then adjust the time interval
652 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
653 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
657 static int balanced_irq(void *unused
)
660 unsigned long prev_balance_time
= jiffies
;
661 long time_remaining
= balanced_irq_interval
;
663 /* push everything to CPU 0 to give us a starting point. */
664 for (i
= 0 ; i
< NR_IRQS
; i
++) {
665 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
666 set_pending_irq(i
, cpumask_of_cpu(0));
671 time_remaining
= schedule_timeout_interruptible(time_remaining
);
673 if (time_after(jiffies
,
674 prev_balance_time
+balanced_irq_interval
)) {
677 prev_balance_time
= jiffies
;
678 time_remaining
= balanced_irq_interval
;
685 static int __init
balanced_irq_init(void)
688 struct cpuinfo_x86
*c
;
691 cpus_shift_right(tmp
, cpu_online_map
, 2);
693 /* When not overwritten by the command line ask subarchitecture. */
694 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
695 irqbalance_disabled
= NO_BALANCE_IRQ
;
696 if (irqbalance_disabled
)
699 /* disable irqbalance completely if there is only one processor online */
700 if (num_online_cpus() < 2) {
701 irqbalance_disabled
= 1;
705 * Enable physical balance only if more than 1 physical processor
708 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
709 physical_balance
= 1;
711 for_each_online_cpu(i
) {
712 irq_cpu_data
[i
].irq_delta
= kzalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
713 irq_cpu_data
[i
].last_irq
= kzalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
714 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
715 printk(KERN_ERR
"balanced_irq_init: out of memory");
720 printk(KERN_INFO
"Starting balanced_irq\n");
721 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
723 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
725 for_each_possible_cpu(i
) {
726 kfree(irq_cpu_data
[i
].irq_delta
);
727 irq_cpu_data
[i
].irq_delta
= NULL
;
728 kfree(irq_cpu_data
[i
].last_irq
);
729 irq_cpu_data
[i
].last_irq
= NULL
;
734 int __devinit
irqbalance_disable(char *str
)
736 irqbalance_disabled
= 1;
740 __setup("noirqbalance", irqbalance_disable
);
742 late_initcall(balanced_irq_init
);
743 #endif /* CONFIG_IRQBALANCE */
744 #endif /* CONFIG_SMP */
747 void send_IPI_self(int vector
)
754 apic_wait_icr_idle();
755 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
757 * Send the IPI. The write to APIC_ICR fires this off.
759 apic_write(APIC_ICR
, cfg
);
761 #endif /* !CONFIG_SMP */
765 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
766 * specific CPU-side IRQs.
770 static int pirq_entries
[MAX_PIRQS
];
771 static int pirqs_enabled
;
772 int skip_ioapic_setup
;
774 static int __init
ioapic_pirq_setup(char *str
)
777 int ints
[MAX_PIRQS
+1];
779 get_options(str
, ARRAY_SIZE(ints
), ints
);
781 for (i
= 0; i
< MAX_PIRQS
; i
++)
782 pirq_entries
[i
] = -1;
785 apic_printk(APIC_VERBOSE
, KERN_INFO
786 "PIRQ redirection, working around broken MP-BIOS.\n");
788 if (ints
[0] < MAX_PIRQS
)
791 for (i
= 0; i
< max
; i
++) {
792 apic_printk(APIC_VERBOSE
, KERN_DEBUG
793 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
795 * PIRQs are mapped upside down, usually.
797 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
802 __setup("pirq=", ioapic_pirq_setup
);
805 * Find the IRQ entry number of a certain pin.
807 static int find_irq_entry(int apic
, int pin
, int type
)
811 for (i
= 0; i
< mp_irq_entries
; i
++)
812 if (mp_irqs
[i
].mp_irqtype
== type
&&
813 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
814 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
815 mp_irqs
[i
].mp_dstirq
== pin
)
822 * Find the pin to which IRQ[irq] (ISA) is connected
824 static int __init
find_isa_irq_pin(int irq
, int type
)
828 for (i
= 0; i
< mp_irq_entries
; i
++) {
829 int lbus
= mp_irqs
[i
].mp_srcbus
;
831 if (test_bit(lbus
, mp_bus_not_pci
) &&
832 (mp_irqs
[i
].mp_irqtype
== type
) &&
833 (mp_irqs
[i
].mp_srcbusirq
== irq
))
835 return mp_irqs
[i
].mp_dstirq
;
840 static int __init
find_isa_irq_apic(int irq
, int type
)
844 for (i
= 0; i
< mp_irq_entries
; i
++) {
845 int lbus
= mp_irqs
[i
].mp_srcbus
;
847 if (test_bit(lbus
, mp_bus_not_pci
) &&
848 (mp_irqs
[i
].mp_irqtype
== type
) &&
849 (mp_irqs
[i
].mp_srcbusirq
== irq
))
852 if (i
< mp_irq_entries
) {
854 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
855 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
864 * Find a specific PCI IRQ entry.
865 * Not an __init, possibly needed by modules
867 static int pin_2_irq(int idx
, int apic
, int pin
);
869 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
871 int apic
, i
, best_guess
= -1;
873 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
874 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
875 if (test_bit(bus
, mp_bus_not_pci
)) {
876 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
879 for (i
= 0; i
< mp_irq_entries
; i
++) {
880 int lbus
= mp_irqs
[i
].mp_srcbus
;
882 for (apic
= 0; apic
< nr_ioapics
; apic
++)
883 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
884 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
887 if (!test_bit(lbus
, mp_bus_not_pci
) &&
888 !mp_irqs
[i
].mp_irqtype
&&
890 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
891 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
893 if (!(apic
|| IO_APIC_IRQ(irq
)))
896 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
899 * Use the first all-but-pin matching entry as a
900 * best-guess fuzzy result for broken mptables.
908 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
911 * This function currently is only a helper for the i386 smp boot process where
912 * we need to reprogram the ioredtbls to cater for the cpus which have come online
913 * so mask in all cases should simply be TARGET_CPUS
916 void __init
setup_ioapic_dest(void)
918 int pin
, ioapic
, irq
, irq_entry
;
920 if (skip_ioapic_setup
== 1)
923 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
924 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
925 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
928 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
929 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
936 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
938 * EISA Edge/Level control register, ELCR
940 static int EISA_ELCR(unsigned int irq
)
943 unsigned int port
= 0x4d0 + (irq
>> 3);
944 return (inb(port
) >> (irq
& 7)) & 1;
946 apic_printk(APIC_VERBOSE
, KERN_INFO
947 "Broken MPtable reports ISA irq %d\n", irq
);
952 /* ISA interrupts are always polarity zero edge triggered,
953 * when listed as conforming in the MP table. */
955 #define default_ISA_trigger(idx) (0)
956 #define default_ISA_polarity(idx) (0)
958 /* EISA interrupts are always polarity zero and can be edge or level
959 * trigger depending on the ELCR value. If an interrupt is listed as
960 * EISA conforming in the MP table, that means its trigger type must
961 * be read in from the ELCR */
963 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
964 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
966 /* PCI interrupts are always polarity one level triggered,
967 * when listed as conforming in the MP table. */
969 #define default_PCI_trigger(idx) (1)
970 #define default_PCI_polarity(idx) (1)
972 /* MCA interrupts are always polarity zero level triggered,
973 * when listed as conforming in the MP table. */
975 #define default_MCA_trigger(idx) (1)
976 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
978 static int MPBIOS_polarity(int idx
)
980 int bus
= mp_irqs
[idx
].mp_srcbus
;
984 * Determine IRQ line polarity (high active or low active):
986 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
987 case 0: /* conforms, ie. bus-type dependent polarity */
989 polarity
= test_bit(bus
, mp_bus_not_pci
)?
990 default_ISA_polarity(idx
):
991 default_PCI_polarity(idx
);
994 case 1: /* high active */
999 case 2: /* reserved */
1001 printk(KERN_WARNING
"broken BIOS!!\n");
1005 case 3: /* low active */
1010 default: /* invalid */
1012 printk(KERN_WARNING
"broken BIOS!!\n");
1020 static int MPBIOS_trigger(int idx
)
1022 int bus
= mp_irqs
[idx
].mp_srcbus
;
1026 * Determine IRQ trigger mode (edge or level sensitive):
1028 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
1029 case 0: /* conforms, ie. bus-type dependent */
1031 trigger
= test_bit(bus
, mp_bus_not_pci
)?
1032 default_ISA_trigger(idx
):
1033 default_PCI_trigger(idx
);
1034 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1035 switch (mp_bus_id_to_type
[bus
]) {
1036 case MP_BUS_ISA
: /* ISA pin */
1038 /* set before the switch */
1041 case MP_BUS_EISA
: /* EISA pin */
1043 trigger
= default_EISA_trigger(idx
);
1046 case MP_BUS_PCI
: /* PCI pin */
1048 /* set before the switch */
1051 case MP_BUS_MCA
: /* MCA pin */
1053 trigger
= default_MCA_trigger(idx
);
1058 printk(KERN_WARNING
"broken BIOS!!\n");
1071 case 2: /* reserved */
1073 printk(KERN_WARNING
"broken BIOS!!\n");
1082 default: /* invalid */
1084 printk(KERN_WARNING
"broken BIOS!!\n");
1092 static inline int irq_polarity(int idx
)
1094 return MPBIOS_polarity(idx
);
1097 static inline int irq_trigger(int idx
)
1099 return MPBIOS_trigger(idx
);
1102 static int pin_2_irq(int idx
, int apic
, int pin
)
1105 int bus
= mp_irqs
[idx
].mp_srcbus
;
1108 * Debugging check, we are in big trouble if this message pops up!
1110 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1111 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1113 if (test_bit(bus
, mp_bus_not_pci
))
1114 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1117 * PCI IRQs are mapped in order
1121 irq
+= nr_ioapic_registers
[i
++];
1125 * For MPS mode, so far only needed by ES7000 platform
1127 if (ioapic_renumber_irq
)
1128 irq
= ioapic_renumber_irq(apic
, irq
);
1132 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1134 if ((pin
>= 16) && (pin
<= 23)) {
1135 if (pirq_entries
[pin
-16] != -1) {
1136 if (!pirq_entries
[pin
-16]) {
1137 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1138 "disabling PIRQ%d\n", pin
-16);
1140 irq
= pirq_entries
[pin
-16];
1141 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1142 "using PIRQ%d -> IRQ %d\n",
1150 static inline int IO_APIC_irq_trigger(int irq
)
1154 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1155 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1156 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1157 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1158 return irq_trigger(idx
);
1162 * nonexistent IRQs are edge default
1167 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1168 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1170 static int __assign_irq_vector(int irq
)
1172 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
;
1175 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1177 if (irq_vector
[irq
] > 0)
1178 return irq_vector
[irq
];
1180 vector
= current_vector
;
1181 offset
= current_offset
;
1184 if (vector
>= first_system_vector
) {
1185 offset
= (offset
+ 1) % 8;
1186 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1188 if (vector
== current_vector
)
1190 if (test_and_set_bit(vector
, used_vectors
))
1193 current_vector
= vector
;
1194 current_offset
= offset
;
1195 irq_vector
[irq
] = vector
;
1200 static int assign_irq_vector(int irq
)
1202 unsigned long flags
;
1205 spin_lock_irqsave(&vector_lock
, flags
);
1206 vector
= __assign_irq_vector(irq
);
1207 spin_unlock_irqrestore(&vector_lock
, flags
);
1212 void setup_vector_irq(int cpu
)
1216 static struct irq_chip ioapic_chip
;
1218 #define IOAPIC_AUTO -1
1219 #define IOAPIC_EDGE 0
1220 #define IOAPIC_LEVEL 1
1222 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1224 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1225 trigger
== IOAPIC_LEVEL
) {
1226 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1227 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1228 handle_fasteoi_irq
, "fasteoi");
1230 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1231 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1232 handle_edge_irq
, "edge");
1234 set_intr_gate(vector
, interrupt
[irq
]);
1237 static void __init
setup_IO_APIC_irqs(void)
1239 struct IO_APIC_route_entry entry
;
1240 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1242 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1244 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1245 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1248 * add it to the IO-APIC irq-routing table:
1250 memset(&entry
, 0, sizeof(entry
));
1252 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1253 entry
.dest_mode
= INT_DEST_MODE
;
1254 entry
.mask
= 0; /* enable IRQ */
1255 entry
.dest
.logical
.logical_dest
=
1256 cpu_mask_to_apicid(TARGET_CPUS
);
1258 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1261 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1262 " IO-APIC (apicid-pin) %d-%d",
1263 mp_ioapics
[apic
].mp_apicid
,
1267 apic_printk(APIC_VERBOSE
, ", %d-%d",
1268 mp_ioapics
[apic
].mp_apicid
, pin
);
1272 if (!first_notcon
) {
1273 apic_printk(APIC_VERBOSE
, " not connected.\n");
1277 entry
.trigger
= irq_trigger(idx
);
1278 entry
.polarity
= irq_polarity(idx
);
1280 if (irq_trigger(idx
)) {
1285 irq
= pin_2_irq(idx
, apic
, pin
);
1287 * skip adding the timer int on secondary nodes, which causes
1288 * a small but painful rift in the time-space continuum
1290 if (multi_timer_check(apic
, irq
))
1293 add_pin_to_irq(irq
, apic
, pin
);
1295 if (!apic
&& !IO_APIC_IRQ(irq
))
1298 if (IO_APIC_IRQ(irq
)) {
1299 vector
= assign_irq_vector(irq
);
1300 entry
.vector
= vector
;
1301 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1303 if (!apic
&& (irq
< 16))
1304 disable_8259A_irq(irq
);
1306 ioapic_write_entry(apic
, pin
, entry
);
1311 apic_printk(APIC_VERBOSE
, " not connected.\n");
1315 * Set up the timer pin, possibly with the 8259A-master behind.
1317 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1320 struct IO_APIC_route_entry entry
;
1322 memset(&entry
, 0, sizeof(entry
));
1325 * We use logical delivery to get the timer IRQ
1328 entry
.dest_mode
= INT_DEST_MODE
;
1329 entry
.mask
= 1; /* mask IRQ now */
1330 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1331 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1334 entry
.vector
= vector
;
1337 * The timer IRQ doesn't have to know that behind the
1338 * scene we may have a 8259A-master in AEOI mode ...
1340 ioapic_register_intr(0, vector
, IOAPIC_EDGE
);
1343 * Add it to the IO-APIC irq-routing table:
1345 ioapic_write_entry(apic
, pin
, entry
);
1348 void __init
print_IO_APIC(void)
1351 union IO_APIC_reg_00 reg_00
;
1352 union IO_APIC_reg_01 reg_01
;
1353 union IO_APIC_reg_02 reg_02
;
1354 union IO_APIC_reg_03 reg_03
;
1355 unsigned long flags
;
1357 if (apic_verbosity
== APIC_QUIET
)
1360 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1361 for (i
= 0; i
< nr_ioapics
; i
++)
1362 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1363 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1366 * We are a bit conservative about what we expect. We have to
1367 * know about every hardware change ASAP.
1369 printk(KERN_INFO
"testing the IO APIC.......................\n");
1371 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1373 spin_lock_irqsave(&ioapic_lock
, flags
);
1374 reg_00
.raw
= io_apic_read(apic
, 0);
1375 reg_01
.raw
= io_apic_read(apic
, 1);
1376 if (reg_01
.bits
.version
>= 0x10)
1377 reg_02
.raw
= io_apic_read(apic
, 2);
1378 if (reg_01
.bits
.version
>= 0x20)
1379 reg_03
.raw
= io_apic_read(apic
, 3);
1380 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1382 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1383 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1384 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1385 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1386 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1388 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1389 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1391 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1392 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1395 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1396 * but the value of reg_02 is read as the previous read register
1397 * value, so ignore it if reg_02 == reg_01.
1399 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1400 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1401 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1405 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1406 * or reg_03, but the value of reg_0[23] is read as the previous read
1407 * register value, so ignore it if reg_03 == reg_0[12].
1409 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1410 reg_03
.raw
!= reg_01
.raw
) {
1411 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1412 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1415 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1417 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1418 " Stat Dest Deli Vect: \n");
1420 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1421 struct IO_APIC_route_entry entry
;
1423 entry
= ioapic_read_entry(apic
, i
);
1425 printk(KERN_DEBUG
" %02x %03X %02X ",
1427 entry
.dest
.logical
.logical_dest
,
1428 entry
.dest
.physical
.physical_dest
1431 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1436 entry
.delivery_status
,
1438 entry
.delivery_mode
,
1443 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1444 for (i
= 0; i
< NR_IRQS
; i
++) {
1445 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1448 printk(KERN_DEBUG
"IRQ%d ", i
);
1450 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1453 entry
= irq_2_pin
+ entry
->next
;
1458 printk(KERN_INFO
".................................... done.\n");
1465 static void print_APIC_bitfield(int base
)
1470 if (apic_verbosity
== APIC_QUIET
)
1473 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1474 for (i
= 0; i
< 8; i
++) {
1475 v
= apic_read(base
+ i
*0x10);
1476 for (j
= 0; j
< 32; j
++) {
1486 void /*__init*/ print_local_APIC(void *dummy
)
1488 unsigned int v
, ver
, maxlvt
;
1490 if (apic_verbosity
== APIC_QUIET
)
1493 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1494 smp_processor_id(), hard_smp_processor_id());
1495 v
= apic_read(APIC_ID
);
1496 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1497 GET_APIC_ID(read_apic_id()));
1498 v
= apic_read(APIC_LVR
);
1499 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1500 ver
= GET_APIC_VERSION(v
);
1501 maxlvt
= lapic_get_maxlvt();
1503 v
= apic_read(APIC_TASKPRI
);
1504 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1506 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1507 v
= apic_read(APIC_ARBPRI
);
1508 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1509 v
& APIC_ARBPRI_MASK
);
1510 v
= apic_read(APIC_PROCPRI
);
1511 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1514 v
= apic_read(APIC_EOI
);
1515 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1516 v
= apic_read(APIC_RRR
);
1517 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1518 v
= apic_read(APIC_LDR
);
1519 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1520 v
= apic_read(APIC_DFR
);
1521 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1522 v
= apic_read(APIC_SPIV
);
1523 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1525 printk(KERN_DEBUG
"... APIC ISR field:\n");
1526 print_APIC_bitfield(APIC_ISR
);
1527 printk(KERN_DEBUG
"... APIC TMR field:\n");
1528 print_APIC_bitfield(APIC_TMR
);
1529 printk(KERN_DEBUG
"... APIC IRR field:\n");
1530 print_APIC_bitfield(APIC_IRR
);
1532 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1533 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1534 apic_write(APIC_ESR
, 0);
1535 v
= apic_read(APIC_ESR
);
1536 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1539 v
= apic_read(APIC_ICR
);
1540 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1541 v
= apic_read(APIC_ICR2
);
1542 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1544 v
= apic_read(APIC_LVTT
);
1545 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1547 if (maxlvt
> 3) { /* PC is LVT#4. */
1548 v
= apic_read(APIC_LVTPC
);
1549 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1551 v
= apic_read(APIC_LVT0
);
1552 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1553 v
= apic_read(APIC_LVT1
);
1554 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1556 if (maxlvt
> 2) { /* ERR is LVT#3. */
1557 v
= apic_read(APIC_LVTERR
);
1558 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1561 v
= apic_read(APIC_TMICT
);
1562 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1563 v
= apic_read(APIC_TMCCT
);
1564 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1565 v
= apic_read(APIC_TDCR
);
1566 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1570 void print_all_local_APICs(void)
1572 on_each_cpu(print_local_APIC
, NULL
, 1);
1575 void /*__init*/ print_PIC(void)
1578 unsigned long flags
;
1580 if (apic_verbosity
== APIC_QUIET
)
1583 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1585 spin_lock_irqsave(&i8259A_lock
, flags
);
1587 v
= inb(0xa1) << 8 | inb(0x21);
1588 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1590 v
= inb(0xa0) << 8 | inb(0x20);
1591 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1595 v
= inb(0xa0) << 8 | inb(0x20);
1599 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1601 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1603 v
= inb(0x4d1) << 8 | inb(0x4d0);
1604 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1609 static void __init
enable_IO_APIC(void)
1611 union IO_APIC_reg_01 reg_01
;
1612 int i8259_apic
, i8259_pin
;
1614 unsigned long flags
;
1616 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1617 irq_2_pin
[i
].pin
= -1;
1618 irq_2_pin
[i
].next
= 0;
1621 for (i
= 0; i
< MAX_PIRQS
; i
++)
1622 pirq_entries
[i
] = -1;
1625 * The number of IO-APIC IRQ registers (== #pins):
1627 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1628 spin_lock_irqsave(&ioapic_lock
, flags
);
1629 reg_01
.raw
= io_apic_read(apic
, 1);
1630 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1631 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1633 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1635 /* See if any of the pins is in ExtINT mode */
1636 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1637 struct IO_APIC_route_entry entry
;
1638 entry
= ioapic_read_entry(apic
, pin
);
1641 /* If the interrupt line is enabled and in ExtInt mode
1642 * I have found the pin where the i8259 is connected.
1644 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1645 ioapic_i8259
.apic
= apic
;
1646 ioapic_i8259
.pin
= pin
;
1652 /* Look to see what if the MP table has reported the ExtINT */
1653 /* If we could not find the appropriate pin by looking at the ioapic
1654 * the i8259 probably is not connected the ioapic but give the
1655 * mptable a chance anyway.
1657 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1658 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1659 /* Trust the MP table if nothing is setup in the hardware */
1660 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1661 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1662 ioapic_i8259
.pin
= i8259_pin
;
1663 ioapic_i8259
.apic
= i8259_apic
;
1665 /* Complain if the MP table and the hardware disagree */
1666 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1667 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1669 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1673 * Do not trust the IO-APIC being empty at bootup
1679 * Not an __init, needed by the reboot code
1681 void disable_IO_APIC(void)
1684 * Clear the IO-APIC before rebooting:
1689 * If the i8259 is routed through an IOAPIC
1690 * Put that IOAPIC in virtual wire mode
1691 * so legacy interrupts can be delivered.
1693 if (ioapic_i8259
.pin
!= -1) {
1694 struct IO_APIC_route_entry entry
;
1696 memset(&entry
, 0, sizeof(entry
));
1697 entry
.mask
= 0; /* Enabled */
1698 entry
.trigger
= 0; /* Edge */
1700 entry
.polarity
= 0; /* High */
1701 entry
.delivery_status
= 0;
1702 entry
.dest_mode
= 0; /* Physical */
1703 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1705 entry
.dest
.physical
.physical_dest
=
1706 GET_APIC_ID(read_apic_id());
1709 * Add it to the IO-APIC irq-routing table:
1711 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1713 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1717 * function to set the IO-APIC physical IDs based on the
1718 * values stored in the MPC table.
1720 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1723 static void __init
setup_ioapic_ids_from_mpc(void)
1725 union IO_APIC_reg_00 reg_00
;
1726 physid_mask_t phys_id_present_map
;
1729 unsigned char old_id
;
1730 unsigned long flags
;
1732 #ifdef CONFIG_X86_NUMAQ
1738 * Don't check I/O APIC IDs for xAPIC systems. They have
1739 * no meaning without the serial APIC bus.
1741 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1742 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1745 * This is broken; anything with a real cpu count has to
1746 * circumvent this idiocy regardless.
1748 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1751 * Set the IOAPIC ID to the value stored in the MPC table.
1753 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1755 /* Read the register 0 value */
1756 spin_lock_irqsave(&ioapic_lock
, flags
);
1757 reg_00
.raw
= io_apic_read(apic
, 0);
1758 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1760 old_id
= mp_ioapics
[apic
].mp_apicid
;
1762 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1763 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1764 apic
, mp_ioapics
[apic
].mp_apicid
);
1765 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1767 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1771 * Sanity check, is the ID really free? Every APIC in a
1772 * system must have a unique ID or we get lots of nice
1773 * 'stuck on smp_invalidate_needed IPI wait' messages.
1775 if (check_apicid_used(phys_id_present_map
,
1776 mp_ioapics
[apic
].mp_apicid
)) {
1777 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1778 apic
, mp_ioapics
[apic
].mp_apicid
);
1779 for (i
= 0; i
< get_physical_broadcast(); i
++)
1780 if (!physid_isset(i
, phys_id_present_map
))
1782 if (i
>= get_physical_broadcast())
1783 panic("Max APIC ID exceeded!\n");
1784 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1786 physid_set(i
, phys_id_present_map
);
1787 mp_ioapics
[apic
].mp_apicid
= i
;
1790 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1791 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1792 "phys_id_present_map\n",
1793 mp_ioapics
[apic
].mp_apicid
);
1794 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1799 * We need to adjust the IRQ routing table
1800 * if the ID changed.
1802 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1803 for (i
= 0; i
< mp_irq_entries
; i
++)
1804 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1805 mp_irqs
[i
].mp_dstapic
1806 = mp_ioapics
[apic
].mp_apicid
;
1809 * Read the right value from the MPC table and
1810 * write it into the ID register.
1812 apic_printk(APIC_VERBOSE
, KERN_INFO
1813 "...changing IO-APIC physical APIC ID to %d ...",
1814 mp_ioapics
[apic
].mp_apicid
);
1816 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1817 spin_lock_irqsave(&ioapic_lock
, flags
);
1818 io_apic_write(apic
, 0, reg_00
.raw
);
1819 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1824 spin_lock_irqsave(&ioapic_lock
, flags
);
1825 reg_00
.raw
= io_apic_read(apic
, 0);
1826 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1827 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1828 printk("could not set ID!\n");
1830 apic_printk(APIC_VERBOSE
, " ok.\n");
1834 int no_timer_check __initdata
;
1836 static int __init
notimercheck(char *s
)
1841 __setup("no_timer_check", notimercheck
);
1844 * There is a nasty bug in some older SMP boards, their mptable lies
1845 * about the timer IRQ. We do the following to work around the situation:
1847 * - timer IRQ defaults to IO-APIC IRQ
1848 * - if this function detects that timer IRQs are defunct, then we fall
1849 * back to ISA timer IRQs
1851 static int __init
timer_irq_works(void)
1853 unsigned long t1
= jiffies
;
1854 unsigned long flags
;
1859 local_save_flags(flags
);
1861 /* Let ten ticks pass... */
1862 mdelay((10 * 1000) / HZ
);
1863 local_irq_restore(flags
);
1866 * Expect a few ticks at least, to be sure some possible
1867 * glue logic does not lock up after one or two first
1868 * ticks in a non-ExtINT mode. Also the local APIC
1869 * might have cached one ExtINT interrupt. Finally, at
1870 * least one tick may be lost due to delays.
1872 if (time_after(jiffies
, t1
+ 4))
1879 * In the SMP+IOAPIC case it might happen that there are an unspecified
1880 * number of pending IRQ events unhandled. These cases are very rare,
1881 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1882 * better to do it this way as thus we do not have to be aware of
1883 * 'pending' interrupts in the IRQ path, except at this point.
1886 * Edge triggered needs to resend any interrupt
1887 * that was delayed but this is now handled in the device
1894 * Starting up a edge-triggered IO-APIC interrupt is
1895 * nasty - we need to make sure that we get the edge.
1896 * If it is already asserted for some reason, we need
1897 * return 1 to indicate that is was pending.
1899 * This is not complete - we should be able to fake
1900 * an edge even if it isn't on the 8259A...
1902 * (We do this for level-triggered IRQs too - it cannot hurt.)
1904 static unsigned int startup_ioapic_irq(unsigned int irq
)
1906 int was_pending
= 0;
1907 unsigned long flags
;
1909 spin_lock_irqsave(&ioapic_lock
, flags
);
1911 disable_8259A_irq(irq
);
1912 if (i8259A_irq_pending(irq
))
1915 __unmask_IO_APIC_irq(irq
);
1916 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1921 static void ack_ioapic_irq(unsigned int irq
)
1923 move_native_irq(irq
);
1927 static void ack_ioapic_quirk_irq(unsigned int irq
)
1932 move_native_irq(irq
);
1934 * It appears there is an erratum which affects at least version 0x11
1935 * of I/O APIC (that's the 82093AA and cores integrated into various
1936 * chipsets). Under certain conditions a level-triggered interrupt is
1937 * erroneously delivered as edge-triggered one but the respective IRR
1938 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1939 * message but it will never arrive and further interrupts are blocked
1940 * from the source. The exact reason is so far unknown, but the
1941 * phenomenon was observed when two consecutive interrupt requests
1942 * from a given source get delivered to the same CPU and the source is
1943 * temporarily disabled in between.
1945 * A workaround is to simulate an EOI message manually. We achieve it
1946 * by setting the trigger mode to edge and then to level when the edge
1947 * trigger mode gets detected in the TMR of a local APIC for a
1948 * level-triggered interrupt. We mask the source for the time of the
1949 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1950 * The idea is from Manfred Spraul. --macro
1952 i
= irq_vector
[irq
];
1954 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1958 if (!(v
& (1 << (i
& 0x1f)))) {
1959 atomic_inc(&irq_mis_count
);
1960 spin_lock(&ioapic_lock
);
1961 __mask_and_edge_IO_APIC_irq(irq
);
1962 __unmask_and_level_IO_APIC_irq(irq
);
1963 spin_unlock(&ioapic_lock
);
1967 static int ioapic_retrigger_irq(unsigned int irq
)
1969 send_IPI_self(irq_vector
[irq
]);
1974 static struct irq_chip ioapic_chip __read_mostly
= {
1976 .startup
= startup_ioapic_irq
,
1977 .mask
= mask_IO_APIC_irq
,
1978 .unmask
= unmask_IO_APIC_irq
,
1979 .ack
= ack_ioapic_irq
,
1980 .eoi
= ack_ioapic_quirk_irq
,
1982 .set_affinity
= set_ioapic_affinity_irq
,
1984 .retrigger
= ioapic_retrigger_irq
,
1988 static inline void init_IO_APIC_traps(void)
1993 * NOTE! The local APIC isn't very good at handling
1994 * multiple interrupts at the same interrupt level.
1995 * As the interrupt level is determined by taking the
1996 * vector number and shifting that right by 4, we
1997 * want to spread these out a bit so that they don't
1998 * all fall in the same interrupt level.
2000 * Also, we've got to be careful not to trash gate
2001 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2003 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2004 if (IO_APIC_IRQ(irq
) && !irq_vector
[irq
]) {
2006 * Hmm.. We don't have an entry for this,
2007 * so default to an old-fashioned 8259
2008 * interrupt if we can..
2011 make_8259A_irq(irq
);
2013 /* Strange. Oh, well.. */
2014 irq_desc
[irq
].chip
= &no_irq_chip
;
2020 * The local APIC irq-chip implementation:
2023 static void ack_lapic_irq(unsigned int irq
)
2028 static void mask_lapic_irq(unsigned int irq
)
2032 v
= apic_read(APIC_LVT0
);
2033 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2036 static void unmask_lapic_irq(unsigned int irq
)
2040 v
= apic_read(APIC_LVT0
);
2041 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2044 static struct irq_chip lapic_chip __read_mostly
= {
2045 .name
= "local-APIC",
2046 .mask
= mask_lapic_irq
,
2047 .unmask
= unmask_lapic_irq
,
2048 .ack
= ack_lapic_irq
,
2051 static void lapic_register_intr(int irq
, int vector
)
2053 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
2054 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2056 set_intr_gate(vector
, interrupt
[irq
]);
2059 static void __init
setup_nmi(void)
2062 * Dirty trick to enable the NMI watchdog ...
2063 * We put the 8259A master into AEOI mode and
2064 * unmask on all local APICs LVT0 as NMI.
2066 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2067 * is from Maciej W. Rozycki - so we do not have to EOI from
2068 * the NMI handler or the timer interrupt.
2070 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2072 enable_NMI_through_LVT0();
2074 apic_printk(APIC_VERBOSE
, " done.\n");
2078 * This looks a bit hackish but it's about the only one way of sending
2079 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2080 * not support the ExtINT mode, unfortunately. We need to send these
2081 * cycles as some i82489DX-based boards have glue logic that keeps the
2082 * 8259A interrupt line asserted until INTA. --macro
2084 static inline void __init
unlock_ExtINT_logic(void)
2087 struct IO_APIC_route_entry entry0
, entry1
;
2088 unsigned char save_control
, save_freq_select
;
2090 pin
= find_isa_irq_pin(8, mp_INT
);
2095 apic
= find_isa_irq_apic(8, mp_INT
);
2101 entry0
= ioapic_read_entry(apic
, pin
);
2102 clear_IO_APIC_pin(apic
, pin
);
2104 memset(&entry1
, 0, sizeof(entry1
));
2106 entry1
.dest_mode
= 0; /* physical delivery */
2107 entry1
.mask
= 0; /* unmask IRQ now */
2108 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2109 entry1
.delivery_mode
= dest_ExtINT
;
2110 entry1
.polarity
= entry0
.polarity
;
2114 ioapic_write_entry(apic
, pin
, entry1
);
2116 save_control
= CMOS_READ(RTC_CONTROL
);
2117 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2118 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2120 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2125 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2129 CMOS_WRITE(save_control
, RTC_CONTROL
);
2130 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2131 clear_IO_APIC_pin(apic
, pin
);
2133 ioapic_write_entry(apic
, pin
, entry0
);
2137 * This code may look a bit paranoid, but it's supposed to cooperate with
2138 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2139 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2140 * fanatically on his truly buggy board.
2142 static inline void __init
check_timer(void)
2144 int apic1
, pin1
, apic2
, pin2
;
2148 unsigned long flags
;
2150 local_irq_save(flags
);
2152 ver
= apic_read(APIC_LVR
);
2153 ver
= GET_APIC_VERSION(ver
);
2156 * get/set the timer IRQ vector:
2158 disable_8259A_irq(0);
2159 vector
= assign_irq_vector(0);
2160 set_intr_gate(vector
, interrupt
[0]);
2163 * As IRQ0 is to be enabled in the 8259A, the virtual
2164 * wire has to be disabled in the local APIC. Also
2165 * timer interrupts need to be acknowledged manually in
2166 * the 8259A for the i82489DX when using the NMI
2167 * watchdog as that APIC treats NMIs as level-triggered.
2168 * The AEOI mode will finish them in the 8259A
2171 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2173 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2175 pin1
= find_isa_irq_pin(0, mp_INT
);
2176 apic1
= find_isa_irq_apic(0, mp_INT
);
2177 pin2
= ioapic_i8259
.pin
;
2178 apic2
= ioapic_i8259
.apic
;
2180 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2181 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2182 vector
, apic1
, pin1
, apic2
, pin2
);
2185 * Some BIOS writers are clueless and report the ExtINTA
2186 * I/O APIC input from the cascaded 8259A as the timer
2187 * interrupt input. So just in case, if only one pin
2188 * was found above, try it both directly and through the
2195 } else if (pin2
== -1) {
2202 * Ok, does IRQ0 through the IOAPIC work?
2205 add_pin_to_irq(0, apic1
, pin1
);
2206 setup_timer_IRQ0_pin(apic1
, pin1
, vector
);
2208 unmask_IO_APIC_irq(0);
2209 if (timer_irq_works()) {
2210 if (nmi_watchdog
== NMI_IO_APIC
) {
2212 enable_8259A_irq(0);
2214 if (disable_timer_pin_1
> 0)
2215 clear_IO_APIC_pin(0, pin1
);
2218 clear_IO_APIC_pin(apic1
, pin1
);
2220 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2221 "8254 timer not connected to IO-APIC\n");
2223 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2224 "(IRQ0) through the 8259A ...\n");
2225 apic_printk(APIC_QUIET
, KERN_INFO
2226 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2228 * legacy devices should be connected to IO APIC #0
2230 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2231 setup_timer_IRQ0_pin(apic2
, pin2
, vector
);
2232 unmask_IO_APIC_irq(0);
2233 enable_8259A_irq(0);
2234 if (timer_irq_works()) {
2235 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2236 timer_through_8259
= 1;
2237 if (nmi_watchdog
== NMI_IO_APIC
) {
2238 disable_8259A_irq(0);
2240 enable_8259A_irq(0);
2245 * Cleanup, just in case ...
2247 disable_8259A_irq(0);
2248 clear_IO_APIC_pin(apic2
, pin2
);
2249 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2252 if (nmi_watchdog
== NMI_IO_APIC
) {
2253 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2254 "through the IO-APIC - disabling NMI Watchdog!\n");
2255 nmi_watchdog
= NMI_NONE
;
2259 apic_printk(APIC_QUIET
, KERN_INFO
2260 "...trying to set up timer as Virtual Wire IRQ...\n");
2262 lapic_register_intr(0, vector
);
2263 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2264 enable_8259A_irq(0);
2266 if (timer_irq_works()) {
2267 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2270 disable_8259A_irq(0);
2271 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2272 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2274 apic_printk(APIC_QUIET
, KERN_INFO
2275 "...trying to set up timer as ExtINT IRQ...\n");
2279 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2281 unlock_ExtINT_logic();
2283 if (timer_irq_works()) {
2284 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2287 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2288 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2289 "report. Then try booting with the 'noapic' option.\n");
2291 local_irq_restore(flags
);
2295 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2296 * to devices. However there may be an I/O APIC pin available for
2297 * this interrupt regardless. The pin may be left unconnected, but
2298 * typically it will be reused as an ExtINT cascade interrupt for
2299 * the master 8259A. In the MPS case such a pin will normally be
2300 * reported as an ExtINT interrupt in the MP table. With ACPI
2301 * there is no provision for ExtINT interrupts, and in the absence
2302 * of an override it would be treated as an ordinary ISA I/O APIC
2303 * interrupt, that is edge-triggered and unmasked by default. We
2304 * used to do this, but it caused problems on some systems because
2305 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2306 * the same ExtINT cascade interrupt to drive the local APIC of the
2307 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2308 * the I/O APIC in all cases now. No actual device should request
2309 * it anyway. --macro
2311 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2313 void __init
setup_IO_APIC(void)
2317 /* Reserve all the system vectors. */
2318 for (i
= first_system_vector
; i
< NR_VECTORS
; i
++)
2319 set_bit(i
, used_vectors
);
2323 io_apic_irqs
= ~PIC_IRQS
;
2325 printk("ENABLING IO-APIC IRQs\n");
2328 * Set up IO-APIC IRQ routing.
2331 setup_ioapic_ids_from_mpc();
2333 setup_IO_APIC_irqs();
2334 init_IO_APIC_traps();
2341 * Called after all the initialization is done. If we didnt find any
2342 * APIC bugs then we can allow the modify fast path
2345 static int __init
io_apic_bug_finalize(void)
2347 if (sis_apic_bug
== -1)
2352 late_initcall(io_apic_bug_finalize
);
2354 struct sysfs_ioapic_data
{
2355 struct sys_device dev
;
2356 struct IO_APIC_route_entry entry
[0];
2358 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2360 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2362 struct IO_APIC_route_entry
*entry
;
2363 struct sysfs_ioapic_data
*data
;
2366 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2367 entry
= data
->entry
;
2368 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2369 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2374 static int ioapic_resume(struct sys_device
*dev
)
2376 struct IO_APIC_route_entry
*entry
;
2377 struct sysfs_ioapic_data
*data
;
2378 unsigned long flags
;
2379 union IO_APIC_reg_00 reg_00
;
2382 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2383 entry
= data
->entry
;
2385 spin_lock_irqsave(&ioapic_lock
, flags
);
2386 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2387 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2388 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2389 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2391 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2392 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2393 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2398 static struct sysdev_class ioapic_sysdev_class
= {
2400 .suspend
= ioapic_suspend
,
2401 .resume
= ioapic_resume
,
2404 static int __init
ioapic_init_sysfs(void)
2406 struct sys_device
*dev
;
2407 int i
, size
, error
= 0;
2409 error
= sysdev_class_register(&ioapic_sysdev_class
);
2413 for (i
= 0; i
< nr_ioapics
; i
++) {
2414 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2415 * sizeof(struct IO_APIC_route_entry
);
2416 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2417 if (!mp_ioapic_data
[i
]) {
2418 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2421 dev
= &mp_ioapic_data
[i
]->dev
;
2423 dev
->cls
= &ioapic_sysdev_class
;
2424 error
= sysdev_register(dev
);
2426 kfree(mp_ioapic_data
[i
]);
2427 mp_ioapic_data
[i
] = NULL
;
2428 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2436 device_initcall(ioapic_init_sysfs
);
2439 * Dynamic irq allocate and deallocation
2441 int create_irq(void)
2443 /* Allocate an unused irq */
2444 int irq
, new, vector
= 0;
2445 unsigned long flags
;
2448 spin_lock_irqsave(&vector_lock
, flags
);
2449 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2450 if (platform_legacy_irq(new))
2452 if (irq_vector
[new] != 0)
2454 vector
= __assign_irq_vector(new);
2455 if (likely(vector
> 0))
2459 spin_unlock_irqrestore(&vector_lock
, flags
);
2462 set_intr_gate(vector
, interrupt
[irq
]);
2463 dynamic_irq_init(irq
);
2468 void destroy_irq(unsigned int irq
)
2470 unsigned long flags
;
2472 dynamic_irq_cleanup(irq
);
2474 spin_lock_irqsave(&vector_lock
, flags
);
2475 clear_bit(irq_vector
[irq
], used_vectors
);
2476 irq_vector
[irq
] = 0;
2477 spin_unlock_irqrestore(&vector_lock
, flags
);
2481 * MSI message composition
2483 #ifdef CONFIG_PCI_MSI
2484 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2489 vector
= assign_irq_vector(irq
);
2491 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2493 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2496 ((INT_DEST_MODE
== 0) ?
2497 MSI_ADDR_DEST_MODE_PHYSICAL
:
2498 MSI_ADDR_DEST_MODE_LOGICAL
) |
2499 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2500 MSI_ADDR_REDIRECTION_CPU
:
2501 MSI_ADDR_REDIRECTION_LOWPRI
) |
2502 MSI_ADDR_DEST_ID(dest
);
2505 MSI_DATA_TRIGGER_EDGE
|
2506 MSI_DATA_LEVEL_ASSERT
|
2507 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2508 MSI_DATA_DELIVERY_FIXED
:
2509 MSI_DATA_DELIVERY_LOWPRI
) |
2510 MSI_DATA_VECTOR(vector
);
2516 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2523 cpus_and(tmp
, mask
, cpu_online_map
);
2524 if (cpus_empty(tmp
))
2527 vector
= assign_irq_vector(irq
);
2531 dest
= cpu_mask_to_apicid(mask
);
2533 read_msi_msg(irq
, &msg
);
2535 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2536 msg
.data
|= MSI_DATA_VECTOR(vector
);
2537 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2538 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2540 write_msi_msg(irq
, &msg
);
2541 irq_desc
[irq
].affinity
= mask
;
2543 #endif /* CONFIG_SMP */
2546 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2547 * which implement the MSI or MSI-X Capability Structure.
2549 static struct irq_chip msi_chip
= {
2551 .unmask
= unmask_msi_irq
,
2552 .mask
= mask_msi_irq
,
2553 .ack
= ack_ioapic_irq
,
2555 .set_affinity
= set_msi_irq_affinity
,
2557 .retrigger
= ioapic_retrigger_irq
,
2560 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2568 ret
= msi_compose_msg(dev
, irq
, &msg
);
2574 set_irq_msi(irq
, desc
);
2575 write_msi_msg(irq
, &msg
);
2577 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2583 void arch_teardown_msi_irq(unsigned int irq
)
2588 #endif /* CONFIG_PCI_MSI */
2591 * Hypertransport interrupt support
2593 #ifdef CONFIG_HT_IRQ
2597 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2599 struct ht_irq_msg msg
;
2600 fetch_ht_irq_msg(irq
, &msg
);
2602 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2603 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2605 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2606 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2608 write_ht_irq_msg(irq
, &msg
);
2611 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2616 cpus_and(tmp
, mask
, cpu_online_map
);
2617 if (cpus_empty(tmp
))
2620 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2622 dest
= cpu_mask_to_apicid(mask
);
2624 target_ht_irq(irq
, dest
);
2625 irq_desc
[irq
].affinity
= mask
;
2629 static struct irq_chip ht_irq_chip
= {
2631 .mask
= mask_ht_irq
,
2632 .unmask
= unmask_ht_irq
,
2633 .ack
= ack_ioapic_irq
,
2635 .set_affinity
= set_ht_irq_affinity
,
2637 .retrigger
= ioapic_retrigger_irq
,
2640 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2644 vector
= assign_irq_vector(irq
);
2646 struct ht_irq_msg msg
;
2651 cpu_set(vector
>> 8, tmp
);
2652 dest
= cpu_mask_to_apicid(tmp
);
2654 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2658 HT_IRQ_LOW_DEST_ID(dest
) |
2659 HT_IRQ_LOW_VECTOR(vector
) |
2660 ((INT_DEST_MODE
== 0) ?
2661 HT_IRQ_LOW_DM_PHYSICAL
:
2662 HT_IRQ_LOW_DM_LOGICAL
) |
2663 HT_IRQ_LOW_RQEOI_EDGE
|
2664 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2665 HT_IRQ_LOW_MT_FIXED
:
2666 HT_IRQ_LOW_MT_ARBITRATED
) |
2667 HT_IRQ_LOW_IRQ_MASKED
;
2669 write_ht_irq_msg(irq
, &msg
);
2671 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2672 handle_edge_irq
, "edge");
2676 #endif /* CONFIG_HT_IRQ */
2678 /* --------------------------------------------------------------------------
2679 ACPI-based IOAPIC Configuration
2680 -------------------------------------------------------------------------- */
2684 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2686 union IO_APIC_reg_00 reg_00
;
2687 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2689 unsigned long flags
;
2693 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2694 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2695 * supports up to 16 on one shared APIC bus.
2697 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2698 * advantage of new APIC bus architecture.
2701 if (physids_empty(apic_id_map
))
2702 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2704 spin_lock_irqsave(&ioapic_lock
, flags
);
2705 reg_00
.raw
= io_apic_read(ioapic
, 0);
2706 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2708 if (apic_id
>= get_physical_broadcast()) {
2709 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2710 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2711 apic_id
= reg_00
.bits
.ID
;
2715 * Every APIC in a system must have a unique ID or we get lots of nice
2716 * 'stuck on smp_invalidate_needed IPI wait' messages.
2718 if (check_apicid_used(apic_id_map
, apic_id
)) {
2720 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2721 if (!check_apicid_used(apic_id_map
, i
))
2725 if (i
== get_physical_broadcast())
2726 panic("Max apic_id exceeded!\n");
2728 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2729 "trying %d\n", ioapic
, apic_id
, i
);
2734 tmp
= apicid_to_cpu_present(apic_id
);
2735 physids_or(apic_id_map
, apic_id_map
, tmp
);
2737 if (reg_00
.bits
.ID
!= apic_id
) {
2738 reg_00
.bits
.ID
= apic_id
;
2740 spin_lock_irqsave(&ioapic_lock
, flags
);
2741 io_apic_write(ioapic
, 0, reg_00
.raw
);
2742 reg_00
.raw
= io_apic_read(ioapic
, 0);
2743 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2746 if (reg_00
.bits
.ID
!= apic_id
) {
2747 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2752 apic_printk(APIC_VERBOSE
, KERN_INFO
2753 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2759 int __init
io_apic_get_version(int ioapic
)
2761 union IO_APIC_reg_01 reg_01
;
2762 unsigned long flags
;
2764 spin_lock_irqsave(&ioapic_lock
, flags
);
2765 reg_01
.raw
= io_apic_read(ioapic
, 1);
2766 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2768 return reg_01
.bits
.version
;
2772 int __init
io_apic_get_redir_entries(int ioapic
)
2774 union IO_APIC_reg_01 reg_01
;
2775 unsigned long flags
;
2777 spin_lock_irqsave(&ioapic_lock
, flags
);
2778 reg_01
.raw
= io_apic_read(ioapic
, 1);
2779 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2781 return reg_01
.bits
.entries
;
2785 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2787 struct IO_APIC_route_entry entry
;
2789 if (!IO_APIC_IRQ(irq
)) {
2790 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2796 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2797 * Note that we mask (disable) IRQs now -- these get enabled when the
2798 * corresponding device driver registers for this IRQ.
2801 memset(&entry
, 0, sizeof(entry
));
2803 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2804 entry
.dest_mode
= INT_DEST_MODE
;
2805 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2806 entry
.trigger
= edge_level
;
2807 entry
.polarity
= active_high_low
;
2811 * IRQs < 16 are already in the irq_2_pin[] map
2814 add_pin_to_irq(irq
, ioapic
, pin
);
2816 entry
.vector
= assign_irq_vector(irq
);
2818 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2819 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2820 mp_ioapics
[ioapic
].mp_apicid
, pin
, entry
.vector
, irq
,
2821 edge_level
, active_high_low
);
2823 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2825 if (!ioapic
&& (irq
< 16))
2826 disable_8259A_irq(irq
);
2828 ioapic_write_entry(ioapic
, pin
, entry
);
2833 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2837 if (skip_ioapic_setup
)
2840 for (i
= 0; i
< mp_irq_entries
; i
++)
2841 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2842 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2844 if (i
>= mp_irq_entries
)
2847 *trigger
= irq_trigger(i
);
2848 *polarity
= irq_polarity(i
);
2852 #endif /* CONFIG_ACPI */
2854 static int __init
parse_disable_timer_pin_1(char *arg
)
2856 disable_timer_pin_1
= 1;
2859 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2861 static int __init
parse_enable_timer_pin_1(char *arg
)
2863 disable_timer_pin_1
= -1;
2866 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2868 static int __init
parse_noapic(char *arg
)
2870 /* disable IO-APIC */
2871 disable_ioapic_setup();
2874 early_param("noapic", parse_noapic
);
2876 void __init
ioapic_init_mappings(void)
2878 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2881 for (i
= 0; i
< nr_ioapics
; i
++) {
2882 if (smp_found_config
) {
2883 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2886 "WARNING: bogus zero IO-APIC "
2887 "address found in MPTABLE, "
2888 "disabling IO/APIC support!\n");
2889 smp_found_config
= 0;
2890 skip_ioapic_setup
= 1;
2891 goto fake_ioapic_page
;
2895 ioapic_phys
= (unsigned long)
2896 alloc_bootmem_pages(PAGE_SIZE
);
2897 ioapic_phys
= __pa(ioapic_phys
);
2899 set_fixmap_nocache(idx
, ioapic_phys
);
2900 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
2901 __fix_to_virt(idx
), ioapic_phys
);