2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/bootmem.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
37 #include <linux/freezer.h>
38 #include <linux/kthread.h>
39 #include <linux/jiffies.h> /* time_after() */
44 #include <asm/timer.h>
45 #include <asm/i8259.h>
47 #include <asm/msidef.h>
48 #include <asm/hypertransport.h>
49 #include <asm/setup.h>
51 #include <mach_apic.h>
52 #include <mach_apicdef.h>
54 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
55 atomic_t irq_mis_count
;
57 /* Where if anywhere is the i8259 connect in external int mode */
58 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
60 static DEFINE_SPINLOCK(ioapic_lock
);
61 static DEFINE_SPINLOCK(vector_lock
);
63 int timer_through_8259 __initdata
;
66 * Is the SiS APIC rmw bug present ?
67 * -1 = don't know, 0 = no, 1 = yes
69 int sis_apic_bug
= -1;
72 * # of IRQ routing registers
74 int nr_ioapic_registers
[MAX_IO_APICS
];
76 /* I/O APIC entries */
77 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
80 /* MP IRQ source entries */
81 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
83 /* # of MP IRQ source entries */
86 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
87 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
90 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
92 static int disable_timer_pin_1 __initdata
;
95 * Rough estimation of how many shared IRQs there are, can
98 #define MAX_PLUS_SHARED_IRQS NR_IRQS
99 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
102 * This is performance-critical, we want to do it O(1)
104 * the indexing order of this array favors 1:1 mappings
105 * between pins and IRQs.
108 static struct irq_pin_list
{
110 } irq_2_pin
[PIN_MAP_SIZE
];
114 unsigned int unused
[3];
118 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
120 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
121 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
124 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
126 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
127 writel(reg
, &io_apic
->index
);
128 return readl(&io_apic
->data
);
131 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
133 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
134 writel(reg
, &io_apic
->index
);
135 writel(value
, &io_apic
->data
);
139 * Re-write a value: to be used for read-modify-write
140 * cycles where the read already set up the index register.
142 * Older SiS APIC requires we rewrite the index register
144 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
146 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
148 writel(reg
, &io_apic
->index
);
149 writel(value
, &io_apic
->data
);
153 struct { u32 w1
, w2
; };
154 struct IO_APIC_route_entry entry
;
157 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
159 union entry_union eu
;
161 spin_lock_irqsave(&ioapic_lock
, flags
);
162 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
163 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
164 spin_unlock_irqrestore(&ioapic_lock
, flags
);
169 * When we write a new IO APIC routing entry, we need to write the high
170 * word first! If the mask bit in the low word is clear, we will enable
171 * the interrupt, and we need to make sure the entry is fully populated
172 * before that happens.
175 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
177 union entry_union eu
;
179 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
180 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
183 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
186 spin_lock_irqsave(&ioapic_lock
, flags
);
187 __ioapic_write_entry(apic
, pin
, e
);
188 spin_unlock_irqrestore(&ioapic_lock
, flags
);
192 * When we mask an IO APIC routing entry, we need to write the low
193 * word first, in order to set the mask bit before we change the
196 static void ioapic_mask_entry(int apic
, int pin
)
199 union entry_union eu
= { .entry
.mask
= 1 };
201 spin_lock_irqsave(&ioapic_lock
, flags
);
202 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
203 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
204 spin_unlock_irqrestore(&ioapic_lock
, flags
);
208 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
209 * shared ISA-space IRQs, so we have to support them. We are super
210 * fast in the common case, and fast for shared ISA-space IRQs.
212 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
214 static int first_free_entry
= NR_IRQS
;
215 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
218 entry
= irq_2_pin
+ entry
->next
;
220 if (entry
->pin
!= -1) {
221 entry
->next
= first_free_entry
;
222 entry
= irq_2_pin
+ entry
->next
;
223 if (++first_free_entry
>= PIN_MAP_SIZE
)
224 panic("io_apic.c: whoops");
231 * Reroute an IRQ to a different pin.
233 static void __init
replace_pin_at_irq(unsigned int irq
,
234 int oldapic
, int oldpin
,
235 int newapic
, int newpin
)
237 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
240 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
241 entry
->apic
= newapic
;
246 entry
= irq_2_pin
+ entry
->next
;
250 static void __modify_IO_APIC_irq(unsigned int irq
, unsigned long enable
, unsigned long disable
)
252 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
253 unsigned int pin
, reg
;
259 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
262 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
265 entry
= irq_2_pin
+ entry
->next
;
270 static void __mask_IO_APIC_irq(unsigned int irq
)
272 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
, 0);
276 static void __unmask_IO_APIC_irq(unsigned int irq
)
278 __modify_IO_APIC_irq(irq
, 0, IO_APIC_REDIR_MASKED
);
281 /* mask = 1, trigger = 0 */
282 static void __mask_and_edge_IO_APIC_irq(unsigned int irq
)
284 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_MASKED
,
285 IO_APIC_REDIR_LEVEL_TRIGGER
);
288 /* mask = 0, trigger = 1 */
289 static void __unmask_and_level_IO_APIC_irq(unsigned int irq
)
291 __modify_IO_APIC_irq(irq
, IO_APIC_REDIR_LEVEL_TRIGGER
,
292 IO_APIC_REDIR_MASKED
);
295 static void mask_IO_APIC_irq(unsigned int irq
)
299 spin_lock_irqsave(&ioapic_lock
, flags
);
300 __mask_IO_APIC_irq(irq
);
301 spin_unlock_irqrestore(&ioapic_lock
, flags
);
304 static void unmask_IO_APIC_irq(unsigned int irq
)
308 spin_lock_irqsave(&ioapic_lock
, flags
);
309 __unmask_IO_APIC_irq(irq
);
310 spin_unlock_irqrestore(&ioapic_lock
, flags
);
313 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
315 struct IO_APIC_route_entry entry
;
317 /* Check delivery_mode to be sure we're not clearing an SMI pin */
318 entry
= ioapic_read_entry(apic
, pin
);
319 if (entry
.delivery_mode
== dest_SMI
)
323 * Disable it in the IO-APIC irq-routing table:
325 ioapic_mask_entry(apic
, pin
);
328 static void clear_IO_APIC(void)
332 for (apic
= 0; apic
< nr_ioapics
; apic
++)
333 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
334 clear_IO_APIC_pin(apic
, pin
);
338 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
342 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
343 unsigned int apicid_value
;
346 cpus_and(tmp
, cpumask
, cpu_online_map
);
350 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
352 apicid_value
= cpu_mask_to_apicid(cpumask
);
353 /* Prepare to do the io_apic_write */
354 apicid_value
= apicid_value
<< 24;
355 spin_lock_irqsave(&ioapic_lock
, flags
);
360 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
363 entry
= irq_2_pin
+ entry
->next
;
365 irq_desc
[irq
].affinity
= cpumask
;
366 spin_unlock_irqrestore(&ioapic_lock
, flags
);
369 #if defined(CONFIG_IRQBALANCE)
370 # include <asm/processor.h> /* kernel_thread() */
371 # include <linux/kernel_stat.h> /* kstat */
372 # include <linux/slab.h> /* kmalloc() */
373 # include <linux/timer.h>
375 #define IRQBALANCE_CHECK_ARCH -999
376 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
377 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
378 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
379 #define BALANCED_IRQ_LESS_DELTA (HZ)
381 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
382 static int physical_balance __read_mostly
;
383 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
385 static struct irq_cpu_info
{
386 unsigned long *last_irq
;
387 unsigned long *irq_delta
;
389 } irq_cpu_data
[NR_CPUS
];
391 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
392 #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
393 #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
395 #define IDLE_ENOUGH(cpu,now) \
396 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
398 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
400 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
402 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
403 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
406 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
408 balance_irq_affinity
[irq
] = mask
;
411 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
412 unsigned long now
, int direction
)
420 if (unlikely(cpu
== curr_cpu
))
423 if (direction
== 1) {
432 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
, allowed_mask
) ||
433 (search_idle
&& !IDLE_ENOUGH(cpu
, now
)));
438 static inline void balance_irq(int cpu
, int irq
)
440 unsigned long now
= jiffies
;
441 cpumask_t allowed_mask
;
442 unsigned int new_cpu
;
444 if (irqbalance_disabled
)
447 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
448 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
450 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
453 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
457 for_each_online_cpu(i
) {
458 for (j
= 0; j
< NR_IRQS
; j
++) {
459 if (!irq_desc
[j
].action
)
461 /* Is it a significant load ? */
462 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
), j
) <
463 useful_load_threshold
)
468 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
469 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
473 static void do_irq_balance(void)
476 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
477 unsigned long move_this_load
= 0;
478 int max_loaded
= 0, min_loaded
= 0;
480 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
482 int tmp_loaded
, first_attempt
= 1;
483 unsigned long tmp_cpu_irq
;
484 unsigned long imbalance
= 0;
485 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
487 for_each_possible_cpu(i
) {
492 package_index
= CPU_TO_PACKAGEINDEX(i
);
493 for (j
= 0; j
< NR_IRQS
; j
++) {
494 unsigned long value_now
, delta
;
495 /* Is this an active IRQ or balancing disabled ? */
496 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
498 if (package_index
== i
)
499 IRQ_DELTA(package_index
, j
) = 0;
500 /* Determine the total count per processor per IRQ */
501 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
503 /* Determine the activity per processor per IRQ */
504 delta
= value_now
- LAST_CPU_IRQ(i
, j
);
506 /* Update last_cpu_irq[][] for the next time */
507 LAST_CPU_IRQ(i
, j
) = value_now
;
509 /* Ignore IRQs whose rate is less than the clock */
510 if (delta
< useful_load_threshold
)
512 /* update the load for the processor or package total */
513 IRQ_DELTA(package_index
, j
) += delta
;
515 /* Keep track of the higher numbered sibling as well */
516 if (i
!= package_index
)
519 * We have sibling A and sibling B in the package
521 * cpu_irq[A] = load for cpu A + load for cpu B
522 * cpu_irq[B] = load for cpu B
524 CPU_IRQ(package_index
) += delta
;
527 /* Find the least loaded processor package */
528 for_each_online_cpu(i
) {
529 if (i
!= CPU_TO_PACKAGEINDEX(i
))
531 if (min_cpu_irq
> CPU_IRQ(i
)) {
532 min_cpu_irq
= CPU_IRQ(i
);
536 max_cpu_irq
= ULONG_MAX
;
540 * Look for heaviest loaded processor.
541 * We may come back to get the next heaviest loaded processor.
542 * Skip processors with trivial loads.
546 for_each_online_cpu(i
) {
547 if (i
!= CPU_TO_PACKAGEINDEX(i
))
549 if (max_cpu_irq
<= CPU_IRQ(i
))
551 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
552 tmp_cpu_irq
= CPU_IRQ(i
);
557 if (tmp_loaded
== -1) {
559 * In the case of small number of heavy interrupt sources,
560 * loading some of the cpus too much. We use Ingo's original
561 * approach to rotate them around.
563 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
564 rotate_irqs_among_cpus(useful_load_threshold
);
567 goto not_worth_the_effort
;
570 first_attempt
= 0; /* heaviest search */
571 max_cpu_irq
= tmp_cpu_irq
; /* load */
572 max_loaded
= tmp_loaded
; /* processor */
573 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
576 * if imbalance is less than approx 10% of max load, then
577 * observe diminishing returns action. - quit
579 if (imbalance
< (max_cpu_irq
>> 3))
580 goto not_worth_the_effort
;
583 /* if we select an IRQ to move that can't go where we want, then
584 * see if there is another one to try.
588 for (j
= 0; j
< NR_IRQS
; j
++) {
589 /* Is this an active IRQ? */
590 if (!irq_desc
[j
].action
)
592 if (imbalance
<= IRQ_DELTA(max_loaded
, j
))
594 /* Try to find the IRQ that is closest to the imbalance
595 * without going over.
597 if (move_this_load
< IRQ_DELTA(max_loaded
, j
)) {
598 move_this_load
= IRQ_DELTA(max_loaded
, j
);
602 if (selected_irq
== -1)
605 imbalance
= move_this_load
;
607 /* For physical_balance case, we accumulated both load
608 * values in the one of the siblings cpu_irq[],
609 * to use the same code for physical and logical processors
610 * as much as possible.
612 * NOTE: the cpu_irq[] array holds the sum of the load for
613 * sibling A and sibling B in the slot for the lowest numbered
614 * sibling (A), _AND_ the load for sibling B in the slot for
615 * the higher numbered sibling.
617 * We seek the least loaded sibling by making the comparison
620 load
= CPU_IRQ(min_loaded
) >> 1;
621 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
622 if (load
> CPU_IRQ(j
)) {
623 /* This won't change cpu_sibling_map[min_loaded] */
629 cpus_and(allowed_mask
,
631 balance_irq_affinity
[selected_irq
]);
632 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
633 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
635 if (!cpus_empty(tmp
)) {
636 /* mark for change destination */
637 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
639 /* Since we made a change, come back sooner to
640 * check for more variation.
642 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
643 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
648 not_worth_the_effort
:
650 * if we did not find an IRQ to move, then adjust the time interval
653 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
654 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
658 static int balanced_irq(void *unused
)
661 unsigned long prev_balance_time
= jiffies
;
662 long time_remaining
= balanced_irq_interval
;
664 /* push everything to CPU 0 to give us a starting point. */
665 for (i
= 0 ; i
< NR_IRQS
; i
++) {
666 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
667 set_pending_irq(i
, cpumask_of_cpu(0));
672 time_remaining
= schedule_timeout_interruptible(time_remaining
);
674 if (time_after(jiffies
,
675 prev_balance_time
+balanced_irq_interval
)) {
678 prev_balance_time
= jiffies
;
679 time_remaining
= balanced_irq_interval
;
686 static int __init
balanced_irq_init(void)
689 struct cpuinfo_x86
*c
;
692 cpus_shift_right(tmp
, cpu_online_map
, 2);
694 /* When not overwritten by the command line ask subarchitecture. */
695 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
696 irqbalance_disabled
= NO_BALANCE_IRQ
;
697 if (irqbalance_disabled
)
700 /* disable irqbalance completely if there is only one processor online */
701 if (num_online_cpus() < 2) {
702 irqbalance_disabled
= 1;
706 * Enable physical balance only if more than 1 physical processor
709 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
710 physical_balance
= 1;
712 for_each_online_cpu(i
) {
713 irq_cpu_data
[i
].irq_delta
= kzalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
714 irq_cpu_data
[i
].last_irq
= kzalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
715 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
716 printk(KERN_ERR
"balanced_irq_init: out of memory");
721 printk(KERN_INFO
"Starting balanced_irq\n");
722 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
724 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
726 for_each_possible_cpu(i
) {
727 kfree(irq_cpu_data
[i
].irq_delta
);
728 irq_cpu_data
[i
].irq_delta
= NULL
;
729 kfree(irq_cpu_data
[i
].last_irq
);
730 irq_cpu_data
[i
].last_irq
= NULL
;
735 int __devinit
irqbalance_disable(char *str
)
737 irqbalance_disabled
= 1;
741 __setup("noirqbalance", irqbalance_disable
);
743 late_initcall(balanced_irq_init
);
744 #endif /* CONFIG_IRQBALANCE */
745 #endif /* CONFIG_SMP */
748 void send_IPI_self(int vector
)
755 apic_wait_icr_idle();
756 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
758 * Send the IPI. The write to APIC_ICR fires this off.
760 apic_write(APIC_ICR
, cfg
);
762 #endif /* !CONFIG_SMP */
766 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
767 * specific CPU-side IRQs.
771 static int pirq_entries
[MAX_PIRQS
];
772 static int pirqs_enabled
;
773 int skip_ioapic_setup
;
775 static int __init
ioapic_pirq_setup(char *str
)
778 int ints
[MAX_PIRQS
+1];
780 get_options(str
, ARRAY_SIZE(ints
), ints
);
782 for (i
= 0; i
< MAX_PIRQS
; i
++)
783 pirq_entries
[i
] = -1;
786 apic_printk(APIC_VERBOSE
, KERN_INFO
787 "PIRQ redirection, working around broken MP-BIOS.\n");
789 if (ints
[0] < MAX_PIRQS
)
792 for (i
= 0; i
< max
; i
++) {
793 apic_printk(APIC_VERBOSE
, KERN_DEBUG
794 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
796 * PIRQs are mapped upside down, usually.
798 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
803 __setup("pirq=", ioapic_pirq_setup
);
806 * Find the IRQ entry number of a certain pin.
808 static int find_irq_entry(int apic
, int pin
, int type
)
812 for (i
= 0; i
< mp_irq_entries
; i
++)
813 if (mp_irqs
[i
].mp_irqtype
== type
&&
814 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
815 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
816 mp_irqs
[i
].mp_dstirq
== pin
)
823 * Find the pin to which IRQ[irq] (ISA) is connected
825 static int __init
find_isa_irq_pin(int irq
, int type
)
829 for (i
= 0; i
< mp_irq_entries
; i
++) {
830 int lbus
= mp_irqs
[i
].mp_srcbus
;
832 if (test_bit(lbus
, mp_bus_not_pci
) &&
833 (mp_irqs
[i
].mp_irqtype
== type
) &&
834 (mp_irqs
[i
].mp_srcbusirq
== irq
))
836 return mp_irqs
[i
].mp_dstirq
;
841 static int __init
find_isa_irq_apic(int irq
, int type
)
845 for (i
= 0; i
< mp_irq_entries
; i
++) {
846 int lbus
= mp_irqs
[i
].mp_srcbus
;
848 if (test_bit(lbus
, mp_bus_not_pci
) &&
849 (mp_irqs
[i
].mp_irqtype
== type
) &&
850 (mp_irqs
[i
].mp_srcbusirq
== irq
))
853 if (i
< mp_irq_entries
) {
855 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
856 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
865 * Find a specific PCI IRQ entry.
866 * Not an __init, possibly needed by modules
868 static int pin_2_irq(int idx
, int apic
, int pin
);
870 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
872 int apic
, i
, best_guess
= -1;
874 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
875 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
876 if (test_bit(bus
, mp_bus_not_pci
)) {
877 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
880 for (i
= 0; i
< mp_irq_entries
; i
++) {
881 int lbus
= mp_irqs
[i
].mp_srcbus
;
883 for (apic
= 0; apic
< nr_ioapics
; apic
++)
884 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
885 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
888 if (!test_bit(lbus
, mp_bus_not_pci
) &&
889 !mp_irqs
[i
].mp_irqtype
&&
891 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
892 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].mp_dstirq
);
894 if (!(apic
|| IO_APIC_IRQ(irq
)))
897 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
900 * Use the first all-but-pin matching entry as a
901 * best-guess fuzzy result for broken mptables.
909 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
912 * This function currently is only a helper for the i386 smp boot process where
913 * we need to reprogram the ioredtbls to cater for the cpus which have come online
914 * so mask in all cases should simply be TARGET_CPUS
917 void __init
setup_ioapic_dest(void)
919 int pin
, ioapic
, irq
, irq_entry
;
921 if (skip_ioapic_setup
== 1)
924 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
925 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
926 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
929 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
930 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
937 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
939 * EISA Edge/Level control register, ELCR
941 static int EISA_ELCR(unsigned int irq
)
944 unsigned int port
= 0x4d0 + (irq
>> 3);
945 return (inb(port
) >> (irq
& 7)) & 1;
947 apic_printk(APIC_VERBOSE
, KERN_INFO
948 "Broken MPtable reports ISA irq %d\n", irq
);
953 /* ISA interrupts are always polarity zero edge triggered,
954 * when listed as conforming in the MP table. */
956 #define default_ISA_trigger(idx) (0)
957 #define default_ISA_polarity(idx) (0)
959 /* EISA interrupts are always polarity zero and can be edge or level
960 * trigger depending on the ELCR value. If an interrupt is listed as
961 * EISA conforming in the MP table, that means its trigger type must
962 * be read in from the ELCR */
964 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
965 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
967 /* PCI interrupts are always polarity one level triggered,
968 * when listed as conforming in the MP table. */
970 #define default_PCI_trigger(idx) (1)
971 #define default_PCI_polarity(idx) (1)
973 /* MCA interrupts are always polarity zero level triggered,
974 * when listed as conforming in the MP table. */
976 #define default_MCA_trigger(idx) (1)
977 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
979 static int MPBIOS_polarity(int idx
)
981 int bus
= mp_irqs
[idx
].mp_srcbus
;
985 * Determine IRQ line polarity (high active or low active):
987 switch (mp_irqs
[idx
].mp_irqflag
& 3) {
988 case 0: /* conforms, ie. bus-type dependent polarity */
990 polarity
= test_bit(bus
, mp_bus_not_pci
)?
991 default_ISA_polarity(idx
):
992 default_PCI_polarity(idx
);
995 case 1: /* high active */
1000 case 2: /* reserved */
1002 printk(KERN_WARNING
"broken BIOS!!\n");
1006 case 3: /* low active */
1011 default: /* invalid */
1013 printk(KERN_WARNING
"broken BIOS!!\n");
1021 static int MPBIOS_trigger(int idx
)
1023 int bus
= mp_irqs
[idx
].mp_srcbus
;
1027 * Determine IRQ trigger mode (edge or level sensitive):
1029 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3) {
1030 case 0: /* conforms, ie. bus-type dependent */
1032 trigger
= test_bit(bus
, mp_bus_not_pci
)?
1033 default_ISA_trigger(idx
):
1034 default_PCI_trigger(idx
);
1035 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1036 switch (mp_bus_id_to_type
[bus
]) {
1037 case MP_BUS_ISA
: /* ISA pin */
1039 /* set before the switch */
1042 case MP_BUS_EISA
: /* EISA pin */
1044 trigger
= default_EISA_trigger(idx
);
1047 case MP_BUS_PCI
: /* PCI pin */
1049 /* set before the switch */
1052 case MP_BUS_MCA
: /* MCA pin */
1054 trigger
= default_MCA_trigger(idx
);
1059 printk(KERN_WARNING
"broken BIOS!!\n");
1072 case 2: /* reserved */
1074 printk(KERN_WARNING
"broken BIOS!!\n");
1083 default: /* invalid */
1085 printk(KERN_WARNING
"broken BIOS!!\n");
1093 static inline int irq_polarity(int idx
)
1095 return MPBIOS_polarity(idx
);
1098 static inline int irq_trigger(int idx
)
1100 return MPBIOS_trigger(idx
);
1103 static int pin_2_irq(int idx
, int apic
, int pin
)
1106 int bus
= mp_irqs
[idx
].mp_srcbus
;
1109 * Debugging check, we are in big trouble if this message pops up!
1111 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1112 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1114 if (test_bit(bus
, mp_bus_not_pci
))
1115 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1118 * PCI IRQs are mapped in order
1122 irq
+= nr_ioapic_registers
[i
++];
1126 * For MPS mode, so far only needed by ES7000 platform
1128 if (ioapic_renumber_irq
)
1129 irq
= ioapic_renumber_irq(apic
, irq
);
1133 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1135 if ((pin
>= 16) && (pin
<= 23)) {
1136 if (pirq_entries
[pin
-16] != -1) {
1137 if (!pirq_entries
[pin
-16]) {
1138 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1139 "disabling PIRQ%d\n", pin
-16);
1141 irq
= pirq_entries
[pin
-16];
1142 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1143 "using PIRQ%d -> IRQ %d\n",
1151 static inline int IO_APIC_irq_trigger(int irq
)
1155 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1156 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1157 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1158 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1159 return irq_trigger(idx
);
1163 * nonexistent IRQs are edge default
1168 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1169 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1171 static int __assign_irq_vector(int irq
)
1173 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
;
1176 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1178 if (irq_vector
[irq
] > 0)
1179 return irq_vector
[irq
];
1181 vector
= current_vector
;
1182 offset
= current_offset
;
1185 if (vector
>= first_system_vector
) {
1186 offset
= (offset
+ 1) % 8;
1187 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1189 if (vector
== current_vector
)
1191 if (test_and_set_bit(vector
, used_vectors
))
1194 current_vector
= vector
;
1195 current_offset
= offset
;
1196 irq_vector
[irq
] = vector
;
1201 static int assign_irq_vector(int irq
)
1203 unsigned long flags
;
1206 spin_lock_irqsave(&vector_lock
, flags
);
1207 vector
= __assign_irq_vector(irq
);
1208 spin_unlock_irqrestore(&vector_lock
, flags
);
1213 void setup_vector_irq(int cpu
)
1217 static struct irq_chip ioapic_chip
;
1219 #define IOAPIC_AUTO -1
1220 #define IOAPIC_EDGE 0
1221 #define IOAPIC_LEVEL 1
1223 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1225 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1226 trigger
== IOAPIC_LEVEL
) {
1227 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1228 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1229 handle_fasteoi_irq
, "fasteoi");
1231 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1232 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1233 handle_edge_irq
, "edge");
1235 set_intr_gate(vector
, interrupt
[irq
]);
1238 static void __init
setup_IO_APIC_irqs(void)
1240 struct IO_APIC_route_entry entry
;
1241 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1243 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1245 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1246 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1249 * add it to the IO-APIC irq-routing table:
1251 memset(&entry
, 0, sizeof(entry
));
1253 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1254 entry
.dest_mode
= INT_DEST_MODE
;
1255 entry
.mask
= 0; /* enable IRQ */
1256 entry
.dest
.logical
.logical_dest
=
1257 cpu_mask_to_apicid(TARGET_CPUS
);
1259 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1262 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1263 " IO-APIC (apicid-pin) %d-%d",
1264 mp_ioapics
[apic
].mp_apicid
,
1268 apic_printk(APIC_VERBOSE
, ", %d-%d",
1269 mp_ioapics
[apic
].mp_apicid
, pin
);
1273 if (!first_notcon
) {
1274 apic_printk(APIC_VERBOSE
, " not connected.\n");
1278 entry
.trigger
= irq_trigger(idx
);
1279 entry
.polarity
= irq_polarity(idx
);
1281 if (irq_trigger(idx
)) {
1286 irq
= pin_2_irq(idx
, apic
, pin
);
1288 * skip adding the timer int on secondary nodes, which causes
1289 * a small but painful rift in the time-space continuum
1291 if (multi_timer_check(apic
, irq
))
1294 add_pin_to_irq(irq
, apic
, pin
);
1296 if (!apic
&& !IO_APIC_IRQ(irq
))
1299 if (IO_APIC_IRQ(irq
)) {
1300 vector
= assign_irq_vector(irq
);
1301 entry
.vector
= vector
;
1302 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1304 if (!apic
&& (irq
< 16))
1305 disable_8259A_irq(irq
);
1307 ioapic_write_entry(apic
, pin
, entry
);
1312 apic_printk(APIC_VERBOSE
, " not connected.\n");
1316 * Set up the timer pin, possibly with the 8259A-master behind.
1318 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1321 struct IO_APIC_route_entry entry
;
1323 memset(&entry
, 0, sizeof(entry
));
1326 * We use logical delivery to get the timer IRQ
1329 entry
.dest_mode
= INT_DEST_MODE
;
1330 entry
.mask
= 1; /* mask IRQ now */
1331 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1332 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1335 entry
.vector
= vector
;
1338 * The timer IRQ doesn't have to know that behind the
1339 * scene we may have a 8259A-master in AEOI mode ...
1341 ioapic_register_intr(0, vector
, IOAPIC_EDGE
);
1344 * Add it to the IO-APIC irq-routing table:
1346 ioapic_write_entry(apic
, pin
, entry
);
1349 void __init
print_IO_APIC(void)
1352 union IO_APIC_reg_00 reg_00
;
1353 union IO_APIC_reg_01 reg_01
;
1354 union IO_APIC_reg_02 reg_02
;
1355 union IO_APIC_reg_03 reg_03
;
1356 unsigned long flags
;
1358 if (apic_verbosity
== APIC_QUIET
)
1361 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1362 for (i
= 0; i
< nr_ioapics
; i
++)
1363 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1364 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1367 * We are a bit conservative about what we expect. We have to
1368 * know about every hardware change ASAP.
1370 printk(KERN_INFO
"testing the IO APIC.......................\n");
1372 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1374 spin_lock_irqsave(&ioapic_lock
, flags
);
1375 reg_00
.raw
= io_apic_read(apic
, 0);
1376 reg_01
.raw
= io_apic_read(apic
, 1);
1377 if (reg_01
.bits
.version
>= 0x10)
1378 reg_02
.raw
= io_apic_read(apic
, 2);
1379 if (reg_01
.bits
.version
>= 0x20)
1380 reg_03
.raw
= io_apic_read(apic
, 3);
1381 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1383 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1384 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1385 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1386 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1387 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1389 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1390 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1392 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1393 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1396 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1397 * but the value of reg_02 is read as the previous read register
1398 * value, so ignore it if reg_02 == reg_01.
1400 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1401 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1402 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1406 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1407 * or reg_03, but the value of reg_0[23] is read as the previous read
1408 * register value, so ignore it if reg_03 == reg_0[12].
1410 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1411 reg_03
.raw
!= reg_01
.raw
) {
1412 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1413 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1416 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1418 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1419 " Stat Dest Deli Vect: \n");
1421 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1422 struct IO_APIC_route_entry entry
;
1424 entry
= ioapic_read_entry(apic
, i
);
1426 printk(KERN_DEBUG
" %02x %03X %02X ",
1428 entry
.dest
.logical
.logical_dest
,
1429 entry
.dest
.physical
.physical_dest
1432 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1437 entry
.delivery_status
,
1439 entry
.delivery_mode
,
1444 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1445 for (i
= 0; i
< NR_IRQS
; i
++) {
1446 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1449 printk(KERN_DEBUG
"IRQ%d ", i
);
1451 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1454 entry
= irq_2_pin
+ entry
->next
;
1459 printk(KERN_INFO
".................................... done.\n");
1466 static void print_APIC_bitfield(int base
)
1471 if (apic_verbosity
== APIC_QUIET
)
1474 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1475 for (i
= 0; i
< 8; i
++) {
1476 v
= apic_read(base
+ i
*0x10);
1477 for (j
= 0; j
< 32; j
++) {
1487 void /*__init*/ print_local_APIC(void *dummy
)
1489 unsigned int v
, ver
, maxlvt
;
1491 if (apic_verbosity
== APIC_QUIET
)
1494 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1495 smp_processor_id(), hard_smp_processor_id());
1496 v
= apic_read(APIC_ID
);
1497 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
,
1499 v
= apic_read(APIC_LVR
);
1500 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1501 ver
= GET_APIC_VERSION(v
);
1502 maxlvt
= lapic_get_maxlvt();
1504 v
= apic_read(APIC_TASKPRI
);
1505 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1507 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1508 v
= apic_read(APIC_ARBPRI
);
1509 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1510 v
& APIC_ARBPRI_MASK
);
1511 v
= apic_read(APIC_PROCPRI
);
1512 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1515 v
= apic_read(APIC_EOI
);
1516 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1517 v
= apic_read(APIC_RRR
);
1518 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1519 v
= apic_read(APIC_LDR
);
1520 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1521 v
= apic_read(APIC_DFR
);
1522 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1523 v
= apic_read(APIC_SPIV
);
1524 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1526 printk(KERN_DEBUG
"... APIC ISR field:\n");
1527 print_APIC_bitfield(APIC_ISR
);
1528 printk(KERN_DEBUG
"... APIC TMR field:\n");
1529 print_APIC_bitfield(APIC_TMR
);
1530 printk(KERN_DEBUG
"... APIC IRR field:\n");
1531 print_APIC_bitfield(APIC_IRR
);
1533 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1534 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1535 apic_write(APIC_ESR
, 0);
1536 v
= apic_read(APIC_ESR
);
1537 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1540 v
= apic_read(APIC_ICR
);
1541 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1542 v
= apic_read(APIC_ICR2
);
1543 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1545 v
= apic_read(APIC_LVTT
);
1546 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1548 if (maxlvt
> 3) { /* PC is LVT#4. */
1549 v
= apic_read(APIC_LVTPC
);
1550 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1552 v
= apic_read(APIC_LVT0
);
1553 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1554 v
= apic_read(APIC_LVT1
);
1555 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1557 if (maxlvt
> 2) { /* ERR is LVT#3. */
1558 v
= apic_read(APIC_LVTERR
);
1559 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1562 v
= apic_read(APIC_TMICT
);
1563 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1564 v
= apic_read(APIC_TMCCT
);
1565 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1566 v
= apic_read(APIC_TDCR
);
1567 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1571 void print_all_local_APICs(void)
1573 on_each_cpu(print_local_APIC
, NULL
, 1);
1576 void /*__init*/ print_PIC(void)
1579 unsigned long flags
;
1581 if (apic_verbosity
== APIC_QUIET
)
1584 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1586 spin_lock_irqsave(&i8259A_lock
, flags
);
1588 v
= inb(0xa1) << 8 | inb(0x21);
1589 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1591 v
= inb(0xa0) << 8 | inb(0x20);
1592 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1596 v
= inb(0xa0) << 8 | inb(0x20);
1600 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1602 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1604 v
= inb(0x4d1) << 8 | inb(0x4d0);
1605 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1610 static void __init
enable_IO_APIC(void)
1612 union IO_APIC_reg_01 reg_01
;
1613 int i8259_apic
, i8259_pin
;
1615 unsigned long flags
;
1617 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1618 irq_2_pin
[i
].pin
= -1;
1619 irq_2_pin
[i
].next
= 0;
1622 for (i
= 0; i
< MAX_PIRQS
; i
++)
1623 pirq_entries
[i
] = -1;
1626 * The number of IO-APIC IRQ registers (== #pins):
1628 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1629 spin_lock_irqsave(&ioapic_lock
, flags
);
1630 reg_01
.raw
= io_apic_read(apic
, 1);
1631 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1632 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1634 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1636 /* See if any of the pins is in ExtINT mode */
1637 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1638 struct IO_APIC_route_entry entry
;
1639 entry
= ioapic_read_entry(apic
, pin
);
1642 /* If the interrupt line is enabled and in ExtInt mode
1643 * I have found the pin where the i8259 is connected.
1645 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1646 ioapic_i8259
.apic
= apic
;
1647 ioapic_i8259
.pin
= pin
;
1653 /* Look to see what if the MP table has reported the ExtINT */
1654 /* If we could not find the appropriate pin by looking at the ioapic
1655 * the i8259 probably is not connected the ioapic but give the
1656 * mptable a chance anyway.
1658 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1659 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1660 /* Trust the MP table if nothing is setup in the hardware */
1661 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1662 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1663 ioapic_i8259
.pin
= i8259_pin
;
1664 ioapic_i8259
.apic
= i8259_apic
;
1666 /* Complain if the MP table and the hardware disagree */
1667 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1668 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1670 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1674 * Do not trust the IO-APIC being empty at bootup
1680 * Not an __init, needed by the reboot code
1682 void disable_IO_APIC(void)
1685 * Clear the IO-APIC before rebooting:
1690 * If the i8259 is routed through an IOAPIC
1691 * Put that IOAPIC in virtual wire mode
1692 * so legacy interrupts can be delivered.
1694 if (ioapic_i8259
.pin
!= -1) {
1695 struct IO_APIC_route_entry entry
;
1697 memset(&entry
, 0, sizeof(entry
));
1698 entry
.mask
= 0; /* Enabled */
1699 entry
.trigger
= 0; /* Edge */
1701 entry
.polarity
= 0; /* High */
1702 entry
.delivery_status
= 0;
1703 entry
.dest_mode
= 0; /* Physical */
1704 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1706 entry
.dest
.physical
.physical_dest
= read_apic_id();
1709 * Add it to the IO-APIC irq-routing table:
1711 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1713 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1717 * function to set the IO-APIC physical IDs based on the
1718 * values stored in the MPC table.
1720 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1723 static void __init
setup_ioapic_ids_from_mpc(void)
1725 union IO_APIC_reg_00 reg_00
;
1726 physid_mask_t phys_id_present_map
;
1729 unsigned char old_id
;
1730 unsigned long flags
;
1732 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
1736 * Don't check I/O APIC IDs for xAPIC systems. They have
1737 * no meaning without the serial APIC bus.
1739 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1740 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1743 * This is broken; anything with a real cpu count has to
1744 * circumvent this idiocy regardless.
1746 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1749 * Set the IOAPIC ID to the value stored in the MPC table.
1751 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1753 /* Read the register 0 value */
1754 spin_lock_irqsave(&ioapic_lock
, flags
);
1755 reg_00
.raw
= io_apic_read(apic
, 0);
1756 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1758 old_id
= mp_ioapics
[apic
].mp_apicid
;
1760 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
1761 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1762 apic
, mp_ioapics
[apic
].mp_apicid
);
1763 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1765 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
1769 * Sanity check, is the ID really free? Every APIC in a
1770 * system must have a unique ID or we get lots of nice
1771 * 'stuck on smp_invalidate_needed IPI wait' messages.
1773 if (check_apicid_used(phys_id_present_map
,
1774 mp_ioapics
[apic
].mp_apicid
)) {
1775 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1776 apic
, mp_ioapics
[apic
].mp_apicid
);
1777 for (i
= 0; i
< get_physical_broadcast(); i
++)
1778 if (!physid_isset(i
, phys_id_present_map
))
1780 if (i
>= get_physical_broadcast())
1781 panic("Max APIC ID exceeded!\n");
1782 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1784 physid_set(i
, phys_id_present_map
);
1785 mp_ioapics
[apic
].mp_apicid
= i
;
1788 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
1789 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1790 "phys_id_present_map\n",
1791 mp_ioapics
[apic
].mp_apicid
);
1792 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1797 * We need to adjust the IRQ routing table
1798 * if the ID changed.
1800 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
1801 for (i
= 0; i
< mp_irq_entries
; i
++)
1802 if (mp_irqs
[i
].mp_dstapic
== old_id
)
1803 mp_irqs
[i
].mp_dstapic
1804 = mp_ioapics
[apic
].mp_apicid
;
1807 * Read the right value from the MPC table and
1808 * write it into the ID register.
1810 apic_printk(APIC_VERBOSE
, KERN_INFO
1811 "...changing IO-APIC physical APIC ID to %d ...",
1812 mp_ioapics
[apic
].mp_apicid
);
1814 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
1815 spin_lock_irqsave(&ioapic_lock
, flags
);
1816 io_apic_write(apic
, 0, reg_00
.raw
);
1817 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1822 spin_lock_irqsave(&ioapic_lock
, flags
);
1823 reg_00
.raw
= io_apic_read(apic
, 0);
1824 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1825 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
1826 printk("could not set ID!\n");
1828 apic_printk(APIC_VERBOSE
, " ok.\n");
1832 int no_timer_check __initdata
;
1834 static int __init
notimercheck(char *s
)
1839 __setup("no_timer_check", notimercheck
);
1842 * There is a nasty bug in some older SMP boards, their mptable lies
1843 * about the timer IRQ. We do the following to work around the situation:
1845 * - timer IRQ defaults to IO-APIC IRQ
1846 * - if this function detects that timer IRQs are defunct, then we fall
1847 * back to ISA timer IRQs
1849 static int __init
timer_irq_works(void)
1851 unsigned long t1
= jiffies
;
1852 unsigned long flags
;
1857 local_save_flags(flags
);
1859 /* Let ten ticks pass... */
1860 mdelay((10 * 1000) / HZ
);
1861 local_irq_restore(flags
);
1864 * Expect a few ticks at least, to be sure some possible
1865 * glue logic does not lock up after one or two first
1866 * ticks in a non-ExtINT mode. Also the local APIC
1867 * might have cached one ExtINT interrupt. Finally, at
1868 * least one tick may be lost due to delays.
1870 if (time_after(jiffies
, t1
+ 4))
1877 * In the SMP+IOAPIC case it might happen that there are an unspecified
1878 * number of pending IRQ events unhandled. These cases are very rare,
1879 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1880 * better to do it this way as thus we do not have to be aware of
1881 * 'pending' interrupts in the IRQ path, except at this point.
1884 * Edge triggered needs to resend any interrupt
1885 * that was delayed but this is now handled in the device
1892 * Starting up a edge-triggered IO-APIC interrupt is
1893 * nasty - we need to make sure that we get the edge.
1894 * If it is already asserted for some reason, we need
1895 * return 1 to indicate that is was pending.
1897 * This is not complete - we should be able to fake
1898 * an edge even if it isn't on the 8259A...
1900 * (We do this for level-triggered IRQs too - it cannot hurt.)
1902 static unsigned int startup_ioapic_irq(unsigned int irq
)
1904 int was_pending
= 0;
1905 unsigned long flags
;
1907 spin_lock_irqsave(&ioapic_lock
, flags
);
1909 disable_8259A_irq(irq
);
1910 if (i8259A_irq_pending(irq
))
1913 __unmask_IO_APIC_irq(irq
);
1914 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1919 static void ack_ioapic_irq(unsigned int irq
)
1921 move_native_irq(irq
);
1925 static void ack_ioapic_quirk_irq(unsigned int irq
)
1930 move_native_irq(irq
);
1932 * It appears there is an erratum which affects at least version 0x11
1933 * of I/O APIC (that's the 82093AA and cores integrated into various
1934 * chipsets). Under certain conditions a level-triggered interrupt is
1935 * erroneously delivered as edge-triggered one but the respective IRR
1936 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1937 * message but it will never arrive and further interrupts are blocked
1938 * from the source. The exact reason is so far unknown, but the
1939 * phenomenon was observed when two consecutive interrupt requests
1940 * from a given source get delivered to the same CPU and the source is
1941 * temporarily disabled in between.
1943 * A workaround is to simulate an EOI message manually. We achieve it
1944 * by setting the trigger mode to edge and then to level when the edge
1945 * trigger mode gets detected in the TMR of a local APIC for a
1946 * level-triggered interrupt. We mask the source for the time of the
1947 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1948 * The idea is from Manfred Spraul. --macro
1950 i
= irq_vector
[irq
];
1952 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1956 if (!(v
& (1 << (i
& 0x1f)))) {
1957 atomic_inc(&irq_mis_count
);
1958 spin_lock(&ioapic_lock
);
1959 __mask_and_edge_IO_APIC_irq(irq
);
1960 __unmask_and_level_IO_APIC_irq(irq
);
1961 spin_unlock(&ioapic_lock
);
1965 static int ioapic_retrigger_irq(unsigned int irq
)
1967 send_IPI_self(irq_vector
[irq
]);
1972 static struct irq_chip ioapic_chip __read_mostly
= {
1974 .startup
= startup_ioapic_irq
,
1975 .mask
= mask_IO_APIC_irq
,
1976 .unmask
= unmask_IO_APIC_irq
,
1977 .ack
= ack_ioapic_irq
,
1978 .eoi
= ack_ioapic_quirk_irq
,
1980 .set_affinity
= set_ioapic_affinity_irq
,
1982 .retrigger
= ioapic_retrigger_irq
,
1986 static inline void init_IO_APIC_traps(void)
1991 * NOTE! The local APIC isn't very good at handling
1992 * multiple interrupts at the same interrupt level.
1993 * As the interrupt level is determined by taking the
1994 * vector number and shifting that right by 4, we
1995 * want to spread these out a bit so that they don't
1996 * all fall in the same interrupt level.
1998 * Also, we've got to be careful not to trash gate
1999 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2001 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
2002 if (IO_APIC_IRQ(irq
) && !irq_vector
[irq
]) {
2004 * Hmm.. We don't have an entry for this,
2005 * so default to an old-fashioned 8259
2006 * interrupt if we can..
2009 make_8259A_irq(irq
);
2011 /* Strange. Oh, well.. */
2012 irq_desc
[irq
].chip
= &no_irq_chip
;
2018 * The local APIC irq-chip implementation:
2021 static void ack_lapic_irq(unsigned int irq
)
2026 static void mask_lapic_irq(unsigned int irq
)
2030 v
= apic_read(APIC_LVT0
);
2031 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2034 static void unmask_lapic_irq(unsigned int irq
)
2038 v
= apic_read(APIC_LVT0
);
2039 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2042 static struct irq_chip lapic_chip __read_mostly
= {
2043 .name
= "local-APIC",
2044 .mask
= mask_lapic_irq
,
2045 .unmask
= unmask_lapic_irq
,
2046 .ack
= ack_lapic_irq
,
2049 static void lapic_register_intr(int irq
, int vector
)
2051 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
2052 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2054 set_intr_gate(vector
, interrupt
[irq
]);
2057 static void __init
setup_nmi(void)
2060 * Dirty trick to enable the NMI watchdog ...
2061 * We put the 8259A master into AEOI mode and
2062 * unmask on all local APICs LVT0 as NMI.
2064 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2065 * is from Maciej W. Rozycki - so we do not have to EOI from
2066 * the NMI handler or the timer interrupt.
2068 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2070 enable_NMI_through_LVT0();
2072 apic_printk(APIC_VERBOSE
, " done.\n");
2076 * This looks a bit hackish but it's about the only one way of sending
2077 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2078 * not support the ExtINT mode, unfortunately. We need to send these
2079 * cycles as some i82489DX-based boards have glue logic that keeps the
2080 * 8259A interrupt line asserted until INTA. --macro
2082 static inline void __init
unlock_ExtINT_logic(void)
2085 struct IO_APIC_route_entry entry0
, entry1
;
2086 unsigned char save_control
, save_freq_select
;
2088 pin
= find_isa_irq_pin(8, mp_INT
);
2093 apic
= find_isa_irq_apic(8, mp_INT
);
2099 entry0
= ioapic_read_entry(apic
, pin
);
2100 clear_IO_APIC_pin(apic
, pin
);
2102 memset(&entry1
, 0, sizeof(entry1
));
2104 entry1
.dest_mode
= 0; /* physical delivery */
2105 entry1
.mask
= 0; /* unmask IRQ now */
2106 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2107 entry1
.delivery_mode
= dest_ExtINT
;
2108 entry1
.polarity
= entry0
.polarity
;
2112 ioapic_write_entry(apic
, pin
, entry1
);
2114 save_control
= CMOS_READ(RTC_CONTROL
);
2115 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2116 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2118 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2123 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2127 CMOS_WRITE(save_control
, RTC_CONTROL
);
2128 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2129 clear_IO_APIC_pin(apic
, pin
);
2131 ioapic_write_entry(apic
, pin
, entry0
);
2135 * This code may look a bit paranoid, but it's supposed to cooperate with
2136 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2137 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2138 * fanatically on his truly buggy board.
2140 static inline void __init
check_timer(void)
2142 int apic1
, pin1
, apic2
, pin2
;
2146 unsigned long flags
;
2148 local_irq_save(flags
);
2150 ver
= apic_read(APIC_LVR
);
2151 ver
= GET_APIC_VERSION(ver
);
2154 * get/set the timer IRQ vector:
2156 disable_8259A_irq(0);
2157 vector
= assign_irq_vector(0);
2158 set_intr_gate(vector
, interrupt
[0]);
2161 * As IRQ0 is to be enabled in the 8259A, the virtual
2162 * wire has to be disabled in the local APIC. Also
2163 * timer interrupts need to be acknowledged manually in
2164 * the 8259A for the i82489DX when using the NMI
2165 * watchdog as that APIC treats NMIs as level-triggered.
2166 * The AEOI mode will finish them in the 8259A
2169 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2171 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2173 pin1
= find_isa_irq_pin(0, mp_INT
);
2174 apic1
= find_isa_irq_apic(0, mp_INT
);
2175 pin2
= ioapic_i8259
.pin
;
2176 apic2
= ioapic_i8259
.apic
;
2178 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2179 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2180 vector
, apic1
, pin1
, apic2
, pin2
);
2183 * Some BIOS writers are clueless and report the ExtINTA
2184 * I/O APIC input from the cascaded 8259A as the timer
2185 * interrupt input. So just in case, if only one pin
2186 * was found above, try it both directly and through the
2193 } else if (pin2
== -1) {
2200 * Ok, does IRQ0 through the IOAPIC work?
2203 add_pin_to_irq(0, apic1
, pin1
);
2204 setup_timer_IRQ0_pin(apic1
, pin1
, vector
);
2206 unmask_IO_APIC_irq(0);
2207 if (timer_irq_works()) {
2208 if (nmi_watchdog
== NMI_IO_APIC
) {
2210 enable_8259A_irq(0);
2212 if (disable_timer_pin_1
> 0)
2213 clear_IO_APIC_pin(0, pin1
);
2216 clear_IO_APIC_pin(apic1
, pin1
);
2218 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2219 "8254 timer not connected to IO-APIC\n");
2221 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2222 "(IRQ0) through the 8259A ...\n");
2223 apic_printk(APIC_QUIET
, KERN_INFO
2224 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2226 * legacy devices should be connected to IO APIC #0
2228 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2229 setup_timer_IRQ0_pin(apic2
, pin2
, vector
);
2230 unmask_IO_APIC_irq(0);
2231 enable_8259A_irq(0);
2232 if (timer_irq_works()) {
2233 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2234 timer_through_8259
= 1;
2235 if (nmi_watchdog
== NMI_IO_APIC
) {
2236 disable_8259A_irq(0);
2238 enable_8259A_irq(0);
2243 * Cleanup, just in case ...
2245 disable_8259A_irq(0);
2246 clear_IO_APIC_pin(apic2
, pin2
);
2247 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2250 if (nmi_watchdog
== NMI_IO_APIC
) {
2251 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2252 "through the IO-APIC - disabling NMI Watchdog!\n");
2253 nmi_watchdog
= NMI_NONE
;
2257 apic_printk(APIC_QUIET
, KERN_INFO
2258 "...trying to set up timer as Virtual Wire IRQ...\n");
2260 lapic_register_intr(0, vector
);
2261 apic_write(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2262 enable_8259A_irq(0);
2264 if (timer_irq_works()) {
2265 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2268 disable_8259A_irq(0);
2269 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2270 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2272 apic_printk(APIC_QUIET
, KERN_INFO
2273 "...trying to set up timer as ExtINT IRQ...\n");
2277 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2279 unlock_ExtINT_logic();
2281 if (timer_irq_works()) {
2282 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2285 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2286 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2287 "report. Then try booting with the 'noapic' option.\n");
2289 local_irq_restore(flags
);
2293 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2294 * to devices. However there may be an I/O APIC pin available for
2295 * this interrupt regardless. The pin may be left unconnected, but
2296 * typically it will be reused as an ExtINT cascade interrupt for
2297 * the master 8259A. In the MPS case such a pin will normally be
2298 * reported as an ExtINT interrupt in the MP table. With ACPI
2299 * there is no provision for ExtINT interrupts, and in the absence
2300 * of an override it would be treated as an ordinary ISA I/O APIC
2301 * interrupt, that is edge-triggered and unmasked by default. We
2302 * used to do this, but it caused problems on some systems because
2303 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2304 * the same ExtINT cascade interrupt to drive the local APIC of the
2305 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2306 * the I/O APIC in all cases now. No actual device should request
2307 * it anyway. --macro
2309 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2311 void __init
setup_IO_APIC(void)
2315 /* Reserve all the system vectors. */
2316 for (i
= first_system_vector
; i
< NR_VECTORS
; i
++)
2317 set_bit(i
, used_vectors
);
2321 io_apic_irqs
= ~PIC_IRQS
;
2323 printk("ENABLING IO-APIC IRQs\n");
2326 * Set up IO-APIC IRQ routing.
2329 setup_ioapic_ids_from_mpc();
2331 setup_IO_APIC_irqs();
2332 init_IO_APIC_traps();
2339 * Called after all the initialization is done. If we didnt find any
2340 * APIC bugs then we can allow the modify fast path
2343 static int __init
io_apic_bug_finalize(void)
2345 if (sis_apic_bug
== -1)
2350 late_initcall(io_apic_bug_finalize
);
2352 struct sysfs_ioapic_data
{
2353 struct sys_device dev
;
2354 struct IO_APIC_route_entry entry
[0];
2356 static struct sysfs_ioapic_data
*mp_ioapic_data
[MAX_IO_APICS
];
2358 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2360 struct IO_APIC_route_entry
*entry
;
2361 struct sysfs_ioapic_data
*data
;
2364 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2365 entry
= data
->entry
;
2366 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2367 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2372 static int ioapic_resume(struct sys_device
*dev
)
2374 struct IO_APIC_route_entry
*entry
;
2375 struct sysfs_ioapic_data
*data
;
2376 unsigned long flags
;
2377 union IO_APIC_reg_00 reg_00
;
2380 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2381 entry
= data
->entry
;
2383 spin_lock_irqsave(&ioapic_lock
, flags
);
2384 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2385 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2386 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2387 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2389 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2390 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2391 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2396 static struct sysdev_class ioapic_sysdev_class
= {
2398 .suspend
= ioapic_suspend
,
2399 .resume
= ioapic_resume
,
2402 static int __init
ioapic_init_sysfs(void)
2404 struct sys_device
*dev
;
2405 int i
, size
, error
= 0;
2407 error
= sysdev_class_register(&ioapic_sysdev_class
);
2411 for (i
= 0; i
< nr_ioapics
; i
++) {
2412 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2413 * sizeof(struct IO_APIC_route_entry
);
2414 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2415 if (!mp_ioapic_data
[i
]) {
2416 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2419 dev
= &mp_ioapic_data
[i
]->dev
;
2421 dev
->cls
= &ioapic_sysdev_class
;
2422 error
= sysdev_register(dev
);
2424 kfree(mp_ioapic_data
[i
]);
2425 mp_ioapic_data
[i
] = NULL
;
2426 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2434 device_initcall(ioapic_init_sysfs
);
2437 * Dynamic irq allocate and deallocation
2439 int create_irq(void)
2441 /* Allocate an unused irq */
2442 int irq
, new, vector
= 0;
2443 unsigned long flags
;
2446 spin_lock_irqsave(&vector_lock
, flags
);
2447 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2448 if (platform_legacy_irq(new))
2450 if (irq_vector
[new] != 0)
2452 vector
= __assign_irq_vector(new);
2453 if (likely(vector
> 0))
2457 spin_unlock_irqrestore(&vector_lock
, flags
);
2460 set_intr_gate(vector
, interrupt
[irq
]);
2461 dynamic_irq_init(irq
);
2466 void destroy_irq(unsigned int irq
)
2468 unsigned long flags
;
2470 dynamic_irq_cleanup(irq
);
2472 spin_lock_irqsave(&vector_lock
, flags
);
2473 clear_bit(irq_vector
[irq
], used_vectors
);
2474 irq_vector
[irq
] = 0;
2475 spin_unlock_irqrestore(&vector_lock
, flags
);
2479 * MSI message composition
2481 #ifdef CONFIG_PCI_MSI
2482 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2487 vector
= assign_irq_vector(irq
);
2489 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2491 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2494 ((INT_DEST_MODE
== 0) ?
2495 MSI_ADDR_DEST_MODE_PHYSICAL
:
2496 MSI_ADDR_DEST_MODE_LOGICAL
) |
2497 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2498 MSI_ADDR_REDIRECTION_CPU
:
2499 MSI_ADDR_REDIRECTION_LOWPRI
) |
2500 MSI_ADDR_DEST_ID(dest
);
2503 MSI_DATA_TRIGGER_EDGE
|
2504 MSI_DATA_LEVEL_ASSERT
|
2505 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2506 MSI_DATA_DELIVERY_FIXED
:
2507 MSI_DATA_DELIVERY_LOWPRI
) |
2508 MSI_DATA_VECTOR(vector
);
2514 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2521 cpus_and(tmp
, mask
, cpu_online_map
);
2522 if (cpus_empty(tmp
))
2525 vector
= assign_irq_vector(irq
);
2529 dest
= cpu_mask_to_apicid(mask
);
2531 read_msi_msg(irq
, &msg
);
2533 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2534 msg
.data
|= MSI_DATA_VECTOR(vector
);
2535 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2536 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2538 write_msi_msg(irq
, &msg
);
2539 irq_desc
[irq
].affinity
= mask
;
2541 #endif /* CONFIG_SMP */
2544 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2545 * which implement the MSI or MSI-X Capability Structure.
2547 static struct irq_chip msi_chip
= {
2549 .unmask
= unmask_msi_irq
,
2550 .mask
= mask_msi_irq
,
2551 .ack
= ack_ioapic_irq
,
2553 .set_affinity
= set_msi_irq_affinity
,
2555 .retrigger
= ioapic_retrigger_irq
,
2558 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2566 ret
= msi_compose_msg(dev
, irq
, &msg
);
2572 set_irq_msi(irq
, desc
);
2573 write_msi_msg(irq
, &msg
);
2575 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2581 void arch_teardown_msi_irq(unsigned int irq
)
2586 #endif /* CONFIG_PCI_MSI */
2589 * Hypertransport interrupt support
2591 #ifdef CONFIG_HT_IRQ
2595 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2597 struct ht_irq_msg msg
;
2598 fetch_ht_irq_msg(irq
, &msg
);
2600 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2601 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2603 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2604 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2606 write_ht_irq_msg(irq
, &msg
);
2609 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2614 cpus_and(tmp
, mask
, cpu_online_map
);
2615 if (cpus_empty(tmp
))
2618 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2620 dest
= cpu_mask_to_apicid(mask
);
2622 target_ht_irq(irq
, dest
);
2623 irq_desc
[irq
].affinity
= mask
;
2627 static struct irq_chip ht_irq_chip
= {
2629 .mask
= mask_ht_irq
,
2630 .unmask
= unmask_ht_irq
,
2631 .ack
= ack_ioapic_irq
,
2633 .set_affinity
= set_ht_irq_affinity
,
2635 .retrigger
= ioapic_retrigger_irq
,
2638 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2642 vector
= assign_irq_vector(irq
);
2644 struct ht_irq_msg msg
;
2649 cpu_set(vector
>> 8, tmp
);
2650 dest
= cpu_mask_to_apicid(tmp
);
2652 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2656 HT_IRQ_LOW_DEST_ID(dest
) |
2657 HT_IRQ_LOW_VECTOR(vector
) |
2658 ((INT_DEST_MODE
== 0) ?
2659 HT_IRQ_LOW_DM_PHYSICAL
:
2660 HT_IRQ_LOW_DM_LOGICAL
) |
2661 HT_IRQ_LOW_RQEOI_EDGE
|
2662 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2663 HT_IRQ_LOW_MT_FIXED
:
2664 HT_IRQ_LOW_MT_ARBITRATED
) |
2665 HT_IRQ_LOW_IRQ_MASKED
;
2667 write_ht_irq_msg(irq
, &msg
);
2669 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2670 handle_edge_irq
, "edge");
2674 #endif /* CONFIG_HT_IRQ */
2676 /* --------------------------------------------------------------------------
2677 ACPI-based IOAPIC Configuration
2678 -------------------------------------------------------------------------- */
2682 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
2684 union IO_APIC_reg_00 reg_00
;
2685 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2687 unsigned long flags
;
2691 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2692 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2693 * supports up to 16 on one shared APIC bus.
2695 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2696 * advantage of new APIC bus architecture.
2699 if (physids_empty(apic_id_map
))
2700 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2702 spin_lock_irqsave(&ioapic_lock
, flags
);
2703 reg_00
.raw
= io_apic_read(ioapic
, 0);
2704 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2706 if (apic_id
>= get_physical_broadcast()) {
2707 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2708 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2709 apic_id
= reg_00
.bits
.ID
;
2713 * Every APIC in a system must have a unique ID or we get lots of nice
2714 * 'stuck on smp_invalidate_needed IPI wait' messages.
2716 if (check_apicid_used(apic_id_map
, apic_id
)) {
2718 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2719 if (!check_apicid_used(apic_id_map
, i
))
2723 if (i
== get_physical_broadcast())
2724 panic("Max apic_id exceeded!\n");
2726 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2727 "trying %d\n", ioapic
, apic_id
, i
);
2732 tmp
= apicid_to_cpu_present(apic_id
);
2733 physids_or(apic_id_map
, apic_id_map
, tmp
);
2735 if (reg_00
.bits
.ID
!= apic_id
) {
2736 reg_00
.bits
.ID
= apic_id
;
2738 spin_lock_irqsave(&ioapic_lock
, flags
);
2739 io_apic_write(ioapic
, 0, reg_00
.raw
);
2740 reg_00
.raw
= io_apic_read(ioapic
, 0);
2741 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2744 if (reg_00
.bits
.ID
!= apic_id
) {
2745 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2750 apic_printk(APIC_VERBOSE
, KERN_INFO
2751 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2757 int __init
io_apic_get_version(int ioapic
)
2759 union IO_APIC_reg_01 reg_01
;
2760 unsigned long flags
;
2762 spin_lock_irqsave(&ioapic_lock
, flags
);
2763 reg_01
.raw
= io_apic_read(ioapic
, 1);
2764 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2766 return reg_01
.bits
.version
;
2770 int __init
io_apic_get_redir_entries(int ioapic
)
2772 union IO_APIC_reg_01 reg_01
;
2773 unsigned long flags
;
2775 spin_lock_irqsave(&ioapic_lock
, flags
);
2776 reg_01
.raw
= io_apic_read(ioapic
, 1);
2777 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2779 return reg_01
.bits
.entries
;
2783 int io_apic_set_pci_routing(int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2785 struct IO_APIC_route_entry entry
;
2787 if (!IO_APIC_IRQ(irq
)) {
2788 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2794 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2795 * Note that we mask (disable) IRQs now -- these get enabled when the
2796 * corresponding device driver registers for this IRQ.
2799 memset(&entry
, 0, sizeof(entry
));
2801 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2802 entry
.dest_mode
= INT_DEST_MODE
;
2803 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2804 entry
.trigger
= edge_level
;
2805 entry
.polarity
= active_high_low
;
2809 * IRQs < 16 are already in the irq_2_pin[] map
2812 add_pin_to_irq(irq
, ioapic
, pin
);
2814 entry
.vector
= assign_irq_vector(irq
);
2816 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2817 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2818 mp_ioapics
[ioapic
].mp_apicid
, pin
, entry
.vector
, irq
,
2819 edge_level
, active_high_low
);
2821 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2823 if (!ioapic
&& (irq
< 16))
2824 disable_8259A_irq(irq
);
2826 ioapic_write_entry(ioapic
, pin
, entry
);
2831 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2835 if (skip_ioapic_setup
)
2838 for (i
= 0; i
< mp_irq_entries
; i
++)
2839 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
2840 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
2842 if (i
>= mp_irq_entries
)
2845 *trigger
= irq_trigger(i
);
2846 *polarity
= irq_polarity(i
);
2850 #endif /* CONFIG_ACPI */
2852 static int __init
parse_disable_timer_pin_1(char *arg
)
2854 disable_timer_pin_1
= 1;
2857 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2859 static int __init
parse_enable_timer_pin_1(char *arg
)
2861 disable_timer_pin_1
= -1;
2864 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2866 static int __init
parse_noapic(char *arg
)
2868 /* disable IO-APIC */
2869 disable_ioapic_setup();
2872 early_param("noapic", parse_noapic
);
2874 void __init
ioapic_init_mappings(void)
2876 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
2879 for (i
= 0; i
< nr_ioapics
; i
++) {
2880 if (smp_found_config
) {
2881 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
2884 "WARNING: bogus zero IO-APIC "
2885 "address found in MPTABLE, "
2886 "disabling IO/APIC support!\n");
2887 smp_found_config
= 0;
2888 skip_ioapic_setup
= 1;
2889 goto fake_ioapic_page
;
2893 ioapic_phys
= (unsigned long)
2894 alloc_bootmem_pages(PAGE_SIZE
);
2895 ioapic_phys
= __pa(ioapic_phys
);
2897 set_fixmap_nocache(idx
, ioapic_phys
);
2898 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
2899 __fix_to_virt(idx
), ioapic_phys
);