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Driver core: change sysdev classes to use dynamic kobject names
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #ifdef CONFIG_ACPI
36 #include <acpi/acpi_bus.h>
37 #endif
38
39 #include <asm/idle.h>
40 #include <asm/io.h>
41 #include <asm/smp.h>
42 #include <asm/desc.h>
43 #include <asm/proto.h>
44 #include <asm/mach_apic.h>
45 #include <asm/acpi.h>
46 #include <asm/dma.h>
47 #include <asm/nmi.h>
48 #include <asm/msidef.h>
49 #include <asm/hypertransport.h>
50
51 struct irq_cfg {
52 cpumask_t domain;
53 cpumask_t old_domain;
54 unsigned move_cleanup_count;
55 u8 vector;
56 u8 move_in_progress : 1;
57 };
58
59 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
60 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
61 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
62 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
63 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
64 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
65 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
66 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
67 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
68 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
69 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
70 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
71 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
72 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
73 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
74 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
75 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
76 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
77 };
78
79 static int assign_irq_vector(int irq, cpumask_t mask);
80
81 #define __apicdebuginit __init
82
83 int sis_apic_bug; /* not actually supported, dummy for compile */
84
85 static int no_timer_check;
86
87 static int disable_timer_pin_1 __initdata;
88
89 int timer_over_8254 __initdata = 1;
90
91 /* Where if anywhere is the i8259 connect in external int mode */
92 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
93
94 static DEFINE_SPINLOCK(ioapic_lock);
95 DEFINE_SPINLOCK(vector_lock);
96
97 /*
98 * # of IRQ routing registers
99 */
100 int nr_ioapic_registers[MAX_IO_APICS];
101
102 /*
103 * Rough estimation of how many shared IRQs there are, can
104 * be changed anytime.
105 */
106 #define MAX_PLUS_SHARED_IRQS NR_IRQS
107 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
108
109 /*
110 * This is performance-critical, we want to do it O(1)
111 *
112 * the indexing order of this array favors 1:1 mappings
113 * between pins and IRQs.
114 */
115
116 static struct irq_pin_list {
117 short apic, pin, next;
118 } irq_2_pin[PIN_MAP_SIZE];
119
120 struct io_apic {
121 unsigned int index;
122 unsigned int unused[3];
123 unsigned int data;
124 };
125
126 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
127 {
128 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
129 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
130 }
131
132 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
133 {
134 struct io_apic __iomem *io_apic = io_apic_base(apic);
135 writel(reg, &io_apic->index);
136 return readl(&io_apic->data);
137 }
138
139 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
140 {
141 struct io_apic __iomem *io_apic = io_apic_base(apic);
142 writel(reg, &io_apic->index);
143 writel(value, &io_apic->data);
144 }
145
146 /*
147 * Re-write a value: to be used for read-modify-write
148 * cycles where the read already set up the index register.
149 */
150 static inline void io_apic_modify(unsigned int apic, unsigned int value)
151 {
152 struct io_apic __iomem *io_apic = io_apic_base(apic);
153 writel(value, &io_apic->data);
154 }
155
156 static int io_apic_level_ack_pending(unsigned int irq)
157 {
158 struct irq_pin_list *entry;
159 unsigned long flags;
160 int pending = 0;
161
162 spin_lock_irqsave(&ioapic_lock, flags);
163 entry = irq_2_pin + irq;
164 for (;;) {
165 unsigned int reg;
166 int pin;
167
168 pin = entry->pin;
169 if (pin == -1)
170 break;
171 reg = io_apic_read(entry->apic, 0x10 + pin*2);
172 /* Is the remote IRR bit set? */
173 pending |= (reg >> 14) & 1;
174 if (!entry->next)
175 break;
176 entry = irq_2_pin + entry->next;
177 }
178 spin_unlock_irqrestore(&ioapic_lock, flags);
179 return pending;
180 }
181
182 /*
183 * Synchronize the IO-APIC and the CPU by doing
184 * a dummy read from the IO-APIC
185 */
186 static inline void io_apic_sync(unsigned int apic)
187 {
188 struct io_apic __iomem *io_apic = io_apic_base(apic);
189 readl(&io_apic->data);
190 }
191
192 #define __DO_ACTION(R, ACTION, FINAL) \
193 \
194 { \
195 int pin; \
196 struct irq_pin_list *entry = irq_2_pin + irq; \
197 \
198 BUG_ON(irq >= NR_IRQS); \
199 for (;;) { \
200 unsigned int reg; \
201 pin = entry->pin; \
202 if (pin == -1) \
203 break; \
204 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
205 reg ACTION; \
206 io_apic_modify(entry->apic, reg); \
207 FINAL; \
208 if (!entry->next) \
209 break; \
210 entry = irq_2_pin + entry->next; \
211 } \
212 }
213
214 union entry_union {
215 struct { u32 w1, w2; };
216 struct IO_APIC_route_entry entry;
217 };
218
219 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
220 {
221 union entry_union eu;
222 unsigned long flags;
223 spin_lock_irqsave(&ioapic_lock, flags);
224 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
225 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
226 spin_unlock_irqrestore(&ioapic_lock, flags);
227 return eu.entry;
228 }
229
230 /*
231 * When we write a new IO APIC routing entry, we need to write the high
232 * word first! If the mask bit in the low word is clear, we will enable
233 * the interrupt, and we need to make sure the entry is fully populated
234 * before that happens.
235 */
236 static void
237 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
238 {
239 union entry_union eu;
240 eu.entry = e;
241 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
242 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
243 }
244
245 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
246 {
247 unsigned long flags;
248 spin_lock_irqsave(&ioapic_lock, flags);
249 __ioapic_write_entry(apic, pin, e);
250 spin_unlock_irqrestore(&ioapic_lock, flags);
251 }
252
253 /*
254 * When we mask an IO APIC routing entry, we need to write the low
255 * word first, in order to set the mask bit before we change the
256 * high bits!
257 */
258 static void ioapic_mask_entry(int apic, int pin)
259 {
260 unsigned long flags;
261 union entry_union eu = { .entry.mask = 1 };
262
263 spin_lock_irqsave(&ioapic_lock, flags);
264 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
265 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
266 spin_unlock_irqrestore(&ioapic_lock, flags);
267 }
268
269 #ifdef CONFIG_SMP
270 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
271 {
272 int apic, pin;
273 struct irq_pin_list *entry = irq_2_pin + irq;
274
275 BUG_ON(irq >= NR_IRQS);
276 for (;;) {
277 unsigned int reg;
278 apic = entry->apic;
279 pin = entry->pin;
280 if (pin == -1)
281 break;
282 io_apic_write(apic, 0x11 + pin*2, dest);
283 reg = io_apic_read(apic, 0x10 + pin*2);
284 reg &= ~0x000000ff;
285 reg |= vector;
286 io_apic_modify(apic, reg);
287 if (!entry->next)
288 break;
289 entry = irq_2_pin + entry->next;
290 }
291 }
292
293 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
294 {
295 struct irq_cfg *cfg = irq_cfg + irq;
296 unsigned long flags;
297 unsigned int dest;
298 cpumask_t tmp;
299
300 cpus_and(tmp, mask, cpu_online_map);
301 if (cpus_empty(tmp))
302 return;
303
304 if (assign_irq_vector(irq, mask))
305 return;
306
307 cpus_and(tmp, cfg->domain, mask);
308 dest = cpu_mask_to_apicid(tmp);
309
310 /*
311 * Only the high 8 bits are valid.
312 */
313 dest = SET_APIC_LOGICAL_ID(dest);
314
315 spin_lock_irqsave(&ioapic_lock, flags);
316 __target_IO_APIC_irq(irq, dest, cfg->vector);
317 irq_desc[irq].affinity = mask;
318 spin_unlock_irqrestore(&ioapic_lock, flags);
319 }
320 #endif
321
322 /*
323 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
324 * shared ISA-space IRQs, so we have to support them. We are super
325 * fast in the common case, and fast for shared ISA-space IRQs.
326 */
327 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
328 {
329 static int first_free_entry = NR_IRQS;
330 struct irq_pin_list *entry = irq_2_pin + irq;
331
332 BUG_ON(irq >= NR_IRQS);
333 while (entry->next)
334 entry = irq_2_pin + entry->next;
335
336 if (entry->pin != -1) {
337 entry->next = first_free_entry;
338 entry = irq_2_pin + entry->next;
339 if (++first_free_entry >= PIN_MAP_SIZE)
340 panic("io_apic.c: ran out of irq_2_pin entries!");
341 }
342 entry->apic = apic;
343 entry->pin = pin;
344 }
345
346
347 #define DO_ACTION(name,R,ACTION, FINAL) \
348 \
349 static void name##_IO_APIC_irq (unsigned int irq) \
350 __DO_ACTION(R, ACTION, FINAL)
351
352 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
353 /* mask = 1 */
354 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
355 /* mask = 0 */
356
357 static void mask_IO_APIC_irq (unsigned int irq)
358 {
359 unsigned long flags;
360
361 spin_lock_irqsave(&ioapic_lock, flags);
362 __mask_IO_APIC_irq(irq);
363 spin_unlock_irqrestore(&ioapic_lock, flags);
364 }
365
366 static void unmask_IO_APIC_irq (unsigned int irq)
367 {
368 unsigned long flags;
369
370 spin_lock_irqsave(&ioapic_lock, flags);
371 __unmask_IO_APIC_irq(irq);
372 spin_unlock_irqrestore(&ioapic_lock, flags);
373 }
374
375 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
376 {
377 struct IO_APIC_route_entry entry;
378
379 /* Check delivery_mode to be sure we're not clearing an SMI pin */
380 entry = ioapic_read_entry(apic, pin);
381 if (entry.delivery_mode == dest_SMI)
382 return;
383 /*
384 * Disable it in the IO-APIC irq-routing table:
385 */
386 ioapic_mask_entry(apic, pin);
387 }
388
389 static void clear_IO_APIC (void)
390 {
391 int apic, pin;
392
393 for (apic = 0; apic < nr_ioapics; apic++)
394 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
395 clear_IO_APIC_pin(apic, pin);
396 }
397
398 int skip_ioapic_setup;
399 int ioapic_force;
400
401 static int __init parse_noapic(char *str)
402 {
403 disable_ioapic_setup();
404 return 0;
405 }
406 early_param("noapic", parse_noapic);
407
408 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
409 static int __init disable_timer_pin_setup(char *arg)
410 {
411 disable_timer_pin_1 = 1;
412 return 1;
413 }
414 __setup("disable_timer_pin_1", disable_timer_pin_setup);
415
416 static int __init setup_disable_8254_timer(char *s)
417 {
418 timer_over_8254 = -1;
419 return 1;
420 }
421 static int __init setup_enable_8254_timer(char *s)
422 {
423 timer_over_8254 = 2;
424 return 1;
425 }
426
427 __setup("disable_8254_timer", setup_disable_8254_timer);
428 __setup("enable_8254_timer", setup_enable_8254_timer);
429
430
431 /*
432 * Find the IRQ entry number of a certain pin.
433 */
434 static int find_irq_entry(int apic, int pin, int type)
435 {
436 int i;
437
438 for (i = 0; i < mp_irq_entries; i++)
439 if (mp_irqs[i].mpc_irqtype == type &&
440 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
441 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
442 mp_irqs[i].mpc_dstirq == pin)
443 return i;
444
445 return -1;
446 }
447
448 /*
449 * Find the pin to which IRQ[irq] (ISA) is connected
450 */
451 static int __init find_isa_irq_pin(int irq, int type)
452 {
453 int i;
454
455 for (i = 0; i < mp_irq_entries; i++) {
456 int lbus = mp_irqs[i].mpc_srcbus;
457
458 if (test_bit(lbus, mp_bus_not_pci) &&
459 (mp_irqs[i].mpc_irqtype == type) &&
460 (mp_irqs[i].mpc_srcbusirq == irq))
461
462 return mp_irqs[i].mpc_dstirq;
463 }
464 return -1;
465 }
466
467 static int __init find_isa_irq_apic(int irq, int type)
468 {
469 int i;
470
471 for (i = 0; i < mp_irq_entries; i++) {
472 int lbus = mp_irqs[i].mpc_srcbus;
473
474 if (test_bit(lbus, mp_bus_not_pci) &&
475 (mp_irqs[i].mpc_irqtype == type) &&
476 (mp_irqs[i].mpc_srcbusirq == irq))
477 break;
478 }
479 if (i < mp_irq_entries) {
480 int apic;
481 for(apic = 0; apic < nr_ioapics; apic++) {
482 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
483 return apic;
484 }
485 }
486
487 return -1;
488 }
489
490 /*
491 * Find a specific PCI IRQ entry.
492 * Not an __init, possibly needed by modules
493 */
494 static int pin_2_irq(int idx, int apic, int pin);
495
496 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
497 {
498 int apic, i, best_guess = -1;
499
500 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
501 bus, slot, pin);
502 if (mp_bus_id_to_pci_bus[bus] == -1) {
503 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
504 return -1;
505 }
506 for (i = 0; i < mp_irq_entries; i++) {
507 int lbus = mp_irqs[i].mpc_srcbus;
508
509 for (apic = 0; apic < nr_ioapics; apic++)
510 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
511 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
512 break;
513
514 if (!test_bit(lbus, mp_bus_not_pci) &&
515 !mp_irqs[i].mpc_irqtype &&
516 (bus == lbus) &&
517 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
518 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
519
520 if (!(apic || IO_APIC_IRQ(irq)))
521 continue;
522
523 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
524 return irq;
525 /*
526 * Use the first all-but-pin matching entry as a
527 * best-guess fuzzy result for broken mptables.
528 */
529 if (best_guess < 0)
530 best_guess = irq;
531 }
532 }
533 BUG_ON(best_guess >= NR_IRQS);
534 return best_guess;
535 }
536
537 /* ISA interrupts are always polarity zero edge triggered,
538 * when listed as conforming in the MP table. */
539
540 #define default_ISA_trigger(idx) (0)
541 #define default_ISA_polarity(idx) (0)
542
543 /* PCI interrupts are always polarity one level triggered,
544 * when listed as conforming in the MP table. */
545
546 #define default_PCI_trigger(idx) (1)
547 #define default_PCI_polarity(idx) (1)
548
549 static int MPBIOS_polarity(int idx)
550 {
551 int bus = mp_irqs[idx].mpc_srcbus;
552 int polarity;
553
554 /*
555 * Determine IRQ line polarity (high active or low active):
556 */
557 switch (mp_irqs[idx].mpc_irqflag & 3)
558 {
559 case 0: /* conforms, ie. bus-type dependent polarity */
560 if (test_bit(bus, mp_bus_not_pci))
561 polarity = default_ISA_polarity(idx);
562 else
563 polarity = default_PCI_polarity(idx);
564 break;
565 case 1: /* high active */
566 {
567 polarity = 0;
568 break;
569 }
570 case 2: /* reserved */
571 {
572 printk(KERN_WARNING "broken BIOS!!\n");
573 polarity = 1;
574 break;
575 }
576 case 3: /* low active */
577 {
578 polarity = 1;
579 break;
580 }
581 default: /* invalid */
582 {
583 printk(KERN_WARNING "broken BIOS!!\n");
584 polarity = 1;
585 break;
586 }
587 }
588 return polarity;
589 }
590
591 static int MPBIOS_trigger(int idx)
592 {
593 int bus = mp_irqs[idx].mpc_srcbus;
594 int trigger;
595
596 /*
597 * Determine IRQ trigger mode (edge or level sensitive):
598 */
599 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
600 {
601 case 0: /* conforms, ie. bus-type dependent */
602 if (test_bit(bus, mp_bus_not_pci))
603 trigger = default_ISA_trigger(idx);
604 else
605 trigger = default_PCI_trigger(idx);
606 break;
607 case 1: /* edge */
608 {
609 trigger = 0;
610 break;
611 }
612 case 2: /* reserved */
613 {
614 printk(KERN_WARNING "broken BIOS!!\n");
615 trigger = 1;
616 break;
617 }
618 case 3: /* level */
619 {
620 trigger = 1;
621 break;
622 }
623 default: /* invalid */
624 {
625 printk(KERN_WARNING "broken BIOS!!\n");
626 trigger = 0;
627 break;
628 }
629 }
630 return trigger;
631 }
632
633 static inline int irq_polarity(int idx)
634 {
635 return MPBIOS_polarity(idx);
636 }
637
638 static inline int irq_trigger(int idx)
639 {
640 return MPBIOS_trigger(idx);
641 }
642
643 static int pin_2_irq(int idx, int apic, int pin)
644 {
645 int irq, i;
646 int bus = mp_irqs[idx].mpc_srcbus;
647
648 /*
649 * Debugging check, we are in big trouble if this message pops up!
650 */
651 if (mp_irqs[idx].mpc_dstirq != pin)
652 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
653
654 if (test_bit(bus, mp_bus_not_pci)) {
655 irq = mp_irqs[idx].mpc_srcbusirq;
656 } else {
657 /*
658 * PCI IRQs are mapped in order
659 */
660 i = irq = 0;
661 while (i < apic)
662 irq += nr_ioapic_registers[i++];
663 irq += pin;
664 }
665 BUG_ON(irq >= NR_IRQS);
666 return irq;
667 }
668
669 static int __assign_irq_vector(int irq, cpumask_t mask)
670 {
671 /*
672 * NOTE! The local APIC isn't very good at handling
673 * multiple interrupts at the same interrupt level.
674 * As the interrupt level is determined by taking the
675 * vector number and shifting that right by 4, we
676 * want to spread these out a bit so that they don't
677 * all fall in the same interrupt level.
678 *
679 * Also, we've got to be careful not to trash gate
680 * 0x80, because int 0x80 is hm, kind of importantish. ;)
681 */
682 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
683 unsigned int old_vector;
684 int cpu;
685 struct irq_cfg *cfg;
686
687 BUG_ON((unsigned)irq >= NR_IRQS);
688 cfg = &irq_cfg[irq];
689
690 /* Only try and allocate irqs on cpus that are present */
691 cpus_and(mask, mask, cpu_online_map);
692
693 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
694 return -EBUSY;
695
696 old_vector = cfg->vector;
697 if (old_vector) {
698 cpumask_t tmp;
699 cpus_and(tmp, cfg->domain, mask);
700 if (!cpus_empty(tmp))
701 return 0;
702 }
703
704 for_each_cpu_mask(cpu, mask) {
705 cpumask_t domain, new_mask;
706 int new_cpu;
707 int vector, offset;
708
709 domain = vector_allocation_domain(cpu);
710 cpus_and(new_mask, domain, cpu_online_map);
711
712 vector = current_vector;
713 offset = current_offset;
714 next:
715 vector += 8;
716 if (vector >= FIRST_SYSTEM_VECTOR) {
717 /* If we run out of vectors on large boxen, must share them. */
718 offset = (offset + 1) % 8;
719 vector = FIRST_DEVICE_VECTOR + offset;
720 }
721 if (unlikely(current_vector == vector))
722 continue;
723 if (vector == IA32_SYSCALL_VECTOR)
724 goto next;
725 for_each_cpu_mask(new_cpu, new_mask)
726 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
727 goto next;
728 /* Found one! */
729 current_vector = vector;
730 current_offset = offset;
731 if (old_vector) {
732 cfg->move_in_progress = 1;
733 cfg->old_domain = cfg->domain;
734 }
735 for_each_cpu_mask(new_cpu, new_mask)
736 per_cpu(vector_irq, new_cpu)[vector] = irq;
737 cfg->vector = vector;
738 cfg->domain = domain;
739 return 0;
740 }
741 return -ENOSPC;
742 }
743
744 static int assign_irq_vector(int irq, cpumask_t mask)
745 {
746 int err;
747 unsigned long flags;
748
749 spin_lock_irqsave(&vector_lock, flags);
750 err = __assign_irq_vector(irq, mask);
751 spin_unlock_irqrestore(&vector_lock, flags);
752 return err;
753 }
754
755 static void __clear_irq_vector(int irq)
756 {
757 struct irq_cfg *cfg;
758 cpumask_t mask;
759 int cpu, vector;
760
761 BUG_ON((unsigned)irq >= NR_IRQS);
762 cfg = &irq_cfg[irq];
763 BUG_ON(!cfg->vector);
764
765 vector = cfg->vector;
766 cpus_and(mask, cfg->domain, cpu_online_map);
767 for_each_cpu_mask(cpu, mask)
768 per_cpu(vector_irq, cpu)[vector] = -1;
769
770 cfg->vector = 0;
771 cfg->domain = CPU_MASK_NONE;
772 }
773
774 void __setup_vector_irq(int cpu)
775 {
776 /* Initialize vector_irq on a new cpu */
777 /* This function must be called with vector_lock held */
778 int irq, vector;
779
780 /* Mark the inuse vectors */
781 for (irq = 0; irq < NR_IRQS; ++irq) {
782 if (!cpu_isset(cpu, irq_cfg[irq].domain))
783 continue;
784 vector = irq_cfg[irq].vector;
785 per_cpu(vector_irq, cpu)[vector] = irq;
786 }
787 /* Mark the free vectors */
788 for (vector = 0; vector < NR_VECTORS; ++vector) {
789 irq = per_cpu(vector_irq, cpu)[vector];
790 if (irq < 0)
791 continue;
792 if (!cpu_isset(cpu, irq_cfg[irq].domain))
793 per_cpu(vector_irq, cpu)[vector] = -1;
794 }
795 }
796
797
798 static struct irq_chip ioapic_chip;
799
800 static void ioapic_register_intr(int irq, unsigned long trigger)
801 {
802 if (trigger) {
803 irq_desc[irq].status |= IRQ_LEVEL;
804 set_irq_chip_and_handler_name(irq, &ioapic_chip,
805 handle_fasteoi_irq, "fasteoi");
806 } else {
807 irq_desc[irq].status &= ~IRQ_LEVEL;
808 set_irq_chip_and_handler_name(irq, &ioapic_chip,
809 handle_edge_irq, "edge");
810 }
811 }
812
813 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
814 int trigger, int polarity)
815 {
816 struct irq_cfg *cfg = irq_cfg + irq;
817 struct IO_APIC_route_entry entry;
818 cpumask_t mask;
819
820 if (!IO_APIC_IRQ(irq))
821 return;
822
823 mask = TARGET_CPUS;
824 if (assign_irq_vector(irq, mask))
825 return;
826
827 cpus_and(mask, cfg->domain, mask);
828
829 apic_printk(APIC_VERBOSE,KERN_DEBUG
830 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
831 "IRQ %d Mode:%i Active:%i)\n",
832 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
833 irq, trigger, polarity);
834
835 /*
836 * add it to the IO-APIC irq-routing table:
837 */
838 memset(&entry,0,sizeof(entry));
839
840 entry.delivery_mode = INT_DELIVERY_MODE;
841 entry.dest_mode = INT_DEST_MODE;
842 entry.dest = cpu_mask_to_apicid(mask);
843 entry.mask = 0; /* enable IRQ */
844 entry.trigger = trigger;
845 entry.polarity = polarity;
846 entry.vector = cfg->vector;
847
848 /* Mask level triggered irqs.
849 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
850 */
851 if (trigger)
852 entry.mask = 1;
853
854 ioapic_register_intr(irq, trigger);
855 if (irq < 16)
856 disable_8259A_irq(irq);
857
858 ioapic_write_entry(apic, pin, entry);
859 }
860
861 static void __init setup_IO_APIC_irqs(void)
862 {
863 int apic, pin, idx, irq, first_notcon = 1;
864
865 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
866
867 for (apic = 0; apic < nr_ioapics; apic++) {
868 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
869
870 idx = find_irq_entry(apic,pin,mp_INT);
871 if (idx == -1) {
872 if (first_notcon) {
873 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
874 first_notcon = 0;
875 } else
876 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
877 continue;
878 }
879 if (!first_notcon) {
880 apic_printk(APIC_VERBOSE, " not connected.\n");
881 first_notcon = 1;
882 }
883
884 irq = pin_2_irq(idx, apic, pin);
885 add_pin_to_irq(irq, apic, pin);
886
887 setup_IO_APIC_irq(apic, pin, irq,
888 irq_trigger(idx), irq_polarity(idx));
889 }
890 }
891
892 if (!first_notcon)
893 apic_printk(APIC_VERBOSE, " not connected.\n");
894 }
895
896 /*
897 * Set up the 8259A-master output pin as broadcast to all
898 * CPUs.
899 */
900 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
901 {
902 struct IO_APIC_route_entry entry;
903 unsigned long flags;
904
905 memset(&entry,0,sizeof(entry));
906
907 disable_8259A_irq(0);
908
909 /* mask LVT0 */
910 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
911
912 /*
913 * We use logical delivery to get the timer IRQ
914 * to the first CPU.
915 */
916 entry.dest_mode = INT_DEST_MODE;
917 entry.mask = 0; /* unmask IRQ now */
918 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
919 entry.delivery_mode = INT_DELIVERY_MODE;
920 entry.polarity = 0;
921 entry.trigger = 0;
922 entry.vector = vector;
923
924 /*
925 * The timer IRQ doesn't have to know that behind the
926 * scene we have a 8259A-master in AEOI mode ...
927 */
928 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
929
930 /*
931 * Add it to the IO-APIC irq-routing table:
932 */
933 spin_lock_irqsave(&ioapic_lock, flags);
934 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
935 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
936 spin_unlock_irqrestore(&ioapic_lock, flags);
937
938 enable_8259A_irq(0);
939 }
940
941 void __apicdebuginit print_IO_APIC(void)
942 {
943 int apic, i;
944 union IO_APIC_reg_00 reg_00;
945 union IO_APIC_reg_01 reg_01;
946 union IO_APIC_reg_02 reg_02;
947 unsigned long flags;
948
949 if (apic_verbosity == APIC_QUIET)
950 return;
951
952 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
953 for (i = 0; i < nr_ioapics; i++)
954 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
955 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
956
957 /*
958 * We are a bit conservative about what we expect. We have to
959 * know about every hardware change ASAP.
960 */
961 printk(KERN_INFO "testing the IO APIC.......................\n");
962
963 for (apic = 0; apic < nr_ioapics; apic++) {
964
965 spin_lock_irqsave(&ioapic_lock, flags);
966 reg_00.raw = io_apic_read(apic, 0);
967 reg_01.raw = io_apic_read(apic, 1);
968 if (reg_01.bits.version >= 0x10)
969 reg_02.raw = io_apic_read(apic, 2);
970 spin_unlock_irqrestore(&ioapic_lock, flags);
971
972 printk("\n");
973 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
974 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
975 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
976
977 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
978 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
979
980 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
981 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
982
983 if (reg_01.bits.version >= 0x10) {
984 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
985 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
986 }
987
988 printk(KERN_DEBUG ".... IRQ redirection table:\n");
989
990 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
991 " Stat Dmod Deli Vect: \n");
992
993 for (i = 0; i <= reg_01.bits.entries; i++) {
994 struct IO_APIC_route_entry entry;
995
996 entry = ioapic_read_entry(apic, i);
997
998 printk(KERN_DEBUG " %02x %03X ",
999 i,
1000 entry.dest
1001 );
1002
1003 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1004 entry.mask,
1005 entry.trigger,
1006 entry.irr,
1007 entry.polarity,
1008 entry.delivery_status,
1009 entry.dest_mode,
1010 entry.delivery_mode,
1011 entry.vector
1012 );
1013 }
1014 }
1015 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1016 for (i = 0; i < NR_IRQS; i++) {
1017 struct irq_pin_list *entry = irq_2_pin + i;
1018 if (entry->pin < 0)
1019 continue;
1020 printk(KERN_DEBUG "IRQ%d ", i);
1021 for (;;) {
1022 printk("-> %d:%d", entry->apic, entry->pin);
1023 if (!entry->next)
1024 break;
1025 entry = irq_2_pin + entry->next;
1026 }
1027 printk("\n");
1028 }
1029
1030 printk(KERN_INFO ".................................... done.\n");
1031
1032 return;
1033 }
1034
1035 #if 0
1036
1037 static __apicdebuginit void print_APIC_bitfield (int base)
1038 {
1039 unsigned int v;
1040 int i, j;
1041
1042 if (apic_verbosity == APIC_QUIET)
1043 return;
1044
1045 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1046 for (i = 0; i < 8; i++) {
1047 v = apic_read(base + i*0x10);
1048 for (j = 0; j < 32; j++) {
1049 if (v & (1<<j))
1050 printk("1");
1051 else
1052 printk("0");
1053 }
1054 printk("\n");
1055 }
1056 }
1057
1058 void __apicdebuginit print_local_APIC(void * dummy)
1059 {
1060 unsigned int v, ver, maxlvt;
1061
1062 if (apic_verbosity == APIC_QUIET)
1063 return;
1064
1065 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1066 smp_processor_id(), hard_smp_processor_id());
1067 v = apic_read(APIC_ID);
1068 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1069 v = apic_read(APIC_LVR);
1070 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1071 ver = GET_APIC_VERSION(v);
1072 maxlvt = get_maxlvt();
1073
1074 v = apic_read(APIC_TASKPRI);
1075 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1076
1077 v = apic_read(APIC_ARBPRI);
1078 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1079 v & APIC_ARBPRI_MASK);
1080 v = apic_read(APIC_PROCPRI);
1081 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1082
1083 v = apic_read(APIC_EOI);
1084 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1085 v = apic_read(APIC_RRR);
1086 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1087 v = apic_read(APIC_LDR);
1088 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1089 v = apic_read(APIC_DFR);
1090 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1091 v = apic_read(APIC_SPIV);
1092 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1093
1094 printk(KERN_DEBUG "... APIC ISR field:\n");
1095 print_APIC_bitfield(APIC_ISR);
1096 printk(KERN_DEBUG "... APIC TMR field:\n");
1097 print_APIC_bitfield(APIC_TMR);
1098 printk(KERN_DEBUG "... APIC IRR field:\n");
1099 print_APIC_bitfield(APIC_IRR);
1100
1101 v = apic_read(APIC_ESR);
1102 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1103
1104 v = apic_read(APIC_ICR);
1105 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1106 v = apic_read(APIC_ICR2);
1107 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1108
1109 v = apic_read(APIC_LVTT);
1110 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1111
1112 if (maxlvt > 3) { /* PC is LVT#4. */
1113 v = apic_read(APIC_LVTPC);
1114 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1115 }
1116 v = apic_read(APIC_LVT0);
1117 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1118 v = apic_read(APIC_LVT1);
1119 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1120
1121 if (maxlvt > 2) { /* ERR is LVT#3. */
1122 v = apic_read(APIC_LVTERR);
1123 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1124 }
1125
1126 v = apic_read(APIC_TMICT);
1127 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1128 v = apic_read(APIC_TMCCT);
1129 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1130 v = apic_read(APIC_TDCR);
1131 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1132 printk("\n");
1133 }
1134
1135 void print_all_local_APICs (void)
1136 {
1137 on_each_cpu(print_local_APIC, NULL, 1, 1);
1138 }
1139
1140 void __apicdebuginit print_PIC(void)
1141 {
1142 unsigned int v;
1143 unsigned long flags;
1144
1145 if (apic_verbosity == APIC_QUIET)
1146 return;
1147
1148 printk(KERN_DEBUG "\nprinting PIC contents\n");
1149
1150 spin_lock_irqsave(&i8259A_lock, flags);
1151
1152 v = inb(0xa1) << 8 | inb(0x21);
1153 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1154
1155 v = inb(0xa0) << 8 | inb(0x20);
1156 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1157
1158 outb(0x0b,0xa0);
1159 outb(0x0b,0x20);
1160 v = inb(0xa0) << 8 | inb(0x20);
1161 outb(0x0a,0xa0);
1162 outb(0x0a,0x20);
1163
1164 spin_unlock_irqrestore(&i8259A_lock, flags);
1165
1166 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1167
1168 v = inb(0x4d1) << 8 | inb(0x4d0);
1169 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1170 }
1171
1172 #endif /* 0 */
1173
1174 static void __init enable_IO_APIC(void)
1175 {
1176 union IO_APIC_reg_01 reg_01;
1177 int i8259_apic, i8259_pin;
1178 int i, apic;
1179 unsigned long flags;
1180
1181 for (i = 0; i < PIN_MAP_SIZE; i++) {
1182 irq_2_pin[i].pin = -1;
1183 irq_2_pin[i].next = 0;
1184 }
1185
1186 /*
1187 * The number of IO-APIC IRQ registers (== #pins):
1188 */
1189 for (apic = 0; apic < nr_ioapics; apic++) {
1190 spin_lock_irqsave(&ioapic_lock, flags);
1191 reg_01.raw = io_apic_read(apic, 1);
1192 spin_unlock_irqrestore(&ioapic_lock, flags);
1193 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1194 }
1195 for(apic = 0; apic < nr_ioapics; apic++) {
1196 int pin;
1197 /* See if any of the pins is in ExtINT mode */
1198 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1199 struct IO_APIC_route_entry entry;
1200 entry = ioapic_read_entry(apic, pin);
1201
1202 /* If the interrupt line is enabled and in ExtInt mode
1203 * I have found the pin where the i8259 is connected.
1204 */
1205 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1206 ioapic_i8259.apic = apic;
1207 ioapic_i8259.pin = pin;
1208 goto found_i8259;
1209 }
1210 }
1211 }
1212 found_i8259:
1213 /* Look to see what if the MP table has reported the ExtINT */
1214 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1215 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1216 /* Trust the MP table if nothing is setup in the hardware */
1217 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1218 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1219 ioapic_i8259.pin = i8259_pin;
1220 ioapic_i8259.apic = i8259_apic;
1221 }
1222 /* Complain if the MP table and the hardware disagree */
1223 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1224 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1225 {
1226 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1227 }
1228
1229 /*
1230 * Do not trust the IO-APIC being empty at bootup
1231 */
1232 clear_IO_APIC();
1233 }
1234
1235 /*
1236 * Not an __init, needed by the reboot code
1237 */
1238 void disable_IO_APIC(void)
1239 {
1240 /*
1241 * Clear the IO-APIC before rebooting:
1242 */
1243 clear_IO_APIC();
1244
1245 /*
1246 * If the i8259 is routed through an IOAPIC
1247 * Put that IOAPIC in virtual wire mode
1248 * so legacy interrupts can be delivered.
1249 */
1250 if (ioapic_i8259.pin != -1) {
1251 struct IO_APIC_route_entry entry;
1252
1253 memset(&entry, 0, sizeof(entry));
1254 entry.mask = 0; /* Enabled */
1255 entry.trigger = 0; /* Edge */
1256 entry.irr = 0;
1257 entry.polarity = 0; /* High */
1258 entry.delivery_status = 0;
1259 entry.dest_mode = 0; /* Physical */
1260 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1261 entry.vector = 0;
1262 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
1263
1264 /*
1265 * Add it to the IO-APIC irq-routing table:
1266 */
1267 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1268 }
1269
1270 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1271 }
1272
1273 /*
1274 * There is a nasty bug in some older SMP boards, their mptable lies
1275 * about the timer IRQ. We do the following to work around the situation:
1276 *
1277 * - timer IRQ defaults to IO-APIC IRQ
1278 * - if this function detects that timer IRQs are defunct, then we fall
1279 * back to ISA timer IRQs
1280 */
1281 static int __init timer_irq_works(void)
1282 {
1283 unsigned long t1 = jiffies;
1284 unsigned long flags;
1285
1286 local_save_flags(flags);
1287 local_irq_enable();
1288 /* Let ten ticks pass... */
1289 mdelay((10 * 1000) / HZ);
1290 local_irq_restore(flags);
1291
1292 /*
1293 * Expect a few ticks at least, to be sure some possible
1294 * glue logic does not lock up after one or two first
1295 * ticks in a non-ExtINT mode. Also the local APIC
1296 * might have cached one ExtINT interrupt. Finally, at
1297 * least one tick may be lost due to delays.
1298 */
1299
1300 /* jiffies wrap? */
1301 if (jiffies - t1 > 4)
1302 return 1;
1303 return 0;
1304 }
1305
1306 /*
1307 * In the SMP+IOAPIC case it might happen that there are an unspecified
1308 * number of pending IRQ events unhandled. These cases are very rare,
1309 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1310 * better to do it this way as thus we do not have to be aware of
1311 * 'pending' interrupts in the IRQ path, except at this point.
1312 */
1313 /*
1314 * Edge triggered needs to resend any interrupt
1315 * that was delayed but this is now handled in the device
1316 * independent code.
1317 */
1318
1319 /*
1320 * Starting up a edge-triggered IO-APIC interrupt is
1321 * nasty - we need to make sure that we get the edge.
1322 * If it is already asserted for some reason, we need
1323 * return 1 to indicate that is was pending.
1324 *
1325 * This is not complete - we should be able to fake
1326 * an edge even if it isn't on the 8259A...
1327 */
1328
1329 static unsigned int startup_ioapic_irq(unsigned int irq)
1330 {
1331 int was_pending = 0;
1332 unsigned long flags;
1333
1334 spin_lock_irqsave(&ioapic_lock, flags);
1335 if (irq < 16) {
1336 disable_8259A_irq(irq);
1337 if (i8259A_irq_pending(irq))
1338 was_pending = 1;
1339 }
1340 __unmask_IO_APIC_irq(irq);
1341 spin_unlock_irqrestore(&ioapic_lock, flags);
1342
1343 return was_pending;
1344 }
1345
1346 static int ioapic_retrigger_irq(unsigned int irq)
1347 {
1348 struct irq_cfg *cfg = &irq_cfg[irq];
1349 cpumask_t mask;
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&vector_lock, flags);
1353 cpus_clear(mask);
1354 cpu_set(first_cpu(cfg->domain), mask);
1355
1356 send_IPI_mask(mask, cfg->vector);
1357 spin_unlock_irqrestore(&vector_lock, flags);
1358
1359 return 1;
1360 }
1361
1362 /*
1363 * Level and edge triggered IO-APIC interrupts need different handling,
1364 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1365 * handled with the level-triggered descriptor, but that one has slightly
1366 * more overhead. Level-triggered interrupts cannot be handled with the
1367 * edge-triggered handler, without risking IRQ storms and other ugly
1368 * races.
1369 */
1370
1371 #ifdef CONFIG_SMP
1372 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1373 {
1374 unsigned vector, me;
1375 ack_APIC_irq();
1376 exit_idle();
1377 irq_enter();
1378
1379 me = smp_processor_id();
1380 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1381 unsigned int irq;
1382 struct irq_desc *desc;
1383 struct irq_cfg *cfg;
1384 irq = __get_cpu_var(vector_irq)[vector];
1385 if (irq >= NR_IRQS)
1386 continue;
1387
1388 desc = irq_desc + irq;
1389 cfg = irq_cfg + irq;
1390 spin_lock(&desc->lock);
1391 if (!cfg->move_cleanup_count)
1392 goto unlock;
1393
1394 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1395 goto unlock;
1396
1397 __get_cpu_var(vector_irq)[vector] = -1;
1398 cfg->move_cleanup_count--;
1399 unlock:
1400 spin_unlock(&desc->lock);
1401 }
1402
1403 irq_exit();
1404 }
1405
1406 static void irq_complete_move(unsigned int irq)
1407 {
1408 struct irq_cfg *cfg = irq_cfg + irq;
1409 unsigned vector, me;
1410
1411 if (likely(!cfg->move_in_progress))
1412 return;
1413
1414 vector = ~get_irq_regs()->orig_rax;
1415 me = smp_processor_id();
1416 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1417 cpumask_t cleanup_mask;
1418
1419 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1420 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1421 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1422 cfg->move_in_progress = 0;
1423 }
1424 }
1425 #else
1426 static inline void irq_complete_move(unsigned int irq) {}
1427 #endif
1428
1429 static void ack_apic_edge(unsigned int irq)
1430 {
1431 irq_complete_move(irq);
1432 move_native_irq(irq);
1433 ack_APIC_irq();
1434 }
1435
1436 static void ack_apic_level(unsigned int irq)
1437 {
1438 int do_unmask_irq = 0;
1439
1440 irq_complete_move(irq);
1441 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1442 /* If we are moving the irq we need to mask it */
1443 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1444 do_unmask_irq = 1;
1445 mask_IO_APIC_irq(irq);
1446 }
1447 #endif
1448
1449 /*
1450 * We must acknowledge the irq before we move it or the acknowledge will
1451 * not propagate properly.
1452 */
1453 ack_APIC_irq();
1454
1455 /* Now we can move and renable the irq */
1456 if (unlikely(do_unmask_irq)) {
1457 /* Only migrate the irq if the ack has been received.
1458 *
1459 * On rare occasions the broadcast level triggered ack gets
1460 * delayed going to ioapics, and if we reprogram the
1461 * vector while Remote IRR is still set the irq will never
1462 * fire again.
1463 *
1464 * To prevent this scenario we read the Remote IRR bit
1465 * of the ioapic. This has two effects.
1466 * - On any sane system the read of the ioapic will
1467 * flush writes (and acks) going to the ioapic from
1468 * this cpu.
1469 * - We get to see if the ACK has actually been delivered.
1470 *
1471 * Based on failed experiments of reprogramming the
1472 * ioapic entry from outside of irq context starting
1473 * with masking the ioapic entry and then polling until
1474 * Remote IRR was clear before reprogramming the
1475 * ioapic I don't trust the Remote IRR bit to be
1476 * completey accurate.
1477 *
1478 * However there appears to be no other way to plug
1479 * this race, so if the Remote IRR bit is not
1480 * accurate and is causing problems then it is a hardware bug
1481 * and you can go talk to the chipset vendor about it.
1482 */
1483 if (!io_apic_level_ack_pending(irq))
1484 move_masked_irq(irq);
1485 unmask_IO_APIC_irq(irq);
1486 }
1487 }
1488
1489 static struct irq_chip ioapic_chip __read_mostly = {
1490 .name = "IO-APIC",
1491 .startup = startup_ioapic_irq,
1492 .mask = mask_IO_APIC_irq,
1493 .unmask = unmask_IO_APIC_irq,
1494 .ack = ack_apic_edge,
1495 .eoi = ack_apic_level,
1496 #ifdef CONFIG_SMP
1497 .set_affinity = set_ioapic_affinity_irq,
1498 #endif
1499 .retrigger = ioapic_retrigger_irq,
1500 };
1501
1502 static inline void init_IO_APIC_traps(void)
1503 {
1504 int irq;
1505
1506 /*
1507 * NOTE! The local APIC isn't very good at handling
1508 * multiple interrupts at the same interrupt level.
1509 * As the interrupt level is determined by taking the
1510 * vector number and shifting that right by 4, we
1511 * want to spread these out a bit so that they don't
1512 * all fall in the same interrupt level.
1513 *
1514 * Also, we've got to be careful not to trash gate
1515 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1516 */
1517 for (irq = 0; irq < NR_IRQS ; irq++) {
1518 int tmp = irq;
1519 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1520 /*
1521 * Hmm.. We don't have an entry for this,
1522 * so default to an old-fashioned 8259
1523 * interrupt if we can..
1524 */
1525 if (irq < 16)
1526 make_8259A_irq(irq);
1527 else
1528 /* Strange. Oh, well.. */
1529 irq_desc[irq].chip = &no_irq_chip;
1530 }
1531 }
1532 }
1533
1534 static void enable_lapic_irq (unsigned int irq)
1535 {
1536 unsigned long v;
1537
1538 v = apic_read(APIC_LVT0);
1539 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1540 }
1541
1542 static void disable_lapic_irq (unsigned int irq)
1543 {
1544 unsigned long v;
1545
1546 v = apic_read(APIC_LVT0);
1547 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1548 }
1549
1550 static void ack_lapic_irq (unsigned int irq)
1551 {
1552 ack_APIC_irq();
1553 }
1554
1555 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1556
1557 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1558 .name = "local-APIC",
1559 .typename = "local-APIC-edge",
1560 .startup = NULL, /* startup_irq() not used for IRQ0 */
1561 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1562 .enable = enable_lapic_irq,
1563 .disable = disable_lapic_irq,
1564 .ack = ack_lapic_irq,
1565 .end = end_lapic_irq,
1566 };
1567
1568 static void setup_nmi (void)
1569 {
1570 /*
1571 * Dirty trick to enable the NMI watchdog ...
1572 * We put the 8259A master into AEOI mode and
1573 * unmask on all local APICs LVT0 as NMI.
1574 *
1575 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1576 * is from Maciej W. Rozycki - so we do not have to EOI from
1577 * the NMI handler or the timer interrupt.
1578 */
1579 printk(KERN_INFO "activating NMI Watchdog ...");
1580
1581 enable_NMI_through_LVT0(NULL);
1582
1583 printk(" done.\n");
1584 }
1585
1586 /*
1587 * This looks a bit hackish but it's about the only one way of sending
1588 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1589 * not support the ExtINT mode, unfortunately. We need to send these
1590 * cycles as some i82489DX-based boards have glue logic that keeps the
1591 * 8259A interrupt line asserted until INTA. --macro
1592 */
1593 static inline void unlock_ExtINT_logic(void)
1594 {
1595 int apic, pin, i;
1596 struct IO_APIC_route_entry entry0, entry1;
1597 unsigned char save_control, save_freq_select;
1598 unsigned long flags;
1599
1600 pin = find_isa_irq_pin(8, mp_INT);
1601 apic = find_isa_irq_apic(8, mp_INT);
1602 if (pin == -1)
1603 return;
1604
1605 spin_lock_irqsave(&ioapic_lock, flags);
1606 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1607 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1608 spin_unlock_irqrestore(&ioapic_lock, flags);
1609 clear_IO_APIC_pin(apic, pin);
1610
1611 memset(&entry1, 0, sizeof(entry1));
1612
1613 entry1.dest_mode = 0; /* physical delivery */
1614 entry1.mask = 0; /* unmask IRQ now */
1615 entry1.dest = hard_smp_processor_id();
1616 entry1.delivery_mode = dest_ExtINT;
1617 entry1.polarity = entry0.polarity;
1618 entry1.trigger = 0;
1619 entry1.vector = 0;
1620
1621 spin_lock_irqsave(&ioapic_lock, flags);
1622 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1623 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1624 spin_unlock_irqrestore(&ioapic_lock, flags);
1625
1626 save_control = CMOS_READ(RTC_CONTROL);
1627 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1628 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1629 RTC_FREQ_SELECT);
1630 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1631
1632 i = 100;
1633 while (i-- > 0) {
1634 mdelay(10);
1635 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1636 i -= 10;
1637 }
1638
1639 CMOS_WRITE(save_control, RTC_CONTROL);
1640 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1641 clear_IO_APIC_pin(apic, pin);
1642
1643 spin_lock_irqsave(&ioapic_lock, flags);
1644 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1645 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1646 spin_unlock_irqrestore(&ioapic_lock, flags);
1647 }
1648
1649 /*
1650 * This code may look a bit paranoid, but it's supposed to cooperate with
1651 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1652 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1653 * fanatically on his truly buggy board.
1654 *
1655 * FIXME: really need to revamp this for modern platforms only.
1656 */
1657 static inline void check_timer(void)
1658 {
1659 struct irq_cfg *cfg = irq_cfg + 0;
1660 int apic1, pin1, apic2, pin2;
1661 unsigned long flags;
1662
1663 local_irq_save(flags);
1664
1665 /*
1666 * get/set the timer IRQ vector:
1667 */
1668 disable_8259A_irq(0);
1669 assign_irq_vector(0, TARGET_CPUS);
1670
1671 /*
1672 * Subtle, code in do_timer_interrupt() expects an AEOI
1673 * mode for the 8259A whenever interrupts are routed
1674 * through I/O APICs. Also IRQ0 has to be enabled in
1675 * the 8259A which implies the virtual wire has to be
1676 * disabled in the local APIC.
1677 */
1678 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1679 init_8259A(1);
1680 if (timer_over_8254 > 0)
1681 enable_8259A_irq(0);
1682
1683 pin1 = find_isa_irq_pin(0, mp_INT);
1684 apic1 = find_isa_irq_apic(0, mp_INT);
1685 pin2 = ioapic_i8259.pin;
1686 apic2 = ioapic_i8259.apic;
1687
1688 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1689 cfg->vector, apic1, pin1, apic2, pin2);
1690
1691 if (pin1 != -1) {
1692 /*
1693 * Ok, does IRQ0 through the IOAPIC work?
1694 */
1695 unmask_IO_APIC_irq(0);
1696 if (!no_timer_check && timer_irq_works()) {
1697 nmi_watchdog_default();
1698 if (nmi_watchdog == NMI_IO_APIC) {
1699 disable_8259A_irq(0);
1700 setup_nmi();
1701 enable_8259A_irq(0);
1702 }
1703 if (disable_timer_pin_1 > 0)
1704 clear_IO_APIC_pin(0, pin1);
1705 goto out;
1706 }
1707 clear_IO_APIC_pin(apic1, pin1);
1708 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1709 "connected to IO-APIC\n");
1710 }
1711
1712 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1713 "through the 8259A ... ");
1714 if (pin2 != -1) {
1715 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1716 apic2, pin2);
1717 /*
1718 * legacy devices should be connected to IO APIC #0
1719 */
1720 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1721 if (timer_irq_works()) {
1722 apic_printk(APIC_VERBOSE," works.\n");
1723 nmi_watchdog_default();
1724 if (nmi_watchdog == NMI_IO_APIC) {
1725 setup_nmi();
1726 }
1727 goto out;
1728 }
1729 /*
1730 * Cleanup, just in case ...
1731 */
1732 clear_IO_APIC_pin(apic2, pin2);
1733 }
1734 apic_printk(APIC_VERBOSE," failed.\n");
1735
1736 if (nmi_watchdog == NMI_IO_APIC) {
1737 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1738 nmi_watchdog = 0;
1739 }
1740
1741 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1742
1743 disable_8259A_irq(0);
1744 irq_desc[0].chip = &lapic_irq_type;
1745 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1746 enable_8259A_irq(0);
1747
1748 if (timer_irq_works()) {
1749 apic_printk(APIC_VERBOSE," works.\n");
1750 goto out;
1751 }
1752 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1753 apic_printk(APIC_VERBOSE," failed.\n");
1754
1755 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1756
1757 init_8259A(0);
1758 make_8259A_irq(0);
1759 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1760
1761 unlock_ExtINT_logic();
1762
1763 if (timer_irq_works()) {
1764 apic_printk(APIC_VERBOSE," works.\n");
1765 goto out;
1766 }
1767 apic_printk(APIC_VERBOSE," failed :(.\n");
1768 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1769 out:
1770 local_irq_restore(flags);
1771 }
1772
1773 static int __init notimercheck(char *s)
1774 {
1775 no_timer_check = 1;
1776 return 1;
1777 }
1778 __setup("no_timer_check", notimercheck);
1779
1780 /*
1781 *
1782 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1783 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1784 * Linux doesn't really care, as it's not actually used
1785 * for any interrupt handling anyway.
1786 */
1787 #define PIC_IRQS (1<<2)
1788
1789 void __init setup_IO_APIC(void)
1790 {
1791 enable_IO_APIC();
1792
1793 if (acpi_ioapic)
1794 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1795 else
1796 io_apic_irqs = ~PIC_IRQS;
1797
1798 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1799
1800 sync_Arb_IDs();
1801 setup_IO_APIC_irqs();
1802 init_IO_APIC_traps();
1803 check_timer();
1804 if (!acpi_ioapic)
1805 print_IO_APIC();
1806 }
1807
1808 struct sysfs_ioapic_data {
1809 struct sys_device dev;
1810 struct IO_APIC_route_entry entry[0];
1811 };
1812 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1813
1814 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1815 {
1816 struct IO_APIC_route_entry *entry;
1817 struct sysfs_ioapic_data *data;
1818 int i;
1819
1820 data = container_of(dev, struct sysfs_ioapic_data, dev);
1821 entry = data->entry;
1822 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1823 *entry = ioapic_read_entry(dev->id, i);
1824
1825 return 0;
1826 }
1827
1828 static int ioapic_resume(struct sys_device *dev)
1829 {
1830 struct IO_APIC_route_entry *entry;
1831 struct sysfs_ioapic_data *data;
1832 unsigned long flags;
1833 union IO_APIC_reg_00 reg_00;
1834 int i;
1835
1836 data = container_of(dev, struct sysfs_ioapic_data, dev);
1837 entry = data->entry;
1838
1839 spin_lock_irqsave(&ioapic_lock, flags);
1840 reg_00.raw = io_apic_read(dev->id, 0);
1841 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1842 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1843 io_apic_write(dev->id, 0, reg_00.raw);
1844 }
1845 spin_unlock_irqrestore(&ioapic_lock, flags);
1846 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1847 ioapic_write_entry(dev->id, i, entry[i]);
1848
1849 return 0;
1850 }
1851
1852 static struct sysdev_class ioapic_sysdev_class = {
1853 .name = "ioapic",
1854 .suspend = ioapic_suspend,
1855 .resume = ioapic_resume,
1856 };
1857
1858 static int __init ioapic_init_sysfs(void)
1859 {
1860 struct sys_device * dev;
1861 int i, size, error;
1862
1863 error = sysdev_class_register(&ioapic_sysdev_class);
1864 if (error)
1865 return error;
1866
1867 for (i = 0; i < nr_ioapics; i++ ) {
1868 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1869 * sizeof(struct IO_APIC_route_entry);
1870 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1871 if (!mp_ioapic_data[i]) {
1872 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1873 continue;
1874 }
1875 dev = &mp_ioapic_data[i]->dev;
1876 dev->id = i;
1877 dev->cls = &ioapic_sysdev_class;
1878 error = sysdev_register(dev);
1879 if (error) {
1880 kfree(mp_ioapic_data[i]);
1881 mp_ioapic_data[i] = NULL;
1882 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1883 continue;
1884 }
1885 }
1886
1887 return 0;
1888 }
1889
1890 device_initcall(ioapic_init_sysfs);
1891
1892 /*
1893 * Dynamic irq allocate and deallocation
1894 */
1895 int create_irq(void)
1896 {
1897 /* Allocate an unused irq */
1898 int irq;
1899 int new;
1900 unsigned long flags;
1901
1902 irq = -ENOSPC;
1903 spin_lock_irqsave(&vector_lock, flags);
1904 for (new = (NR_IRQS - 1); new >= 0; new--) {
1905 if (platform_legacy_irq(new))
1906 continue;
1907 if (irq_cfg[new].vector != 0)
1908 continue;
1909 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1910 irq = new;
1911 break;
1912 }
1913 spin_unlock_irqrestore(&vector_lock, flags);
1914
1915 if (irq >= 0) {
1916 dynamic_irq_init(irq);
1917 }
1918 return irq;
1919 }
1920
1921 void destroy_irq(unsigned int irq)
1922 {
1923 unsigned long flags;
1924
1925 dynamic_irq_cleanup(irq);
1926
1927 spin_lock_irqsave(&vector_lock, flags);
1928 __clear_irq_vector(irq);
1929 spin_unlock_irqrestore(&vector_lock, flags);
1930 }
1931
1932 /*
1933 * MSI message composition
1934 */
1935 #ifdef CONFIG_PCI_MSI
1936 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1937 {
1938 struct irq_cfg *cfg = irq_cfg + irq;
1939 int err;
1940 unsigned dest;
1941 cpumask_t tmp;
1942
1943 tmp = TARGET_CPUS;
1944 err = assign_irq_vector(irq, tmp);
1945 if (!err) {
1946 cpus_and(tmp, cfg->domain, tmp);
1947 dest = cpu_mask_to_apicid(tmp);
1948
1949 msg->address_hi = MSI_ADDR_BASE_HI;
1950 msg->address_lo =
1951 MSI_ADDR_BASE_LO |
1952 ((INT_DEST_MODE == 0) ?
1953 MSI_ADDR_DEST_MODE_PHYSICAL:
1954 MSI_ADDR_DEST_MODE_LOGICAL) |
1955 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1956 MSI_ADDR_REDIRECTION_CPU:
1957 MSI_ADDR_REDIRECTION_LOWPRI) |
1958 MSI_ADDR_DEST_ID(dest);
1959
1960 msg->data =
1961 MSI_DATA_TRIGGER_EDGE |
1962 MSI_DATA_LEVEL_ASSERT |
1963 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1964 MSI_DATA_DELIVERY_FIXED:
1965 MSI_DATA_DELIVERY_LOWPRI) |
1966 MSI_DATA_VECTOR(cfg->vector);
1967 }
1968 return err;
1969 }
1970
1971 #ifdef CONFIG_SMP
1972 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1973 {
1974 struct irq_cfg *cfg = irq_cfg + irq;
1975 struct msi_msg msg;
1976 unsigned int dest;
1977 cpumask_t tmp;
1978
1979 cpus_and(tmp, mask, cpu_online_map);
1980 if (cpus_empty(tmp))
1981 return;
1982
1983 if (assign_irq_vector(irq, mask))
1984 return;
1985
1986 cpus_and(tmp, cfg->domain, mask);
1987 dest = cpu_mask_to_apicid(tmp);
1988
1989 read_msi_msg(irq, &msg);
1990
1991 msg.data &= ~MSI_DATA_VECTOR_MASK;
1992 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1993 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1994 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1995
1996 write_msi_msg(irq, &msg);
1997 irq_desc[irq].affinity = mask;
1998 }
1999 #endif /* CONFIG_SMP */
2000
2001 /*
2002 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2003 * which implement the MSI or MSI-X Capability Structure.
2004 */
2005 static struct irq_chip msi_chip = {
2006 .name = "PCI-MSI",
2007 .unmask = unmask_msi_irq,
2008 .mask = mask_msi_irq,
2009 .ack = ack_apic_edge,
2010 #ifdef CONFIG_SMP
2011 .set_affinity = set_msi_irq_affinity,
2012 #endif
2013 .retrigger = ioapic_retrigger_irq,
2014 };
2015
2016 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2017 {
2018 struct msi_msg msg;
2019 int irq, ret;
2020 irq = create_irq();
2021 if (irq < 0)
2022 return irq;
2023
2024 ret = msi_compose_msg(dev, irq, &msg);
2025 if (ret < 0) {
2026 destroy_irq(irq);
2027 return ret;
2028 }
2029
2030 set_irq_msi(irq, desc);
2031 write_msi_msg(irq, &msg);
2032
2033 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2034
2035 return 0;
2036 }
2037
2038 void arch_teardown_msi_irq(unsigned int irq)
2039 {
2040 destroy_irq(irq);
2041 }
2042
2043 #ifdef CONFIG_DMAR
2044 #ifdef CONFIG_SMP
2045 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2046 {
2047 struct irq_cfg *cfg = irq_cfg + irq;
2048 struct msi_msg msg;
2049 unsigned int dest;
2050 cpumask_t tmp;
2051
2052 cpus_and(tmp, mask, cpu_online_map);
2053 if (cpus_empty(tmp))
2054 return;
2055
2056 if (assign_irq_vector(irq, mask))
2057 return;
2058
2059 cpus_and(tmp, cfg->domain, mask);
2060 dest = cpu_mask_to_apicid(tmp);
2061
2062 dmar_msi_read(irq, &msg);
2063
2064 msg.data &= ~MSI_DATA_VECTOR_MASK;
2065 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2066 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2067 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2068
2069 dmar_msi_write(irq, &msg);
2070 irq_desc[irq].affinity = mask;
2071 }
2072 #endif /* CONFIG_SMP */
2073
2074 struct irq_chip dmar_msi_type = {
2075 .name = "DMAR_MSI",
2076 .unmask = dmar_msi_unmask,
2077 .mask = dmar_msi_mask,
2078 .ack = ack_apic_edge,
2079 #ifdef CONFIG_SMP
2080 .set_affinity = dmar_msi_set_affinity,
2081 #endif
2082 .retrigger = ioapic_retrigger_irq,
2083 };
2084
2085 int arch_setup_dmar_msi(unsigned int irq)
2086 {
2087 int ret;
2088 struct msi_msg msg;
2089
2090 ret = msi_compose_msg(NULL, irq, &msg);
2091 if (ret < 0)
2092 return ret;
2093 dmar_msi_write(irq, &msg);
2094 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2095 "edge");
2096 return 0;
2097 }
2098 #endif
2099
2100 #endif /* CONFIG_PCI_MSI */
2101 /*
2102 * Hypertransport interrupt support
2103 */
2104 #ifdef CONFIG_HT_IRQ
2105
2106 #ifdef CONFIG_SMP
2107
2108 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2109 {
2110 struct ht_irq_msg msg;
2111 fetch_ht_irq_msg(irq, &msg);
2112
2113 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2114 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2115
2116 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2117 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2118
2119 write_ht_irq_msg(irq, &msg);
2120 }
2121
2122 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2123 {
2124 struct irq_cfg *cfg = irq_cfg + irq;
2125 unsigned int dest;
2126 cpumask_t tmp;
2127
2128 cpus_and(tmp, mask, cpu_online_map);
2129 if (cpus_empty(tmp))
2130 return;
2131
2132 if (assign_irq_vector(irq, mask))
2133 return;
2134
2135 cpus_and(tmp, cfg->domain, mask);
2136 dest = cpu_mask_to_apicid(tmp);
2137
2138 target_ht_irq(irq, dest, cfg->vector);
2139 irq_desc[irq].affinity = mask;
2140 }
2141 #endif
2142
2143 static struct irq_chip ht_irq_chip = {
2144 .name = "PCI-HT",
2145 .mask = mask_ht_irq,
2146 .unmask = unmask_ht_irq,
2147 .ack = ack_apic_edge,
2148 #ifdef CONFIG_SMP
2149 .set_affinity = set_ht_irq_affinity,
2150 #endif
2151 .retrigger = ioapic_retrigger_irq,
2152 };
2153
2154 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2155 {
2156 struct irq_cfg *cfg = irq_cfg + irq;
2157 int err;
2158 cpumask_t tmp;
2159
2160 tmp = TARGET_CPUS;
2161 err = assign_irq_vector(irq, tmp);
2162 if (!err) {
2163 struct ht_irq_msg msg;
2164 unsigned dest;
2165
2166 cpus_and(tmp, cfg->domain, tmp);
2167 dest = cpu_mask_to_apicid(tmp);
2168
2169 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2170
2171 msg.address_lo =
2172 HT_IRQ_LOW_BASE |
2173 HT_IRQ_LOW_DEST_ID(dest) |
2174 HT_IRQ_LOW_VECTOR(cfg->vector) |
2175 ((INT_DEST_MODE == 0) ?
2176 HT_IRQ_LOW_DM_PHYSICAL :
2177 HT_IRQ_LOW_DM_LOGICAL) |
2178 HT_IRQ_LOW_RQEOI_EDGE |
2179 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2180 HT_IRQ_LOW_MT_FIXED :
2181 HT_IRQ_LOW_MT_ARBITRATED) |
2182 HT_IRQ_LOW_IRQ_MASKED;
2183
2184 write_ht_irq_msg(irq, &msg);
2185
2186 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2187 handle_edge_irq, "edge");
2188 }
2189 return err;
2190 }
2191 #endif /* CONFIG_HT_IRQ */
2192
2193 /* --------------------------------------------------------------------------
2194 ACPI-based IOAPIC Configuration
2195 -------------------------------------------------------------------------- */
2196
2197 #ifdef CONFIG_ACPI
2198
2199 #define IO_APIC_MAX_ID 0xFE
2200
2201 int __init io_apic_get_redir_entries (int ioapic)
2202 {
2203 union IO_APIC_reg_01 reg_01;
2204 unsigned long flags;
2205
2206 spin_lock_irqsave(&ioapic_lock, flags);
2207 reg_01.raw = io_apic_read(ioapic, 1);
2208 spin_unlock_irqrestore(&ioapic_lock, flags);
2209
2210 return reg_01.bits.entries;
2211 }
2212
2213
2214 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2215 {
2216 if (!IO_APIC_IRQ(irq)) {
2217 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2218 ioapic);
2219 return -EINVAL;
2220 }
2221
2222 /*
2223 * IRQs < 16 are already in the irq_2_pin[] map
2224 */
2225 if (irq >= 16)
2226 add_pin_to_irq(irq, ioapic, pin);
2227
2228 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2229
2230 return 0;
2231 }
2232
2233
2234 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2235 {
2236 int i;
2237
2238 if (skip_ioapic_setup)
2239 return -1;
2240
2241 for (i = 0; i < mp_irq_entries; i++)
2242 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2243 mp_irqs[i].mpc_srcbusirq == bus_irq)
2244 break;
2245 if (i >= mp_irq_entries)
2246 return -1;
2247
2248 *trigger = irq_trigger(i);
2249 *polarity = irq_polarity(i);
2250 return 0;
2251 }
2252
2253 #endif /* CONFIG_ACPI */
2254
2255 /*
2256 * This function currently is only a helper for the i386 smp boot process where
2257 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2258 * so mask in all cases should simply be TARGET_CPUS
2259 */
2260 #ifdef CONFIG_SMP
2261 void __init setup_ioapic_dest(void)
2262 {
2263 int pin, ioapic, irq, irq_entry;
2264
2265 if (skip_ioapic_setup == 1)
2266 return;
2267
2268 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2269 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2270 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2271 if (irq_entry == -1)
2272 continue;
2273 irq = pin_2_irq(irq_entry, ioapic, pin);
2274
2275 /* setup_IO_APIC_irqs could fail to get vector for some device
2276 * when you have too many devices, because at that time only boot
2277 * cpu is online.
2278 */
2279 if (!irq_cfg[irq].vector)
2280 setup_IO_APIC_irq(ioapic, pin, irq,
2281 irq_trigger(irq_entry),
2282 irq_polarity(irq_entry));
2283 else
2284 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2285 }
2286
2287 }
2288 }
2289 #endif
2290
Linux kernel - Deliverables
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