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[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
41
42 #include <asm/idle.h>
43 #include <asm/io.h>
44 #include <asm/smp.h>
45 #include <asm/desc.h>
46 #include <asm/proto.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/i8259.h>
50 #include <asm/nmi.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
54
55 #include <mach_ipi.h>
56 #include <mach_apic.h>
57
58 #define __apicdebuginit(type) static type __init
59
60 struct irq_cfg;
61 struct irq_pin_list;
62 struct irq_cfg {
63 unsigned int irq;
64 struct irq_cfg *next;
65 struct irq_pin_list *irq_2_pin;
66 cpumask_t domain;
67 cpumask_t old_domain;
68 unsigned move_cleanup_count;
69 u8 vector;
70 u8 move_in_progress : 1;
71 };
72
73 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
74 static struct irq_cfg irq_cfg_legacy[] __initdata = {
75 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
76 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
77 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
78 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
79 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
80 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
81 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
82 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
83 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
84 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
85 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
86 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
87 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
88 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
89 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
90 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
91 };
92
93 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
94 /* need to be biger than size of irq_cfg_legacy */
95 static int nr_irq_cfg = 32;
96
97 static int __init parse_nr_irq_cfg(char *arg)
98 {
99 if (arg) {
100 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
101 if (nr_irq_cfg < 32)
102 nr_irq_cfg = 32;
103 }
104 return 0;
105 }
106
107 early_param("nr_irq_cfg", parse_nr_irq_cfg);
108
109 static void init_one_irq_cfg(struct irq_cfg *cfg)
110 {
111 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
112 }
113
114 static struct irq_cfg *irq_cfgx;
115 static struct irq_cfg *irq_cfgx_free;
116 static void __init init_work(void *data)
117 {
118 struct dyn_array *da = data;
119 struct irq_cfg *cfg;
120 int legacy_count;
121 int i;
122
123 cfg = *da->name;
124
125 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
126
127 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
128 for (i = legacy_count; i < *da->nr; i++)
129 init_one_irq_cfg(&cfg[i]);
130
131 for (i = 1; i < *da->nr; i++)
132 cfg[i-1].next = &cfg[i];
133
134 irq_cfgx_free = &irq_cfgx[legacy_count];
135 irq_cfgx[legacy_count - 1].next = NULL;
136 }
137
138 #define for_each_irq_cfg(cfg) \
139 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
140
141 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
142
143 static struct irq_cfg *irq_cfg(unsigned int irq)
144 {
145 struct irq_cfg *cfg;
146
147 cfg = irq_cfgx;
148 while (cfg) {
149 if (cfg->irq == irq)
150 return cfg;
151
152 cfg = cfg->next;
153 }
154
155 return NULL;
156 }
157
158 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
159 {
160 struct irq_cfg *cfg, *cfg_pri;
161 int i;
162 int count = 0;
163
164 cfg_pri = cfg = irq_cfgx;
165 while (cfg) {
166 if (cfg->irq == irq)
167 return cfg;
168
169 cfg_pri = cfg;
170 cfg = cfg->next;
171 count++;
172 }
173
174 if (!irq_cfgx_free) {
175 unsigned long phys;
176 unsigned long total_bytes;
177 /*
178 * we run out of pre-allocate ones, allocate more
179 */
180 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
181
182 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
183 if (after_bootmem)
184 cfg = kzalloc(total_bytes, GFP_ATOMIC);
185 else
186 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
187
188 if (!cfg)
189 panic("please boot with nr_irq_cfg= %d\n", count * 2);
190
191 phys = __pa(cfg);
192 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
193
194 for (i = 0; i < nr_irq_cfg; i++)
195 init_one_irq_cfg(&cfg[i]);
196
197 for (i = 1; i < nr_irq_cfg; i++)
198 cfg[i-1].next = &cfg[i];
199
200 irq_cfgx_free = cfg;
201 }
202
203 cfg = irq_cfgx_free;
204 irq_cfgx_free = irq_cfgx_free->next;
205 cfg->next = NULL;
206 if (cfg_pri)
207 cfg_pri->next = cfg;
208 else
209 irq_cfgx = cfg;
210 cfg->irq = irq;
211 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
212 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
213 {
214 /* dump the results */
215 struct irq_cfg *cfg;
216 unsigned long phys;
217 unsigned long bytes = sizeof(struct irq_cfg);
218
219 printk(KERN_DEBUG "=========================== %d\n", irq);
220 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
221 for_each_irq_cfg(cfg) {
222 phys = __pa(cfg);
223 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
224 }
225 printk(KERN_DEBUG "===========================\n");
226 }
227 #endif
228 return cfg;
229 }
230
231 static int assign_irq_vector(int irq, cpumask_t mask);
232
233 int first_system_vector = 0xfe;
234
235 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
236
237 int sis_apic_bug; /* not actually supported, dummy for compile */
238
239 static int no_timer_check;
240
241 static int disable_timer_pin_1 __initdata;
242
243 int timer_through_8259 __initdata;
244
245 /* Where if anywhere is the i8259 connect in external int mode */
246 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
247
248 static DEFINE_SPINLOCK(ioapic_lock);
249 static DEFINE_SPINLOCK(vector_lock);
250
251 /*
252 * # of IRQ routing registers
253 */
254 int nr_ioapic_registers[MAX_IO_APICS];
255
256 /* I/O APIC RTE contents at the OS boot up */
257 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
258
259 /* I/O APIC entries */
260 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
261 int nr_ioapics;
262
263 /* MP IRQ source entries */
264 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
265
266 /* # of MP IRQ source entries */
267 int mp_irq_entries;
268
269 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
270
271 /*
272 * Rough estimation of how many shared IRQs there are, can
273 * be changed anytime.
274 */
275
276 int pin_map_size;
277
278 /*
279 * This is performance-critical, we want to do it O(1)
280 *
281 * the indexing order of this array favors 1:1 mappings
282 * between pins and IRQs.
283 */
284
285 struct irq_pin_list {
286 int apic, pin;
287 struct irq_pin_list *next;
288 };
289
290 static struct irq_pin_list *irq_2_pin_head;
291 /* fill one page ? */
292 static int nr_irq_2_pin = 0x100;
293 static struct irq_pin_list *irq_2_pin_ptr;
294 static void __init irq_2_pin_init_work(void *data)
295 {
296 struct dyn_array *da = data;
297 struct irq_pin_list *pin;
298 int i;
299
300 pin = *da->name;
301
302 for (i = 1; i < *da->nr; i++)
303 pin[i-1].next = &pin[i];
304
305 irq_2_pin_ptr = &pin[0];
306 }
307 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
308
309 static struct irq_pin_list *get_one_free_irq_2_pin(void)
310 {
311 struct irq_pin_list *pin;
312 int i;
313
314 pin = irq_2_pin_ptr;
315
316 if (pin) {
317 irq_2_pin_ptr = pin->next;
318 pin->next = NULL;
319 return pin;
320 }
321
322 /*
323 * we run out of pre-allocate ones, allocate more
324 */
325 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
326
327 if (after_bootmem)
328 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
329 GFP_ATOMIC);
330 else
331 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
332 nr_irq_2_pin, PAGE_SIZE, 0);
333
334 if (!pin)
335 panic("can not get more irq_2_pin\n");
336
337 for (i = 1; i < nr_irq_2_pin; i++)
338 pin[i-1].next = &pin[i];
339
340 irq_2_pin_ptr = pin->next;
341 pin->next = NULL;
342
343 return pin;
344 }
345
346 struct io_apic {
347 unsigned int index;
348 unsigned int unused[3];
349 unsigned int data;
350 };
351
352 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
353 {
354 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
355 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
356 }
357
358 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
359 {
360 struct io_apic __iomem *io_apic = io_apic_base(apic);
361 writel(reg, &io_apic->index);
362 return readl(&io_apic->data);
363 }
364
365 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
366 {
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 writel(value, &io_apic->data);
370 }
371
372 /*
373 * Re-write a value: to be used for read-modify-write
374 * cycles where the read already set up the index register.
375 */
376 static inline void io_apic_modify(unsigned int apic, unsigned int value)
377 {
378 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(value, &io_apic->data);
380 }
381
382 static bool io_apic_level_ack_pending(unsigned int irq)
383 {
384 struct irq_pin_list *entry;
385 unsigned long flags;
386 struct irq_cfg *cfg = irq_cfg(irq);
387
388 spin_lock_irqsave(&ioapic_lock, flags);
389 entry = cfg->irq_2_pin;
390 for (;;) {
391 unsigned int reg;
392 int pin;
393
394 if (!entry)
395 break;
396 pin = entry->pin;
397 reg = io_apic_read(entry->apic, 0x10 + pin*2);
398 /* Is the remote IRR bit set? */
399 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
400 spin_unlock_irqrestore(&ioapic_lock, flags);
401 return true;
402 }
403 if (!entry->next)
404 break;
405 entry = entry->next;
406 }
407 spin_unlock_irqrestore(&ioapic_lock, flags);
408
409 return false;
410 }
411
412 /*
413 * Synchronize the IO-APIC and the CPU by doing
414 * a dummy read from the IO-APIC
415 */
416 static inline void io_apic_sync(unsigned int apic)
417 {
418 struct io_apic __iomem *io_apic = io_apic_base(apic);
419 readl(&io_apic->data);
420 }
421
422 #define __DO_ACTION(R, ACTION, FINAL) \
423 \
424 { \
425 int pin; \
426 struct irq_cfg *cfg; \
427 struct irq_pin_list *entry; \
428 \
429 cfg = irq_cfg(irq); \
430 entry = cfg->irq_2_pin; \
431 for (;;) { \
432 unsigned int reg; \
433 if (!entry) \
434 break; \
435 pin = entry->pin; \
436 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
437 reg ACTION; \
438 io_apic_modify(entry->apic, reg); \
439 FINAL; \
440 if (!entry->next) \
441 break; \
442 entry = entry->next; \
443 } \
444 }
445
446 union entry_union {
447 struct { u32 w1, w2; };
448 struct IO_APIC_route_entry entry;
449 };
450
451 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
452 {
453 union entry_union eu;
454 unsigned long flags;
455 spin_lock_irqsave(&ioapic_lock, flags);
456 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
457 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
458 spin_unlock_irqrestore(&ioapic_lock, flags);
459 return eu.entry;
460 }
461
462 /*
463 * When we write a new IO APIC routing entry, we need to write the high
464 * word first! If the mask bit in the low word is clear, we will enable
465 * the interrupt, and we need to make sure the entry is fully populated
466 * before that happens.
467 */
468 static void
469 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
470 {
471 union entry_union eu;
472 eu.entry = e;
473 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
474 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
475 }
476
477 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
478 {
479 unsigned long flags;
480 spin_lock_irqsave(&ioapic_lock, flags);
481 __ioapic_write_entry(apic, pin, e);
482 spin_unlock_irqrestore(&ioapic_lock, flags);
483 }
484
485 /*
486 * When we mask an IO APIC routing entry, we need to write the low
487 * word first, in order to set the mask bit before we change the
488 * high bits!
489 */
490 static void ioapic_mask_entry(int apic, int pin)
491 {
492 unsigned long flags;
493 union entry_union eu = { .entry.mask = 1 };
494
495 spin_lock_irqsave(&ioapic_lock, flags);
496 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
497 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
498 spin_unlock_irqrestore(&ioapic_lock, flags);
499 }
500
501 #ifdef CONFIG_SMP
502 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
503 {
504 int apic, pin;
505 struct irq_cfg *cfg;
506 struct irq_pin_list *entry;
507
508 cfg = irq_cfg(irq);
509 entry = cfg->irq_2_pin;
510 for (;;) {
511 unsigned int reg;
512
513 if (!entry)
514 break;
515
516 apic = entry->apic;
517 pin = entry->pin;
518 /*
519 * With interrupt-remapping, destination information comes
520 * from interrupt-remapping table entry.
521 */
522 if (!irq_remapped(irq))
523 io_apic_write(apic, 0x11 + pin*2, dest);
524 reg = io_apic_read(apic, 0x10 + pin*2);
525 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
526 reg |= vector;
527 io_apic_modify(apic, reg);
528 if (!entry->next)
529 break;
530 entry = entry->next;
531 }
532 }
533
534 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
535 {
536 struct irq_cfg *cfg = irq_cfg(irq);
537 unsigned long flags;
538 unsigned int dest;
539 cpumask_t tmp;
540 struct irq_desc *desc;
541
542 cpus_and(tmp, mask, cpu_online_map);
543 if (cpus_empty(tmp))
544 return;
545
546 if (assign_irq_vector(irq, mask))
547 return;
548
549 cpus_and(tmp, cfg->domain, mask);
550 dest = cpu_mask_to_apicid(tmp);
551
552 /*
553 * Only the high 8 bits are valid.
554 */
555 dest = SET_APIC_LOGICAL_ID(dest);
556
557 desc = irq_to_desc(irq);
558 spin_lock_irqsave(&ioapic_lock, flags);
559 __target_IO_APIC_irq(irq, dest, cfg->vector);
560 desc->affinity = mask;
561 spin_unlock_irqrestore(&ioapic_lock, flags);
562 }
563 #endif
564
565 /*
566 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
567 * shared ISA-space IRQs, so we have to support them. We are super
568 * fast in the common case, and fast for shared ISA-space IRQs.
569 */
570 int first_free_entry;
571 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
572 {
573 struct irq_cfg *cfg;
574 struct irq_pin_list *entry;
575
576 /* first time to refer irq_cfg, so with new */
577 cfg = irq_cfg_alloc(irq);
578 entry = cfg->irq_2_pin;
579 if (!entry) {
580 entry = get_one_free_irq_2_pin();
581 cfg->irq_2_pin = entry;
582 entry->apic = apic;
583 entry->pin = pin;
584 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
585 return;
586 }
587
588 while (entry->next) {
589 /* not again, please */
590 if (entry->apic == apic && entry->pin == pin)
591 return;
592
593 entry = entry->next;
594 }
595
596 entry->next = get_one_free_irq_2_pin();
597 entry = entry->next;
598 entry->apic = apic;
599 entry->pin = pin;
600 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
601 }
602
603 /*
604 * Reroute an IRQ to a different pin.
605 */
606 static void __init replace_pin_at_irq(unsigned int irq,
607 int oldapic, int oldpin,
608 int newapic, int newpin)
609 {
610 struct irq_cfg *cfg = irq_cfg(irq);
611 struct irq_pin_list *entry = cfg->irq_2_pin;
612 int replaced = 0;
613
614 while (entry) {
615 if (entry->apic == oldapic && entry->pin == oldpin) {
616 entry->apic = newapic;
617 entry->pin = newpin;
618 replaced = 1;
619 /* every one is different, right? */
620 break;
621 }
622 entry = entry->next;
623 }
624
625 /* why? call replace before add? */
626 if (!replaced)
627 add_pin_to_irq(irq, newapic, newpin);
628 }
629
630
631 #define DO_ACTION(name,R,ACTION, FINAL) \
632 \
633 static void name##_IO_APIC_irq (unsigned int irq) \
634 __DO_ACTION(R, ACTION, FINAL)
635
636 /* mask = 1 */
637 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
638
639 /* mask = 0 */
640 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
641
642 static void mask_IO_APIC_irq (unsigned int irq)
643 {
644 unsigned long flags;
645
646 spin_lock_irqsave(&ioapic_lock, flags);
647 __mask_IO_APIC_irq(irq);
648 spin_unlock_irqrestore(&ioapic_lock, flags);
649 }
650
651 static void unmask_IO_APIC_irq (unsigned int irq)
652 {
653 unsigned long flags;
654
655 spin_lock_irqsave(&ioapic_lock, flags);
656 __unmask_IO_APIC_irq(irq);
657 spin_unlock_irqrestore(&ioapic_lock, flags);
658 }
659
660 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
661 {
662 struct IO_APIC_route_entry entry;
663
664 /* Check delivery_mode to be sure we're not clearing an SMI pin */
665 entry = ioapic_read_entry(apic, pin);
666 if (entry.delivery_mode == dest_SMI)
667 return;
668 /*
669 * Disable it in the IO-APIC irq-routing table:
670 */
671 ioapic_mask_entry(apic, pin);
672 }
673
674 static void clear_IO_APIC (void)
675 {
676 int apic, pin;
677
678 for (apic = 0; apic < nr_ioapics; apic++)
679 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
680 clear_IO_APIC_pin(apic, pin);
681 }
682
683 /*
684 * Saves and masks all the unmasked IO-APIC RTE's
685 */
686 int save_mask_IO_APIC_setup(void)
687 {
688 union IO_APIC_reg_01 reg_01;
689 unsigned long flags;
690 int apic, pin;
691
692 /*
693 * The number of IO-APIC IRQ registers (== #pins):
694 */
695 for (apic = 0; apic < nr_ioapics; apic++) {
696 spin_lock_irqsave(&ioapic_lock, flags);
697 reg_01.raw = io_apic_read(apic, 1);
698 spin_unlock_irqrestore(&ioapic_lock, flags);
699 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
700 }
701
702 for (apic = 0; apic < nr_ioapics; apic++) {
703 early_ioapic_entries[apic] =
704 kzalloc(sizeof(struct IO_APIC_route_entry) *
705 nr_ioapic_registers[apic], GFP_KERNEL);
706 if (!early_ioapic_entries[apic])
707 return -ENOMEM;
708 }
709
710 for (apic = 0; apic < nr_ioapics; apic++)
711 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
712 struct IO_APIC_route_entry entry;
713
714 entry = early_ioapic_entries[apic][pin] =
715 ioapic_read_entry(apic, pin);
716 if (!entry.mask) {
717 entry.mask = 1;
718 ioapic_write_entry(apic, pin, entry);
719 }
720 }
721 return 0;
722 }
723
724 void restore_IO_APIC_setup(void)
725 {
726 int apic, pin;
727
728 for (apic = 0; apic < nr_ioapics; apic++)
729 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
730 ioapic_write_entry(apic, pin,
731 early_ioapic_entries[apic][pin]);
732 }
733
734 void reinit_intr_remapped_IO_APIC(int intr_remapping)
735 {
736 /*
737 * for now plain restore of previous settings.
738 * TBD: In the case of OS enabling interrupt-remapping,
739 * IO-APIC RTE's need to be setup to point to interrupt-remapping
740 * table entries. for now, do a plain restore, and wait for
741 * the setup_IO_APIC_irqs() to do proper initialization.
742 */
743 restore_IO_APIC_setup();
744 }
745
746 int skip_ioapic_setup;
747 int ioapic_force;
748
749 static int __init parse_noapic(char *str)
750 {
751 disable_ioapic_setup();
752 return 0;
753 }
754 early_param("noapic", parse_noapic);
755
756 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
757 static int __init disable_timer_pin_setup(char *arg)
758 {
759 disable_timer_pin_1 = 1;
760 return 1;
761 }
762 __setup("disable_timer_pin_1", disable_timer_pin_setup);
763
764
765 /*
766 * Find the IRQ entry number of a certain pin.
767 */
768 static int find_irq_entry(int apic, int pin, int type)
769 {
770 int i;
771
772 for (i = 0; i < mp_irq_entries; i++)
773 if (mp_irqs[i].mp_irqtype == type &&
774 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
775 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
776 mp_irqs[i].mp_dstirq == pin)
777 return i;
778
779 return -1;
780 }
781
782 /*
783 * Find the pin to which IRQ[irq] (ISA) is connected
784 */
785 static int __init find_isa_irq_pin(int irq, int type)
786 {
787 int i;
788
789 for (i = 0; i < mp_irq_entries; i++) {
790 int lbus = mp_irqs[i].mp_srcbus;
791
792 if (test_bit(lbus, mp_bus_not_pci) &&
793 (mp_irqs[i].mp_irqtype == type) &&
794 (mp_irqs[i].mp_srcbusirq == irq))
795
796 return mp_irqs[i].mp_dstirq;
797 }
798 return -1;
799 }
800
801 static int __init find_isa_irq_apic(int irq, int type)
802 {
803 int i;
804
805 for (i = 0; i < mp_irq_entries; i++) {
806 int lbus = mp_irqs[i].mp_srcbus;
807
808 if (test_bit(lbus, mp_bus_not_pci) &&
809 (mp_irqs[i].mp_irqtype == type) &&
810 (mp_irqs[i].mp_srcbusirq == irq))
811 break;
812 }
813 if (i < mp_irq_entries) {
814 int apic;
815 for(apic = 0; apic < nr_ioapics; apic++) {
816 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
817 return apic;
818 }
819 }
820
821 return -1;
822 }
823
824 /*
825 * Find a specific PCI IRQ entry.
826 * Not an __init, possibly needed by modules
827 */
828 static int pin_2_irq(int idx, int apic, int pin);
829
830 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
831 {
832 int apic, i, best_guess = -1;
833
834 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
835 bus, slot, pin);
836 if (test_bit(bus, mp_bus_not_pci)) {
837 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
838 return -1;
839 }
840 for (i = 0; i < mp_irq_entries; i++) {
841 int lbus = mp_irqs[i].mp_srcbus;
842
843 for (apic = 0; apic < nr_ioapics; apic++)
844 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
845 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
846 break;
847
848 if (!test_bit(lbus, mp_bus_not_pci) &&
849 !mp_irqs[i].mp_irqtype &&
850 (bus == lbus) &&
851 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
852 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
853
854 if (!(apic || IO_APIC_IRQ(irq)))
855 continue;
856
857 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
858 return irq;
859 /*
860 * Use the first all-but-pin matching entry as a
861 * best-guess fuzzy result for broken mptables.
862 */
863 if (best_guess < 0)
864 best_guess = irq;
865 }
866 }
867 return best_guess;
868 }
869
870 /* ISA interrupts are always polarity zero edge triggered,
871 * when listed as conforming in the MP table. */
872
873 #define default_ISA_trigger(idx) (0)
874 #define default_ISA_polarity(idx) (0)
875
876 /* PCI interrupts are always polarity one level triggered,
877 * when listed as conforming in the MP table. */
878
879 #define default_PCI_trigger(idx) (1)
880 #define default_PCI_polarity(idx) (1)
881
882 static int MPBIOS_polarity(int idx)
883 {
884 int bus = mp_irqs[idx].mp_srcbus;
885 int polarity;
886
887 /*
888 * Determine IRQ line polarity (high active or low active):
889 */
890 switch (mp_irqs[idx].mp_irqflag & 3)
891 {
892 case 0: /* conforms, ie. bus-type dependent polarity */
893 if (test_bit(bus, mp_bus_not_pci))
894 polarity = default_ISA_polarity(idx);
895 else
896 polarity = default_PCI_polarity(idx);
897 break;
898 case 1: /* high active */
899 {
900 polarity = 0;
901 break;
902 }
903 case 2: /* reserved */
904 {
905 printk(KERN_WARNING "broken BIOS!!\n");
906 polarity = 1;
907 break;
908 }
909 case 3: /* low active */
910 {
911 polarity = 1;
912 break;
913 }
914 default: /* invalid */
915 {
916 printk(KERN_WARNING "broken BIOS!!\n");
917 polarity = 1;
918 break;
919 }
920 }
921 return polarity;
922 }
923
924 static int MPBIOS_trigger(int idx)
925 {
926 int bus = mp_irqs[idx].mp_srcbus;
927 int trigger;
928
929 /*
930 * Determine IRQ trigger mode (edge or level sensitive):
931 */
932 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
933 {
934 case 0: /* conforms, ie. bus-type dependent */
935 if (test_bit(bus, mp_bus_not_pci))
936 trigger = default_ISA_trigger(idx);
937 else
938 trigger = default_PCI_trigger(idx);
939 break;
940 case 1: /* edge */
941 {
942 trigger = 0;
943 break;
944 }
945 case 2: /* reserved */
946 {
947 printk(KERN_WARNING "broken BIOS!!\n");
948 trigger = 1;
949 break;
950 }
951 case 3: /* level */
952 {
953 trigger = 1;
954 break;
955 }
956 default: /* invalid */
957 {
958 printk(KERN_WARNING "broken BIOS!!\n");
959 trigger = 0;
960 break;
961 }
962 }
963 return trigger;
964 }
965
966 static inline int irq_polarity(int idx)
967 {
968 return MPBIOS_polarity(idx);
969 }
970
971 static inline int irq_trigger(int idx)
972 {
973 return MPBIOS_trigger(idx);
974 }
975
976 static int pin_2_irq(int idx, int apic, int pin)
977 {
978 int irq, i;
979 int bus = mp_irqs[idx].mp_srcbus;
980
981 /*
982 * Debugging check, we are in big trouble if this message pops up!
983 */
984 if (mp_irqs[idx].mp_dstirq != pin)
985 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
986
987 if (test_bit(bus, mp_bus_not_pci)) {
988 irq = mp_irqs[idx].mp_srcbusirq;
989 } else {
990 /*
991 * PCI IRQs are mapped in order
992 */
993 i = irq = 0;
994 while (i < apic)
995 irq += nr_ioapic_registers[i++];
996 irq += pin;
997 }
998 return irq;
999 }
1000
1001 void lock_vector_lock(void)
1002 {
1003 /* Used to the online set of cpus does not change
1004 * during assign_irq_vector.
1005 */
1006 spin_lock(&vector_lock);
1007 }
1008
1009 void unlock_vector_lock(void)
1010 {
1011 spin_unlock(&vector_lock);
1012 }
1013
1014 static int __assign_irq_vector(int irq, cpumask_t mask)
1015 {
1016 /*
1017 * NOTE! The local APIC isn't very good at handling
1018 * multiple interrupts at the same interrupt level.
1019 * As the interrupt level is determined by taking the
1020 * vector number and shifting that right by 4, we
1021 * want to spread these out a bit so that they don't
1022 * all fall in the same interrupt level.
1023 *
1024 * Also, we've got to be careful not to trash gate
1025 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1026 */
1027 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1028 unsigned int old_vector;
1029 int cpu;
1030 struct irq_cfg *cfg;
1031
1032 cfg = irq_cfg(irq);
1033
1034 /* Only try and allocate irqs on cpus that are present */
1035 cpus_and(mask, mask, cpu_online_map);
1036
1037 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1038 return -EBUSY;
1039
1040 old_vector = cfg->vector;
1041 if (old_vector) {
1042 cpumask_t tmp;
1043 cpus_and(tmp, cfg->domain, mask);
1044 if (!cpus_empty(tmp))
1045 return 0;
1046 }
1047
1048 for_each_cpu_mask_nr(cpu, mask) {
1049 cpumask_t domain, new_mask;
1050 int new_cpu;
1051 int vector, offset;
1052
1053 domain = vector_allocation_domain(cpu);
1054 cpus_and(new_mask, domain, cpu_online_map);
1055
1056 vector = current_vector;
1057 offset = current_offset;
1058 next:
1059 vector += 8;
1060 if (vector >= first_system_vector) {
1061 /* If we run out of vectors on large boxen, must share them. */
1062 offset = (offset + 1) % 8;
1063 vector = FIRST_DEVICE_VECTOR + offset;
1064 }
1065 if (unlikely(current_vector == vector))
1066 continue;
1067 if (vector == IA32_SYSCALL_VECTOR)
1068 goto next;
1069 for_each_cpu_mask_nr(new_cpu, new_mask)
1070 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1071 goto next;
1072 /* Found one! */
1073 current_vector = vector;
1074 current_offset = offset;
1075 if (old_vector) {
1076 cfg->move_in_progress = 1;
1077 cfg->old_domain = cfg->domain;
1078 }
1079 for_each_cpu_mask_nr(new_cpu, new_mask)
1080 per_cpu(vector_irq, new_cpu)[vector] = irq;
1081 cfg->vector = vector;
1082 cfg->domain = domain;
1083 return 0;
1084 }
1085 return -ENOSPC;
1086 }
1087
1088 static int assign_irq_vector(int irq, cpumask_t mask)
1089 {
1090 int err;
1091 unsigned long flags;
1092
1093 spin_lock_irqsave(&vector_lock, flags);
1094 err = __assign_irq_vector(irq, mask);
1095 spin_unlock_irqrestore(&vector_lock, flags);
1096 return err;
1097 }
1098
1099 static void __clear_irq_vector(int irq)
1100 {
1101 struct irq_cfg *cfg;
1102 cpumask_t mask;
1103 int cpu, vector;
1104
1105 cfg = irq_cfg(irq);
1106 BUG_ON(!cfg->vector);
1107
1108 vector = cfg->vector;
1109 cpus_and(mask, cfg->domain, cpu_online_map);
1110 for_each_cpu_mask_nr(cpu, mask)
1111 per_cpu(vector_irq, cpu)[vector] = -1;
1112
1113 cfg->vector = 0;
1114 cpus_clear(cfg->domain);
1115 }
1116
1117 void __setup_vector_irq(int cpu)
1118 {
1119 /* Initialize vector_irq on a new cpu */
1120 /* This function must be called with vector_lock held */
1121 int irq, vector;
1122 struct irq_cfg *cfg;
1123
1124 /* Mark the inuse vectors */
1125 for_each_irq_cfg(cfg) {
1126 if (!cpu_isset(cpu, cfg->domain))
1127 continue;
1128 vector = cfg->vector;
1129 irq = cfg->irq;
1130 per_cpu(vector_irq, cpu)[vector] = irq;
1131 }
1132 /* Mark the free vectors */
1133 for (vector = 0; vector < NR_VECTORS; ++vector) {
1134 irq = per_cpu(vector_irq, cpu)[vector];
1135 if (irq < 0)
1136 continue;
1137
1138 cfg = irq_cfg(irq);
1139 if (!cpu_isset(cpu, cfg->domain))
1140 per_cpu(vector_irq, cpu)[vector] = -1;
1141 }
1142 }
1143
1144 static struct irq_chip ioapic_chip;
1145 #ifdef CONFIG_INTR_REMAP
1146 static struct irq_chip ir_ioapic_chip;
1147 #endif
1148
1149 static void ioapic_register_intr(int irq, unsigned long trigger)
1150 {
1151 struct irq_desc *desc;
1152
1153 /* first time to use this irq_desc */
1154 if (irq < 16)
1155 desc = irq_to_desc(irq);
1156 else
1157 desc = irq_to_desc_alloc(irq);
1158
1159 if (trigger)
1160 desc->status |= IRQ_LEVEL;
1161 else
1162 desc->status &= ~IRQ_LEVEL;
1163
1164 #ifdef CONFIG_INTR_REMAP
1165 if (irq_remapped(irq)) {
1166 desc->status |= IRQ_MOVE_PCNTXT;
1167 if (trigger)
1168 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1169 handle_fasteoi_irq,
1170 "fasteoi");
1171 else
1172 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1173 handle_edge_irq, "edge");
1174 return;
1175 }
1176 #endif
1177 if (trigger)
1178 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1179 handle_fasteoi_irq,
1180 "fasteoi");
1181 else
1182 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1183 handle_edge_irq, "edge");
1184 }
1185
1186 static int setup_ioapic_entry(int apic, int irq,
1187 struct IO_APIC_route_entry *entry,
1188 unsigned int destination, int trigger,
1189 int polarity, int vector)
1190 {
1191 /*
1192 * add it to the IO-APIC irq-routing table:
1193 */
1194 memset(entry,0,sizeof(*entry));
1195
1196 #ifdef CONFIG_INTR_REMAP
1197 if (intr_remapping_enabled) {
1198 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1199 struct irte irte;
1200 struct IR_IO_APIC_route_entry *ir_entry =
1201 (struct IR_IO_APIC_route_entry *) entry;
1202 int index;
1203
1204 if (!iommu)
1205 panic("No mapping iommu for ioapic %d\n", apic);
1206
1207 index = alloc_irte(iommu, irq, 1);
1208 if (index < 0)
1209 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1210
1211 memset(&irte, 0, sizeof(irte));
1212
1213 irte.present = 1;
1214 irte.dst_mode = INT_DEST_MODE;
1215 irte.trigger_mode = trigger;
1216 irte.dlvry_mode = INT_DELIVERY_MODE;
1217 irte.vector = vector;
1218 irte.dest_id = IRTE_DEST(destination);
1219
1220 modify_irte(irq, &irte);
1221
1222 ir_entry->index2 = (index >> 15) & 0x1;
1223 ir_entry->zero = 0;
1224 ir_entry->format = 1;
1225 ir_entry->index = (index & 0x7fff);
1226 } else
1227 #endif
1228 {
1229 entry->delivery_mode = INT_DELIVERY_MODE;
1230 entry->dest_mode = INT_DEST_MODE;
1231 entry->dest = destination;
1232 }
1233
1234 entry->mask = 0; /* enable IRQ */
1235 entry->trigger = trigger;
1236 entry->polarity = polarity;
1237 entry->vector = vector;
1238
1239 /* Mask level triggered irqs.
1240 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1241 */
1242 if (trigger)
1243 entry->mask = 1;
1244 return 0;
1245 }
1246
1247 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1248 int trigger, int polarity)
1249 {
1250 struct irq_cfg *cfg;
1251 struct IO_APIC_route_entry entry;
1252 cpumask_t mask;
1253
1254 if (!IO_APIC_IRQ(irq))
1255 return;
1256
1257 cfg = irq_cfg(irq);
1258
1259 mask = TARGET_CPUS;
1260 if (assign_irq_vector(irq, mask))
1261 return;
1262
1263 cpus_and(mask, cfg->domain, mask);
1264
1265 apic_printk(APIC_VERBOSE,KERN_DEBUG
1266 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1267 "IRQ %d Mode:%i Active:%i)\n",
1268 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1269 irq, trigger, polarity);
1270
1271
1272 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1273 cpu_mask_to_apicid(mask), trigger, polarity,
1274 cfg->vector)) {
1275 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1276 mp_ioapics[apic].mp_apicid, pin);
1277 __clear_irq_vector(irq);
1278 return;
1279 }
1280
1281 ioapic_register_intr(irq, trigger);
1282 if (irq < 16)
1283 disable_8259A_irq(irq);
1284
1285 ioapic_write_entry(apic, pin, entry);
1286 }
1287
1288 static void __init setup_IO_APIC_irqs(void)
1289 {
1290 int apic, pin, idx, irq, first_notcon = 1;
1291
1292 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1293
1294 for (apic = 0; apic < nr_ioapics; apic++) {
1295 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1296
1297 idx = find_irq_entry(apic,pin,mp_INT);
1298 if (idx == -1) {
1299 if (first_notcon) {
1300 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1301 first_notcon = 0;
1302 } else
1303 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1304 continue;
1305 }
1306 if (!first_notcon) {
1307 apic_printk(APIC_VERBOSE, " not connected.\n");
1308 first_notcon = 1;
1309 }
1310
1311 irq = pin_2_irq(idx, apic, pin);
1312 add_pin_to_irq(irq, apic, pin);
1313
1314 setup_IO_APIC_irq(apic, pin, irq,
1315 irq_trigger(idx), irq_polarity(idx));
1316 }
1317 }
1318
1319 if (!first_notcon)
1320 apic_printk(APIC_VERBOSE, " not connected.\n");
1321 }
1322
1323 /*
1324 * Set up the timer pin, possibly with the 8259A-master behind.
1325 */
1326 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1327 int vector)
1328 {
1329 struct IO_APIC_route_entry entry;
1330
1331 if (intr_remapping_enabled)
1332 return;
1333
1334 memset(&entry, 0, sizeof(entry));
1335
1336 /*
1337 * We use logical delivery to get the timer IRQ
1338 * to the first CPU.
1339 */
1340 entry.dest_mode = INT_DEST_MODE;
1341 entry.mask = 1; /* mask IRQ now */
1342 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1343 entry.delivery_mode = INT_DELIVERY_MODE;
1344 entry.polarity = 0;
1345 entry.trigger = 0;
1346 entry.vector = vector;
1347
1348 /*
1349 * The timer IRQ doesn't have to know that behind the
1350 * scene we may have a 8259A-master in AEOI mode ...
1351 */
1352 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1353
1354 /*
1355 * Add it to the IO-APIC irq-routing table:
1356 */
1357 ioapic_write_entry(apic, pin, entry);
1358 }
1359
1360
1361 __apicdebuginit(void) print_IO_APIC(void)
1362 {
1363 int apic, i;
1364 union IO_APIC_reg_00 reg_00;
1365 union IO_APIC_reg_01 reg_01;
1366 union IO_APIC_reg_02 reg_02;
1367 unsigned long flags;
1368 struct irq_cfg *cfg;
1369
1370 if (apic_verbosity == APIC_QUIET)
1371 return;
1372
1373 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1374 for (i = 0; i < nr_ioapics; i++)
1375 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1376 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1377
1378 /*
1379 * We are a bit conservative about what we expect. We have to
1380 * know about every hardware change ASAP.
1381 */
1382 printk(KERN_INFO "testing the IO APIC.......................\n");
1383
1384 for (apic = 0; apic < nr_ioapics; apic++) {
1385
1386 spin_lock_irqsave(&ioapic_lock, flags);
1387 reg_00.raw = io_apic_read(apic, 0);
1388 reg_01.raw = io_apic_read(apic, 1);
1389 if (reg_01.bits.version >= 0x10)
1390 reg_02.raw = io_apic_read(apic, 2);
1391 spin_unlock_irqrestore(&ioapic_lock, flags);
1392
1393 printk("\n");
1394 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1395 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1396 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1397 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1398 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1399
1400 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1401 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1402
1403 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1404 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1405
1406 if (reg_01.bits.version >= 0x10) {
1407 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1408 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1409 }
1410
1411 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1412
1413 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1414 " Stat Dmod Deli Vect: \n");
1415
1416 for (i = 0; i <= reg_01.bits.entries; i++) {
1417 struct IO_APIC_route_entry entry;
1418
1419 entry = ioapic_read_entry(apic, i);
1420
1421 printk(KERN_DEBUG " %02x %03X ",
1422 i,
1423 entry.dest
1424 );
1425
1426 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1427 entry.mask,
1428 entry.trigger,
1429 entry.irr,
1430 entry.polarity,
1431 entry.delivery_status,
1432 entry.dest_mode,
1433 entry.delivery_mode,
1434 entry.vector
1435 );
1436 }
1437 }
1438 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1439 for_each_irq_cfg(cfg) {
1440 struct irq_pin_list *entry = cfg->irq_2_pin;
1441 if (!entry)
1442 continue;
1443 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1444 for (;;) {
1445 printk("-> %d:%d", entry->apic, entry->pin);
1446 if (!entry->next)
1447 break;
1448 entry = entry->next;
1449 }
1450 printk("\n");
1451 }
1452
1453 printk(KERN_INFO ".................................... done.\n");
1454
1455 return;
1456 }
1457
1458 __apicdebuginit(void) print_APIC_bitfield(int base)
1459 {
1460 unsigned int v;
1461 int i, j;
1462
1463 if (apic_verbosity == APIC_QUIET)
1464 return;
1465
1466 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1467 for (i = 0; i < 8; i++) {
1468 v = apic_read(base + i*0x10);
1469 for (j = 0; j < 32; j++) {
1470 if (v & (1<<j))
1471 printk("1");
1472 else
1473 printk("0");
1474 }
1475 printk("\n");
1476 }
1477 }
1478
1479 __apicdebuginit(void) print_local_APIC(void *dummy)
1480 {
1481 unsigned int v, ver, maxlvt;
1482 unsigned long icr;
1483
1484 if (apic_verbosity == APIC_QUIET)
1485 return;
1486
1487 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1488 smp_processor_id(), hard_smp_processor_id());
1489 v = apic_read(APIC_ID);
1490 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1491 v = apic_read(APIC_LVR);
1492 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1493 ver = GET_APIC_VERSION(v);
1494 maxlvt = lapic_get_maxlvt();
1495
1496 v = apic_read(APIC_TASKPRI);
1497 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1498
1499 v = apic_read(APIC_ARBPRI);
1500 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1501 v & APIC_ARBPRI_MASK);
1502 v = apic_read(APIC_PROCPRI);
1503 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1504
1505 v = apic_read(APIC_EOI);
1506 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1507 v = apic_read(APIC_RRR);
1508 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1509 v = apic_read(APIC_LDR);
1510 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1511 v = apic_read(APIC_DFR);
1512 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1513 v = apic_read(APIC_SPIV);
1514 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1515
1516 printk(KERN_DEBUG "... APIC ISR field:\n");
1517 print_APIC_bitfield(APIC_ISR);
1518 printk(KERN_DEBUG "... APIC TMR field:\n");
1519 print_APIC_bitfield(APIC_TMR);
1520 printk(KERN_DEBUG "... APIC IRR field:\n");
1521 print_APIC_bitfield(APIC_IRR);
1522
1523 v = apic_read(APIC_ESR);
1524 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1525
1526 icr = apic_icr_read();
1527 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1528 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1529
1530 v = apic_read(APIC_LVTT);
1531 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1532
1533 if (maxlvt > 3) { /* PC is LVT#4. */
1534 v = apic_read(APIC_LVTPC);
1535 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1536 }
1537 v = apic_read(APIC_LVT0);
1538 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1539 v = apic_read(APIC_LVT1);
1540 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1541
1542 if (maxlvt > 2) { /* ERR is LVT#3. */
1543 v = apic_read(APIC_LVTERR);
1544 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1545 }
1546
1547 v = apic_read(APIC_TMICT);
1548 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1549 v = apic_read(APIC_TMCCT);
1550 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1551 v = apic_read(APIC_TDCR);
1552 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1553 printk("\n");
1554 }
1555
1556 __apicdebuginit(void) print_all_local_APICs(void)
1557 {
1558 on_each_cpu(print_local_APIC, NULL, 1);
1559 }
1560
1561 __apicdebuginit(void) print_PIC(void)
1562 {
1563 unsigned int v;
1564 unsigned long flags;
1565
1566 if (apic_verbosity == APIC_QUIET)
1567 return;
1568
1569 printk(KERN_DEBUG "\nprinting PIC contents\n");
1570
1571 spin_lock_irqsave(&i8259A_lock, flags);
1572
1573 v = inb(0xa1) << 8 | inb(0x21);
1574 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1575
1576 v = inb(0xa0) << 8 | inb(0x20);
1577 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1578
1579 outb(0x0b,0xa0);
1580 outb(0x0b,0x20);
1581 v = inb(0xa0) << 8 | inb(0x20);
1582 outb(0x0a,0xa0);
1583 outb(0x0a,0x20);
1584
1585 spin_unlock_irqrestore(&i8259A_lock, flags);
1586
1587 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1588
1589 v = inb(0x4d1) << 8 | inb(0x4d0);
1590 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1591 }
1592
1593 __apicdebuginit(int) print_all_ICs(void)
1594 {
1595 print_PIC();
1596 print_all_local_APICs();
1597 print_IO_APIC();
1598
1599 return 0;
1600 }
1601
1602 fs_initcall(print_all_ICs);
1603
1604
1605 void __init enable_IO_APIC(void)
1606 {
1607 union IO_APIC_reg_01 reg_01;
1608 int i8259_apic, i8259_pin;
1609 int apic;
1610 unsigned long flags;
1611
1612 /*
1613 * The number of IO-APIC IRQ registers (== #pins):
1614 */
1615 for (apic = 0; apic < nr_ioapics; apic++) {
1616 spin_lock_irqsave(&ioapic_lock, flags);
1617 reg_01.raw = io_apic_read(apic, 1);
1618 spin_unlock_irqrestore(&ioapic_lock, flags);
1619 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1620 }
1621 for(apic = 0; apic < nr_ioapics; apic++) {
1622 int pin;
1623 /* See if any of the pins is in ExtINT mode */
1624 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1625 struct IO_APIC_route_entry entry;
1626 entry = ioapic_read_entry(apic, pin);
1627
1628 /* If the interrupt line is enabled and in ExtInt mode
1629 * I have found the pin where the i8259 is connected.
1630 */
1631 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1632 ioapic_i8259.apic = apic;
1633 ioapic_i8259.pin = pin;
1634 goto found_i8259;
1635 }
1636 }
1637 }
1638 found_i8259:
1639 /* Look to see what if the MP table has reported the ExtINT */
1640 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1641 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1642 /* Trust the MP table if nothing is setup in the hardware */
1643 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1644 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1645 ioapic_i8259.pin = i8259_pin;
1646 ioapic_i8259.apic = i8259_apic;
1647 }
1648 /* Complain if the MP table and the hardware disagree */
1649 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1650 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1651 {
1652 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1653 }
1654
1655 /*
1656 * Do not trust the IO-APIC being empty at bootup
1657 */
1658 clear_IO_APIC();
1659 }
1660
1661 /*
1662 * Not an __init, needed by the reboot code
1663 */
1664 void disable_IO_APIC(void)
1665 {
1666 /*
1667 * Clear the IO-APIC before rebooting:
1668 */
1669 clear_IO_APIC();
1670
1671 /*
1672 * If the i8259 is routed through an IOAPIC
1673 * Put that IOAPIC in virtual wire mode
1674 * so legacy interrupts can be delivered.
1675 */
1676 if (ioapic_i8259.pin != -1) {
1677 struct IO_APIC_route_entry entry;
1678
1679 memset(&entry, 0, sizeof(entry));
1680 entry.mask = 0; /* Enabled */
1681 entry.trigger = 0; /* Edge */
1682 entry.irr = 0;
1683 entry.polarity = 0; /* High */
1684 entry.delivery_status = 0;
1685 entry.dest_mode = 0; /* Physical */
1686 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1687 entry.vector = 0;
1688 entry.dest = read_apic_id();
1689
1690 /*
1691 * Add it to the IO-APIC irq-routing table:
1692 */
1693 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1694 }
1695
1696 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1697 }
1698
1699 /*
1700 * There is a nasty bug in some older SMP boards, their mptable lies
1701 * about the timer IRQ. We do the following to work around the situation:
1702 *
1703 * - timer IRQ defaults to IO-APIC IRQ
1704 * - if this function detects that timer IRQs are defunct, then we fall
1705 * back to ISA timer IRQs
1706 */
1707 static int __init timer_irq_works(void)
1708 {
1709 unsigned long t1 = jiffies;
1710 unsigned long flags;
1711
1712 local_save_flags(flags);
1713 local_irq_enable();
1714 /* Let ten ticks pass... */
1715 mdelay((10 * 1000) / HZ);
1716 local_irq_restore(flags);
1717
1718 /*
1719 * Expect a few ticks at least, to be sure some possible
1720 * glue logic does not lock up after one or two first
1721 * ticks in a non-ExtINT mode. Also the local APIC
1722 * might have cached one ExtINT interrupt. Finally, at
1723 * least one tick may be lost due to delays.
1724 */
1725
1726 /* jiffies wrap? */
1727 if (time_after(jiffies, t1 + 4))
1728 return 1;
1729 return 0;
1730 }
1731
1732 /*
1733 * In the SMP+IOAPIC case it might happen that there are an unspecified
1734 * number of pending IRQ events unhandled. These cases are very rare,
1735 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1736 * better to do it this way as thus we do not have to be aware of
1737 * 'pending' interrupts in the IRQ path, except at this point.
1738 */
1739 /*
1740 * Edge triggered needs to resend any interrupt
1741 * that was delayed but this is now handled in the device
1742 * independent code.
1743 */
1744
1745 /*
1746 * Starting up a edge-triggered IO-APIC interrupt is
1747 * nasty - we need to make sure that we get the edge.
1748 * If it is already asserted for some reason, we need
1749 * return 1 to indicate that is was pending.
1750 *
1751 * This is not complete - we should be able to fake
1752 * an edge even if it isn't on the 8259A...
1753 */
1754
1755 static unsigned int startup_ioapic_irq(unsigned int irq)
1756 {
1757 int was_pending = 0;
1758 unsigned long flags;
1759
1760 spin_lock_irqsave(&ioapic_lock, flags);
1761 if (irq < 16) {
1762 disable_8259A_irq(irq);
1763 if (i8259A_irq_pending(irq))
1764 was_pending = 1;
1765 }
1766 __unmask_IO_APIC_irq(irq);
1767 spin_unlock_irqrestore(&ioapic_lock, flags);
1768
1769 return was_pending;
1770 }
1771
1772 static int ioapic_retrigger_irq(unsigned int irq)
1773 {
1774 struct irq_cfg *cfg = irq_cfg(irq);
1775 unsigned long flags;
1776
1777 spin_lock_irqsave(&vector_lock, flags);
1778 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1779 spin_unlock_irqrestore(&vector_lock, flags);
1780
1781 return 1;
1782 }
1783
1784 /*
1785 * Level and edge triggered IO-APIC interrupts need different handling,
1786 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1787 * handled with the level-triggered descriptor, but that one has slightly
1788 * more overhead. Level-triggered interrupts cannot be handled with the
1789 * edge-triggered handler, without risking IRQ storms and other ugly
1790 * races.
1791 */
1792
1793 #ifdef CONFIG_SMP
1794
1795 #ifdef CONFIG_INTR_REMAP
1796 static void ir_irq_migration(struct work_struct *work);
1797
1798 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1799
1800 /*
1801 * Migrate the IO-APIC irq in the presence of intr-remapping.
1802 *
1803 * For edge triggered, irq migration is a simple atomic update(of vector
1804 * and cpu destination) of IRTE and flush the hardware cache.
1805 *
1806 * For level triggered, we need to modify the io-apic RTE aswell with the update
1807 * vector information, along with modifying IRTE with vector and destination.
1808 * So irq migration for level triggered is little bit more complex compared to
1809 * edge triggered migration. But the good news is, we use the same algorithm
1810 * for level triggered migration as we have today, only difference being,
1811 * we now initiate the irq migration from process context instead of the
1812 * interrupt context.
1813 *
1814 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1815 * suppression) to the IO-APIC, level triggered irq migration will also be
1816 * as simple as edge triggered migration and we can do the irq migration
1817 * with a simple atomic update to IO-APIC RTE.
1818 */
1819 static void migrate_ioapic_irq(int irq, cpumask_t mask)
1820 {
1821 struct irq_cfg *cfg;
1822 struct irq_desc *desc;
1823 cpumask_t tmp, cleanup_mask;
1824 struct irte irte;
1825 int modify_ioapic_rte;
1826 unsigned int dest;
1827 unsigned long flags;
1828
1829 cpus_and(tmp, mask, cpu_online_map);
1830 if (cpus_empty(tmp))
1831 return;
1832
1833 if (get_irte(irq, &irte))
1834 return;
1835
1836 if (assign_irq_vector(irq, mask))
1837 return;
1838
1839 cfg = irq_cfg(irq);
1840 cpus_and(tmp, cfg->domain, mask);
1841 dest = cpu_mask_to_apicid(tmp);
1842
1843 desc = irq_to_desc(irq);
1844 modify_ioapic_rte = desc->status & IRQ_LEVEL;
1845 if (modify_ioapic_rte) {
1846 spin_lock_irqsave(&ioapic_lock, flags);
1847 __target_IO_APIC_irq(irq, dest, cfg->vector);
1848 spin_unlock_irqrestore(&ioapic_lock, flags);
1849 }
1850
1851 irte.vector = cfg->vector;
1852 irte.dest_id = IRTE_DEST(dest);
1853
1854 /*
1855 * Modified the IRTE and flushes the Interrupt entry cache.
1856 */
1857 modify_irte(irq, &irte);
1858
1859 if (cfg->move_in_progress) {
1860 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1861 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1862 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1863 cfg->move_in_progress = 0;
1864 }
1865
1866 desc->affinity = mask;
1867 }
1868
1869 static int migrate_irq_remapped_level(int irq)
1870 {
1871 int ret = -1;
1872 struct irq_desc *desc = irq_to_desc(irq);
1873
1874 mask_IO_APIC_irq(irq);
1875
1876 if (io_apic_level_ack_pending(irq)) {
1877 /*
1878 * Interrupt in progress. Migrating irq now will change the
1879 * vector information in the IO-APIC RTE and that will confuse
1880 * the EOI broadcast performed by cpu.
1881 * So, delay the irq migration to the next instance.
1882 */
1883 schedule_delayed_work(&ir_migration_work, 1);
1884 goto unmask;
1885 }
1886
1887 /* everthing is clear. we have right of way */
1888 migrate_ioapic_irq(irq, desc->pending_mask);
1889
1890 ret = 0;
1891 desc->status &= ~IRQ_MOVE_PENDING;
1892 cpus_clear(desc->pending_mask);
1893
1894 unmask:
1895 unmask_IO_APIC_irq(irq);
1896 return ret;
1897 }
1898
1899 static void ir_irq_migration(struct work_struct *work)
1900 {
1901 unsigned int irq;
1902 struct irq_desc *desc;
1903
1904 for_each_irq_desc(irq, desc) {
1905 if (desc->status & IRQ_MOVE_PENDING) {
1906 unsigned long flags;
1907
1908 spin_lock_irqsave(&desc->lock, flags);
1909 if (!desc->chip->set_affinity ||
1910 !(desc->status & IRQ_MOVE_PENDING)) {
1911 desc->status &= ~IRQ_MOVE_PENDING;
1912 spin_unlock_irqrestore(&desc->lock, flags);
1913 continue;
1914 }
1915
1916 desc->chip->set_affinity(irq, desc->pending_mask);
1917 spin_unlock_irqrestore(&desc->lock, flags);
1918 }
1919 }
1920 }
1921
1922 /*
1923 * Migrates the IRQ destination in the process context.
1924 */
1925 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1926 {
1927 struct irq_desc *desc = irq_to_desc(irq);
1928
1929 if (desc->status & IRQ_LEVEL) {
1930 desc->status |= IRQ_MOVE_PENDING;
1931 desc->pending_mask = mask;
1932 migrate_irq_remapped_level(irq);
1933 return;
1934 }
1935
1936 migrate_ioapic_irq(irq, mask);
1937 }
1938 #endif
1939
1940 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1941 {
1942 unsigned vector, me;
1943 ack_APIC_irq();
1944 exit_idle();
1945 irq_enter();
1946
1947 me = smp_processor_id();
1948 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1949 unsigned int irq;
1950 struct irq_desc *desc;
1951 struct irq_cfg *cfg;
1952 irq = __get_cpu_var(vector_irq)[vector];
1953
1954 desc = irq_to_desc(irq);
1955 if (!desc)
1956 continue;
1957
1958 cfg = irq_cfg(irq);
1959 spin_lock(&desc->lock);
1960 if (!cfg->move_cleanup_count)
1961 goto unlock;
1962
1963 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1964 goto unlock;
1965
1966 __get_cpu_var(vector_irq)[vector] = -1;
1967 cfg->move_cleanup_count--;
1968 unlock:
1969 spin_unlock(&desc->lock);
1970 }
1971
1972 irq_exit();
1973 }
1974
1975 static void irq_complete_move(unsigned int irq)
1976 {
1977 struct irq_cfg *cfg = irq_cfg(irq);
1978 unsigned vector, me;
1979
1980 if (likely(!cfg->move_in_progress))
1981 return;
1982
1983 vector = ~get_irq_regs()->orig_ax;
1984 me = smp_processor_id();
1985 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1986 cpumask_t cleanup_mask;
1987
1988 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1989 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1990 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1991 cfg->move_in_progress = 0;
1992 }
1993 }
1994 #else
1995 static inline void irq_complete_move(unsigned int irq) {}
1996 #endif
1997 #ifdef CONFIG_INTR_REMAP
1998 static void ack_x2apic_level(unsigned int irq)
1999 {
2000 ack_x2APIC_irq();
2001 }
2002
2003 static void ack_x2apic_edge(unsigned int irq)
2004 {
2005 ack_x2APIC_irq();
2006 }
2007 #endif
2008
2009 static void ack_apic_edge(unsigned int irq)
2010 {
2011 irq_complete_move(irq);
2012 move_native_irq(irq);
2013 ack_APIC_irq();
2014 }
2015
2016 static void ack_apic_level(unsigned int irq)
2017 {
2018 int do_unmask_irq = 0;
2019
2020 irq_complete_move(irq);
2021 #ifdef CONFIG_GENERIC_PENDING_IRQ
2022 /* If we are moving the irq we need to mask it */
2023 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2024 do_unmask_irq = 1;
2025 mask_IO_APIC_irq(irq);
2026 }
2027 #endif
2028
2029 /*
2030 * We must acknowledge the irq before we move it or the acknowledge will
2031 * not propagate properly.
2032 */
2033 ack_APIC_irq();
2034
2035 /* Now we can move and renable the irq */
2036 if (unlikely(do_unmask_irq)) {
2037 /* Only migrate the irq if the ack has been received.
2038 *
2039 * On rare occasions the broadcast level triggered ack gets
2040 * delayed going to ioapics, and if we reprogram the
2041 * vector while Remote IRR is still set the irq will never
2042 * fire again.
2043 *
2044 * To prevent this scenario we read the Remote IRR bit
2045 * of the ioapic. This has two effects.
2046 * - On any sane system the read of the ioapic will
2047 * flush writes (and acks) going to the ioapic from
2048 * this cpu.
2049 * - We get to see if the ACK has actually been delivered.
2050 *
2051 * Based on failed experiments of reprogramming the
2052 * ioapic entry from outside of irq context starting
2053 * with masking the ioapic entry and then polling until
2054 * Remote IRR was clear before reprogramming the
2055 * ioapic I don't trust the Remote IRR bit to be
2056 * completey accurate.
2057 *
2058 * However there appears to be no other way to plug
2059 * this race, so if the Remote IRR bit is not
2060 * accurate and is causing problems then it is a hardware bug
2061 * and you can go talk to the chipset vendor about it.
2062 */
2063 if (!io_apic_level_ack_pending(irq))
2064 move_masked_irq(irq);
2065 unmask_IO_APIC_irq(irq);
2066 }
2067 }
2068
2069 static struct irq_chip ioapic_chip __read_mostly = {
2070 .name = "IO-APIC",
2071 .startup = startup_ioapic_irq,
2072 .mask = mask_IO_APIC_irq,
2073 .unmask = unmask_IO_APIC_irq,
2074 .ack = ack_apic_edge,
2075 .eoi = ack_apic_level,
2076 #ifdef CONFIG_SMP
2077 .set_affinity = set_ioapic_affinity_irq,
2078 #endif
2079 .retrigger = ioapic_retrigger_irq,
2080 };
2081
2082 #ifdef CONFIG_INTR_REMAP
2083 static struct irq_chip ir_ioapic_chip __read_mostly = {
2084 .name = "IR-IO-APIC",
2085 .startup = startup_ioapic_irq,
2086 .mask = mask_IO_APIC_irq,
2087 .unmask = unmask_IO_APIC_irq,
2088 .ack = ack_x2apic_edge,
2089 .eoi = ack_x2apic_level,
2090 #ifdef CONFIG_SMP
2091 .set_affinity = set_ir_ioapic_affinity_irq,
2092 #endif
2093 .retrigger = ioapic_retrigger_irq,
2094 };
2095 #endif
2096
2097 static inline void init_IO_APIC_traps(void)
2098 {
2099 int irq;
2100 struct irq_desc *desc;
2101 struct irq_cfg *cfg;
2102
2103 /*
2104 * NOTE! The local APIC isn't very good at handling
2105 * multiple interrupts at the same interrupt level.
2106 * As the interrupt level is determined by taking the
2107 * vector number and shifting that right by 4, we
2108 * want to spread these out a bit so that they don't
2109 * all fall in the same interrupt level.
2110 *
2111 * Also, we've got to be careful not to trash gate
2112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2113 */
2114 for_each_irq_cfg(cfg) {
2115 irq = cfg->irq;
2116 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2117 /*
2118 * Hmm.. We don't have an entry for this,
2119 * so default to an old-fashioned 8259
2120 * interrupt if we can..
2121 */
2122 if (irq < 16)
2123 make_8259A_irq(irq);
2124 else {
2125 desc = irq_to_desc(irq);
2126 /* Strange. Oh, well.. */
2127 desc->chip = &no_irq_chip;
2128 }
2129 }
2130 }
2131 }
2132
2133 static void unmask_lapic_irq(unsigned int irq)
2134 {
2135 unsigned long v;
2136
2137 v = apic_read(APIC_LVT0);
2138 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2139 }
2140
2141 static void mask_lapic_irq(unsigned int irq)
2142 {
2143 unsigned long v;
2144
2145 v = apic_read(APIC_LVT0);
2146 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2147 }
2148
2149 static void ack_lapic_irq (unsigned int irq)
2150 {
2151 ack_APIC_irq();
2152 }
2153
2154 static struct irq_chip lapic_chip __read_mostly = {
2155 .name = "local-APIC",
2156 .mask = mask_lapic_irq,
2157 .unmask = unmask_lapic_irq,
2158 .ack = ack_lapic_irq,
2159 };
2160
2161 static void lapic_register_intr(int irq)
2162 {
2163 struct irq_desc *desc;
2164
2165 desc = irq_to_desc(irq);
2166 desc->status &= ~IRQ_LEVEL;
2167 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2168 "edge");
2169 }
2170
2171 static void __init setup_nmi(void)
2172 {
2173 /*
2174 * Dirty trick to enable the NMI watchdog ...
2175 * We put the 8259A master into AEOI mode and
2176 * unmask on all local APICs LVT0 as NMI.
2177 *
2178 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2179 * is from Maciej W. Rozycki - so we do not have to EOI from
2180 * the NMI handler or the timer interrupt.
2181 */
2182 printk(KERN_INFO "activating NMI Watchdog ...");
2183
2184 enable_NMI_through_LVT0();
2185
2186 printk(" done.\n");
2187 }
2188
2189 /*
2190 * This looks a bit hackish but it's about the only one way of sending
2191 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2192 * not support the ExtINT mode, unfortunately. We need to send these
2193 * cycles as some i82489DX-based boards have glue logic that keeps the
2194 * 8259A interrupt line asserted until INTA. --macro
2195 */
2196 static inline void __init unlock_ExtINT_logic(void)
2197 {
2198 int apic, pin, i;
2199 struct IO_APIC_route_entry entry0, entry1;
2200 unsigned char save_control, save_freq_select;
2201
2202 pin = find_isa_irq_pin(8, mp_INT);
2203 apic = find_isa_irq_apic(8, mp_INT);
2204 if (pin == -1)
2205 return;
2206
2207 entry0 = ioapic_read_entry(apic, pin);
2208
2209 clear_IO_APIC_pin(apic, pin);
2210
2211 memset(&entry1, 0, sizeof(entry1));
2212
2213 entry1.dest_mode = 0; /* physical delivery */
2214 entry1.mask = 0; /* unmask IRQ now */
2215 entry1.dest = hard_smp_processor_id();
2216 entry1.delivery_mode = dest_ExtINT;
2217 entry1.polarity = entry0.polarity;
2218 entry1.trigger = 0;
2219 entry1.vector = 0;
2220
2221 ioapic_write_entry(apic, pin, entry1);
2222
2223 save_control = CMOS_READ(RTC_CONTROL);
2224 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2225 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2226 RTC_FREQ_SELECT);
2227 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2228
2229 i = 100;
2230 while (i-- > 0) {
2231 mdelay(10);
2232 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2233 i -= 10;
2234 }
2235
2236 CMOS_WRITE(save_control, RTC_CONTROL);
2237 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2238 clear_IO_APIC_pin(apic, pin);
2239
2240 ioapic_write_entry(apic, pin, entry0);
2241 }
2242
2243 /*
2244 * This code may look a bit paranoid, but it's supposed to cooperate with
2245 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2246 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2247 * fanatically on his truly buggy board.
2248 *
2249 * FIXME: really need to revamp this for modern platforms only.
2250 */
2251 static inline void __init check_timer(void)
2252 {
2253 struct irq_cfg *cfg = irq_cfg(0);
2254 int apic1, pin1, apic2, pin2;
2255 unsigned long flags;
2256 int no_pin1 = 0;
2257
2258 local_irq_save(flags);
2259
2260 /*
2261 * get/set the timer IRQ vector:
2262 */
2263 disable_8259A_irq(0);
2264 assign_irq_vector(0, TARGET_CPUS);
2265
2266 /*
2267 * As IRQ0 is to be enabled in the 8259A, the virtual
2268 * wire has to be disabled in the local APIC.
2269 */
2270 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2271 init_8259A(1);
2272
2273 pin1 = find_isa_irq_pin(0, mp_INT);
2274 apic1 = find_isa_irq_apic(0, mp_INT);
2275 pin2 = ioapic_i8259.pin;
2276 apic2 = ioapic_i8259.apic;
2277
2278 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2279 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2280 cfg->vector, apic1, pin1, apic2, pin2);
2281
2282 /*
2283 * Some BIOS writers are clueless and report the ExtINTA
2284 * I/O APIC input from the cascaded 8259A as the timer
2285 * interrupt input. So just in case, if only one pin
2286 * was found above, try it both directly and through the
2287 * 8259A.
2288 */
2289 if (pin1 == -1) {
2290 if (intr_remapping_enabled)
2291 panic("BIOS bug: timer not connected to IO-APIC");
2292 pin1 = pin2;
2293 apic1 = apic2;
2294 no_pin1 = 1;
2295 } else if (pin2 == -1) {
2296 pin2 = pin1;
2297 apic2 = apic1;
2298 }
2299
2300 if (pin1 != -1) {
2301 /*
2302 * Ok, does IRQ0 through the IOAPIC work?
2303 */
2304 if (no_pin1) {
2305 add_pin_to_irq(0, apic1, pin1);
2306 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2307 }
2308 unmask_IO_APIC_irq(0);
2309 if (!no_timer_check && timer_irq_works()) {
2310 if (nmi_watchdog == NMI_IO_APIC) {
2311 setup_nmi();
2312 enable_8259A_irq(0);
2313 }
2314 if (disable_timer_pin_1 > 0)
2315 clear_IO_APIC_pin(0, pin1);
2316 goto out;
2317 }
2318 if (intr_remapping_enabled)
2319 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2320 clear_IO_APIC_pin(apic1, pin1);
2321 if (!no_pin1)
2322 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2323 "8254 timer not connected to IO-APIC\n");
2324
2325 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2326 "(IRQ0) through the 8259A ...\n");
2327 apic_printk(APIC_QUIET, KERN_INFO
2328 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2329 /*
2330 * legacy devices should be connected to IO APIC #0
2331 */
2332 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2333 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2334 unmask_IO_APIC_irq(0);
2335 enable_8259A_irq(0);
2336 if (timer_irq_works()) {
2337 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2338 timer_through_8259 = 1;
2339 if (nmi_watchdog == NMI_IO_APIC) {
2340 disable_8259A_irq(0);
2341 setup_nmi();
2342 enable_8259A_irq(0);
2343 }
2344 goto out;
2345 }
2346 /*
2347 * Cleanup, just in case ...
2348 */
2349 disable_8259A_irq(0);
2350 clear_IO_APIC_pin(apic2, pin2);
2351 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2352 }
2353
2354 if (nmi_watchdog == NMI_IO_APIC) {
2355 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2356 "through the IO-APIC - disabling NMI Watchdog!\n");
2357 nmi_watchdog = NMI_NONE;
2358 }
2359
2360 apic_printk(APIC_QUIET, KERN_INFO
2361 "...trying to set up timer as Virtual Wire IRQ...\n");
2362
2363 lapic_register_intr(0);
2364 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2365 enable_8259A_irq(0);
2366
2367 if (timer_irq_works()) {
2368 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2369 goto out;
2370 }
2371 disable_8259A_irq(0);
2372 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2373 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2374
2375 apic_printk(APIC_QUIET, KERN_INFO
2376 "...trying to set up timer as ExtINT IRQ...\n");
2377
2378 init_8259A(0);
2379 make_8259A_irq(0);
2380 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2381
2382 unlock_ExtINT_logic();
2383
2384 if (timer_irq_works()) {
2385 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2386 goto out;
2387 }
2388 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2389 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2390 "report. Then try booting with the 'noapic' option.\n");
2391 out:
2392 local_irq_restore(flags);
2393 }
2394
2395 static int __init notimercheck(char *s)
2396 {
2397 no_timer_check = 1;
2398 return 1;
2399 }
2400 __setup("no_timer_check", notimercheck);
2401
2402 /*
2403 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2404 * to devices. However there may be an I/O APIC pin available for
2405 * this interrupt regardless. The pin may be left unconnected, but
2406 * typically it will be reused as an ExtINT cascade interrupt for
2407 * the master 8259A. In the MPS case such a pin will normally be
2408 * reported as an ExtINT interrupt in the MP table. With ACPI
2409 * there is no provision for ExtINT interrupts, and in the absence
2410 * of an override it would be treated as an ordinary ISA I/O APIC
2411 * interrupt, that is edge-triggered and unmasked by default. We
2412 * used to do this, but it caused problems on some systems because
2413 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2414 * the same ExtINT cascade interrupt to drive the local APIC of the
2415 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2416 * the I/O APIC in all cases now. No actual device should request
2417 * it anyway. --macro
2418 */
2419 #define PIC_IRQS (1<<2)
2420
2421 void __init setup_IO_APIC(void)
2422 {
2423
2424 /*
2425 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2426 */
2427
2428 io_apic_irqs = ~PIC_IRQS;
2429
2430 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2431
2432 sync_Arb_IDs();
2433 setup_IO_APIC_irqs();
2434 init_IO_APIC_traps();
2435 check_timer();
2436 }
2437
2438 struct sysfs_ioapic_data {
2439 struct sys_device dev;
2440 struct IO_APIC_route_entry entry[0];
2441 };
2442 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2443
2444 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2445 {
2446 struct IO_APIC_route_entry *entry;
2447 struct sysfs_ioapic_data *data;
2448 int i;
2449
2450 data = container_of(dev, struct sysfs_ioapic_data, dev);
2451 entry = data->entry;
2452 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2453 *entry = ioapic_read_entry(dev->id, i);
2454
2455 return 0;
2456 }
2457
2458 static int ioapic_resume(struct sys_device *dev)
2459 {
2460 struct IO_APIC_route_entry *entry;
2461 struct sysfs_ioapic_data *data;
2462 unsigned long flags;
2463 union IO_APIC_reg_00 reg_00;
2464 int i;
2465
2466 data = container_of(dev, struct sysfs_ioapic_data, dev);
2467 entry = data->entry;
2468
2469 spin_lock_irqsave(&ioapic_lock, flags);
2470 reg_00.raw = io_apic_read(dev->id, 0);
2471 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2472 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2473 io_apic_write(dev->id, 0, reg_00.raw);
2474 }
2475 spin_unlock_irqrestore(&ioapic_lock, flags);
2476 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2477 ioapic_write_entry(dev->id, i, entry[i]);
2478
2479 return 0;
2480 }
2481
2482 static struct sysdev_class ioapic_sysdev_class = {
2483 .name = "ioapic",
2484 .suspend = ioapic_suspend,
2485 .resume = ioapic_resume,
2486 };
2487
2488 static int __init ioapic_init_sysfs(void)
2489 {
2490 struct sys_device * dev;
2491 int i, size, error;
2492
2493 error = sysdev_class_register(&ioapic_sysdev_class);
2494 if (error)
2495 return error;
2496
2497 for (i = 0; i < nr_ioapics; i++ ) {
2498 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2499 * sizeof(struct IO_APIC_route_entry);
2500 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2501 if (!mp_ioapic_data[i]) {
2502 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2503 continue;
2504 }
2505 dev = &mp_ioapic_data[i]->dev;
2506 dev->id = i;
2507 dev->cls = &ioapic_sysdev_class;
2508 error = sysdev_register(dev);
2509 if (error) {
2510 kfree(mp_ioapic_data[i]);
2511 mp_ioapic_data[i] = NULL;
2512 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2513 continue;
2514 }
2515 }
2516
2517 return 0;
2518 }
2519
2520 device_initcall(ioapic_init_sysfs);
2521
2522 /*
2523 * Dynamic irq allocate and deallocation
2524 */
2525 unsigned int create_irq_nr(unsigned int irq_want)
2526 {
2527 /* Allocate an unused irq */
2528 unsigned int irq;
2529 unsigned int new;
2530 unsigned long flags;
2531 struct irq_cfg *cfg_new;
2532
2533 #ifndef CONFIG_HAVE_SPARSE_IRQ
2534 irq_want = nr_irqs - 1;
2535 #endif
2536
2537 irq = 0;
2538 spin_lock_irqsave(&vector_lock, flags);
2539 for (new = irq_want; new > 0; new--) {
2540 if (platform_legacy_irq(new))
2541 continue;
2542 cfg_new = irq_cfg(new);
2543 if (cfg_new && cfg_new->vector != 0)
2544 continue;
2545 /* check if need to create one */
2546 if (!cfg_new)
2547 cfg_new = irq_cfg_alloc(new);
2548 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2549 irq = new;
2550 break;
2551 }
2552 spin_unlock_irqrestore(&vector_lock, flags);
2553
2554 if (irq > 0) {
2555 dynamic_irq_init(irq);
2556 }
2557 return irq;
2558 }
2559
2560 int create_irq(void)
2561 {
2562 int irq;
2563
2564 irq = create_irq_nr(nr_irqs - 1);
2565
2566 if (irq == 0)
2567 irq = -1;
2568
2569 return irq;
2570 }
2571
2572 void destroy_irq(unsigned int irq)
2573 {
2574 unsigned long flags;
2575
2576 dynamic_irq_cleanup(irq);
2577
2578 #ifdef CONFIG_INTR_REMAP
2579 free_irte(irq);
2580 #endif
2581 spin_lock_irqsave(&vector_lock, flags);
2582 __clear_irq_vector(irq);
2583 spin_unlock_irqrestore(&vector_lock, flags);
2584 }
2585
2586 /*
2587 * MSI message composition
2588 */
2589 #ifdef CONFIG_PCI_MSI
2590 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2591 {
2592 struct irq_cfg *cfg;
2593 int err;
2594 unsigned dest;
2595 cpumask_t tmp;
2596
2597 tmp = TARGET_CPUS;
2598 err = assign_irq_vector(irq, tmp);
2599 if (err)
2600 return err;
2601
2602 cfg = irq_cfg(irq);
2603 cpus_and(tmp, cfg->domain, tmp);
2604 dest = cpu_mask_to_apicid(tmp);
2605
2606 #ifdef CONFIG_INTR_REMAP
2607 if (irq_remapped(irq)) {
2608 struct irte irte;
2609 int ir_index;
2610 u16 sub_handle;
2611
2612 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2613 BUG_ON(ir_index == -1);
2614
2615 memset (&irte, 0, sizeof(irte));
2616
2617 irte.present = 1;
2618 irte.dst_mode = INT_DEST_MODE;
2619 irte.trigger_mode = 0; /* edge */
2620 irte.dlvry_mode = INT_DELIVERY_MODE;
2621 irte.vector = cfg->vector;
2622 irte.dest_id = IRTE_DEST(dest);
2623
2624 modify_irte(irq, &irte);
2625
2626 msg->address_hi = MSI_ADDR_BASE_HI;
2627 msg->data = sub_handle;
2628 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2629 MSI_ADDR_IR_SHV |
2630 MSI_ADDR_IR_INDEX1(ir_index) |
2631 MSI_ADDR_IR_INDEX2(ir_index);
2632 } else
2633 #endif
2634 {
2635 msg->address_hi = MSI_ADDR_BASE_HI;
2636 msg->address_lo =
2637 MSI_ADDR_BASE_LO |
2638 ((INT_DEST_MODE == 0) ?
2639 MSI_ADDR_DEST_MODE_PHYSICAL:
2640 MSI_ADDR_DEST_MODE_LOGICAL) |
2641 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2642 MSI_ADDR_REDIRECTION_CPU:
2643 MSI_ADDR_REDIRECTION_LOWPRI) |
2644 MSI_ADDR_DEST_ID(dest);
2645
2646 msg->data =
2647 MSI_DATA_TRIGGER_EDGE |
2648 MSI_DATA_LEVEL_ASSERT |
2649 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2650 MSI_DATA_DELIVERY_FIXED:
2651 MSI_DATA_DELIVERY_LOWPRI) |
2652 MSI_DATA_VECTOR(cfg->vector);
2653 }
2654 return err;
2655 }
2656
2657 #ifdef CONFIG_SMP
2658 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2659 {
2660 struct irq_cfg *cfg;
2661 struct msi_msg msg;
2662 unsigned int dest;
2663 cpumask_t tmp;
2664 struct irq_desc *desc;
2665
2666 cpus_and(tmp, mask, cpu_online_map);
2667 if (cpus_empty(tmp))
2668 return;
2669
2670 if (assign_irq_vector(irq, mask))
2671 return;
2672
2673 cfg = irq_cfg(irq);
2674 cpus_and(tmp, cfg->domain, mask);
2675 dest = cpu_mask_to_apicid(tmp);
2676
2677 read_msi_msg(irq, &msg);
2678
2679 msg.data &= ~MSI_DATA_VECTOR_MASK;
2680 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2681 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2682 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2683
2684 write_msi_msg(irq, &msg);
2685 desc = irq_to_desc(irq);
2686 desc->affinity = mask;
2687 }
2688
2689 #ifdef CONFIG_INTR_REMAP
2690 /*
2691 * Migrate the MSI irq to another cpumask. This migration is
2692 * done in the process context using interrupt-remapping hardware.
2693 */
2694 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2695 {
2696 struct irq_cfg *cfg;
2697 unsigned int dest;
2698 cpumask_t tmp, cleanup_mask;
2699 struct irte irte;
2700 struct irq_desc *desc;
2701
2702 cpus_and(tmp, mask, cpu_online_map);
2703 if (cpus_empty(tmp))
2704 return;
2705
2706 if (get_irte(irq, &irte))
2707 return;
2708
2709 if (assign_irq_vector(irq, mask))
2710 return;
2711
2712 cfg = irq_cfg(irq);
2713 cpus_and(tmp, cfg->domain, mask);
2714 dest = cpu_mask_to_apicid(tmp);
2715
2716 irte.vector = cfg->vector;
2717 irte.dest_id = IRTE_DEST(dest);
2718
2719 /*
2720 * atomically update the IRTE with the new destination and vector.
2721 */
2722 modify_irte(irq, &irte);
2723
2724 /*
2725 * After this point, all the interrupts will start arriving
2726 * at the new destination. So, time to cleanup the previous
2727 * vector allocation.
2728 */
2729 if (cfg->move_in_progress) {
2730 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2731 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2732 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2733 cfg->move_in_progress = 0;
2734 }
2735
2736 desc = irq_to_desc(irq);
2737 desc->affinity = mask;
2738 }
2739 #endif
2740 #endif /* CONFIG_SMP */
2741
2742 /*
2743 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2744 * which implement the MSI or MSI-X Capability Structure.
2745 */
2746 static struct irq_chip msi_chip = {
2747 .name = "PCI-MSI",
2748 .unmask = unmask_msi_irq,
2749 .mask = mask_msi_irq,
2750 .ack = ack_apic_edge,
2751 #ifdef CONFIG_SMP
2752 .set_affinity = set_msi_irq_affinity,
2753 #endif
2754 .retrigger = ioapic_retrigger_irq,
2755 };
2756
2757 #ifdef CONFIG_INTR_REMAP
2758 static struct irq_chip msi_ir_chip = {
2759 .name = "IR-PCI-MSI",
2760 .unmask = unmask_msi_irq,
2761 .mask = mask_msi_irq,
2762 .ack = ack_x2apic_edge,
2763 #ifdef CONFIG_SMP
2764 .set_affinity = ir_set_msi_irq_affinity,
2765 #endif
2766 .retrigger = ioapic_retrigger_irq,
2767 };
2768
2769 /*
2770 * Map the PCI dev to the corresponding remapping hardware unit
2771 * and allocate 'nvec' consecutive interrupt-remapping table entries
2772 * in it.
2773 */
2774 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
2775 {
2776 struct intel_iommu *iommu;
2777 int index;
2778
2779 iommu = map_dev_to_ir(dev);
2780 if (!iommu) {
2781 printk(KERN_ERR
2782 "Unable to map PCI %s to iommu\n", pci_name(dev));
2783 return -ENOENT;
2784 }
2785
2786 index = alloc_irte(iommu, irq, nvec);
2787 if (index < 0) {
2788 printk(KERN_ERR
2789 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2790 pci_name(dev));
2791 return -ENOSPC;
2792 }
2793 return index;
2794 }
2795 #endif
2796
2797 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2798 {
2799 int ret;
2800 struct msi_msg msg;
2801
2802 ret = msi_compose_msg(dev, irq, &msg);
2803 if (ret < 0)
2804 return ret;
2805
2806 set_irq_msi(irq, desc);
2807 write_msi_msg(irq, &msg);
2808
2809 #ifdef CONFIG_INTR_REMAP
2810 if (irq_remapped(irq)) {
2811 struct irq_desc *desc = irq_to_desc(irq);
2812 /*
2813 * irq migration in process context
2814 */
2815 desc->status |= IRQ_MOVE_PCNTXT;
2816 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2817 } else
2818 #endif
2819 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2820
2821 return 0;
2822 }
2823
2824 static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2825 {
2826 unsigned int irq;
2827
2828 irq = dev->bus->number;
2829 irq <<= 8;
2830 irq |= dev->devfn;
2831 irq <<= 12;
2832
2833 return irq;
2834 }
2835
2836 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2837 {
2838 unsigned int irq;
2839 int ret;
2840 unsigned int irq_want;
2841
2842 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2843
2844 irq = create_irq_nr(irq_want);
2845 if (irq == 0)
2846 return -1;
2847
2848 #ifdef CONFIG_INTR_REMAP
2849 if (!intr_remapping_enabled)
2850 goto no_ir;
2851
2852 ret = msi_alloc_irte(dev, irq, 1);
2853 if (ret < 0)
2854 goto error;
2855 no_ir:
2856 #endif
2857 ret = setup_msi_irq(dev, desc, irq);
2858 if (ret < 0) {
2859 destroy_irq(irq);
2860 return ret;
2861 }
2862 return 0;
2863
2864 #ifdef CONFIG_INTR_REMAP
2865 error:
2866 destroy_irq(irq);
2867 return ret;
2868 #endif
2869 }
2870
2871 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2872 {
2873 unsigned int irq;
2874 int ret, sub_handle;
2875 struct msi_desc *desc;
2876 unsigned int irq_want;
2877
2878 #ifdef CONFIG_INTR_REMAP
2879 struct intel_iommu *iommu = 0;
2880 int index = 0;
2881 #endif
2882
2883 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2884 sub_handle = 0;
2885 list_for_each_entry(desc, &dev->msi_list, list) {
2886 irq = create_irq_nr(irq_want--);
2887 if (irq == 0)
2888 return -1;
2889 #ifdef CONFIG_INTR_REMAP
2890 if (!intr_remapping_enabled)
2891 goto no_ir;
2892
2893 if (!sub_handle) {
2894 /*
2895 * allocate the consecutive block of IRTE's
2896 * for 'nvec'
2897 */
2898 index = msi_alloc_irte(dev, irq, nvec);
2899 if (index < 0) {
2900 ret = index;
2901 goto error;
2902 }
2903 } else {
2904 iommu = map_dev_to_ir(dev);
2905 if (!iommu) {
2906 ret = -ENOENT;
2907 goto error;
2908 }
2909 /*
2910 * setup the mapping between the irq and the IRTE
2911 * base index, the sub_handle pointing to the
2912 * appropriate interrupt remap table entry.
2913 */
2914 set_irte_irq(irq, iommu, index, sub_handle);
2915 }
2916 no_ir:
2917 #endif
2918 ret = setup_msi_irq(dev, desc, irq);
2919 if (ret < 0)
2920 goto error;
2921 sub_handle++;
2922 }
2923 return 0;
2924
2925 error:
2926 destroy_irq(irq);
2927 return ret;
2928 }
2929
2930 void arch_teardown_msi_irq(unsigned int irq)
2931 {
2932 destroy_irq(irq);
2933 }
2934
2935 #ifdef CONFIG_DMAR
2936 #ifdef CONFIG_SMP
2937 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2938 {
2939 struct irq_cfg *cfg;
2940 struct msi_msg msg;
2941 unsigned int dest;
2942 cpumask_t tmp;
2943 struct irq_desc *desc;
2944
2945 cpus_and(tmp, mask, cpu_online_map);
2946 if (cpus_empty(tmp))
2947 return;
2948
2949 if (assign_irq_vector(irq, mask))
2950 return;
2951
2952 cfg = irq_cfg(irq);
2953 cpus_and(tmp, cfg->domain, mask);
2954 dest = cpu_mask_to_apicid(tmp);
2955
2956 dmar_msi_read(irq, &msg);
2957
2958 msg.data &= ~MSI_DATA_VECTOR_MASK;
2959 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2960 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2961 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2962
2963 dmar_msi_write(irq, &msg);
2964 desc = irq_to_desc(irq);
2965 desc->affinity = mask;
2966 }
2967 #endif /* CONFIG_SMP */
2968
2969 struct irq_chip dmar_msi_type = {
2970 .name = "DMAR_MSI",
2971 .unmask = dmar_msi_unmask,
2972 .mask = dmar_msi_mask,
2973 .ack = ack_apic_edge,
2974 #ifdef CONFIG_SMP
2975 .set_affinity = dmar_msi_set_affinity,
2976 #endif
2977 .retrigger = ioapic_retrigger_irq,
2978 };
2979
2980 int arch_setup_dmar_msi(unsigned int irq)
2981 {
2982 int ret;
2983 struct msi_msg msg;
2984
2985 ret = msi_compose_msg(NULL, irq, &msg);
2986 if (ret < 0)
2987 return ret;
2988 dmar_msi_write(irq, &msg);
2989 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2990 "edge");
2991 return 0;
2992 }
2993 #endif
2994
2995 #endif /* CONFIG_PCI_MSI */
2996 /*
2997 * Hypertransport interrupt support
2998 */
2999 #ifdef CONFIG_HT_IRQ
3000
3001 #ifdef CONFIG_SMP
3002
3003 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3004 {
3005 struct ht_irq_msg msg;
3006 fetch_ht_irq_msg(irq, &msg);
3007
3008 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3009 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3010
3011 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3012 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3013
3014 write_ht_irq_msg(irq, &msg);
3015 }
3016
3017 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3018 {
3019 struct irq_cfg *cfg;
3020 unsigned int dest;
3021 cpumask_t tmp;
3022 struct irq_desc *desc;
3023
3024 cpus_and(tmp, mask, cpu_online_map);
3025 if (cpus_empty(tmp))
3026 return;
3027
3028 if (assign_irq_vector(irq, mask))
3029 return;
3030
3031 cfg = irq_cfg(irq);
3032 cpus_and(tmp, cfg->domain, mask);
3033 dest = cpu_mask_to_apicid(tmp);
3034
3035 target_ht_irq(irq, dest, cfg->vector);
3036 desc = irq_to_desc(irq);
3037 desc->affinity = mask;
3038 }
3039 #endif
3040
3041 static struct irq_chip ht_irq_chip = {
3042 .name = "PCI-HT",
3043 .mask = mask_ht_irq,
3044 .unmask = unmask_ht_irq,
3045 .ack = ack_apic_edge,
3046 #ifdef CONFIG_SMP
3047 .set_affinity = set_ht_irq_affinity,
3048 #endif
3049 .retrigger = ioapic_retrigger_irq,
3050 };
3051
3052 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3053 {
3054 struct irq_cfg *cfg;
3055 int err;
3056 cpumask_t tmp;
3057
3058 tmp = TARGET_CPUS;
3059 err = assign_irq_vector(irq, tmp);
3060 if (!err) {
3061 struct ht_irq_msg msg;
3062 unsigned dest;
3063
3064 cfg = irq_cfg(irq);
3065 cpus_and(tmp, cfg->domain, tmp);
3066 dest = cpu_mask_to_apicid(tmp);
3067
3068 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3069
3070 msg.address_lo =
3071 HT_IRQ_LOW_BASE |
3072 HT_IRQ_LOW_DEST_ID(dest) |
3073 HT_IRQ_LOW_VECTOR(cfg->vector) |
3074 ((INT_DEST_MODE == 0) ?
3075 HT_IRQ_LOW_DM_PHYSICAL :
3076 HT_IRQ_LOW_DM_LOGICAL) |
3077 HT_IRQ_LOW_RQEOI_EDGE |
3078 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3079 HT_IRQ_LOW_MT_FIXED :
3080 HT_IRQ_LOW_MT_ARBITRATED) |
3081 HT_IRQ_LOW_IRQ_MASKED;
3082
3083 write_ht_irq_msg(irq, &msg);
3084
3085 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3086 handle_edge_irq, "edge");
3087 }
3088 return err;
3089 }
3090 #endif /* CONFIG_HT_IRQ */
3091
3092 /* --------------------------------------------------------------------------
3093 ACPI-based IOAPIC Configuration
3094 -------------------------------------------------------------------------- */
3095
3096 #ifdef CONFIG_ACPI
3097
3098 #define IO_APIC_MAX_ID 0xFE
3099
3100 int __init io_apic_get_redir_entries (int ioapic)
3101 {
3102 union IO_APIC_reg_01 reg_01;
3103 unsigned long flags;
3104
3105 spin_lock_irqsave(&ioapic_lock, flags);
3106 reg_01.raw = io_apic_read(ioapic, 1);
3107 spin_unlock_irqrestore(&ioapic_lock, flags);
3108
3109 return reg_01.bits.entries;
3110 }
3111
3112
3113 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3114 {
3115 if (!IO_APIC_IRQ(irq)) {
3116 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3117 ioapic);
3118 return -EINVAL;
3119 }
3120
3121 /*
3122 * IRQs < 16 are already in the irq_2_pin[] map
3123 */
3124 if (irq >= 16)
3125 add_pin_to_irq(irq, ioapic, pin);
3126
3127 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3128
3129 return 0;
3130 }
3131
3132
3133 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3134 {
3135 int i;
3136
3137 if (skip_ioapic_setup)
3138 return -1;
3139
3140 for (i = 0; i < mp_irq_entries; i++)
3141 if (mp_irqs[i].mp_irqtype == mp_INT &&
3142 mp_irqs[i].mp_srcbusirq == bus_irq)
3143 break;
3144 if (i >= mp_irq_entries)
3145 return -1;
3146
3147 *trigger = irq_trigger(i);
3148 *polarity = irq_polarity(i);
3149 return 0;
3150 }
3151
3152 #endif /* CONFIG_ACPI */
3153
3154 /*
3155 * This function currently is only a helper for the i386 smp boot process where
3156 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3157 * so mask in all cases should simply be TARGET_CPUS
3158 */
3159 #ifdef CONFIG_SMP
3160 void __init setup_ioapic_dest(void)
3161 {
3162 int pin, ioapic, irq, irq_entry;
3163 struct irq_cfg *cfg;
3164
3165 if (skip_ioapic_setup == 1)
3166 return;
3167
3168 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3169 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3170 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3171 if (irq_entry == -1)
3172 continue;
3173 irq = pin_2_irq(irq_entry, ioapic, pin);
3174
3175 /* setup_IO_APIC_irqs could fail to get vector for some device
3176 * when you have too many devices, because at that time only boot
3177 * cpu is online.
3178 */
3179 cfg = irq_cfg(irq);
3180 if (!cfg->vector)
3181 setup_IO_APIC_irq(ioapic, pin, irq,
3182 irq_trigger(irq_entry),
3183 irq_polarity(irq_entry));
3184 #ifdef CONFIG_INTR_REMAP
3185 else if (intr_remapping_enabled)
3186 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3187 #endif
3188 else
3189 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3190 }
3191
3192 }
3193 }
3194 #endif
3195
3196 #define IOAPIC_RESOURCE_NAME_SIZE 11
3197
3198 static struct resource *ioapic_resources;
3199
3200 static struct resource * __init ioapic_setup_resources(void)
3201 {
3202 unsigned long n;
3203 struct resource *res;
3204 char *mem;
3205 int i;
3206
3207 if (nr_ioapics <= 0)
3208 return NULL;
3209
3210 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3211 n *= nr_ioapics;
3212
3213 mem = alloc_bootmem(n);
3214 res = (void *)mem;
3215
3216 if (mem != NULL) {
3217 mem += sizeof(struct resource) * nr_ioapics;
3218
3219 for (i = 0; i < nr_ioapics; i++) {
3220 res[i].name = mem;
3221 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3222 sprintf(mem, "IOAPIC %u", i);
3223 mem += IOAPIC_RESOURCE_NAME_SIZE;
3224 }
3225 }
3226
3227 ioapic_resources = res;
3228
3229 return res;
3230 }
3231
3232 void __init ioapic_init_mappings(void)
3233 {
3234 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3235 struct resource *ioapic_res;
3236 int i;
3237
3238 ioapic_res = ioapic_setup_resources();
3239 for (i = 0; i < nr_ioapics; i++) {
3240 if (smp_found_config) {
3241 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3242 } else {
3243 ioapic_phys = (unsigned long)
3244 alloc_bootmem_pages(PAGE_SIZE);
3245 ioapic_phys = __pa(ioapic_phys);
3246 }
3247 set_fixmap_nocache(idx, ioapic_phys);
3248 apic_printk(APIC_VERBOSE,
3249 "mapped IOAPIC to %016lx (%016lx)\n",
3250 __fix_to_virt(idx), ioapic_phys);
3251 idx++;
3252
3253 if (ioapic_res != NULL) {
3254 ioapic_res->start = ioapic_phys;
3255 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3256 ioapic_res++;
3257 }
3258 }
3259 }
3260
3261 static int __init ioapic_insert_resources(void)
3262 {
3263 int i;
3264 struct resource *r = ioapic_resources;
3265
3266 if (!r) {
3267 printk(KERN_ERR
3268 "IO APIC resources could be not be allocated.\n");
3269 return -1;
3270 }
3271
3272 for (i = 0; i < nr_ioapics; i++) {
3273 insert_resource(&iomem_resource, r);
3274 r++;
3275 }
3276
3277 return 0;
3278 }
3279
3280 /* Insert the IO APIC resources after PCI initialization has occured to handle
3281 * IO APICS that are mapped in on a BAR in PCI space. */
3282 late_initcall(ioapic_insert_resources);
3283
Linux kernel - Deliverables
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