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x86, io-apic: use predefined names instead of numeric constants
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 #define __apicdebuginit __init
86
87 int sis_apic_bug; /* not actually supported, dummy for compile */
88
89 static int no_timer_check;
90
91 static int disable_timer_pin_1 __initdata;
92
93 int timer_through_8259 __initdata;
94
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
97
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
100
101 /*
102 * # of IRQ routing registers
103 */
104 int nr_ioapic_registers[MAX_IO_APICS];
105
106 /* I/O APIC entries */
107 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
108 int nr_ioapics;
109
110 /* MP IRQ source entries */
111 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
112
113 /* # of MP IRQ source entries */
114 int mp_irq_entries;
115
116 /*
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
119 */
120 #define MAX_PLUS_SHARED_IRQS NR_IRQS
121 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
122
123 /*
124 * This is performance-critical, we want to do it O(1)
125 *
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
128 */
129
130 static struct irq_pin_list {
131 short apic, pin, next;
132 } irq_2_pin[PIN_MAP_SIZE];
133
134 struct io_apic {
135 unsigned int index;
136 unsigned int unused[3];
137 unsigned int data;
138 };
139
140 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
141 {
142 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
143 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
144 }
145
146 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
147 {
148 struct io_apic __iomem *io_apic = io_apic_base(apic);
149 writel(reg, &io_apic->index);
150 return readl(&io_apic->data);
151 }
152
153 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
154 {
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 writel(value, &io_apic->data);
158 }
159
160 /*
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
163 */
164 static inline void io_apic_modify(unsigned int apic, unsigned int value)
165 {
166 struct io_apic __iomem *io_apic = io_apic_base(apic);
167 writel(value, &io_apic->data);
168 }
169
170 static bool io_apic_level_ack_pending(unsigned int irq)
171 {
172 struct irq_pin_list *entry;
173 unsigned long flags;
174
175 spin_lock_irqsave(&ioapic_lock, flags);
176 entry = irq_2_pin + irq;
177 for (;;) {
178 unsigned int reg;
179 int pin;
180
181 pin = entry->pin;
182 if (pin == -1)
183 break;
184 reg = io_apic_read(entry->apic, 0x10 + pin*2);
185 /* Is the remote IRR bit set? */
186 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
187 spin_unlock_irqrestore(&ioapic_lock, flags);
188 return true;
189 }
190 if (!entry->next)
191 break;
192 entry = irq_2_pin + entry->next;
193 }
194 spin_unlock_irqrestore(&ioapic_lock, flags);
195
196 return false;
197 }
198
199 /*
200 * Synchronize the IO-APIC and the CPU by doing
201 * a dummy read from the IO-APIC
202 */
203 static inline void io_apic_sync(unsigned int apic)
204 {
205 struct io_apic __iomem *io_apic = io_apic_base(apic);
206 readl(&io_apic->data);
207 }
208
209 #define __DO_ACTION(R, ACTION, FINAL) \
210 \
211 { \
212 int pin; \
213 struct irq_pin_list *entry = irq_2_pin + irq; \
214 \
215 BUG_ON(irq >= NR_IRQS); \
216 for (;;) { \
217 unsigned int reg; \
218 pin = entry->pin; \
219 if (pin == -1) \
220 break; \
221 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
222 reg ACTION; \
223 io_apic_modify(entry->apic, reg); \
224 FINAL; \
225 if (!entry->next) \
226 break; \
227 entry = irq_2_pin + entry->next; \
228 } \
229 }
230
231 union entry_union {
232 struct { u32 w1, w2; };
233 struct IO_APIC_route_entry entry;
234 };
235
236 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
237 {
238 union entry_union eu;
239 unsigned long flags;
240 spin_lock_irqsave(&ioapic_lock, flags);
241 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
242 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
244 return eu.entry;
245 }
246
247 /*
248 * When we write a new IO APIC routing entry, we need to write the high
249 * word first! If the mask bit in the low word is clear, we will enable
250 * the interrupt, and we need to make sure the entry is fully populated
251 * before that happens.
252 */
253 static void
254 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
255 {
256 union entry_union eu;
257 eu.entry = e;
258 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
259 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
260 }
261
262 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
263 {
264 unsigned long flags;
265 spin_lock_irqsave(&ioapic_lock, flags);
266 __ioapic_write_entry(apic, pin, e);
267 spin_unlock_irqrestore(&ioapic_lock, flags);
268 }
269
270 /*
271 * When we mask an IO APIC routing entry, we need to write the low
272 * word first, in order to set the mask bit before we change the
273 * high bits!
274 */
275 static void ioapic_mask_entry(int apic, int pin)
276 {
277 unsigned long flags;
278 union entry_union eu = { .entry.mask = 1 };
279
280 spin_lock_irqsave(&ioapic_lock, flags);
281 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
282 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
284 }
285
286 #ifdef CONFIG_SMP
287 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
288 {
289 int apic, pin;
290 struct irq_pin_list *entry = irq_2_pin + irq;
291
292 BUG_ON(irq >= NR_IRQS);
293 for (;;) {
294 unsigned int reg;
295 apic = entry->apic;
296 pin = entry->pin;
297 if (pin == -1)
298 break;
299 io_apic_write(apic, 0x11 + pin*2, dest);
300 reg = io_apic_read(apic, 0x10 + pin*2);
301 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
302 reg |= vector;
303 io_apic_modify(apic, reg);
304 if (!entry->next)
305 break;
306 entry = irq_2_pin + entry->next;
307 }
308 }
309
310 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
311 {
312 struct irq_cfg *cfg = irq_cfg + irq;
313 unsigned long flags;
314 unsigned int dest;
315 cpumask_t tmp;
316
317 cpus_and(tmp, mask, cpu_online_map);
318 if (cpus_empty(tmp))
319 return;
320
321 if (assign_irq_vector(irq, mask))
322 return;
323
324 cpus_and(tmp, cfg->domain, mask);
325 dest = cpu_mask_to_apicid(tmp);
326
327 /*
328 * Only the high 8 bits are valid.
329 */
330 dest = SET_APIC_LOGICAL_ID(dest);
331
332 spin_lock_irqsave(&ioapic_lock, flags);
333 __target_IO_APIC_irq(irq, dest, cfg->vector);
334 irq_desc[irq].affinity = mask;
335 spin_unlock_irqrestore(&ioapic_lock, flags);
336 }
337 #endif
338
339 /*
340 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
341 * shared ISA-space IRQs, so we have to support them. We are super
342 * fast in the common case, and fast for shared ISA-space IRQs.
343 */
344 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
345 {
346 static int first_free_entry = NR_IRQS;
347 struct irq_pin_list *entry = irq_2_pin + irq;
348
349 BUG_ON(irq >= NR_IRQS);
350 while (entry->next)
351 entry = irq_2_pin + entry->next;
352
353 if (entry->pin != -1) {
354 entry->next = first_free_entry;
355 entry = irq_2_pin + entry->next;
356 if (++first_free_entry >= PIN_MAP_SIZE)
357 panic("io_apic.c: ran out of irq_2_pin entries!");
358 }
359 entry->apic = apic;
360 entry->pin = pin;
361 }
362
363
364 #define DO_ACTION(name,R,ACTION, FINAL) \
365 \
366 static void name##_IO_APIC_irq (unsigned int irq) \
367 __DO_ACTION(R, ACTION, FINAL)
368
369 /* mask = 1 */
370 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
371
372 /* mask = 0 */
373 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
374
375 static void mask_IO_APIC_irq (unsigned int irq)
376 {
377 unsigned long flags;
378
379 spin_lock_irqsave(&ioapic_lock, flags);
380 __mask_IO_APIC_irq(irq);
381 spin_unlock_irqrestore(&ioapic_lock, flags);
382 }
383
384 static void unmask_IO_APIC_irq (unsigned int irq)
385 {
386 unsigned long flags;
387
388 spin_lock_irqsave(&ioapic_lock, flags);
389 __unmask_IO_APIC_irq(irq);
390 spin_unlock_irqrestore(&ioapic_lock, flags);
391 }
392
393 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
394 {
395 struct IO_APIC_route_entry entry;
396
397 /* Check delivery_mode to be sure we're not clearing an SMI pin */
398 entry = ioapic_read_entry(apic, pin);
399 if (entry.delivery_mode == dest_SMI)
400 return;
401 /*
402 * Disable it in the IO-APIC irq-routing table:
403 */
404 ioapic_mask_entry(apic, pin);
405 }
406
407 static void clear_IO_APIC (void)
408 {
409 int apic, pin;
410
411 for (apic = 0; apic < nr_ioapics; apic++)
412 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
413 clear_IO_APIC_pin(apic, pin);
414 }
415
416 int skip_ioapic_setup;
417 int ioapic_force;
418
419 static int __init parse_noapic(char *str)
420 {
421 disable_ioapic_setup();
422 return 0;
423 }
424 early_param("noapic", parse_noapic);
425
426 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
427 static int __init disable_timer_pin_setup(char *arg)
428 {
429 disable_timer_pin_1 = 1;
430 return 1;
431 }
432 __setup("disable_timer_pin_1", disable_timer_pin_setup);
433
434
435 /*
436 * Find the IRQ entry number of a certain pin.
437 */
438 static int find_irq_entry(int apic, int pin, int type)
439 {
440 int i;
441
442 for (i = 0; i < mp_irq_entries; i++)
443 if (mp_irqs[i].mpc_irqtype == type &&
444 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
445 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
446 mp_irqs[i].mpc_dstirq == pin)
447 return i;
448
449 return -1;
450 }
451
452 /*
453 * Find the pin to which IRQ[irq] (ISA) is connected
454 */
455 static int __init find_isa_irq_pin(int irq, int type)
456 {
457 int i;
458
459 for (i = 0; i < mp_irq_entries; i++) {
460 int lbus = mp_irqs[i].mpc_srcbus;
461
462 if (test_bit(lbus, mp_bus_not_pci) &&
463 (mp_irqs[i].mpc_irqtype == type) &&
464 (mp_irqs[i].mpc_srcbusirq == irq))
465
466 return mp_irqs[i].mpc_dstirq;
467 }
468 return -1;
469 }
470
471 static int __init find_isa_irq_apic(int irq, int type)
472 {
473 int i;
474
475 for (i = 0; i < mp_irq_entries; i++) {
476 int lbus = mp_irqs[i].mpc_srcbus;
477
478 if (test_bit(lbus, mp_bus_not_pci) &&
479 (mp_irqs[i].mpc_irqtype == type) &&
480 (mp_irqs[i].mpc_srcbusirq == irq))
481 break;
482 }
483 if (i < mp_irq_entries) {
484 int apic;
485 for(apic = 0; apic < nr_ioapics; apic++) {
486 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
487 return apic;
488 }
489 }
490
491 return -1;
492 }
493
494 /*
495 * Find a specific PCI IRQ entry.
496 * Not an __init, possibly needed by modules
497 */
498 static int pin_2_irq(int idx, int apic, int pin);
499
500 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
501 {
502 int apic, i, best_guess = -1;
503
504 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
505 bus, slot, pin);
506 if (mp_bus_id_to_pci_bus[bus] == -1) {
507 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
508 return -1;
509 }
510 for (i = 0; i < mp_irq_entries; i++) {
511 int lbus = mp_irqs[i].mpc_srcbus;
512
513 for (apic = 0; apic < nr_ioapics; apic++)
514 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
515 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
516 break;
517
518 if (!test_bit(lbus, mp_bus_not_pci) &&
519 !mp_irqs[i].mpc_irqtype &&
520 (bus == lbus) &&
521 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
522 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
523
524 if (!(apic || IO_APIC_IRQ(irq)))
525 continue;
526
527 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
528 return irq;
529 /*
530 * Use the first all-but-pin matching entry as a
531 * best-guess fuzzy result for broken mptables.
532 */
533 if (best_guess < 0)
534 best_guess = irq;
535 }
536 }
537 BUG_ON(best_guess >= NR_IRQS);
538 return best_guess;
539 }
540
541 /* ISA interrupts are always polarity zero edge triggered,
542 * when listed as conforming in the MP table. */
543
544 #define default_ISA_trigger(idx) (0)
545 #define default_ISA_polarity(idx) (0)
546
547 /* PCI interrupts are always polarity one level triggered,
548 * when listed as conforming in the MP table. */
549
550 #define default_PCI_trigger(idx) (1)
551 #define default_PCI_polarity(idx) (1)
552
553 static int MPBIOS_polarity(int idx)
554 {
555 int bus = mp_irqs[idx].mpc_srcbus;
556 int polarity;
557
558 /*
559 * Determine IRQ line polarity (high active or low active):
560 */
561 switch (mp_irqs[idx].mpc_irqflag & 3)
562 {
563 case 0: /* conforms, ie. bus-type dependent polarity */
564 if (test_bit(bus, mp_bus_not_pci))
565 polarity = default_ISA_polarity(idx);
566 else
567 polarity = default_PCI_polarity(idx);
568 break;
569 case 1: /* high active */
570 {
571 polarity = 0;
572 break;
573 }
574 case 2: /* reserved */
575 {
576 printk(KERN_WARNING "broken BIOS!!\n");
577 polarity = 1;
578 break;
579 }
580 case 3: /* low active */
581 {
582 polarity = 1;
583 break;
584 }
585 default: /* invalid */
586 {
587 printk(KERN_WARNING "broken BIOS!!\n");
588 polarity = 1;
589 break;
590 }
591 }
592 return polarity;
593 }
594
595 static int MPBIOS_trigger(int idx)
596 {
597 int bus = mp_irqs[idx].mpc_srcbus;
598 int trigger;
599
600 /*
601 * Determine IRQ trigger mode (edge or level sensitive):
602 */
603 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
604 {
605 case 0: /* conforms, ie. bus-type dependent */
606 if (test_bit(bus, mp_bus_not_pci))
607 trigger = default_ISA_trigger(idx);
608 else
609 trigger = default_PCI_trigger(idx);
610 break;
611 case 1: /* edge */
612 {
613 trigger = 0;
614 break;
615 }
616 case 2: /* reserved */
617 {
618 printk(KERN_WARNING "broken BIOS!!\n");
619 trigger = 1;
620 break;
621 }
622 case 3: /* level */
623 {
624 trigger = 1;
625 break;
626 }
627 default: /* invalid */
628 {
629 printk(KERN_WARNING "broken BIOS!!\n");
630 trigger = 0;
631 break;
632 }
633 }
634 return trigger;
635 }
636
637 static inline int irq_polarity(int idx)
638 {
639 return MPBIOS_polarity(idx);
640 }
641
642 static inline int irq_trigger(int idx)
643 {
644 return MPBIOS_trigger(idx);
645 }
646
647 static int pin_2_irq(int idx, int apic, int pin)
648 {
649 int irq, i;
650 int bus = mp_irqs[idx].mpc_srcbus;
651
652 /*
653 * Debugging check, we are in big trouble if this message pops up!
654 */
655 if (mp_irqs[idx].mpc_dstirq != pin)
656 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
657
658 if (test_bit(bus, mp_bus_not_pci)) {
659 irq = mp_irqs[idx].mpc_srcbusirq;
660 } else {
661 /*
662 * PCI IRQs are mapped in order
663 */
664 i = irq = 0;
665 while (i < apic)
666 irq += nr_ioapic_registers[i++];
667 irq += pin;
668 }
669 BUG_ON(irq >= NR_IRQS);
670 return irq;
671 }
672
673 static int __assign_irq_vector(int irq, cpumask_t mask)
674 {
675 /*
676 * NOTE! The local APIC isn't very good at handling
677 * multiple interrupts at the same interrupt level.
678 * As the interrupt level is determined by taking the
679 * vector number and shifting that right by 4, we
680 * want to spread these out a bit so that they don't
681 * all fall in the same interrupt level.
682 *
683 * Also, we've got to be careful not to trash gate
684 * 0x80, because int 0x80 is hm, kind of importantish. ;)
685 */
686 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
687 unsigned int old_vector;
688 int cpu;
689 struct irq_cfg *cfg;
690
691 BUG_ON((unsigned)irq >= NR_IRQS);
692 cfg = &irq_cfg[irq];
693
694 /* Only try and allocate irqs on cpus that are present */
695 cpus_and(mask, mask, cpu_online_map);
696
697 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
698 return -EBUSY;
699
700 old_vector = cfg->vector;
701 if (old_vector) {
702 cpumask_t tmp;
703 cpus_and(tmp, cfg->domain, mask);
704 if (!cpus_empty(tmp))
705 return 0;
706 }
707
708 for_each_cpu_mask(cpu, mask) {
709 cpumask_t domain, new_mask;
710 int new_cpu;
711 int vector, offset;
712
713 domain = vector_allocation_domain(cpu);
714 cpus_and(new_mask, domain, cpu_online_map);
715
716 vector = current_vector;
717 offset = current_offset;
718 next:
719 vector += 8;
720 if (vector >= FIRST_SYSTEM_VECTOR) {
721 /* If we run out of vectors on large boxen, must share them. */
722 offset = (offset + 1) % 8;
723 vector = FIRST_DEVICE_VECTOR + offset;
724 }
725 if (unlikely(current_vector == vector))
726 continue;
727 if (vector == IA32_SYSCALL_VECTOR)
728 goto next;
729 for_each_cpu_mask(new_cpu, new_mask)
730 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
731 goto next;
732 /* Found one! */
733 current_vector = vector;
734 current_offset = offset;
735 if (old_vector) {
736 cfg->move_in_progress = 1;
737 cfg->old_domain = cfg->domain;
738 }
739 for_each_cpu_mask(new_cpu, new_mask)
740 per_cpu(vector_irq, new_cpu)[vector] = irq;
741 cfg->vector = vector;
742 cfg->domain = domain;
743 return 0;
744 }
745 return -ENOSPC;
746 }
747
748 static int assign_irq_vector(int irq, cpumask_t mask)
749 {
750 int err;
751 unsigned long flags;
752
753 spin_lock_irqsave(&vector_lock, flags);
754 err = __assign_irq_vector(irq, mask);
755 spin_unlock_irqrestore(&vector_lock, flags);
756 return err;
757 }
758
759 static void __clear_irq_vector(int irq)
760 {
761 struct irq_cfg *cfg;
762 cpumask_t mask;
763 int cpu, vector;
764
765 BUG_ON((unsigned)irq >= NR_IRQS);
766 cfg = &irq_cfg[irq];
767 BUG_ON(!cfg->vector);
768
769 vector = cfg->vector;
770 cpus_and(mask, cfg->domain, cpu_online_map);
771 for_each_cpu_mask(cpu, mask)
772 per_cpu(vector_irq, cpu)[vector] = -1;
773
774 cfg->vector = 0;
775 cpus_clear(cfg->domain);
776 }
777
778 void __setup_vector_irq(int cpu)
779 {
780 /* Initialize vector_irq on a new cpu */
781 /* This function must be called with vector_lock held */
782 int irq, vector;
783
784 /* Mark the inuse vectors */
785 for (irq = 0; irq < NR_IRQS; ++irq) {
786 if (!cpu_isset(cpu, irq_cfg[irq].domain))
787 continue;
788 vector = irq_cfg[irq].vector;
789 per_cpu(vector_irq, cpu)[vector] = irq;
790 }
791 /* Mark the free vectors */
792 for (vector = 0; vector < NR_VECTORS; ++vector) {
793 irq = per_cpu(vector_irq, cpu)[vector];
794 if (irq < 0)
795 continue;
796 if (!cpu_isset(cpu, irq_cfg[irq].domain))
797 per_cpu(vector_irq, cpu)[vector] = -1;
798 }
799 }
800
801
802 static struct irq_chip ioapic_chip;
803
804 static void ioapic_register_intr(int irq, unsigned long trigger)
805 {
806 if (trigger) {
807 irq_desc[irq].status |= IRQ_LEVEL;
808 set_irq_chip_and_handler_name(irq, &ioapic_chip,
809 handle_fasteoi_irq, "fasteoi");
810 } else {
811 irq_desc[irq].status &= ~IRQ_LEVEL;
812 set_irq_chip_and_handler_name(irq, &ioapic_chip,
813 handle_edge_irq, "edge");
814 }
815 }
816
817 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
818 int trigger, int polarity)
819 {
820 struct irq_cfg *cfg = irq_cfg + irq;
821 struct IO_APIC_route_entry entry;
822 cpumask_t mask;
823
824 if (!IO_APIC_IRQ(irq))
825 return;
826
827 mask = TARGET_CPUS;
828 if (assign_irq_vector(irq, mask))
829 return;
830
831 cpus_and(mask, cfg->domain, mask);
832
833 apic_printk(APIC_VERBOSE,KERN_DEBUG
834 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
835 "IRQ %d Mode:%i Active:%i)\n",
836 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
837 irq, trigger, polarity);
838
839 /*
840 * add it to the IO-APIC irq-routing table:
841 */
842 memset(&entry,0,sizeof(entry));
843
844 entry.delivery_mode = INT_DELIVERY_MODE;
845 entry.dest_mode = INT_DEST_MODE;
846 entry.dest = cpu_mask_to_apicid(mask);
847 entry.mask = 0; /* enable IRQ */
848 entry.trigger = trigger;
849 entry.polarity = polarity;
850 entry.vector = cfg->vector;
851
852 /* Mask level triggered irqs.
853 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
854 */
855 if (trigger)
856 entry.mask = 1;
857
858 ioapic_register_intr(irq, trigger);
859 if (irq < 16)
860 disable_8259A_irq(irq);
861
862 ioapic_write_entry(apic, pin, entry);
863 }
864
865 static void __init setup_IO_APIC_irqs(void)
866 {
867 int apic, pin, idx, irq, first_notcon = 1;
868
869 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
870
871 for (apic = 0; apic < nr_ioapics; apic++) {
872 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
873
874 idx = find_irq_entry(apic,pin,mp_INT);
875 if (idx == -1) {
876 if (first_notcon) {
877 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
878 first_notcon = 0;
879 } else
880 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
881 continue;
882 }
883 if (!first_notcon) {
884 apic_printk(APIC_VERBOSE, " not connected.\n");
885 first_notcon = 1;
886 }
887
888 irq = pin_2_irq(idx, apic, pin);
889 add_pin_to_irq(irq, apic, pin);
890
891 setup_IO_APIC_irq(apic, pin, irq,
892 irq_trigger(idx), irq_polarity(idx));
893 }
894 }
895
896 if (!first_notcon)
897 apic_printk(APIC_VERBOSE, " not connected.\n");
898 }
899
900 /*
901 * Set up the timer pin, possibly with the 8259A-master behind.
902 */
903 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
904 int vector)
905 {
906 struct IO_APIC_route_entry entry;
907
908 memset(&entry, 0, sizeof(entry));
909
910 /*
911 * We use logical delivery to get the timer IRQ
912 * to the first CPU.
913 */
914 entry.dest_mode = INT_DEST_MODE;
915 entry.mask = 1; /* mask IRQ now */
916 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
917 entry.delivery_mode = INT_DELIVERY_MODE;
918 entry.polarity = 0;
919 entry.trigger = 0;
920 entry.vector = vector;
921
922 /*
923 * The timer IRQ doesn't have to know that behind the
924 * scene we may have a 8259A-master in AEOI mode ...
925 */
926 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
927
928 /*
929 * Add it to the IO-APIC irq-routing table:
930 */
931 ioapic_write_entry(apic, pin, entry);
932 }
933
934 void __apicdebuginit print_IO_APIC(void)
935 {
936 int apic, i;
937 union IO_APIC_reg_00 reg_00;
938 union IO_APIC_reg_01 reg_01;
939 union IO_APIC_reg_02 reg_02;
940 unsigned long flags;
941
942 if (apic_verbosity == APIC_QUIET)
943 return;
944
945 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
946 for (i = 0; i < nr_ioapics; i++)
947 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
948 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
949
950 /*
951 * We are a bit conservative about what we expect. We have to
952 * know about every hardware change ASAP.
953 */
954 printk(KERN_INFO "testing the IO APIC.......................\n");
955
956 for (apic = 0; apic < nr_ioapics; apic++) {
957
958 spin_lock_irqsave(&ioapic_lock, flags);
959 reg_00.raw = io_apic_read(apic, 0);
960 reg_01.raw = io_apic_read(apic, 1);
961 if (reg_01.bits.version >= 0x10)
962 reg_02.raw = io_apic_read(apic, 2);
963 spin_unlock_irqrestore(&ioapic_lock, flags);
964
965 printk("\n");
966 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
967 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
968 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
969
970 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
971 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
972
973 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
974 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
975
976 if (reg_01.bits.version >= 0x10) {
977 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
978 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
979 }
980
981 printk(KERN_DEBUG ".... IRQ redirection table:\n");
982
983 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
984 " Stat Dmod Deli Vect: \n");
985
986 for (i = 0; i <= reg_01.bits.entries; i++) {
987 struct IO_APIC_route_entry entry;
988
989 entry = ioapic_read_entry(apic, i);
990
991 printk(KERN_DEBUG " %02x %03X ",
992 i,
993 entry.dest
994 );
995
996 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
997 entry.mask,
998 entry.trigger,
999 entry.irr,
1000 entry.polarity,
1001 entry.delivery_status,
1002 entry.dest_mode,
1003 entry.delivery_mode,
1004 entry.vector
1005 );
1006 }
1007 }
1008 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1009 for (i = 0; i < NR_IRQS; i++) {
1010 struct irq_pin_list *entry = irq_2_pin + i;
1011 if (entry->pin < 0)
1012 continue;
1013 printk(KERN_DEBUG "IRQ%d ", i);
1014 for (;;) {
1015 printk("-> %d:%d", entry->apic, entry->pin);
1016 if (!entry->next)
1017 break;
1018 entry = irq_2_pin + entry->next;
1019 }
1020 printk("\n");
1021 }
1022
1023 printk(KERN_INFO ".................................... done.\n");
1024
1025 return;
1026 }
1027
1028 #if 0
1029
1030 static __apicdebuginit void print_APIC_bitfield (int base)
1031 {
1032 unsigned int v;
1033 int i, j;
1034
1035 if (apic_verbosity == APIC_QUIET)
1036 return;
1037
1038 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1039 for (i = 0; i < 8; i++) {
1040 v = apic_read(base + i*0x10);
1041 for (j = 0; j < 32; j++) {
1042 if (v & (1<<j))
1043 printk("1");
1044 else
1045 printk("0");
1046 }
1047 printk("\n");
1048 }
1049 }
1050
1051 void __apicdebuginit print_local_APIC(void * dummy)
1052 {
1053 unsigned int v, ver, maxlvt;
1054
1055 if (apic_verbosity == APIC_QUIET)
1056 return;
1057
1058 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1059 smp_processor_id(), hard_smp_processor_id());
1060 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1061 v = apic_read(APIC_LVR);
1062 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1063 ver = GET_APIC_VERSION(v);
1064 maxlvt = lapic_get_maxlvt();
1065
1066 v = apic_read(APIC_TASKPRI);
1067 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1068
1069 v = apic_read(APIC_ARBPRI);
1070 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1071 v & APIC_ARBPRI_MASK);
1072 v = apic_read(APIC_PROCPRI);
1073 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1074
1075 v = apic_read(APIC_EOI);
1076 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1077 v = apic_read(APIC_RRR);
1078 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1079 v = apic_read(APIC_LDR);
1080 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1081 v = apic_read(APIC_DFR);
1082 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1083 v = apic_read(APIC_SPIV);
1084 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1085
1086 printk(KERN_DEBUG "... APIC ISR field:\n");
1087 print_APIC_bitfield(APIC_ISR);
1088 printk(KERN_DEBUG "... APIC TMR field:\n");
1089 print_APIC_bitfield(APIC_TMR);
1090 printk(KERN_DEBUG "... APIC IRR field:\n");
1091 print_APIC_bitfield(APIC_IRR);
1092
1093 v = apic_read(APIC_ESR);
1094 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1095
1096 v = apic_read(APIC_ICR);
1097 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1098 v = apic_read(APIC_ICR2);
1099 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1100
1101 v = apic_read(APIC_LVTT);
1102 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1103
1104 if (maxlvt > 3) { /* PC is LVT#4. */
1105 v = apic_read(APIC_LVTPC);
1106 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1107 }
1108 v = apic_read(APIC_LVT0);
1109 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1110 v = apic_read(APIC_LVT1);
1111 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1112
1113 if (maxlvt > 2) { /* ERR is LVT#3. */
1114 v = apic_read(APIC_LVTERR);
1115 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1116 }
1117
1118 v = apic_read(APIC_TMICT);
1119 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1120 v = apic_read(APIC_TMCCT);
1121 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1122 v = apic_read(APIC_TDCR);
1123 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1124 printk("\n");
1125 }
1126
1127 void print_all_local_APICs (void)
1128 {
1129 on_each_cpu(print_local_APIC, NULL, 1, 1);
1130 }
1131
1132 void __apicdebuginit print_PIC(void)
1133 {
1134 unsigned int v;
1135 unsigned long flags;
1136
1137 if (apic_verbosity == APIC_QUIET)
1138 return;
1139
1140 printk(KERN_DEBUG "\nprinting PIC contents\n");
1141
1142 spin_lock_irqsave(&i8259A_lock, flags);
1143
1144 v = inb(0xa1) << 8 | inb(0x21);
1145 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1146
1147 v = inb(0xa0) << 8 | inb(0x20);
1148 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1149
1150 outb(0x0b,0xa0);
1151 outb(0x0b,0x20);
1152 v = inb(0xa0) << 8 | inb(0x20);
1153 outb(0x0a,0xa0);
1154 outb(0x0a,0x20);
1155
1156 spin_unlock_irqrestore(&i8259A_lock, flags);
1157
1158 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1159
1160 v = inb(0x4d1) << 8 | inb(0x4d0);
1161 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1162 }
1163
1164 #endif /* 0 */
1165
1166 void __init enable_IO_APIC(void)
1167 {
1168 union IO_APIC_reg_01 reg_01;
1169 int i8259_apic, i8259_pin;
1170 int i, apic;
1171 unsigned long flags;
1172
1173 for (i = 0; i < PIN_MAP_SIZE; i++) {
1174 irq_2_pin[i].pin = -1;
1175 irq_2_pin[i].next = 0;
1176 }
1177
1178 /*
1179 * The number of IO-APIC IRQ registers (== #pins):
1180 */
1181 for (apic = 0; apic < nr_ioapics; apic++) {
1182 spin_lock_irqsave(&ioapic_lock, flags);
1183 reg_01.raw = io_apic_read(apic, 1);
1184 spin_unlock_irqrestore(&ioapic_lock, flags);
1185 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1186 }
1187 for(apic = 0; apic < nr_ioapics; apic++) {
1188 int pin;
1189 /* See if any of the pins is in ExtINT mode */
1190 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1191 struct IO_APIC_route_entry entry;
1192 entry = ioapic_read_entry(apic, pin);
1193
1194 /* If the interrupt line is enabled and in ExtInt mode
1195 * I have found the pin where the i8259 is connected.
1196 */
1197 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1198 ioapic_i8259.apic = apic;
1199 ioapic_i8259.pin = pin;
1200 goto found_i8259;
1201 }
1202 }
1203 }
1204 found_i8259:
1205 /* Look to see what if the MP table has reported the ExtINT */
1206 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1207 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1208 /* Trust the MP table if nothing is setup in the hardware */
1209 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1210 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1211 ioapic_i8259.pin = i8259_pin;
1212 ioapic_i8259.apic = i8259_apic;
1213 }
1214 /* Complain if the MP table and the hardware disagree */
1215 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1216 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1217 {
1218 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1219 }
1220
1221 /*
1222 * Do not trust the IO-APIC being empty at bootup
1223 */
1224 clear_IO_APIC();
1225 }
1226
1227 /*
1228 * Not an __init, needed by the reboot code
1229 */
1230 void disable_IO_APIC(void)
1231 {
1232 /*
1233 * Clear the IO-APIC before rebooting:
1234 */
1235 clear_IO_APIC();
1236
1237 /*
1238 * If the i8259 is routed through an IOAPIC
1239 * Put that IOAPIC in virtual wire mode
1240 * so legacy interrupts can be delivered.
1241 */
1242 if (ioapic_i8259.pin != -1) {
1243 struct IO_APIC_route_entry entry;
1244
1245 memset(&entry, 0, sizeof(entry));
1246 entry.mask = 0; /* Enabled */
1247 entry.trigger = 0; /* Edge */
1248 entry.irr = 0;
1249 entry.polarity = 0; /* High */
1250 entry.delivery_status = 0;
1251 entry.dest_mode = 0; /* Physical */
1252 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1253 entry.vector = 0;
1254 entry.dest = GET_APIC_ID(read_apic_id());
1255
1256 /*
1257 * Add it to the IO-APIC irq-routing table:
1258 */
1259 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1260 }
1261
1262 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1263 }
1264
1265 /*
1266 * There is a nasty bug in some older SMP boards, their mptable lies
1267 * about the timer IRQ. We do the following to work around the situation:
1268 *
1269 * - timer IRQ defaults to IO-APIC IRQ
1270 * - if this function detects that timer IRQs are defunct, then we fall
1271 * back to ISA timer IRQs
1272 */
1273 static int __init timer_irq_works(void)
1274 {
1275 unsigned long t1 = jiffies;
1276 unsigned long flags;
1277
1278 local_save_flags(flags);
1279 local_irq_enable();
1280 /* Let ten ticks pass... */
1281 mdelay((10 * 1000) / HZ);
1282 local_irq_restore(flags);
1283
1284 /*
1285 * Expect a few ticks at least, to be sure some possible
1286 * glue logic does not lock up after one or two first
1287 * ticks in a non-ExtINT mode. Also the local APIC
1288 * might have cached one ExtINT interrupt. Finally, at
1289 * least one tick may be lost due to delays.
1290 */
1291
1292 /* jiffies wrap? */
1293 if (time_after(jiffies, t1 + 4))
1294 return 1;
1295 return 0;
1296 }
1297
1298 /*
1299 * In the SMP+IOAPIC case it might happen that there are an unspecified
1300 * number of pending IRQ events unhandled. These cases are very rare,
1301 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1302 * better to do it this way as thus we do not have to be aware of
1303 * 'pending' interrupts in the IRQ path, except at this point.
1304 */
1305 /*
1306 * Edge triggered needs to resend any interrupt
1307 * that was delayed but this is now handled in the device
1308 * independent code.
1309 */
1310
1311 /*
1312 * Starting up a edge-triggered IO-APIC interrupt is
1313 * nasty - we need to make sure that we get the edge.
1314 * If it is already asserted for some reason, we need
1315 * return 1 to indicate that is was pending.
1316 *
1317 * This is not complete - we should be able to fake
1318 * an edge even if it isn't on the 8259A...
1319 */
1320
1321 static unsigned int startup_ioapic_irq(unsigned int irq)
1322 {
1323 int was_pending = 0;
1324 unsigned long flags;
1325
1326 spin_lock_irqsave(&ioapic_lock, flags);
1327 if (irq < 16) {
1328 disable_8259A_irq(irq);
1329 if (i8259A_irq_pending(irq))
1330 was_pending = 1;
1331 }
1332 __unmask_IO_APIC_irq(irq);
1333 spin_unlock_irqrestore(&ioapic_lock, flags);
1334
1335 return was_pending;
1336 }
1337
1338 static int ioapic_retrigger_irq(unsigned int irq)
1339 {
1340 struct irq_cfg *cfg = &irq_cfg[irq];
1341 cpumask_t mask;
1342 unsigned long flags;
1343
1344 spin_lock_irqsave(&vector_lock, flags);
1345 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1346 send_IPI_mask(mask, cfg->vector);
1347 spin_unlock_irqrestore(&vector_lock, flags);
1348
1349 return 1;
1350 }
1351
1352 /*
1353 * Level and edge triggered IO-APIC interrupts need different handling,
1354 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1355 * handled with the level-triggered descriptor, but that one has slightly
1356 * more overhead. Level-triggered interrupts cannot be handled with the
1357 * edge-triggered handler, without risking IRQ storms and other ugly
1358 * races.
1359 */
1360
1361 #ifdef CONFIG_SMP
1362 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1363 {
1364 unsigned vector, me;
1365 ack_APIC_irq();
1366 exit_idle();
1367 irq_enter();
1368
1369 me = smp_processor_id();
1370 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1371 unsigned int irq;
1372 struct irq_desc *desc;
1373 struct irq_cfg *cfg;
1374 irq = __get_cpu_var(vector_irq)[vector];
1375 if (irq >= NR_IRQS)
1376 continue;
1377
1378 desc = irq_desc + irq;
1379 cfg = irq_cfg + irq;
1380 spin_lock(&desc->lock);
1381 if (!cfg->move_cleanup_count)
1382 goto unlock;
1383
1384 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1385 goto unlock;
1386
1387 __get_cpu_var(vector_irq)[vector] = -1;
1388 cfg->move_cleanup_count--;
1389 unlock:
1390 spin_unlock(&desc->lock);
1391 }
1392
1393 irq_exit();
1394 }
1395
1396 static void irq_complete_move(unsigned int irq)
1397 {
1398 struct irq_cfg *cfg = irq_cfg + irq;
1399 unsigned vector, me;
1400
1401 if (likely(!cfg->move_in_progress))
1402 return;
1403
1404 vector = ~get_irq_regs()->orig_ax;
1405 me = smp_processor_id();
1406 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1407 cpumask_t cleanup_mask;
1408
1409 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1410 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1411 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1412 cfg->move_in_progress = 0;
1413 }
1414 }
1415 #else
1416 static inline void irq_complete_move(unsigned int irq) {}
1417 #endif
1418
1419 static void ack_apic_edge(unsigned int irq)
1420 {
1421 irq_complete_move(irq);
1422 move_native_irq(irq);
1423 ack_APIC_irq();
1424 }
1425
1426 static void ack_apic_level(unsigned int irq)
1427 {
1428 int do_unmask_irq = 0;
1429
1430 irq_complete_move(irq);
1431 #ifdef CONFIG_GENERIC_PENDING_IRQ
1432 /* If we are moving the irq we need to mask it */
1433 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1434 do_unmask_irq = 1;
1435 mask_IO_APIC_irq(irq);
1436 }
1437 #endif
1438
1439 /*
1440 * We must acknowledge the irq before we move it or the acknowledge will
1441 * not propagate properly.
1442 */
1443 ack_APIC_irq();
1444
1445 /* Now we can move and renable the irq */
1446 if (unlikely(do_unmask_irq)) {
1447 /* Only migrate the irq if the ack has been received.
1448 *
1449 * On rare occasions the broadcast level triggered ack gets
1450 * delayed going to ioapics, and if we reprogram the
1451 * vector while Remote IRR is still set the irq will never
1452 * fire again.
1453 *
1454 * To prevent this scenario we read the Remote IRR bit
1455 * of the ioapic. This has two effects.
1456 * - On any sane system the read of the ioapic will
1457 * flush writes (and acks) going to the ioapic from
1458 * this cpu.
1459 * - We get to see if the ACK has actually been delivered.
1460 *
1461 * Based on failed experiments of reprogramming the
1462 * ioapic entry from outside of irq context starting
1463 * with masking the ioapic entry and then polling until
1464 * Remote IRR was clear before reprogramming the
1465 * ioapic I don't trust the Remote IRR bit to be
1466 * completey accurate.
1467 *
1468 * However there appears to be no other way to plug
1469 * this race, so if the Remote IRR bit is not
1470 * accurate and is causing problems then it is a hardware bug
1471 * and you can go talk to the chipset vendor about it.
1472 */
1473 if (!io_apic_level_ack_pending(irq))
1474 move_masked_irq(irq);
1475 unmask_IO_APIC_irq(irq);
1476 }
1477 }
1478
1479 static struct irq_chip ioapic_chip __read_mostly = {
1480 .name = "IO-APIC",
1481 .startup = startup_ioapic_irq,
1482 .mask = mask_IO_APIC_irq,
1483 .unmask = unmask_IO_APIC_irq,
1484 .ack = ack_apic_edge,
1485 .eoi = ack_apic_level,
1486 #ifdef CONFIG_SMP
1487 .set_affinity = set_ioapic_affinity_irq,
1488 #endif
1489 .retrigger = ioapic_retrigger_irq,
1490 };
1491
1492 static inline void init_IO_APIC_traps(void)
1493 {
1494 int irq;
1495
1496 /*
1497 * NOTE! The local APIC isn't very good at handling
1498 * multiple interrupts at the same interrupt level.
1499 * As the interrupt level is determined by taking the
1500 * vector number and shifting that right by 4, we
1501 * want to spread these out a bit so that they don't
1502 * all fall in the same interrupt level.
1503 *
1504 * Also, we've got to be careful not to trash gate
1505 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1506 */
1507 for (irq = 0; irq < NR_IRQS ; irq++) {
1508 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1509 /*
1510 * Hmm.. We don't have an entry for this,
1511 * so default to an old-fashioned 8259
1512 * interrupt if we can..
1513 */
1514 if (irq < 16)
1515 make_8259A_irq(irq);
1516 else
1517 /* Strange. Oh, well.. */
1518 irq_desc[irq].chip = &no_irq_chip;
1519 }
1520 }
1521 }
1522
1523 static void enable_lapic_irq (unsigned int irq)
1524 {
1525 unsigned long v;
1526
1527 v = apic_read(APIC_LVT0);
1528 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1529 }
1530
1531 static void disable_lapic_irq (unsigned int irq)
1532 {
1533 unsigned long v;
1534
1535 v = apic_read(APIC_LVT0);
1536 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1537 }
1538
1539 static void ack_lapic_irq (unsigned int irq)
1540 {
1541 ack_APIC_irq();
1542 }
1543
1544 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1545
1546 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1547 .name = "local-APIC",
1548 .typename = "local-APIC-edge",
1549 .startup = NULL, /* startup_irq() not used for IRQ0 */
1550 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1551 .enable = enable_lapic_irq,
1552 .disable = disable_lapic_irq,
1553 .ack = ack_lapic_irq,
1554 .end = end_lapic_irq,
1555 };
1556
1557 static void __init setup_nmi(void)
1558 {
1559 /*
1560 * Dirty trick to enable the NMI watchdog ...
1561 * We put the 8259A master into AEOI mode and
1562 * unmask on all local APICs LVT0 as NMI.
1563 *
1564 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1565 * is from Maciej W. Rozycki - so we do not have to EOI from
1566 * the NMI handler or the timer interrupt.
1567 */
1568 printk(KERN_INFO "activating NMI Watchdog ...");
1569
1570 enable_NMI_through_LVT0();
1571
1572 printk(" done.\n");
1573 }
1574
1575 /*
1576 * This looks a bit hackish but it's about the only one way of sending
1577 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1578 * not support the ExtINT mode, unfortunately. We need to send these
1579 * cycles as some i82489DX-based boards have glue logic that keeps the
1580 * 8259A interrupt line asserted until INTA. --macro
1581 */
1582 static inline void __init unlock_ExtINT_logic(void)
1583 {
1584 int apic, pin, i;
1585 struct IO_APIC_route_entry entry0, entry1;
1586 unsigned char save_control, save_freq_select;
1587
1588 pin = find_isa_irq_pin(8, mp_INT);
1589 apic = find_isa_irq_apic(8, mp_INT);
1590 if (pin == -1)
1591 return;
1592
1593 entry0 = ioapic_read_entry(apic, pin);
1594
1595 clear_IO_APIC_pin(apic, pin);
1596
1597 memset(&entry1, 0, sizeof(entry1));
1598
1599 entry1.dest_mode = 0; /* physical delivery */
1600 entry1.mask = 0; /* unmask IRQ now */
1601 entry1.dest = hard_smp_processor_id();
1602 entry1.delivery_mode = dest_ExtINT;
1603 entry1.polarity = entry0.polarity;
1604 entry1.trigger = 0;
1605 entry1.vector = 0;
1606
1607 ioapic_write_entry(apic, pin, entry1);
1608
1609 save_control = CMOS_READ(RTC_CONTROL);
1610 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1611 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1612 RTC_FREQ_SELECT);
1613 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1614
1615 i = 100;
1616 while (i-- > 0) {
1617 mdelay(10);
1618 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1619 i -= 10;
1620 }
1621
1622 CMOS_WRITE(save_control, RTC_CONTROL);
1623 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1624 clear_IO_APIC_pin(apic, pin);
1625
1626 ioapic_write_entry(apic, pin, entry0);
1627 }
1628
1629 /*
1630 * This code may look a bit paranoid, but it's supposed to cooperate with
1631 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1632 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1633 * fanatically on his truly buggy board.
1634 *
1635 * FIXME: really need to revamp this for modern platforms only.
1636 */
1637 static inline void __init check_timer(void)
1638 {
1639 struct irq_cfg *cfg = irq_cfg + 0;
1640 int apic1, pin1, apic2, pin2;
1641 unsigned long flags;
1642 int no_pin1 = 0;
1643
1644 local_irq_save(flags);
1645
1646 /*
1647 * get/set the timer IRQ vector:
1648 */
1649 disable_8259A_irq(0);
1650 assign_irq_vector(0, TARGET_CPUS);
1651
1652 /*
1653 * As IRQ0 is to be enabled in the 8259A, the virtual
1654 * wire has to be disabled in the local APIC.
1655 */
1656 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1657 init_8259A(1);
1658
1659 pin1 = find_isa_irq_pin(0, mp_INT);
1660 apic1 = find_isa_irq_apic(0, mp_INT);
1661 pin2 = ioapic_i8259.pin;
1662 apic2 = ioapic_i8259.apic;
1663
1664 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1665 cfg->vector, apic1, pin1, apic2, pin2);
1666
1667 /*
1668 * Some BIOS writers are clueless and report the ExtINTA
1669 * I/O APIC input from the cascaded 8259A as the timer
1670 * interrupt input. So just in case, if only one pin
1671 * was found above, try it both directly and through the
1672 * 8259A.
1673 */
1674 if (pin1 == -1) {
1675 pin1 = pin2;
1676 apic1 = apic2;
1677 no_pin1 = 1;
1678 } else if (pin2 == -1) {
1679 pin2 = pin1;
1680 apic2 = apic1;
1681 }
1682
1683 if (pin1 != -1) {
1684 /*
1685 * Ok, does IRQ0 through the IOAPIC work?
1686 */
1687 if (no_pin1) {
1688 add_pin_to_irq(0, apic1, pin1);
1689 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1690 }
1691 unmask_IO_APIC_irq(0);
1692 if (!no_timer_check && timer_irq_works()) {
1693 nmi_watchdog_default();
1694 if (nmi_watchdog == NMI_IO_APIC) {
1695 setup_nmi();
1696 enable_8259A_irq(0);
1697 }
1698 if (disable_timer_pin_1 > 0)
1699 clear_IO_APIC_pin(0, pin1);
1700 goto out;
1701 }
1702 clear_IO_APIC_pin(apic1, pin1);
1703 if (!no_pin1)
1704 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1705 "8254 timer not connected to IO-APIC\n");
1706
1707 apic_printk(APIC_VERBOSE,KERN_INFO
1708 "...trying to set up timer (IRQ0) "
1709 "through the 8259A ... ");
1710 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1711 apic2, pin2);
1712 /*
1713 * legacy devices should be connected to IO APIC #0
1714 */
1715 /* replace_pin_at_irq(0, apic1, pin1, apic2, pin2); */
1716 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1717 unmask_IO_APIC_irq(0);
1718 enable_8259A_irq(0);
1719 if (timer_irq_works()) {
1720 apic_printk(APIC_VERBOSE," works.\n");
1721 timer_through_8259 = 1;
1722 nmi_watchdog_default();
1723 if (nmi_watchdog == NMI_IO_APIC) {
1724 disable_8259A_irq(0);
1725 setup_nmi();
1726 enable_8259A_irq(0);
1727 }
1728 goto out;
1729 }
1730 /*
1731 * Cleanup, just in case ...
1732 */
1733 disable_8259A_irq(0);
1734 clear_IO_APIC_pin(apic2, pin2);
1735 apic_printk(APIC_VERBOSE," failed.\n");
1736 }
1737
1738 if (nmi_watchdog == NMI_IO_APIC) {
1739 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1740 nmi_watchdog = NMI_NONE;
1741 }
1742
1743 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1744
1745 irq_desc[0].chip = &lapic_irq_type;
1746 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1747 enable_8259A_irq(0);
1748
1749 if (timer_irq_works()) {
1750 apic_printk(APIC_VERBOSE," works.\n");
1751 goto out;
1752 }
1753 disable_8259A_irq(0);
1754 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1755 apic_printk(APIC_VERBOSE," failed.\n");
1756
1757 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1758
1759 init_8259A(0);
1760 make_8259A_irq(0);
1761 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1762
1763 unlock_ExtINT_logic();
1764
1765 if (timer_irq_works()) {
1766 apic_printk(APIC_VERBOSE," works.\n");
1767 goto out;
1768 }
1769 apic_printk(APIC_VERBOSE," failed :(.\n");
1770 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1771 out:
1772 local_irq_restore(flags);
1773 }
1774
1775 static int __init notimercheck(char *s)
1776 {
1777 no_timer_check = 1;
1778 return 1;
1779 }
1780 __setup("no_timer_check", notimercheck);
1781
1782 /*
1783 *
1784 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1785 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1786 * Linux doesn't really care, as it's not actually used
1787 * for any interrupt handling anyway.
1788 */
1789 #define PIC_IRQS (1<<2)
1790
1791 void __init setup_IO_APIC(void)
1792 {
1793
1794 /*
1795 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1796 */
1797
1798 if (acpi_ioapic)
1799 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1800 else
1801 io_apic_irqs = ~PIC_IRQS;
1802
1803 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1804
1805 sync_Arb_IDs();
1806 setup_IO_APIC_irqs();
1807 init_IO_APIC_traps();
1808 check_timer();
1809 if (!acpi_ioapic)
1810 print_IO_APIC();
1811 }
1812
1813 struct sysfs_ioapic_data {
1814 struct sys_device dev;
1815 struct IO_APIC_route_entry entry[0];
1816 };
1817 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1818
1819 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1820 {
1821 struct IO_APIC_route_entry *entry;
1822 struct sysfs_ioapic_data *data;
1823 int i;
1824
1825 data = container_of(dev, struct sysfs_ioapic_data, dev);
1826 entry = data->entry;
1827 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1828 *entry = ioapic_read_entry(dev->id, i);
1829
1830 return 0;
1831 }
1832
1833 static int ioapic_resume(struct sys_device *dev)
1834 {
1835 struct IO_APIC_route_entry *entry;
1836 struct sysfs_ioapic_data *data;
1837 unsigned long flags;
1838 union IO_APIC_reg_00 reg_00;
1839 int i;
1840
1841 data = container_of(dev, struct sysfs_ioapic_data, dev);
1842 entry = data->entry;
1843
1844 spin_lock_irqsave(&ioapic_lock, flags);
1845 reg_00.raw = io_apic_read(dev->id, 0);
1846 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1847 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1848 io_apic_write(dev->id, 0, reg_00.raw);
1849 }
1850 spin_unlock_irqrestore(&ioapic_lock, flags);
1851 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1852 ioapic_write_entry(dev->id, i, entry[i]);
1853
1854 return 0;
1855 }
1856
1857 static struct sysdev_class ioapic_sysdev_class = {
1858 .name = "ioapic",
1859 .suspend = ioapic_suspend,
1860 .resume = ioapic_resume,
1861 };
1862
1863 static int __init ioapic_init_sysfs(void)
1864 {
1865 struct sys_device * dev;
1866 int i, size, error;
1867
1868 error = sysdev_class_register(&ioapic_sysdev_class);
1869 if (error)
1870 return error;
1871
1872 for (i = 0; i < nr_ioapics; i++ ) {
1873 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1874 * sizeof(struct IO_APIC_route_entry);
1875 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1876 if (!mp_ioapic_data[i]) {
1877 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1878 continue;
1879 }
1880 dev = &mp_ioapic_data[i]->dev;
1881 dev->id = i;
1882 dev->cls = &ioapic_sysdev_class;
1883 error = sysdev_register(dev);
1884 if (error) {
1885 kfree(mp_ioapic_data[i]);
1886 mp_ioapic_data[i] = NULL;
1887 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1888 continue;
1889 }
1890 }
1891
1892 return 0;
1893 }
1894
1895 device_initcall(ioapic_init_sysfs);
1896
1897 /*
1898 * Dynamic irq allocate and deallocation
1899 */
1900 int create_irq(void)
1901 {
1902 /* Allocate an unused irq */
1903 int irq;
1904 int new;
1905 unsigned long flags;
1906
1907 irq = -ENOSPC;
1908 spin_lock_irqsave(&vector_lock, flags);
1909 for (new = (NR_IRQS - 1); new >= 0; new--) {
1910 if (platform_legacy_irq(new))
1911 continue;
1912 if (irq_cfg[new].vector != 0)
1913 continue;
1914 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1915 irq = new;
1916 break;
1917 }
1918 spin_unlock_irqrestore(&vector_lock, flags);
1919
1920 if (irq >= 0) {
1921 dynamic_irq_init(irq);
1922 }
1923 return irq;
1924 }
1925
1926 void destroy_irq(unsigned int irq)
1927 {
1928 unsigned long flags;
1929
1930 dynamic_irq_cleanup(irq);
1931
1932 spin_lock_irqsave(&vector_lock, flags);
1933 __clear_irq_vector(irq);
1934 spin_unlock_irqrestore(&vector_lock, flags);
1935 }
1936
1937 /*
1938 * MSI message composition
1939 */
1940 #ifdef CONFIG_PCI_MSI
1941 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1942 {
1943 struct irq_cfg *cfg = irq_cfg + irq;
1944 int err;
1945 unsigned dest;
1946 cpumask_t tmp;
1947
1948 tmp = TARGET_CPUS;
1949 err = assign_irq_vector(irq, tmp);
1950 if (!err) {
1951 cpus_and(tmp, cfg->domain, tmp);
1952 dest = cpu_mask_to_apicid(tmp);
1953
1954 msg->address_hi = MSI_ADDR_BASE_HI;
1955 msg->address_lo =
1956 MSI_ADDR_BASE_LO |
1957 ((INT_DEST_MODE == 0) ?
1958 MSI_ADDR_DEST_MODE_PHYSICAL:
1959 MSI_ADDR_DEST_MODE_LOGICAL) |
1960 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1961 MSI_ADDR_REDIRECTION_CPU:
1962 MSI_ADDR_REDIRECTION_LOWPRI) |
1963 MSI_ADDR_DEST_ID(dest);
1964
1965 msg->data =
1966 MSI_DATA_TRIGGER_EDGE |
1967 MSI_DATA_LEVEL_ASSERT |
1968 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1969 MSI_DATA_DELIVERY_FIXED:
1970 MSI_DATA_DELIVERY_LOWPRI) |
1971 MSI_DATA_VECTOR(cfg->vector);
1972 }
1973 return err;
1974 }
1975
1976 #ifdef CONFIG_SMP
1977 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1978 {
1979 struct irq_cfg *cfg = irq_cfg + irq;
1980 struct msi_msg msg;
1981 unsigned int dest;
1982 cpumask_t tmp;
1983
1984 cpus_and(tmp, mask, cpu_online_map);
1985 if (cpus_empty(tmp))
1986 return;
1987
1988 if (assign_irq_vector(irq, mask))
1989 return;
1990
1991 cpus_and(tmp, cfg->domain, mask);
1992 dest = cpu_mask_to_apicid(tmp);
1993
1994 read_msi_msg(irq, &msg);
1995
1996 msg.data &= ~MSI_DATA_VECTOR_MASK;
1997 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1998 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1999 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2000
2001 write_msi_msg(irq, &msg);
2002 irq_desc[irq].affinity = mask;
2003 }
2004 #endif /* CONFIG_SMP */
2005
2006 /*
2007 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2008 * which implement the MSI or MSI-X Capability Structure.
2009 */
2010 static struct irq_chip msi_chip = {
2011 .name = "PCI-MSI",
2012 .unmask = unmask_msi_irq,
2013 .mask = mask_msi_irq,
2014 .ack = ack_apic_edge,
2015 #ifdef CONFIG_SMP
2016 .set_affinity = set_msi_irq_affinity,
2017 #endif
2018 .retrigger = ioapic_retrigger_irq,
2019 };
2020
2021 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2022 {
2023 struct msi_msg msg;
2024 int irq, ret;
2025 irq = create_irq();
2026 if (irq < 0)
2027 return irq;
2028
2029 ret = msi_compose_msg(dev, irq, &msg);
2030 if (ret < 0) {
2031 destroy_irq(irq);
2032 return ret;
2033 }
2034
2035 set_irq_msi(irq, desc);
2036 write_msi_msg(irq, &msg);
2037
2038 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2039
2040 return 0;
2041 }
2042
2043 void arch_teardown_msi_irq(unsigned int irq)
2044 {
2045 destroy_irq(irq);
2046 }
2047
2048 #ifdef CONFIG_DMAR
2049 #ifdef CONFIG_SMP
2050 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2051 {
2052 struct irq_cfg *cfg = irq_cfg + irq;
2053 struct msi_msg msg;
2054 unsigned int dest;
2055 cpumask_t tmp;
2056
2057 cpus_and(tmp, mask, cpu_online_map);
2058 if (cpus_empty(tmp))
2059 return;
2060
2061 if (assign_irq_vector(irq, mask))
2062 return;
2063
2064 cpus_and(tmp, cfg->domain, mask);
2065 dest = cpu_mask_to_apicid(tmp);
2066
2067 dmar_msi_read(irq, &msg);
2068
2069 msg.data &= ~MSI_DATA_VECTOR_MASK;
2070 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2071 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2072 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2073
2074 dmar_msi_write(irq, &msg);
2075 irq_desc[irq].affinity = mask;
2076 }
2077 #endif /* CONFIG_SMP */
2078
2079 struct irq_chip dmar_msi_type = {
2080 .name = "DMAR_MSI",
2081 .unmask = dmar_msi_unmask,
2082 .mask = dmar_msi_mask,
2083 .ack = ack_apic_edge,
2084 #ifdef CONFIG_SMP
2085 .set_affinity = dmar_msi_set_affinity,
2086 #endif
2087 .retrigger = ioapic_retrigger_irq,
2088 };
2089
2090 int arch_setup_dmar_msi(unsigned int irq)
2091 {
2092 int ret;
2093 struct msi_msg msg;
2094
2095 ret = msi_compose_msg(NULL, irq, &msg);
2096 if (ret < 0)
2097 return ret;
2098 dmar_msi_write(irq, &msg);
2099 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2100 "edge");
2101 return 0;
2102 }
2103 #endif
2104
2105 #endif /* CONFIG_PCI_MSI */
2106 /*
2107 * Hypertransport interrupt support
2108 */
2109 #ifdef CONFIG_HT_IRQ
2110
2111 #ifdef CONFIG_SMP
2112
2113 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2114 {
2115 struct ht_irq_msg msg;
2116 fetch_ht_irq_msg(irq, &msg);
2117
2118 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2119 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2120
2121 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2122 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2123
2124 write_ht_irq_msg(irq, &msg);
2125 }
2126
2127 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2128 {
2129 struct irq_cfg *cfg = irq_cfg + irq;
2130 unsigned int dest;
2131 cpumask_t tmp;
2132
2133 cpus_and(tmp, mask, cpu_online_map);
2134 if (cpus_empty(tmp))
2135 return;
2136
2137 if (assign_irq_vector(irq, mask))
2138 return;
2139
2140 cpus_and(tmp, cfg->domain, mask);
2141 dest = cpu_mask_to_apicid(tmp);
2142
2143 target_ht_irq(irq, dest, cfg->vector);
2144 irq_desc[irq].affinity = mask;
2145 }
2146 #endif
2147
2148 static struct irq_chip ht_irq_chip = {
2149 .name = "PCI-HT",
2150 .mask = mask_ht_irq,
2151 .unmask = unmask_ht_irq,
2152 .ack = ack_apic_edge,
2153 #ifdef CONFIG_SMP
2154 .set_affinity = set_ht_irq_affinity,
2155 #endif
2156 .retrigger = ioapic_retrigger_irq,
2157 };
2158
2159 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2160 {
2161 struct irq_cfg *cfg = irq_cfg + irq;
2162 int err;
2163 cpumask_t tmp;
2164
2165 tmp = TARGET_CPUS;
2166 err = assign_irq_vector(irq, tmp);
2167 if (!err) {
2168 struct ht_irq_msg msg;
2169 unsigned dest;
2170
2171 cpus_and(tmp, cfg->domain, tmp);
2172 dest = cpu_mask_to_apicid(tmp);
2173
2174 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2175
2176 msg.address_lo =
2177 HT_IRQ_LOW_BASE |
2178 HT_IRQ_LOW_DEST_ID(dest) |
2179 HT_IRQ_LOW_VECTOR(cfg->vector) |
2180 ((INT_DEST_MODE == 0) ?
2181 HT_IRQ_LOW_DM_PHYSICAL :
2182 HT_IRQ_LOW_DM_LOGICAL) |
2183 HT_IRQ_LOW_RQEOI_EDGE |
2184 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2185 HT_IRQ_LOW_MT_FIXED :
2186 HT_IRQ_LOW_MT_ARBITRATED) |
2187 HT_IRQ_LOW_IRQ_MASKED;
2188
2189 write_ht_irq_msg(irq, &msg);
2190
2191 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2192 handle_edge_irq, "edge");
2193 }
2194 return err;
2195 }
2196 #endif /* CONFIG_HT_IRQ */
2197
2198 /* --------------------------------------------------------------------------
2199 ACPI-based IOAPIC Configuration
2200 -------------------------------------------------------------------------- */
2201
2202 #ifdef CONFIG_ACPI
2203
2204 #define IO_APIC_MAX_ID 0xFE
2205
2206 int __init io_apic_get_redir_entries (int ioapic)
2207 {
2208 union IO_APIC_reg_01 reg_01;
2209 unsigned long flags;
2210
2211 spin_lock_irqsave(&ioapic_lock, flags);
2212 reg_01.raw = io_apic_read(ioapic, 1);
2213 spin_unlock_irqrestore(&ioapic_lock, flags);
2214
2215 return reg_01.bits.entries;
2216 }
2217
2218
2219 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2220 {
2221 if (!IO_APIC_IRQ(irq)) {
2222 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2223 ioapic);
2224 return -EINVAL;
2225 }
2226
2227 /*
2228 * IRQs < 16 are already in the irq_2_pin[] map
2229 */
2230 if (irq >= 16)
2231 add_pin_to_irq(irq, ioapic, pin);
2232
2233 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2234
2235 return 0;
2236 }
2237
2238
2239 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2240 {
2241 int i;
2242
2243 if (skip_ioapic_setup)
2244 return -1;
2245
2246 for (i = 0; i < mp_irq_entries; i++)
2247 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2248 mp_irqs[i].mpc_srcbusirq == bus_irq)
2249 break;
2250 if (i >= mp_irq_entries)
2251 return -1;
2252
2253 *trigger = irq_trigger(i);
2254 *polarity = irq_polarity(i);
2255 return 0;
2256 }
2257
2258 #endif /* CONFIG_ACPI */
2259
2260 /*
2261 * This function currently is only a helper for the i386 smp boot process where
2262 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2263 * so mask in all cases should simply be TARGET_CPUS
2264 */
2265 #ifdef CONFIG_SMP
2266 void __init setup_ioapic_dest(void)
2267 {
2268 int pin, ioapic, irq, irq_entry;
2269
2270 if (skip_ioapic_setup == 1)
2271 return;
2272
2273 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2274 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2275 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2276 if (irq_entry == -1)
2277 continue;
2278 irq = pin_2_irq(irq_entry, ioapic, pin);
2279
2280 /* setup_IO_APIC_irqs could fail to get vector for some device
2281 * when you have too many devices, because at that time only boot
2282 * cpu is online.
2283 */
2284 if (!irq_cfg[irq].vector)
2285 setup_IO_APIC_irq(ioapic, pin, irq,
2286 irq_trigger(irq_entry),
2287 irq_polarity(irq_entry));
2288 else
2289 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2290 }
2291
2292 }
2293 }
2294 #endif
2295
2296 #define IOAPIC_RESOURCE_NAME_SIZE 11
2297
2298 static struct resource *ioapic_resources;
2299
2300 static struct resource * __init ioapic_setup_resources(void)
2301 {
2302 unsigned long n;
2303 struct resource *res;
2304 char *mem;
2305 int i;
2306
2307 if (nr_ioapics <= 0)
2308 return NULL;
2309
2310 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2311 n *= nr_ioapics;
2312
2313 mem = alloc_bootmem(n);
2314 res = (void *)mem;
2315
2316 if (mem != NULL) {
2317 mem += sizeof(struct resource) * nr_ioapics;
2318
2319 for (i = 0; i < nr_ioapics; i++) {
2320 res[i].name = mem;
2321 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2322 sprintf(mem, "IOAPIC %u", i);
2323 mem += IOAPIC_RESOURCE_NAME_SIZE;
2324 }
2325 }
2326
2327 ioapic_resources = res;
2328
2329 return res;
2330 }
2331
2332 void __init ioapic_init_mappings(void)
2333 {
2334 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2335 struct resource *ioapic_res;
2336 int i;
2337
2338 ioapic_res = ioapic_setup_resources();
2339 for (i = 0; i < nr_ioapics; i++) {
2340 if (smp_found_config) {
2341 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2342 } else {
2343 ioapic_phys = (unsigned long)
2344 alloc_bootmem_pages(PAGE_SIZE);
2345 ioapic_phys = __pa(ioapic_phys);
2346 }
2347 set_fixmap_nocache(idx, ioapic_phys);
2348 apic_printk(APIC_VERBOSE,
2349 "mapped IOAPIC to %016lx (%016lx)\n",
2350 __fix_to_virt(idx), ioapic_phys);
2351 idx++;
2352
2353 if (ioapic_res != NULL) {
2354 ioapic_res->start = ioapic_phys;
2355 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2356 ioapic_res++;
2357 }
2358 }
2359 }
2360
2361 static int __init ioapic_insert_resources(void)
2362 {
2363 int i;
2364 struct resource *r = ioapic_resources;
2365
2366 if (!r) {
2367 printk(KERN_ERR
2368 "IO APIC resources could be not be allocated.\n");
2369 return -1;
2370 }
2371
2372 for (i = 0; i < nr_ioapics; i++) {
2373 insert_resource(&iomem_resource, r);
2374 r++;
2375 }
2376
2377 return 0;
2378 }
2379
2380 /* Insert the IO APIC resources after PCI initialization has occured to handle
2381 * IO APICS that are mapped in on a BAR in PCI space. */
2382 late_initcall(ioapic_insert_resources);
2383
Linux kernel - Deliverables
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