projects / deliverable / linux.git / blob
? search:


616c53afb711dd0b594273f5189c502610df1af7
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 #define __apicdebuginit __init
86
87 int sis_apic_bug; /* not actually supported, dummy for compile */
88
89 static int no_timer_check;
90
91 static int disable_timer_pin_1 __initdata;
92
93 int timer_over_8254 __initdata = 1;
94
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
97
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
100
101 /*
102 * # of IRQ routing registers
103 */
104 int nr_ioapic_registers[MAX_IO_APICS];
105
106 /* I/O APIC entries */
107 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
108 int nr_ioapics;
109
110 /* MP IRQ source entries */
111 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
112
113 /* # of MP IRQ source entries */
114 int mp_irq_entries;
115
116 /*
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
119 */
120 #define MAX_PLUS_SHARED_IRQS NR_IRQS
121 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
122
123 /*
124 * This is performance-critical, we want to do it O(1)
125 *
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
128 */
129
130 static struct irq_pin_list {
131 short apic, pin, next;
132 } irq_2_pin[PIN_MAP_SIZE];
133
134 struct io_apic {
135 unsigned int index;
136 unsigned int unused[3];
137 unsigned int data;
138 };
139
140 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
141 {
142 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
143 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
144 }
145
146 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
147 {
148 struct io_apic __iomem *io_apic = io_apic_base(apic);
149 writel(reg, &io_apic->index);
150 return readl(&io_apic->data);
151 }
152
153 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
154 {
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 writel(value, &io_apic->data);
158 }
159
160 /*
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
163 */
164 static inline void io_apic_modify(unsigned int apic, unsigned int value)
165 {
166 struct io_apic __iomem *io_apic = io_apic_base(apic);
167 writel(value, &io_apic->data);
168 }
169
170 static bool io_apic_level_ack_pending(unsigned int irq)
171 {
172 struct irq_pin_list *entry;
173 unsigned long flags;
174
175 spin_lock_irqsave(&ioapic_lock, flags);
176 entry = irq_2_pin + irq;
177 for (;;) {
178 unsigned int reg;
179 int pin;
180
181 pin = entry->pin;
182 if (pin == -1)
183 break;
184 reg = io_apic_read(entry->apic, 0x10 + pin*2);
185 /* Is the remote IRR bit set? */
186 if ((reg >> 14) & 1) {
187 spin_unlock_irqrestore(&ioapic_lock, flags);
188 return true;
189 }
190 if (!entry->next)
191 break;
192 entry = irq_2_pin + entry->next;
193 }
194 spin_unlock_irqrestore(&ioapic_lock, flags);
195
196 return false;
197 }
198
199 /*
200 * Synchronize the IO-APIC and the CPU by doing
201 * a dummy read from the IO-APIC
202 */
203 static inline void io_apic_sync(unsigned int apic)
204 {
205 struct io_apic __iomem *io_apic = io_apic_base(apic);
206 readl(&io_apic->data);
207 }
208
209 #define __DO_ACTION(R, ACTION, FINAL) \
210 \
211 { \
212 int pin; \
213 struct irq_pin_list *entry = irq_2_pin + irq; \
214 \
215 BUG_ON(irq >= NR_IRQS); \
216 for (;;) { \
217 unsigned int reg; \
218 pin = entry->pin; \
219 if (pin == -1) \
220 break; \
221 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
222 reg ACTION; \
223 io_apic_modify(entry->apic, reg); \
224 FINAL; \
225 if (!entry->next) \
226 break; \
227 entry = irq_2_pin + entry->next; \
228 } \
229 }
230
231 union entry_union {
232 struct { u32 w1, w2; };
233 struct IO_APIC_route_entry entry;
234 };
235
236 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
237 {
238 union entry_union eu;
239 unsigned long flags;
240 spin_lock_irqsave(&ioapic_lock, flags);
241 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
242 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
244 return eu.entry;
245 }
246
247 /*
248 * When we write a new IO APIC routing entry, we need to write the high
249 * word first! If the mask bit in the low word is clear, we will enable
250 * the interrupt, and we need to make sure the entry is fully populated
251 * before that happens.
252 */
253 static void
254 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
255 {
256 union entry_union eu;
257 eu.entry = e;
258 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
259 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
260 }
261
262 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
263 {
264 unsigned long flags;
265 spin_lock_irqsave(&ioapic_lock, flags);
266 __ioapic_write_entry(apic, pin, e);
267 spin_unlock_irqrestore(&ioapic_lock, flags);
268 }
269
270 /*
271 * When we mask an IO APIC routing entry, we need to write the low
272 * word first, in order to set the mask bit before we change the
273 * high bits!
274 */
275 static void ioapic_mask_entry(int apic, int pin)
276 {
277 unsigned long flags;
278 union entry_union eu = { .entry.mask = 1 };
279
280 spin_lock_irqsave(&ioapic_lock, flags);
281 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
282 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
284 }
285
286 #ifdef CONFIG_SMP
287 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
288 {
289 int apic, pin;
290 struct irq_pin_list *entry = irq_2_pin + irq;
291
292 BUG_ON(irq >= NR_IRQS);
293 for (;;) {
294 unsigned int reg;
295 apic = entry->apic;
296 pin = entry->pin;
297 if (pin == -1)
298 break;
299 io_apic_write(apic, 0x11 + pin*2, dest);
300 reg = io_apic_read(apic, 0x10 + pin*2);
301 reg &= ~0x000000ff;
302 reg |= vector;
303 io_apic_modify(apic, reg);
304 if (!entry->next)
305 break;
306 entry = irq_2_pin + entry->next;
307 }
308 }
309
310 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
311 {
312 struct irq_cfg *cfg = irq_cfg + irq;
313 unsigned long flags;
314 unsigned int dest;
315 cpumask_t tmp;
316
317 cpus_and(tmp, mask, cpu_online_map);
318 if (cpus_empty(tmp))
319 return;
320
321 if (assign_irq_vector(irq, mask))
322 return;
323
324 cpus_and(tmp, cfg->domain, mask);
325 dest = cpu_mask_to_apicid(tmp);
326
327 /*
328 * Only the high 8 bits are valid.
329 */
330 dest = SET_APIC_LOGICAL_ID(dest);
331
332 spin_lock_irqsave(&ioapic_lock, flags);
333 __target_IO_APIC_irq(irq, dest, cfg->vector);
334 irq_desc[irq].affinity = mask;
335 spin_unlock_irqrestore(&ioapic_lock, flags);
336 }
337 #endif
338
339 /*
340 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
341 * shared ISA-space IRQs, so we have to support them. We are super
342 * fast in the common case, and fast for shared ISA-space IRQs.
343 */
344 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
345 {
346 static int first_free_entry = NR_IRQS;
347 struct irq_pin_list *entry = irq_2_pin + irq;
348
349 BUG_ON(irq >= NR_IRQS);
350 while (entry->next)
351 entry = irq_2_pin + entry->next;
352
353 if (entry->pin != -1) {
354 entry->next = first_free_entry;
355 entry = irq_2_pin + entry->next;
356 if (++first_free_entry >= PIN_MAP_SIZE)
357 panic("io_apic.c: ran out of irq_2_pin entries!");
358 }
359 entry->apic = apic;
360 entry->pin = pin;
361 }
362
363
364 #define DO_ACTION(name,R,ACTION, FINAL) \
365 \
366 static void name##_IO_APIC_irq (unsigned int irq) \
367 __DO_ACTION(R, ACTION, FINAL)
368
369 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
370 /* mask = 1 */
371 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
372 /* mask = 0 */
373
374 static void mask_IO_APIC_irq (unsigned int irq)
375 {
376 unsigned long flags;
377
378 spin_lock_irqsave(&ioapic_lock, flags);
379 __mask_IO_APIC_irq(irq);
380 spin_unlock_irqrestore(&ioapic_lock, flags);
381 }
382
383 static void unmask_IO_APIC_irq (unsigned int irq)
384 {
385 unsigned long flags;
386
387 spin_lock_irqsave(&ioapic_lock, flags);
388 __unmask_IO_APIC_irq(irq);
389 spin_unlock_irqrestore(&ioapic_lock, flags);
390 }
391
392 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
393 {
394 struct IO_APIC_route_entry entry;
395
396 /* Check delivery_mode to be sure we're not clearing an SMI pin */
397 entry = ioapic_read_entry(apic, pin);
398 if (entry.delivery_mode == dest_SMI)
399 return;
400 /*
401 * Disable it in the IO-APIC irq-routing table:
402 */
403 ioapic_mask_entry(apic, pin);
404 }
405
406 static void clear_IO_APIC (void)
407 {
408 int apic, pin;
409
410 for (apic = 0; apic < nr_ioapics; apic++)
411 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
412 clear_IO_APIC_pin(apic, pin);
413 }
414
415 int skip_ioapic_setup;
416 int ioapic_force;
417
418 static int __init parse_noapic(char *str)
419 {
420 disable_ioapic_setup();
421 return 0;
422 }
423 early_param("noapic", parse_noapic);
424
425 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
426 static int __init disable_timer_pin_setup(char *arg)
427 {
428 disable_timer_pin_1 = 1;
429 return 1;
430 }
431 __setup("disable_timer_pin_1", disable_timer_pin_setup);
432
433 static int __init setup_disable_8254_timer(char *s)
434 {
435 timer_over_8254 = -1;
436 return 1;
437 }
438 static int __init setup_enable_8254_timer(char *s)
439 {
440 timer_over_8254 = 2;
441 return 1;
442 }
443
444 __setup("disable_8254_timer", setup_disable_8254_timer);
445 __setup("enable_8254_timer", setup_enable_8254_timer);
446
447
448 /*
449 * Find the IRQ entry number of a certain pin.
450 */
451 static int find_irq_entry(int apic, int pin, int type)
452 {
453 int i;
454
455 for (i = 0; i < mp_irq_entries; i++)
456 if (mp_irqs[i].mpc_irqtype == type &&
457 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
458 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
459 mp_irqs[i].mpc_dstirq == pin)
460 return i;
461
462 return -1;
463 }
464
465 /*
466 * Find the pin to which IRQ[irq] (ISA) is connected
467 */
468 static int __init find_isa_irq_pin(int irq, int type)
469 {
470 int i;
471
472 for (i = 0; i < mp_irq_entries; i++) {
473 int lbus = mp_irqs[i].mpc_srcbus;
474
475 if (test_bit(lbus, mp_bus_not_pci) &&
476 (mp_irqs[i].mpc_irqtype == type) &&
477 (mp_irqs[i].mpc_srcbusirq == irq))
478
479 return mp_irqs[i].mpc_dstirq;
480 }
481 return -1;
482 }
483
484 static int __init find_isa_irq_apic(int irq, int type)
485 {
486 int i;
487
488 for (i = 0; i < mp_irq_entries; i++) {
489 int lbus = mp_irqs[i].mpc_srcbus;
490
491 if (test_bit(lbus, mp_bus_not_pci) &&
492 (mp_irqs[i].mpc_irqtype == type) &&
493 (mp_irqs[i].mpc_srcbusirq == irq))
494 break;
495 }
496 if (i < mp_irq_entries) {
497 int apic;
498 for(apic = 0; apic < nr_ioapics; apic++) {
499 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
500 return apic;
501 }
502 }
503
504 return -1;
505 }
506
507 /*
508 * Find a specific PCI IRQ entry.
509 * Not an __init, possibly needed by modules
510 */
511 static int pin_2_irq(int idx, int apic, int pin);
512
513 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
514 {
515 int apic, i, best_guess = -1;
516
517 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
518 bus, slot, pin);
519 if (mp_bus_id_to_pci_bus[bus] == -1) {
520 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
521 return -1;
522 }
523 for (i = 0; i < mp_irq_entries; i++) {
524 int lbus = mp_irqs[i].mpc_srcbus;
525
526 for (apic = 0; apic < nr_ioapics; apic++)
527 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
528 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
529 break;
530
531 if (!test_bit(lbus, mp_bus_not_pci) &&
532 !mp_irqs[i].mpc_irqtype &&
533 (bus == lbus) &&
534 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
535 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
536
537 if (!(apic || IO_APIC_IRQ(irq)))
538 continue;
539
540 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
541 return irq;
542 /*
543 * Use the first all-but-pin matching entry as a
544 * best-guess fuzzy result for broken mptables.
545 */
546 if (best_guess < 0)
547 best_guess = irq;
548 }
549 }
550 BUG_ON(best_guess >= NR_IRQS);
551 return best_guess;
552 }
553
554 /* ISA interrupts are always polarity zero edge triggered,
555 * when listed as conforming in the MP table. */
556
557 #define default_ISA_trigger(idx) (0)
558 #define default_ISA_polarity(idx) (0)
559
560 /* PCI interrupts are always polarity one level triggered,
561 * when listed as conforming in the MP table. */
562
563 #define default_PCI_trigger(idx) (1)
564 #define default_PCI_polarity(idx) (1)
565
566 static int MPBIOS_polarity(int idx)
567 {
568 int bus = mp_irqs[idx].mpc_srcbus;
569 int polarity;
570
571 /*
572 * Determine IRQ line polarity (high active or low active):
573 */
574 switch (mp_irqs[idx].mpc_irqflag & 3)
575 {
576 case 0: /* conforms, ie. bus-type dependent polarity */
577 if (test_bit(bus, mp_bus_not_pci))
578 polarity = default_ISA_polarity(idx);
579 else
580 polarity = default_PCI_polarity(idx);
581 break;
582 case 1: /* high active */
583 {
584 polarity = 0;
585 break;
586 }
587 case 2: /* reserved */
588 {
589 printk(KERN_WARNING "broken BIOS!!\n");
590 polarity = 1;
591 break;
592 }
593 case 3: /* low active */
594 {
595 polarity = 1;
596 break;
597 }
598 default: /* invalid */
599 {
600 printk(KERN_WARNING "broken BIOS!!\n");
601 polarity = 1;
602 break;
603 }
604 }
605 return polarity;
606 }
607
608 static int MPBIOS_trigger(int idx)
609 {
610 int bus = mp_irqs[idx].mpc_srcbus;
611 int trigger;
612
613 /*
614 * Determine IRQ trigger mode (edge or level sensitive):
615 */
616 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
617 {
618 case 0: /* conforms, ie. bus-type dependent */
619 if (test_bit(bus, mp_bus_not_pci))
620 trigger = default_ISA_trigger(idx);
621 else
622 trigger = default_PCI_trigger(idx);
623 break;
624 case 1: /* edge */
625 {
626 trigger = 0;
627 break;
628 }
629 case 2: /* reserved */
630 {
631 printk(KERN_WARNING "broken BIOS!!\n");
632 trigger = 1;
633 break;
634 }
635 case 3: /* level */
636 {
637 trigger = 1;
638 break;
639 }
640 default: /* invalid */
641 {
642 printk(KERN_WARNING "broken BIOS!!\n");
643 trigger = 0;
644 break;
645 }
646 }
647 return trigger;
648 }
649
650 static inline int irq_polarity(int idx)
651 {
652 return MPBIOS_polarity(idx);
653 }
654
655 static inline int irq_trigger(int idx)
656 {
657 return MPBIOS_trigger(idx);
658 }
659
660 static int pin_2_irq(int idx, int apic, int pin)
661 {
662 int irq, i;
663 int bus = mp_irqs[idx].mpc_srcbus;
664
665 /*
666 * Debugging check, we are in big trouble if this message pops up!
667 */
668 if (mp_irqs[idx].mpc_dstirq != pin)
669 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
670
671 if (test_bit(bus, mp_bus_not_pci)) {
672 irq = mp_irqs[idx].mpc_srcbusirq;
673 } else {
674 /*
675 * PCI IRQs are mapped in order
676 */
677 i = irq = 0;
678 while (i < apic)
679 irq += nr_ioapic_registers[i++];
680 irq += pin;
681 }
682 BUG_ON(irq >= NR_IRQS);
683 return irq;
684 }
685
686 static int __assign_irq_vector(int irq, cpumask_t mask)
687 {
688 /*
689 * NOTE! The local APIC isn't very good at handling
690 * multiple interrupts at the same interrupt level.
691 * As the interrupt level is determined by taking the
692 * vector number and shifting that right by 4, we
693 * want to spread these out a bit so that they don't
694 * all fall in the same interrupt level.
695 *
696 * Also, we've got to be careful not to trash gate
697 * 0x80, because int 0x80 is hm, kind of importantish. ;)
698 */
699 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
700 unsigned int old_vector;
701 int cpu;
702 struct irq_cfg *cfg;
703
704 BUG_ON((unsigned)irq >= NR_IRQS);
705 cfg = &irq_cfg[irq];
706
707 /* Only try and allocate irqs on cpus that are present */
708 cpus_and(mask, mask, cpu_online_map);
709
710 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
711 return -EBUSY;
712
713 old_vector = cfg->vector;
714 if (old_vector) {
715 cpumask_t tmp;
716 cpus_and(tmp, cfg->domain, mask);
717 if (!cpus_empty(tmp))
718 return 0;
719 }
720
721 for_each_cpu_mask(cpu, mask) {
722 cpumask_t domain, new_mask;
723 int new_cpu;
724 int vector, offset;
725
726 domain = vector_allocation_domain(cpu);
727 cpus_and(new_mask, domain, cpu_online_map);
728
729 vector = current_vector;
730 offset = current_offset;
731 next:
732 vector += 8;
733 if (vector >= FIRST_SYSTEM_VECTOR) {
734 /* If we run out of vectors on large boxen, must share them. */
735 offset = (offset + 1) % 8;
736 vector = FIRST_DEVICE_VECTOR + offset;
737 }
738 if (unlikely(current_vector == vector))
739 continue;
740 if (vector == IA32_SYSCALL_VECTOR)
741 goto next;
742 for_each_cpu_mask(new_cpu, new_mask)
743 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
744 goto next;
745 /* Found one! */
746 current_vector = vector;
747 current_offset = offset;
748 if (old_vector) {
749 cfg->move_in_progress = 1;
750 cfg->old_domain = cfg->domain;
751 }
752 for_each_cpu_mask(new_cpu, new_mask)
753 per_cpu(vector_irq, new_cpu)[vector] = irq;
754 cfg->vector = vector;
755 cfg->domain = domain;
756 return 0;
757 }
758 return -ENOSPC;
759 }
760
761 static int assign_irq_vector(int irq, cpumask_t mask)
762 {
763 int err;
764 unsigned long flags;
765
766 spin_lock_irqsave(&vector_lock, flags);
767 err = __assign_irq_vector(irq, mask);
768 spin_unlock_irqrestore(&vector_lock, flags);
769 return err;
770 }
771
772 static void __clear_irq_vector(int irq)
773 {
774 struct irq_cfg *cfg;
775 cpumask_t mask;
776 int cpu, vector;
777
778 BUG_ON((unsigned)irq >= NR_IRQS);
779 cfg = &irq_cfg[irq];
780 BUG_ON(!cfg->vector);
781
782 vector = cfg->vector;
783 cpus_and(mask, cfg->domain, cpu_online_map);
784 for_each_cpu_mask(cpu, mask)
785 per_cpu(vector_irq, cpu)[vector] = -1;
786
787 cfg->vector = 0;
788 cfg->domain = CPU_MASK_NONE;
789 }
790
791 void __setup_vector_irq(int cpu)
792 {
793 /* Initialize vector_irq on a new cpu */
794 /* This function must be called with vector_lock held */
795 int irq, vector;
796
797 /* Mark the inuse vectors */
798 for (irq = 0; irq < NR_IRQS; ++irq) {
799 if (!cpu_isset(cpu, irq_cfg[irq].domain))
800 continue;
801 vector = irq_cfg[irq].vector;
802 per_cpu(vector_irq, cpu)[vector] = irq;
803 }
804 /* Mark the free vectors */
805 for (vector = 0; vector < NR_VECTORS; ++vector) {
806 irq = per_cpu(vector_irq, cpu)[vector];
807 if (irq < 0)
808 continue;
809 if (!cpu_isset(cpu, irq_cfg[irq].domain))
810 per_cpu(vector_irq, cpu)[vector] = -1;
811 }
812 }
813
814
815 static struct irq_chip ioapic_chip;
816
817 static void ioapic_register_intr(int irq, unsigned long trigger)
818 {
819 if (trigger) {
820 irq_desc[irq].status |= IRQ_LEVEL;
821 set_irq_chip_and_handler_name(irq, &ioapic_chip,
822 handle_fasteoi_irq, "fasteoi");
823 } else {
824 irq_desc[irq].status &= ~IRQ_LEVEL;
825 set_irq_chip_and_handler_name(irq, &ioapic_chip,
826 handle_edge_irq, "edge");
827 }
828 }
829
830 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
831 int trigger, int polarity)
832 {
833 struct irq_cfg *cfg = irq_cfg + irq;
834 struct IO_APIC_route_entry entry;
835 cpumask_t mask;
836
837 if (!IO_APIC_IRQ(irq))
838 return;
839
840 mask = TARGET_CPUS;
841 if (assign_irq_vector(irq, mask))
842 return;
843
844 cpus_and(mask, cfg->domain, mask);
845
846 apic_printk(APIC_VERBOSE,KERN_DEBUG
847 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
848 "IRQ %d Mode:%i Active:%i)\n",
849 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
850 irq, trigger, polarity);
851
852 /*
853 * add it to the IO-APIC irq-routing table:
854 */
855 memset(&entry,0,sizeof(entry));
856
857 entry.delivery_mode = INT_DELIVERY_MODE;
858 entry.dest_mode = INT_DEST_MODE;
859 entry.dest = cpu_mask_to_apicid(mask);
860 entry.mask = 0; /* enable IRQ */
861 entry.trigger = trigger;
862 entry.polarity = polarity;
863 entry.vector = cfg->vector;
864
865 /* Mask level triggered irqs.
866 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
867 */
868 if (trigger)
869 entry.mask = 1;
870
871 ioapic_register_intr(irq, trigger);
872 if (irq < 16)
873 disable_8259A_irq(irq);
874
875 ioapic_write_entry(apic, pin, entry);
876 }
877
878 static void __init setup_IO_APIC_irqs(void)
879 {
880 int apic, pin, idx, irq, first_notcon = 1;
881
882 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
883
884 for (apic = 0; apic < nr_ioapics; apic++) {
885 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
886
887 idx = find_irq_entry(apic,pin,mp_INT);
888 if (idx == -1) {
889 if (first_notcon) {
890 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
891 first_notcon = 0;
892 } else
893 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
894 continue;
895 }
896 if (!first_notcon) {
897 apic_printk(APIC_VERBOSE, " not connected.\n");
898 first_notcon = 1;
899 }
900
901 irq = pin_2_irq(idx, apic, pin);
902 add_pin_to_irq(irq, apic, pin);
903
904 setup_IO_APIC_irq(apic, pin, irq,
905 irq_trigger(idx), irq_polarity(idx));
906 }
907 }
908
909 if (!first_notcon)
910 apic_printk(APIC_VERBOSE, " not connected.\n");
911 }
912
913 /*
914 * Set up the 8259A-master output pin as broadcast to all
915 * CPUs.
916 */
917 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
918 {
919 struct IO_APIC_route_entry entry;
920
921 memset(&entry, 0, sizeof(entry));
922
923 disable_8259A_irq(0);
924
925 /* mask LVT0 */
926 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
927
928 /*
929 * We use logical delivery to get the timer IRQ
930 * to the first CPU.
931 */
932 entry.dest_mode = INT_DEST_MODE;
933 entry.mask = 0; /* unmask IRQ now */
934 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
935 entry.delivery_mode = INT_DELIVERY_MODE;
936 entry.polarity = 0;
937 entry.trigger = 0;
938 entry.vector = vector;
939
940 /*
941 * The timer IRQ doesn't have to know that behind the
942 * scene we have a 8259A-master in AEOI mode ...
943 */
944 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
945
946 /*
947 * Add it to the IO-APIC irq-routing table:
948 */
949 ioapic_write_entry(apic, pin, entry);
950
951 enable_8259A_irq(0);
952 }
953
954 void __apicdebuginit print_IO_APIC(void)
955 {
956 int apic, i;
957 union IO_APIC_reg_00 reg_00;
958 union IO_APIC_reg_01 reg_01;
959 union IO_APIC_reg_02 reg_02;
960 unsigned long flags;
961
962 if (apic_verbosity == APIC_QUIET)
963 return;
964
965 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
966 for (i = 0; i < nr_ioapics; i++)
967 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
968 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
969
970 /*
971 * We are a bit conservative about what we expect. We have to
972 * know about every hardware change ASAP.
973 */
974 printk(KERN_INFO "testing the IO APIC.......................\n");
975
976 for (apic = 0; apic < nr_ioapics; apic++) {
977
978 spin_lock_irqsave(&ioapic_lock, flags);
979 reg_00.raw = io_apic_read(apic, 0);
980 reg_01.raw = io_apic_read(apic, 1);
981 if (reg_01.bits.version >= 0x10)
982 reg_02.raw = io_apic_read(apic, 2);
983 spin_unlock_irqrestore(&ioapic_lock, flags);
984
985 printk("\n");
986 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
987 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
988 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
989
990 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
991 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
992
993 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
994 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
995
996 if (reg_01.bits.version >= 0x10) {
997 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
998 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
999 }
1000
1001 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1002
1003 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1004 " Stat Dmod Deli Vect: \n");
1005
1006 for (i = 0; i <= reg_01.bits.entries; i++) {
1007 struct IO_APIC_route_entry entry;
1008
1009 entry = ioapic_read_entry(apic, i);
1010
1011 printk(KERN_DEBUG " %02x %03X ",
1012 i,
1013 entry.dest
1014 );
1015
1016 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1017 entry.mask,
1018 entry.trigger,
1019 entry.irr,
1020 entry.polarity,
1021 entry.delivery_status,
1022 entry.dest_mode,
1023 entry.delivery_mode,
1024 entry.vector
1025 );
1026 }
1027 }
1028 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1029 for (i = 0; i < NR_IRQS; i++) {
1030 struct irq_pin_list *entry = irq_2_pin + i;
1031 if (entry->pin < 0)
1032 continue;
1033 printk(KERN_DEBUG "IRQ%d ", i);
1034 for (;;) {
1035 printk("-> %d:%d", entry->apic, entry->pin);
1036 if (!entry->next)
1037 break;
1038 entry = irq_2_pin + entry->next;
1039 }
1040 printk("\n");
1041 }
1042
1043 printk(KERN_INFO ".................................... done.\n");
1044
1045 return;
1046 }
1047
1048 #if 0
1049
1050 static __apicdebuginit void print_APIC_bitfield (int base)
1051 {
1052 unsigned int v;
1053 int i, j;
1054
1055 if (apic_verbosity == APIC_QUIET)
1056 return;
1057
1058 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1059 for (i = 0; i < 8; i++) {
1060 v = apic_read(base + i*0x10);
1061 for (j = 0; j < 32; j++) {
1062 if (v & (1<<j))
1063 printk("1");
1064 else
1065 printk("0");
1066 }
1067 printk("\n");
1068 }
1069 }
1070
1071 void __apicdebuginit print_local_APIC(void * dummy)
1072 {
1073 unsigned int v, ver, maxlvt;
1074
1075 if (apic_verbosity == APIC_QUIET)
1076 return;
1077
1078 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1079 smp_processor_id(), hard_smp_processor_id());
1080 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1081 v = apic_read(APIC_LVR);
1082 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1083 ver = GET_APIC_VERSION(v);
1084 maxlvt = lapic_get_maxlvt();
1085
1086 v = apic_read(APIC_TASKPRI);
1087 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1088
1089 v = apic_read(APIC_ARBPRI);
1090 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1091 v & APIC_ARBPRI_MASK);
1092 v = apic_read(APIC_PROCPRI);
1093 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1094
1095 v = apic_read(APIC_EOI);
1096 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1097 v = apic_read(APIC_RRR);
1098 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1099 v = apic_read(APIC_LDR);
1100 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1101 v = apic_read(APIC_DFR);
1102 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1103 v = apic_read(APIC_SPIV);
1104 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1105
1106 printk(KERN_DEBUG "... APIC ISR field:\n");
1107 print_APIC_bitfield(APIC_ISR);
1108 printk(KERN_DEBUG "... APIC TMR field:\n");
1109 print_APIC_bitfield(APIC_TMR);
1110 printk(KERN_DEBUG "... APIC IRR field:\n");
1111 print_APIC_bitfield(APIC_IRR);
1112
1113 v = apic_read(APIC_ESR);
1114 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1115
1116 v = apic_read(APIC_ICR);
1117 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1118 v = apic_read(APIC_ICR2);
1119 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1120
1121 v = apic_read(APIC_LVTT);
1122 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1123
1124 if (maxlvt > 3) { /* PC is LVT#4. */
1125 v = apic_read(APIC_LVTPC);
1126 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1127 }
1128 v = apic_read(APIC_LVT0);
1129 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1130 v = apic_read(APIC_LVT1);
1131 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1132
1133 if (maxlvt > 2) { /* ERR is LVT#3. */
1134 v = apic_read(APIC_LVTERR);
1135 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1136 }
1137
1138 v = apic_read(APIC_TMICT);
1139 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1140 v = apic_read(APIC_TMCCT);
1141 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1142 v = apic_read(APIC_TDCR);
1143 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1144 printk("\n");
1145 }
1146
1147 void print_all_local_APICs (void)
1148 {
1149 on_each_cpu(print_local_APIC, NULL, 1, 1);
1150 }
1151
1152 void __apicdebuginit print_PIC(void)
1153 {
1154 unsigned int v;
1155 unsigned long flags;
1156
1157 if (apic_verbosity == APIC_QUIET)
1158 return;
1159
1160 printk(KERN_DEBUG "\nprinting PIC contents\n");
1161
1162 spin_lock_irqsave(&i8259A_lock, flags);
1163
1164 v = inb(0xa1) << 8 | inb(0x21);
1165 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1166
1167 v = inb(0xa0) << 8 | inb(0x20);
1168 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1169
1170 outb(0x0b,0xa0);
1171 outb(0x0b,0x20);
1172 v = inb(0xa0) << 8 | inb(0x20);
1173 outb(0x0a,0xa0);
1174 outb(0x0a,0x20);
1175
1176 spin_unlock_irqrestore(&i8259A_lock, flags);
1177
1178 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1179
1180 v = inb(0x4d1) << 8 | inb(0x4d0);
1181 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1182 }
1183
1184 #endif /* 0 */
1185
1186 void __init enable_IO_APIC(void)
1187 {
1188 union IO_APIC_reg_01 reg_01;
1189 int i8259_apic, i8259_pin;
1190 int i, apic;
1191 unsigned long flags;
1192
1193 for (i = 0; i < PIN_MAP_SIZE; i++) {
1194 irq_2_pin[i].pin = -1;
1195 irq_2_pin[i].next = 0;
1196 }
1197
1198 /*
1199 * The number of IO-APIC IRQ registers (== #pins):
1200 */
1201 for (apic = 0; apic < nr_ioapics; apic++) {
1202 spin_lock_irqsave(&ioapic_lock, flags);
1203 reg_01.raw = io_apic_read(apic, 1);
1204 spin_unlock_irqrestore(&ioapic_lock, flags);
1205 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1206 }
1207 for(apic = 0; apic < nr_ioapics; apic++) {
1208 int pin;
1209 /* See if any of the pins is in ExtINT mode */
1210 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1211 struct IO_APIC_route_entry entry;
1212 entry = ioapic_read_entry(apic, pin);
1213
1214 /* If the interrupt line is enabled and in ExtInt mode
1215 * I have found the pin where the i8259 is connected.
1216 */
1217 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1218 ioapic_i8259.apic = apic;
1219 ioapic_i8259.pin = pin;
1220 goto found_i8259;
1221 }
1222 }
1223 }
1224 found_i8259:
1225 /* Look to see what if the MP table has reported the ExtINT */
1226 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1227 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1228 /* Trust the MP table if nothing is setup in the hardware */
1229 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1230 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1231 ioapic_i8259.pin = i8259_pin;
1232 ioapic_i8259.apic = i8259_apic;
1233 }
1234 /* Complain if the MP table and the hardware disagree */
1235 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1236 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1237 {
1238 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1239 }
1240
1241 /*
1242 * Do not trust the IO-APIC being empty at bootup
1243 */
1244 clear_IO_APIC();
1245 }
1246
1247 /*
1248 * Not an __init, needed by the reboot code
1249 */
1250 void disable_IO_APIC(void)
1251 {
1252 /*
1253 * Clear the IO-APIC before rebooting:
1254 */
1255 clear_IO_APIC();
1256
1257 /*
1258 * If the i8259 is routed through an IOAPIC
1259 * Put that IOAPIC in virtual wire mode
1260 * so legacy interrupts can be delivered.
1261 */
1262 if (ioapic_i8259.pin != -1) {
1263 struct IO_APIC_route_entry entry;
1264
1265 memset(&entry, 0, sizeof(entry));
1266 entry.mask = 0; /* Enabled */
1267 entry.trigger = 0; /* Edge */
1268 entry.irr = 0;
1269 entry.polarity = 0; /* High */
1270 entry.delivery_status = 0;
1271 entry.dest_mode = 0; /* Physical */
1272 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1273 entry.vector = 0;
1274 entry.dest = GET_APIC_ID(read_apic_id());
1275
1276 /*
1277 * Add it to the IO-APIC irq-routing table:
1278 */
1279 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1280 }
1281
1282 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1283 }
1284
1285 /*
1286 * There is a nasty bug in some older SMP boards, their mptable lies
1287 * about the timer IRQ. We do the following to work around the situation:
1288 *
1289 * - timer IRQ defaults to IO-APIC IRQ
1290 * - if this function detects that timer IRQs are defunct, then we fall
1291 * back to ISA timer IRQs
1292 */
1293 static int __init timer_irq_works(void)
1294 {
1295 unsigned long t1 = jiffies;
1296 unsigned long flags;
1297
1298 local_save_flags(flags);
1299 local_irq_enable();
1300 /* Let ten ticks pass... */
1301 mdelay((10 * 1000) / HZ);
1302 local_irq_restore(flags);
1303
1304 /*
1305 * Expect a few ticks at least, to be sure some possible
1306 * glue logic does not lock up after one or two first
1307 * ticks in a non-ExtINT mode. Also the local APIC
1308 * might have cached one ExtINT interrupt. Finally, at
1309 * least one tick may be lost due to delays.
1310 */
1311
1312 /* jiffies wrap? */
1313 if (time_after(jiffies, t1 + 4))
1314 return 1;
1315 return 0;
1316 }
1317
1318 /*
1319 * In the SMP+IOAPIC case it might happen that there are an unspecified
1320 * number of pending IRQ events unhandled. These cases are very rare,
1321 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1322 * better to do it this way as thus we do not have to be aware of
1323 * 'pending' interrupts in the IRQ path, except at this point.
1324 */
1325 /*
1326 * Edge triggered needs to resend any interrupt
1327 * that was delayed but this is now handled in the device
1328 * independent code.
1329 */
1330
1331 /*
1332 * Starting up a edge-triggered IO-APIC interrupt is
1333 * nasty - we need to make sure that we get the edge.
1334 * If it is already asserted for some reason, we need
1335 * return 1 to indicate that is was pending.
1336 *
1337 * This is not complete - we should be able to fake
1338 * an edge even if it isn't on the 8259A...
1339 */
1340
1341 static unsigned int startup_ioapic_irq(unsigned int irq)
1342 {
1343 int was_pending = 0;
1344 unsigned long flags;
1345
1346 spin_lock_irqsave(&ioapic_lock, flags);
1347 if (irq < 16) {
1348 disable_8259A_irq(irq);
1349 if (i8259A_irq_pending(irq))
1350 was_pending = 1;
1351 }
1352 __unmask_IO_APIC_irq(irq);
1353 spin_unlock_irqrestore(&ioapic_lock, flags);
1354
1355 return was_pending;
1356 }
1357
1358 static int ioapic_retrigger_irq(unsigned int irq)
1359 {
1360 struct irq_cfg *cfg = &irq_cfg[irq];
1361 cpumask_t mask;
1362 unsigned long flags;
1363
1364 spin_lock_irqsave(&vector_lock, flags);
1365 cpus_clear(mask);
1366 cpu_set(first_cpu(cfg->domain), mask);
1367
1368 send_IPI_mask(mask, cfg->vector);
1369 spin_unlock_irqrestore(&vector_lock, flags);
1370
1371 return 1;
1372 }
1373
1374 /*
1375 * Level and edge triggered IO-APIC interrupts need different handling,
1376 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1377 * handled with the level-triggered descriptor, but that one has slightly
1378 * more overhead. Level-triggered interrupts cannot be handled with the
1379 * edge-triggered handler, without risking IRQ storms and other ugly
1380 * races.
1381 */
1382
1383 #ifdef CONFIG_SMP
1384 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1385 {
1386 unsigned vector, me;
1387 ack_APIC_irq();
1388 exit_idle();
1389 irq_enter();
1390
1391 me = smp_processor_id();
1392 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1393 unsigned int irq;
1394 struct irq_desc *desc;
1395 struct irq_cfg *cfg;
1396 irq = __get_cpu_var(vector_irq)[vector];
1397 if (irq >= NR_IRQS)
1398 continue;
1399
1400 desc = irq_desc + irq;
1401 cfg = irq_cfg + irq;
1402 spin_lock(&desc->lock);
1403 if (!cfg->move_cleanup_count)
1404 goto unlock;
1405
1406 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1407 goto unlock;
1408
1409 __get_cpu_var(vector_irq)[vector] = -1;
1410 cfg->move_cleanup_count--;
1411 unlock:
1412 spin_unlock(&desc->lock);
1413 }
1414
1415 irq_exit();
1416 }
1417
1418 static void irq_complete_move(unsigned int irq)
1419 {
1420 struct irq_cfg *cfg = irq_cfg + irq;
1421 unsigned vector, me;
1422
1423 if (likely(!cfg->move_in_progress))
1424 return;
1425
1426 vector = ~get_irq_regs()->orig_ax;
1427 me = smp_processor_id();
1428 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1429 cpumask_t cleanup_mask;
1430
1431 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1432 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1433 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1434 cfg->move_in_progress = 0;
1435 }
1436 }
1437 #else
1438 static inline void irq_complete_move(unsigned int irq) {}
1439 #endif
1440
1441 static void ack_apic_edge(unsigned int irq)
1442 {
1443 irq_complete_move(irq);
1444 move_native_irq(irq);
1445 ack_APIC_irq();
1446 }
1447
1448 static void ack_apic_level(unsigned int irq)
1449 {
1450 int do_unmask_irq = 0;
1451
1452 irq_complete_move(irq);
1453 #ifdef CONFIG_GENERIC_PENDING_IRQ
1454 /* If we are moving the irq we need to mask it */
1455 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1456 do_unmask_irq = 1;
1457 mask_IO_APIC_irq(irq);
1458 }
1459 #endif
1460
1461 /*
1462 * We must acknowledge the irq before we move it or the acknowledge will
1463 * not propagate properly.
1464 */
1465 ack_APIC_irq();
1466
1467 /* Now we can move and renable the irq */
1468 if (unlikely(do_unmask_irq)) {
1469 /* Only migrate the irq if the ack has been received.
1470 *
1471 * On rare occasions the broadcast level triggered ack gets
1472 * delayed going to ioapics, and if we reprogram the
1473 * vector while Remote IRR is still set the irq will never
1474 * fire again.
1475 *
1476 * To prevent this scenario we read the Remote IRR bit
1477 * of the ioapic. This has two effects.
1478 * - On any sane system the read of the ioapic will
1479 * flush writes (and acks) going to the ioapic from
1480 * this cpu.
1481 * - We get to see if the ACK has actually been delivered.
1482 *
1483 * Based on failed experiments of reprogramming the
1484 * ioapic entry from outside of irq context starting
1485 * with masking the ioapic entry and then polling until
1486 * Remote IRR was clear before reprogramming the
1487 * ioapic I don't trust the Remote IRR bit to be
1488 * completey accurate.
1489 *
1490 * However there appears to be no other way to plug
1491 * this race, so if the Remote IRR bit is not
1492 * accurate and is causing problems then it is a hardware bug
1493 * and you can go talk to the chipset vendor about it.
1494 */
1495 if (!io_apic_level_ack_pending(irq))
1496 move_masked_irq(irq);
1497 unmask_IO_APIC_irq(irq);
1498 }
1499 }
1500
1501 static struct irq_chip ioapic_chip __read_mostly = {
1502 .name = "IO-APIC",
1503 .startup = startup_ioapic_irq,
1504 .mask = mask_IO_APIC_irq,
1505 .unmask = unmask_IO_APIC_irq,
1506 .ack = ack_apic_edge,
1507 .eoi = ack_apic_level,
1508 #ifdef CONFIG_SMP
1509 .set_affinity = set_ioapic_affinity_irq,
1510 #endif
1511 .retrigger = ioapic_retrigger_irq,
1512 };
1513
1514 static inline void init_IO_APIC_traps(void)
1515 {
1516 int irq;
1517
1518 /*
1519 * NOTE! The local APIC isn't very good at handling
1520 * multiple interrupts at the same interrupt level.
1521 * As the interrupt level is determined by taking the
1522 * vector number and shifting that right by 4, we
1523 * want to spread these out a bit so that they don't
1524 * all fall in the same interrupt level.
1525 *
1526 * Also, we've got to be careful not to trash gate
1527 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1528 */
1529 for (irq = 0; irq < NR_IRQS ; irq++) {
1530 int tmp = irq;
1531 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1532 /*
1533 * Hmm.. We don't have an entry for this,
1534 * so default to an old-fashioned 8259
1535 * interrupt if we can..
1536 */
1537 if (irq < 16)
1538 make_8259A_irq(irq);
1539 else
1540 /* Strange. Oh, well.. */
1541 irq_desc[irq].chip = &no_irq_chip;
1542 }
1543 }
1544 }
1545
1546 static void enable_lapic_irq (unsigned int irq)
1547 {
1548 unsigned long v;
1549
1550 v = apic_read(APIC_LVT0);
1551 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1552 }
1553
1554 static void disable_lapic_irq (unsigned int irq)
1555 {
1556 unsigned long v;
1557
1558 v = apic_read(APIC_LVT0);
1559 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1560 }
1561
1562 static void ack_lapic_irq (unsigned int irq)
1563 {
1564 ack_APIC_irq();
1565 }
1566
1567 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1568
1569 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1570 .name = "local-APIC",
1571 .typename = "local-APIC-edge",
1572 .startup = NULL, /* startup_irq() not used for IRQ0 */
1573 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1574 .enable = enable_lapic_irq,
1575 .disable = disable_lapic_irq,
1576 .ack = ack_lapic_irq,
1577 .end = end_lapic_irq,
1578 };
1579
1580 static void __init setup_nmi(void)
1581 {
1582 /*
1583 * Dirty trick to enable the NMI watchdog ...
1584 * We put the 8259A master into AEOI mode and
1585 * unmask on all local APICs LVT0 as NMI.
1586 *
1587 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1588 * is from Maciej W. Rozycki - so we do not have to EOI from
1589 * the NMI handler or the timer interrupt.
1590 */
1591 printk(KERN_INFO "activating NMI Watchdog ...");
1592
1593 enable_NMI_through_LVT0();
1594
1595 printk(" done.\n");
1596 }
1597
1598 /*
1599 * This looks a bit hackish but it's about the only one way of sending
1600 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1601 * not support the ExtINT mode, unfortunately. We need to send these
1602 * cycles as some i82489DX-based boards have glue logic that keeps the
1603 * 8259A interrupt line asserted until INTA. --macro
1604 */
1605 static inline void unlock_ExtINT_logic(void)
1606 {
1607 int apic, pin, i;
1608 struct IO_APIC_route_entry entry0, entry1;
1609 unsigned char save_control, save_freq_select;
1610
1611 pin = find_isa_irq_pin(8, mp_INT);
1612 apic = find_isa_irq_apic(8, mp_INT);
1613 if (pin == -1)
1614 return;
1615
1616 entry0 = ioapic_read_entry(apic, pin);
1617
1618 clear_IO_APIC_pin(apic, pin);
1619
1620 memset(&entry1, 0, sizeof(entry1));
1621
1622 entry1.dest_mode = 0; /* physical delivery */
1623 entry1.mask = 0; /* unmask IRQ now */
1624 entry1.dest = hard_smp_processor_id();
1625 entry1.delivery_mode = dest_ExtINT;
1626 entry1.polarity = entry0.polarity;
1627 entry1.trigger = 0;
1628 entry1.vector = 0;
1629
1630 ioapic_write_entry(apic, pin, entry1);
1631
1632 save_control = CMOS_READ(RTC_CONTROL);
1633 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1634 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1635 RTC_FREQ_SELECT);
1636 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1637
1638 i = 100;
1639 while (i-- > 0) {
1640 mdelay(10);
1641 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1642 i -= 10;
1643 }
1644
1645 CMOS_WRITE(save_control, RTC_CONTROL);
1646 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1647 clear_IO_APIC_pin(apic, pin);
1648
1649 ioapic_write_entry(apic, pin, entry0);
1650 }
1651
1652 /*
1653 * This code may look a bit paranoid, but it's supposed to cooperate with
1654 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1655 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1656 * fanatically on his truly buggy board.
1657 *
1658 * FIXME: really need to revamp this for modern platforms only.
1659 */
1660 static inline void __init check_timer(void)
1661 {
1662 struct irq_cfg *cfg = irq_cfg + 0;
1663 int apic1, pin1, apic2, pin2;
1664 unsigned long flags;
1665
1666 local_irq_save(flags);
1667
1668 /*
1669 * get/set the timer IRQ vector:
1670 */
1671 disable_8259A_irq(0);
1672 assign_irq_vector(0, TARGET_CPUS);
1673
1674 /*
1675 * Subtle, code in do_timer_interrupt() expects an AEOI
1676 * mode for the 8259A whenever interrupts are routed
1677 * through I/O APICs. Also IRQ0 has to be enabled in
1678 * the 8259A which implies the virtual wire has to be
1679 * disabled in the local APIC.
1680 */
1681 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1682 init_8259A(1);
1683 if (timer_over_8254 > 0)
1684 enable_8259A_irq(0);
1685
1686 pin1 = find_isa_irq_pin(0, mp_INT);
1687 apic1 = find_isa_irq_apic(0, mp_INT);
1688 pin2 = ioapic_i8259.pin;
1689 apic2 = ioapic_i8259.apic;
1690
1691 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1692 cfg->vector, apic1, pin1, apic2, pin2);
1693
1694 if (pin1 != -1) {
1695 /*
1696 * Ok, does IRQ0 through the IOAPIC work?
1697 */
1698 unmask_IO_APIC_irq(0);
1699 if (!no_timer_check && timer_irq_works()) {
1700 nmi_watchdog_default();
1701 if (nmi_watchdog == NMI_IO_APIC) {
1702 disable_8259A_irq(0);
1703 setup_nmi();
1704 enable_8259A_irq(0);
1705 }
1706 if (disable_timer_pin_1 > 0)
1707 clear_IO_APIC_pin(0, pin1);
1708 goto out;
1709 }
1710 clear_IO_APIC_pin(apic1, pin1);
1711 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1712 "connected to IO-APIC\n");
1713 }
1714
1715 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1716 "through the 8259A ... ");
1717 if (pin2 != -1) {
1718 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1719 apic2, pin2);
1720 /*
1721 * legacy devices should be connected to IO APIC #0
1722 */
1723 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1724 if (timer_irq_works()) {
1725 apic_printk(APIC_VERBOSE," works.\n");
1726 nmi_watchdog_default();
1727 if (nmi_watchdog == NMI_IO_APIC) {
1728 setup_nmi();
1729 }
1730 goto out;
1731 }
1732 /*
1733 * Cleanup, just in case ...
1734 */
1735 clear_IO_APIC_pin(apic2, pin2);
1736 }
1737 apic_printk(APIC_VERBOSE," failed.\n");
1738
1739 if (nmi_watchdog == NMI_IO_APIC) {
1740 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1741 nmi_watchdog = 0;
1742 }
1743
1744 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1745
1746 disable_8259A_irq(0);
1747 irq_desc[0].chip = &lapic_irq_type;
1748 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1749 enable_8259A_irq(0);
1750
1751 if (timer_irq_works()) {
1752 apic_printk(APIC_VERBOSE," works.\n");
1753 goto out;
1754 }
1755 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1756 apic_printk(APIC_VERBOSE," failed.\n");
1757
1758 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1759
1760 init_8259A(0);
1761 make_8259A_irq(0);
1762 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1763
1764 unlock_ExtINT_logic();
1765
1766 if (timer_irq_works()) {
1767 apic_printk(APIC_VERBOSE," works.\n");
1768 goto out;
1769 }
1770 apic_printk(APIC_VERBOSE," failed :(.\n");
1771 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1772 out:
1773 local_irq_restore(flags);
1774 }
1775
1776 static int __init notimercheck(char *s)
1777 {
1778 no_timer_check = 1;
1779 return 1;
1780 }
1781 __setup("no_timer_check", notimercheck);
1782
1783 /*
1784 *
1785 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1786 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1787 * Linux doesn't really care, as it's not actually used
1788 * for any interrupt handling anyway.
1789 */
1790 #define PIC_IRQS (1<<2)
1791
1792 void __init setup_IO_APIC(void)
1793 {
1794
1795 /*
1796 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1797 */
1798
1799 if (acpi_ioapic)
1800 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1801 else
1802 io_apic_irqs = ~PIC_IRQS;
1803
1804 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1805
1806 sync_Arb_IDs();
1807 setup_IO_APIC_irqs();
1808 init_IO_APIC_traps();
1809 check_timer();
1810 if (!acpi_ioapic)
1811 print_IO_APIC();
1812 }
1813
1814 struct sysfs_ioapic_data {
1815 struct sys_device dev;
1816 struct IO_APIC_route_entry entry[0];
1817 };
1818 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1819
1820 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1821 {
1822 struct IO_APIC_route_entry *entry;
1823 struct sysfs_ioapic_data *data;
1824 int i;
1825
1826 data = container_of(dev, struct sysfs_ioapic_data, dev);
1827 entry = data->entry;
1828 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1829 *entry = ioapic_read_entry(dev->id, i);
1830
1831 return 0;
1832 }
1833
1834 static int ioapic_resume(struct sys_device *dev)
1835 {
1836 struct IO_APIC_route_entry *entry;
1837 struct sysfs_ioapic_data *data;
1838 unsigned long flags;
1839 union IO_APIC_reg_00 reg_00;
1840 int i;
1841
1842 data = container_of(dev, struct sysfs_ioapic_data, dev);
1843 entry = data->entry;
1844
1845 spin_lock_irqsave(&ioapic_lock, flags);
1846 reg_00.raw = io_apic_read(dev->id, 0);
1847 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1848 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1849 io_apic_write(dev->id, 0, reg_00.raw);
1850 }
1851 spin_unlock_irqrestore(&ioapic_lock, flags);
1852 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1853 ioapic_write_entry(dev->id, i, entry[i]);
1854
1855 return 0;
1856 }
1857
1858 static struct sysdev_class ioapic_sysdev_class = {
1859 .name = "ioapic",
1860 .suspend = ioapic_suspend,
1861 .resume = ioapic_resume,
1862 };
1863
1864 static int __init ioapic_init_sysfs(void)
1865 {
1866 struct sys_device * dev;
1867 int i, size, error;
1868
1869 error = sysdev_class_register(&ioapic_sysdev_class);
1870 if (error)
1871 return error;
1872
1873 for (i = 0; i < nr_ioapics; i++ ) {
1874 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1875 * sizeof(struct IO_APIC_route_entry);
1876 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1877 if (!mp_ioapic_data[i]) {
1878 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1879 continue;
1880 }
1881 dev = &mp_ioapic_data[i]->dev;
1882 dev->id = i;
1883 dev->cls = &ioapic_sysdev_class;
1884 error = sysdev_register(dev);
1885 if (error) {
1886 kfree(mp_ioapic_data[i]);
1887 mp_ioapic_data[i] = NULL;
1888 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1889 continue;
1890 }
1891 }
1892
1893 return 0;
1894 }
1895
1896 device_initcall(ioapic_init_sysfs);
1897
1898 /*
1899 * Dynamic irq allocate and deallocation
1900 */
1901 int create_irq(void)
1902 {
1903 /* Allocate an unused irq */
1904 int irq;
1905 int new;
1906 unsigned long flags;
1907
1908 irq = -ENOSPC;
1909 spin_lock_irqsave(&vector_lock, flags);
1910 for (new = (NR_IRQS - 1); new >= 0; new--) {
1911 if (platform_legacy_irq(new))
1912 continue;
1913 if (irq_cfg[new].vector != 0)
1914 continue;
1915 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1916 irq = new;
1917 break;
1918 }
1919 spin_unlock_irqrestore(&vector_lock, flags);
1920
1921 if (irq >= 0) {
1922 dynamic_irq_init(irq);
1923 }
1924 return irq;
1925 }
1926
1927 void destroy_irq(unsigned int irq)
1928 {
1929 unsigned long flags;
1930
1931 dynamic_irq_cleanup(irq);
1932
1933 spin_lock_irqsave(&vector_lock, flags);
1934 __clear_irq_vector(irq);
1935 spin_unlock_irqrestore(&vector_lock, flags);
1936 }
1937
1938 /*
1939 * MSI message composition
1940 */
1941 #ifdef CONFIG_PCI_MSI
1942 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1943 {
1944 struct irq_cfg *cfg = irq_cfg + irq;
1945 int err;
1946 unsigned dest;
1947 cpumask_t tmp;
1948
1949 tmp = TARGET_CPUS;
1950 err = assign_irq_vector(irq, tmp);
1951 if (!err) {
1952 cpus_and(tmp, cfg->domain, tmp);
1953 dest = cpu_mask_to_apicid(tmp);
1954
1955 msg->address_hi = MSI_ADDR_BASE_HI;
1956 msg->address_lo =
1957 MSI_ADDR_BASE_LO |
1958 ((INT_DEST_MODE == 0) ?
1959 MSI_ADDR_DEST_MODE_PHYSICAL:
1960 MSI_ADDR_DEST_MODE_LOGICAL) |
1961 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1962 MSI_ADDR_REDIRECTION_CPU:
1963 MSI_ADDR_REDIRECTION_LOWPRI) |
1964 MSI_ADDR_DEST_ID(dest);
1965
1966 msg->data =
1967 MSI_DATA_TRIGGER_EDGE |
1968 MSI_DATA_LEVEL_ASSERT |
1969 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1970 MSI_DATA_DELIVERY_FIXED:
1971 MSI_DATA_DELIVERY_LOWPRI) |
1972 MSI_DATA_VECTOR(cfg->vector);
1973 }
1974 return err;
1975 }
1976
1977 #ifdef CONFIG_SMP
1978 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1979 {
1980 struct irq_cfg *cfg = irq_cfg + irq;
1981 struct msi_msg msg;
1982 unsigned int dest;
1983 cpumask_t tmp;
1984
1985 cpus_and(tmp, mask, cpu_online_map);
1986 if (cpus_empty(tmp))
1987 return;
1988
1989 if (assign_irq_vector(irq, mask))
1990 return;
1991
1992 cpus_and(tmp, cfg->domain, mask);
1993 dest = cpu_mask_to_apicid(tmp);
1994
1995 read_msi_msg(irq, &msg);
1996
1997 msg.data &= ~MSI_DATA_VECTOR_MASK;
1998 msg.data |= MSI_DATA_VECTOR(cfg->vector);
1999 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2000 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2001
2002 write_msi_msg(irq, &msg);
2003 irq_desc[irq].affinity = mask;
2004 }
2005 #endif /* CONFIG_SMP */
2006
2007 /*
2008 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2009 * which implement the MSI or MSI-X Capability Structure.
2010 */
2011 static struct irq_chip msi_chip = {
2012 .name = "PCI-MSI",
2013 .unmask = unmask_msi_irq,
2014 .mask = mask_msi_irq,
2015 .ack = ack_apic_edge,
2016 #ifdef CONFIG_SMP
2017 .set_affinity = set_msi_irq_affinity,
2018 #endif
2019 .retrigger = ioapic_retrigger_irq,
2020 };
2021
2022 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2023 {
2024 struct msi_msg msg;
2025 int irq, ret;
2026 irq = create_irq();
2027 if (irq < 0)
2028 return irq;
2029
2030 ret = msi_compose_msg(dev, irq, &msg);
2031 if (ret < 0) {
2032 destroy_irq(irq);
2033 return ret;
2034 }
2035
2036 set_irq_msi(irq, desc);
2037 write_msi_msg(irq, &msg);
2038
2039 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2040
2041 return 0;
2042 }
2043
2044 void arch_teardown_msi_irq(unsigned int irq)
2045 {
2046 destroy_irq(irq);
2047 }
2048
2049 #ifdef CONFIG_DMAR
2050 #ifdef CONFIG_SMP
2051 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2052 {
2053 struct irq_cfg *cfg = irq_cfg + irq;
2054 struct msi_msg msg;
2055 unsigned int dest;
2056 cpumask_t tmp;
2057
2058 cpus_and(tmp, mask, cpu_online_map);
2059 if (cpus_empty(tmp))
2060 return;
2061
2062 if (assign_irq_vector(irq, mask))
2063 return;
2064
2065 cpus_and(tmp, cfg->domain, mask);
2066 dest = cpu_mask_to_apicid(tmp);
2067
2068 dmar_msi_read(irq, &msg);
2069
2070 msg.data &= ~MSI_DATA_VECTOR_MASK;
2071 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2072 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2073 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2074
2075 dmar_msi_write(irq, &msg);
2076 irq_desc[irq].affinity = mask;
2077 }
2078 #endif /* CONFIG_SMP */
2079
2080 struct irq_chip dmar_msi_type = {
2081 .name = "DMAR_MSI",
2082 .unmask = dmar_msi_unmask,
2083 .mask = dmar_msi_mask,
2084 .ack = ack_apic_edge,
2085 #ifdef CONFIG_SMP
2086 .set_affinity = dmar_msi_set_affinity,
2087 #endif
2088 .retrigger = ioapic_retrigger_irq,
2089 };
2090
2091 int arch_setup_dmar_msi(unsigned int irq)
2092 {
2093 int ret;
2094 struct msi_msg msg;
2095
2096 ret = msi_compose_msg(NULL, irq, &msg);
2097 if (ret < 0)
2098 return ret;
2099 dmar_msi_write(irq, &msg);
2100 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2101 "edge");
2102 return 0;
2103 }
2104 #endif
2105
2106 #endif /* CONFIG_PCI_MSI */
2107 /*
2108 * Hypertransport interrupt support
2109 */
2110 #ifdef CONFIG_HT_IRQ
2111
2112 #ifdef CONFIG_SMP
2113
2114 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2115 {
2116 struct ht_irq_msg msg;
2117 fetch_ht_irq_msg(irq, &msg);
2118
2119 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2120 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2121
2122 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2123 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2124
2125 write_ht_irq_msg(irq, &msg);
2126 }
2127
2128 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2129 {
2130 struct irq_cfg *cfg = irq_cfg + irq;
2131 unsigned int dest;
2132 cpumask_t tmp;
2133
2134 cpus_and(tmp, mask, cpu_online_map);
2135 if (cpus_empty(tmp))
2136 return;
2137
2138 if (assign_irq_vector(irq, mask))
2139 return;
2140
2141 cpus_and(tmp, cfg->domain, mask);
2142 dest = cpu_mask_to_apicid(tmp);
2143
2144 target_ht_irq(irq, dest, cfg->vector);
2145 irq_desc[irq].affinity = mask;
2146 }
2147 #endif
2148
2149 static struct irq_chip ht_irq_chip = {
2150 .name = "PCI-HT",
2151 .mask = mask_ht_irq,
2152 .unmask = unmask_ht_irq,
2153 .ack = ack_apic_edge,
2154 #ifdef CONFIG_SMP
2155 .set_affinity = set_ht_irq_affinity,
2156 #endif
2157 .retrigger = ioapic_retrigger_irq,
2158 };
2159
2160 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2161 {
2162 struct irq_cfg *cfg = irq_cfg + irq;
2163 int err;
2164 cpumask_t tmp;
2165
2166 tmp = TARGET_CPUS;
2167 err = assign_irq_vector(irq, tmp);
2168 if (!err) {
2169 struct ht_irq_msg msg;
2170 unsigned dest;
2171
2172 cpus_and(tmp, cfg->domain, tmp);
2173 dest = cpu_mask_to_apicid(tmp);
2174
2175 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2176
2177 msg.address_lo =
2178 HT_IRQ_LOW_BASE |
2179 HT_IRQ_LOW_DEST_ID(dest) |
2180 HT_IRQ_LOW_VECTOR(cfg->vector) |
2181 ((INT_DEST_MODE == 0) ?
2182 HT_IRQ_LOW_DM_PHYSICAL :
2183 HT_IRQ_LOW_DM_LOGICAL) |
2184 HT_IRQ_LOW_RQEOI_EDGE |
2185 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2186 HT_IRQ_LOW_MT_FIXED :
2187 HT_IRQ_LOW_MT_ARBITRATED) |
2188 HT_IRQ_LOW_IRQ_MASKED;
2189
2190 write_ht_irq_msg(irq, &msg);
2191
2192 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2193 handle_edge_irq, "edge");
2194 }
2195 return err;
2196 }
2197 #endif /* CONFIG_HT_IRQ */
2198
2199 /* --------------------------------------------------------------------------
2200 ACPI-based IOAPIC Configuration
2201 -------------------------------------------------------------------------- */
2202
2203 #ifdef CONFIG_ACPI
2204
2205 #define IO_APIC_MAX_ID 0xFE
2206
2207 int __init io_apic_get_redir_entries (int ioapic)
2208 {
2209 union IO_APIC_reg_01 reg_01;
2210 unsigned long flags;
2211
2212 spin_lock_irqsave(&ioapic_lock, flags);
2213 reg_01.raw = io_apic_read(ioapic, 1);
2214 spin_unlock_irqrestore(&ioapic_lock, flags);
2215
2216 return reg_01.bits.entries;
2217 }
2218
2219
2220 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2221 {
2222 if (!IO_APIC_IRQ(irq)) {
2223 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2224 ioapic);
2225 return -EINVAL;
2226 }
2227
2228 /*
2229 * IRQs < 16 are already in the irq_2_pin[] map
2230 */
2231 if (irq >= 16)
2232 add_pin_to_irq(irq, ioapic, pin);
2233
2234 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2235
2236 return 0;
2237 }
2238
2239
2240 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2241 {
2242 int i;
2243
2244 if (skip_ioapic_setup)
2245 return -1;
2246
2247 for (i = 0; i < mp_irq_entries; i++)
2248 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2249 mp_irqs[i].mpc_srcbusirq == bus_irq)
2250 break;
2251 if (i >= mp_irq_entries)
2252 return -1;
2253
2254 *trigger = irq_trigger(i);
2255 *polarity = irq_polarity(i);
2256 return 0;
2257 }
2258
2259 #endif /* CONFIG_ACPI */
2260
2261 /*
2262 * This function currently is only a helper for the i386 smp boot process where
2263 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2264 * so mask in all cases should simply be TARGET_CPUS
2265 */
2266 #ifdef CONFIG_SMP
2267 void __init setup_ioapic_dest(void)
2268 {
2269 int pin, ioapic, irq, irq_entry;
2270
2271 if (skip_ioapic_setup == 1)
2272 return;
2273
2274 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2275 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2276 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2277 if (irq_entry == -1)
2278 continue;
2279 irq = pin_2_irq(irq_entry, ioapic, pin);
2280
2281 /* setup_IO_APIC_irqs could fail to get vector for some device
2282 * when you have too many devices, because at that time only boot
2283 * cpu is online.
2284 */
2285 if (!irq_cfg[irq].vector)
2286 setup_IO_APIC_irq(ioapic, pin, irq,
2287 irq_trigger(irq_entry),
2288 irq_polarity(irq_entry));
2289 else
2290 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2291 }
2292
2293 }
2294 }
2295 #endif
2296
2297 #define IOAPIC_RESOURCE_NAME_SIZE 11
2298
2299 static struct resource *ioapic_resources;
2300
2301 static struct resource * __init ioapic_setup_resources(void)
2302 {
2303 unsigned long n;
2304 struct resource *res;
2305 char *mem;
2306 int i;
2307
2308 if (nr_ioapics <= 0)
2309 return NULL;
2310
2311 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2312 n *= nr_ioapics;
2313
2314 mem = alloc_bootmem(n);
2315 res = (void *)mem;
2316
2317 if (mem != NULL) {
2318 mem += sizeof(struct resource) * nr_ioapics;
2319
2320 for (i = 0; i < nr_ioapics; i++) {
2321 res[i].name = mem;
2322 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2323 sprintf(mem, "IOAPIC %u", i);
2324 mem += IOAPIC_RESOURCE_NAME_SIZE;
2325 }
2326 }
2327
2328 ioapic_resources = res;
2329
2330 return res;
2331 }
2332
2333 void __init ioapic_init_mappings(void)
2334 {
2335 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2336 struct resource *ioapic_res;
2337 int i;
2338
2339 ioapic_res = ioapic_setup_resources();
2340 for (i = 0; i < nr_ioapics; i++) {
2341 if (smp_found_config) {
2342 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2343 } else {
2344 ioapic_phys = (unsigned long)
2345 alloc_bootmem_pages(PAGE_SIZE);
2346 ioapic_phys = __pa(ioapic_phys);
2347 }
2348 set_fixmap_nocache(idx, ioapic_phys);
2349 apic_printk(APIC_VERBOSE,
2350 "mapped IOAPIC to %016lx (%016lx)\n",
2351 __fix_to_virt(idx), ioapic_phys);
2352 idx++;
2353
2354 if (ioapic_res != NULL) {
2355 ioapic_res->start = ioapic_phys;
2356 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2357 ioapic_res++;
2358 }
2359 }
2360 }
2361
2362 static int __init ioapic_insert_resources(void)
2363 {
2364 int i;
2365 struct resource *r = ioapic_resources;
2366
2367 if (!r) {
2368 printk(KERN_ERR
2369 "IO APIC resources could be not be allocated.\n");
2370 return -1;
2371 }
2372
2373 for (i = 0; i < nr_ioapics; i++) {
2374 insert_resource(&iomem_resource, r);
2375 r++;
2376 }
2377
2378 return 0;
2379 }
2380
2381 /* Insert the IO APIC resources after PCI initialization has occured to handle
2382 * IO APICS that are mapped in on a BAR in PCI space. */
2383 late_initcall(ioapic_insert_resources);
2384
Linux kernel - Deliverables
This page took 0.084399 seconds and 4 git commands to generate.