2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
49 #include <asm/i8259.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
56 #include <mach_apic.h>
58 #define __apicdebuginit(type) static type __init
62 int sis_apic_bug
; /* not actually supported, dummy for compile */
64 static DEFINE_SPINLOCK(ioapic_lock
);
65 static DEFINE_SPINLOCK(vector_lock
);
69 * Rough estimation of how many shared IRQs there are, can
75 * # of IRQ routing registers
77 int nr_ioapic_registers
[MAX_IO_APICS
];
79 /* I/O APIC entries */
80 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
83 /* MP IRQ source entries */
84 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
86 /* # of MP IRQ source entries */
89 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
91 int skip_ioapic_setup
;
93 static int __init
parse_noapic(char *str
)
95 disable_ioapic_setup();
98 early_param("noapic", parse_noapic
);
105 struct irq_cfg
*next
;
106 struct irq_pin_list
*irq_2_pin
;
108 cpumask_t old_domain
;
109 unsigned move_cleanup_count
;
111 u8 move_in_progress
: 1;
114 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
115 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
116 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
117 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
118 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
119 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
120 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
121 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
122 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
123 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
124 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
125 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
126 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
127 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
128 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
129 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
130 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
131 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
134 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
135 /* need to be biger than size of irq_cfg_legacy */
136 static int nr_irq_cfg
= 32;
138 static int __init
parse_nr_irq_cfg(char *arg
)
141 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
148 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
150 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
152 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
155 static struct irq_cfg
*irq_cfgx
;
156 static struct irq_cfg
*irq_cfgx_free
;
157 static void __init
init_work(void *data
)
159 struct dyn_array
*da
= data
;
166 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
168 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
169 for (i
= legacy_count
; i
< *da
->nr
; i
++)
170 init_one_irq_cfg(&cfg
[i
]);
172 for (i
= 1; i
< *da
->nr
; i
++)
173 cfg
[i
-1].next
= &cfg
[i
];
175 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
176 irq_cfgx
[legacy_count
- 1].next
= NULL
;
179 #define for_each_irq_cfg(cfg) \
180 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
182 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
184 static struct irq_cfg
*irq_cfg(unsigned int irq
)
199 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
201 struct irq_cfg
*cfg
, *cfg_pri
;
205 cfg_pri
= cfg
= irq_cfgx
;
215 if (!irq_cfgx_free
) {
217 unsigned long total_bytes
;
219 * we run out of pre-allocate ones, allocate more
221 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
223 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
225 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
227 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
230 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
233 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
235 for (i
= 0; i
< nr_irq_cfg
; i
++)
236 init_one_irq_cfg(&cfg
[i
]);
238 for (i
= 1; i
< nr_irq_cfg
; i
++)
239 cfg
[i
-1].next
= &cfg
[i
];
245 irq_cfgx_free
= irq_cfgx_free
->next
;
252 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
253 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
255 /* dump the results */
258 unsigned long bytes
= sizeof(struct irq_cfg
);
260 printk(KERN_DEBUG
"=========================== %d\n", irq
);
261 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
262 for_each_irq_cfg(cfg
) {
264 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
266 printk(KERN_DEBUG
"===========================\n");
273 * This is performance-critical, we want to do it O(1)
275 * the indexing order of this array favors 1:1 mappings
276 * between pins and IRQs.
279 struct irq_pin_list
{
281 struct irq_pin_list
*next
;
284 static struct irq_pin_list
*irq_2_pin_head
;
285 /* fill one page ? */
286 static int nr_irq_2_pin
= 0x100;
287 static struct irq_pin_list
*irq_2_pin_ptr
;
288 static void __init
irq_2_pin_init_work(void *data
)
290 struct dyn_array
*da
= data
;
291 struct irq_pin_list
*pin
;
296 for (i
= 1; i
< *da
->nr
; i
++)
297 pin
[i
-1].next
= &pin
[i
];
299 irq_2_pin_ptr
= &pin
[0];
301 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
303 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
305 struct irq_pin_list
*pin
;
311 irq_2_pin_ptr
= pin
->next
;
317 * we run out of pre-allocate ones, allocate more
319 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
322 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
325 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
326 nr_irq_2_pin
, PAGE_SIZE
, 0);
329 panic("can not get more irq_2_pin\n");
331 for (i
= 1; i
< nr_irq_2_pin
; i
++)
332 pin
[i
-1].next
= &pin
[i
];
334 irq_2_pin_ptr
= pin
->next
;
342 unsigned int unused
[3];
346 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
348 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
349 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
352 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
354 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
355 writel(reg
, &io_apic
->index
);
356 return readl(&io_apic
->data
);
359 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
361 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
362 writel(reg
, &io_apic
->index
);
363 writel(value
, &io_apic
->data
);
367 * Re-write a value: to be used for read-modify-write
368 * cycles where the read already set up the index register.
370 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
372 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
373 writel(value
, &io_apic
->data
);
376 static bool io_apic_level_ack_pending(unsigned int irq
)
378 struct irq_pin_list
*entry
;
380 struct irq_cfg
*cfg
= irq_cfg(irq
);
382 spin_lock_irqsave(&ioapic_lock
, flags
);
383 entry
= cfg
->irq_2_pin
;
391 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
392 /* Is the remote IRR bit set? */
393 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
394 spin_unlock_irqrestore(&ioapic_lock
, flags
);
401 spin_unlock_irqrestore(&ioapic_lock
, flags
);
407 struct { u32 w1
, w2
; };
408 struct IO_APIC_route_entry entry
;
411 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
413 union entry_union eu
;
415 spin_lock_irqsave(&ioapic_lock
, flags
);
416 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
417 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
418 spin_unlock_irqrestore(&ioapic_lock
, flags
);
423 * When we write a new IO APIC routing entry, we need to write the high
424 * word first! If the mask bit in the low word is clear, we will enable
425 * the interrupt, and we need to make sure the entry is fully populated
426 * before that happens.
429 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
431 union entry_union eu
;
433 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
434 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
437 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
440 spin_lock_irqsave(&ioapic_lock
, flags
);
441 __ioapic_write_entry(apic
, pin
, e
);
442 spin_unlock_irqrestore(&ioapic_lock
, flags
);
446 * When we mask an IO APIC routing entry, we need to write the low
447 * word first, in order to set the mask bit before we change the
450 static void ioapic_mask_entry(int apic
, int pin
)
453 union entry_union eu
= { .entry
.mask
= 1 };
455 spin_lock_irqsave(&ioapic_lock
, flags
);
456 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
457 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
458 spin_unlock_irqrestore(&ioapic_lock
, flags
);
462 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
466 struct irq_pin_list
*entry
;
469 entry
= cfg
->irq_2_pin
;
478 #ifdef CONFIG_INTR_REMAP
480 * With interrupt-remapping, destination information comes
481 * from interrupt-remapping table entry.
483 if (!irq_remapped(irq
))
484 io_apic_write(apic
, 0x11 + pin
*2, dest
);
486 io_apic_write(apic
, 0x11 + pin
*2, dest
);
488 reg
= io_apic_read(apic
, 0x10 + pin
*2);
489 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
491 io_apic_modify(apic
, reg
);
498 static int assign_irq_vector(int irq
, cpumask_t mask
);
500 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
502 struct irq_cfg
*cfg
= irq_cfg(irq
);
506 struct irq_desc
*desc
;
508 cpus_and(tmp
, mask
, cpu_online_map
);
512 if (assign_irq_vector(irq
, mask
))
515 cpus_and(tmp
, cfg
->domain
, mask
);
516 dest
= cpu_mask_to_apicid(tmp
);
519 * Only the high 8 bits are valid.
521 dest
= SET_APIC_LOGICAL_ID(dest
);
523 desc
= irq_to_desc(irq
);
524 spin_lock_irqsave(&ioapic_lock
, flags
);
525 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
526 desc
->affinity
= mask
;
527 spin_unlock_irqrestore(&ioapic_lock
, flags
);
532 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
533 * shared ISA-space IRQs, so we have to support them. We are super
534 * fast in the common case, and fast for shared ISA-space IRQs.
536 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
539 struct irq_pin_list
*entry
;
541 /* first time to refer irq_cfg, so with new */
542 cfg
= irq_cfg_alloc(irq
);
543 entry
= cfg
->irq_2_pin
;
545 entry
= get_one_free_irq_2_pin();
546 cfg
->irq_2_pin
= entry
;
549 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
553 while (entry
->next
) {
554 /* not again, please */
555 if (entry
->apic
== apic
&& entry
->pin
== pin
)
561 entry
->next
= get_one_free_irq_2_pin();
565 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
569 * Reroute an IRQ to a different pin.
571 static void __init
replace_pin_at_irq(unsigned int irq
,
572 int oldapic
, int oldpin
,
573 int newapic
, int newpin
)
575 struct irq_cfg
*cfg
= irq_cfg(irq
);
576 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
580 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
581 entry
->apic
= newapic
;
584 /* every one is different, right? */
590 /* why? call replace before add? */
592 add_pin_to_irq(irq
, newapic
, newpin
);
596 * Synchronize the IO-APIC and the CPU by doing
597 * a dummy read from the IO-APIC
599 static inline void io_apic_sync(unsigned int apic
)
601 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
602 readl(&io_apic
->data
);
605 #define __DO_ACTION(R, ACTION, FINAL) \
609 struct irq_cfg *cfg; \
610 struct irq_pin_list *entry; \
612 cfg = irq_cfg(irq); \
613 entry = cfg->irq_2_pin; \
619 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
621 io_apic_modify(entry->apic, reg); \
625 entry = entry->next; \
629 #define DO_ACTION(name,R,ACTION, FINAL) \
631 static void name##_IO_APIC_irq (unsigned int irq) \
632 __DO_ACTION(R, ACTION, FINAL)
635 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, io_apic_sync(entry
->apic
))
638 DO_ACTION(__unmask
, 0, &= ~IO_APIC_REDIR_MASKED
, )
640 static void mask_IO_APIC_irq (unsigned int irq
)
644 spin_lock_irqsave(&ioapic_lock
, flags
);
645 __mask_IO_APIC_irq(irq
);
646 spin_unlock_irqrestore(&ioapic_lock
, flags
);
649 static void unmask_IO_APIC_irq (unsigned int irq
)
653 spin_lock_irqsave(&ioapic_lock
, flags
);
654 __unmask_IO_APIC_irq(irq
);
655 spin_unlock_irqrestore(&ioapic_lock
, flags
);
658 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
660 struct IO_APIC_route_entry entry
;
662 /* Check delivery_mode to be sure we're not clearing an SMI pin */
663 entry
= ioapic_read_entry(apic
, pin
);
664 if (entry
.delivery_mode
== dest_SMI
)
667 * Disable it in the IO-APIC irq-routing table:
669 ioapic_mask_entry(apic
, pin
);
672 static void clear_IO_APIC (void)
676 for (apic
= 0; apic
< nr_ioapics
; apic
++)
677 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
678 clear_IO_APIC_pin(apic
, pin
);
681 #ifdef CONFIG_INTR_REMAP
682 /* I/O APIC RTE contents at the OS boot up */
683 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
686 * Saves and masks all the unmasked IO-APIC RTE's
688 int save_mask_IO_APIC_setup(void)
690 union IO_APIC_reg_01 reg_01
;
695 * The number of IO-APIC IRQ registers (== #pins):
697 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
698 spin_lock_irqsave(&ioapic_lock
, flags
);
699 reg_01
.raw
= io_apic_read(apic
, 1);
700 spin_unlock_irqrestore(&ioapic_lock
, flags
);
701 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
704 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
705 early_ioapic_entries
[apic
] =
706 kzalloc(sizeof(struct IO_APIC_route_entry
) *
707 nr_ioapic_registers
[apic
], GFP_KERNEL
);
708 if (!early_ioapic_entries
[apic
])
712 for (apic
= 0; apic
< nr_ioapics
; apic
++)
713 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
714 struct IO_APIC_route_entry entry
;
716 entry
= early_ioapic_entries
[apic
][pin
] =
717 ioapic_read_entry(apic
, pin
);
720 ioapic_write_entry(apic
, pin
, entry
);
726 void restore_IO_APIC_setup(void)
730 for (apic
= 0; apic
< nr_ioapics
; apic
++)
731 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
732 ioapic_write_entry(apic
, pin
,
733 early_ioapic_entries
[apic
][pin
]);
736 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
739 * for now plain restore of previous settings.
740 * TBD: In the case of OS enabling interrupt-remapping,
741 * IO-APIC RTE's need to be setup to point to interrupt-remapping
742 * table entries. for now, do a plain restore, and wait for
743 * the setup_IO_APIC_irqs() to do proper initialization.
745 restore_IO_APIC_setup();
750 * Find the IRQ entry number of a certain pin.
752 static int find_irq_entry(int apic
, int pin
, int type
)
756 for (i
= 0; i
< mp_irq_entries
; i
++)
757 if (mp_irqs
[i
].mp_irqtype
== type
&&
758 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
759 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
760 mp_irqs
[i
].mp_dstirq
== pin
)
767 * Find the pin to which IRQ[irq] (ISA) is connected
769 static int __init
find_isa_irq_pin(int irq
, int type
)
773 for (i
= 0; i
< mp_irq_entries
; i
++) {
774 int lbus
= mp_irqs
[i
].mp_srcbus
;
776 if (test_bit(lbus
, mp_bus_not_pci
) &&
777 (mp_irqs
[i
].mp_irqtype
== type
) &&
778 (mp_irqs
[i
].mp_srcbusirq
== irq
))
780 return mp_irqs
[i
].mp_dstirq
;
785 static int __init
find_isa_irq_apic(int irq
, int type
)
789 for (i
= 0; i
< mp_irq_entries
; i
++) {
790 int lbus
= mp_irqs
[i
].mp_srcbus
;
792 if (test_bit(lbus
, mp_bus_not_pci
) &&
793 (mp_irqs
[i
].mp_irqtype
== type
) &&
794 (mp_irqs
[i
].mp_srcbusirq
== irq
))
797 if (i
< mp_irq_entries
) {
799 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
800 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
809 * Find a specific PCI IRQ entry.
810 * Not an __init, possibly needed by modules
812 static int pin_2_irq(int idx
, int apic
, int pin
);
814 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
816 int apic
, i
, best_guess
= -1;
818 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
820 if (test_bit(bus
, mp_bus_not_pci
)) {
821 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
824 for (i
= 0; i
< mp_irq_entries
; i
++) {
825 int lbus
= mp_irqs
[i
].mp_srcbus
;
827 for (apic
= 0; apic
< nr_ioapics
; apic
++)
828 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
829 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
832 if (!test_bit(lbus
, mp_bus_not_pci
) &&
833 !mp_irqs
[i
].mp_irqtype
&&
835 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
836 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
838 if (!(apic
|| IO_APIC_IRQ(irq
)))
841 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
844 * Use the first all-but-pin matching entry as a
845 * best-guess fuzzy result for broken mptables.
854 /* ISA interrupts are always polarity zero edge triggered,
855 * when listed as conforming in the MP table. */
857 #define default_ISA_trigger(idx) (0)
858 #define default_ISA_polarity(idx) (0)
860 /* PCI interrupts are always polarity one level triggered,
861 * when listed as conforming in the MP table. */
863 #define default_PCI_trigger(idx) (1)
864 #define default_PCI_polarity(idx) (1)
866 static int MPBIOS_polarity(int idx
)
868 int bus
= mp_irqs
[idx
].mp_srcbus
;
872 * Determine IRQ line polarity (high active or low active):
874 switch (mp_irqs
[idx
].mp_irqflag
& 3)
876 case 0: /* conforms, ie. bus-type dependent polarity */
877 if (test_bit(bus
, mp_bus_not_pci
))
878 polarity
= default_ISA_polarity(idx
);
880 polarity
= default_PCI_polarity(idx
);
882 case 1: /* high active */
887 case 2: /* reserved */
889 printk(KERN_WARNING
"broken BIOS!!\n");
893 case 3: /* low active */
898 default: /* invalid */
900 printk(KERN_WARNING
"broken BIOS!!\n");
908 static int MPBIOS_trigger(int idx
)
910 int bus
= mp_irqs
[idx
].mp_srcbus
;
914 * Determine IRQ trigger mode (edge or level sensitive):
916 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
918 case 0: /* conforms, ie. bus-type dependent */
919 if (test_bit(bus
, mp_bus_not_pci
))
920 trigger
= default_ISA_trigger(idx
);
922 trigger
= default_PCI_trigger(idx
);
929 case 2: /* reserved */
931 printk(KERN_WARNING
"broken BIOS!!\n");
940 default: /* invalid */
942 printk(KERN_WARNING
"broken BIOS!!\n");
950 static inline int irq_polarity(int idx
)
952 return MPBIOS_polarity(idx
);
955 static inline int irq_trigger(int idx
)
957 return MPBIOS_trigger(idx
);
960 static int pin_2_irq(int idx
, int apic
, int pin
)
963 int bus
= mp_irqs
[idx
].mp_srcbus
;
966 * Debugging check, we are in big trouble if this message pops up!
968 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
969 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
971 if (test_bit(bus
, mp_bus_not_pci
)) {
972 irq
= mp_irqs
[idx
].mp_srcbusirq
;
975 * PCI IRQs are mapped in order
979 irq
+= nr_ioapic_registers
[i
++];
985 void lock_vector_lock(void)
987 /* Used to the online set of cpus does not change
988 * during assign_irq_vector.
990 spin_lock(&vector_lock
);
993 void unlock_vector_lock(void)
995 spin_unlock(&vector_lock
);
998 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1001 * NOTE! The local APIC isn't very good at handling
1002 * multiple interrupts at the same interrupt level.
1003 * As the interrupt level is determined by taking the
1004 * vector number and shifting that right by 4, we
1005 * want to spread these out a bit so that they don't
1006 * all fall in the same interrupt level.
1008 * Also, we've got to be careful not to trash gate
1009 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1011 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1012 unsigned int old_vector
;
1014 struct irq_cfg
*cfg
;
1018 /* Only try and allocate irqs on cpus that are present */
1019 cpus_and(mask
, mask
, cpu_online_map
);
1021 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1024 old_vector
= cfg
->vector
;
1027 cpus_and(tmp
, cfg
->domain
, mask
);
1028 if (!cpus_empty(tmp
))
1032 for_each_cpu_mask_nr(cpu
, mask
) {
1033 cpumask_t domain
, new_mask
;
1037 domain
= vector_allocation_domain(cpu
);
1038 cpus_and(new_mask
, domain
, cpu_online_map
);
1040 vector
= current_vector
;
1041 offset
= current_offset
;
1044 if (vector
>= first_system_vector
) {
1045 /* If we run out of vectors on large boxen, must share them. */
1046 offset
= (offset
+ 1) % 8;
1047 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1049 if (unlikely(current_vector
== vector
))
1051 if (vector
== IA32_SYSCALL_VECTOR
)
1053 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1054 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1057 current_vector
= vector
;
1058 current_offset
= offset
;
1060 cfg
->move_in_progress
= 1;
1061 cfg
->old_domain
= cfg
->domain
;
1063 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1064 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1065 cfg
->vector
= vector
;
1066 cfg
->domain
= domain
;
1072 static int assign_irq_vector(int irq
, cpumask_t mask
)
1075 unsigned long flags
;
1077 spin_lock_irqsave(&vector_lock
, flags
);
1078 err
= __assign_irq_vector(irq
, mask
);
1079 spin_unlock_irqrestore(&vector_lock
, flags
);
1083 static void __clear_irq_vector(int irq
)
1085 struct irq_cfg
*cfg
;
1090 BUG_ON(!cfg
->vector
);
1092 vector
= cfg
->vector
;
1093 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1094 for_each_cpu_mask_nr(cpu
, mask
)
1095 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1098 cpus_clear(cfg
->domain
);
1101 void __setup_vector_irq(int cpu
)
1103 /* Initialize vector_irq on a new cpu */
1104 /* This function must be called with vector_lock held */
1106 struct irq_cfg
*cfg
;
1108 /* Mark the inuse vectors */
1109 for_each_irq_cfg(cfg
) {
1110 if (!cpu_isset(cpu
, cfg
->domain
))
1112 vector
= cfg
->vector
;
1114 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1116 /* Mark the free vectors */
1117 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1118 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1123 if (!cpu_isset(cpu
, cfg
->domain
))
1124 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1128 static struct irq_chip ioapic_chip
;
1129 #ifdef CONFIG_INTR_REMAP
1130 static struct irq_chip ir_ioapic_chip
;
1133 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1135 struct irq_desc
*desc
;
1137 /* first time to use this irq_desc */
1139 desc
= irq_to_desc(irq
);
1141 desc
= irq_to_desc_alloc(irq
);
1144 desc
->status
|= IRQ_LEVEL
;
1146 desc
->status
&= ~IRQ_LEVEL
;
1148 #ifdef CONFIG_INTR_REMAP
1149 if (irq_remapped(irq
)) {
1150 desc
->status
|= IRQ_MOVE_PCNTXT
;
1152 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1156 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1157 handle_edge_irq
, "edge");
1162 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1166 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1167 handle_edge_irq
, "edge");
1170 static int setup_ioapic_entry(int apic
, int irq
,
1171 struct IO_APIC_route_entry
*entry
,
1172 unsigned int destination
, int trigger
,
1173 int polarity
, int vector
)
1176 * add it to the IO-APIC irq-routing table:
1178 memset(entry
,0,sizeof(*entry
));
1180 #ifdef CONFIG_INTR_REMAP
1181 if (intr_remapping_enabled
) {
1182 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1184 struct IR_IO_APIC_route_entry
*ir_entry
=
1185 (struct IR_IO_APIC_route_entry
*) entry
;
1189 panic("No mapping iommu for ioapic %d\n", apic
);
1191 index
= alloc_irte(iommu
, irq
, 1);
1193 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1195 memset(&irte
, 0, sizeof(irte
));
1198 irte
.dst_mode
= INT_DEST_MODE
;
1199 irte
.trigger_mode
= trigger
;
1200 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1201 irte
.vector
= vector
;
1202 irte
.dest_id
= IRTE_DEST(destination
);
1204 modify_irte(irq
, &irte
);
1206 ir_entry
->index2
= (index
>> 15) & 0x1;
1208 ir_entry
->format
= 1;
1209 ir_entry
->index
= (index
& 0x7fff);
1213 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1214 entry
->dest_mode
= INT_DEST_MODE
;
1215 entry
->dest
= destination
;
1218 entry
->mask
= 0; /* enable IRQ */
1219 entry
->trigger
= trigger
;
1220 entry
->polarity
= polarity
;
1221 entry
->vector
= vector
;
1223 /* Mask level triggered irqs.
1224 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1231 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1232 int trigger
, int polarity
)
1234 struct irq_cfg
*cfg
;
1235 struct IO_APIC_route_entry entry
;
1238 if (!IO_APIC_IRQ(irq
))
1244 if (assign_irq_vector(irq
, mask
))
1247 cpus_and(mask
, cfg
->domain
, mask
);
1249 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1250 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1251 "IRQ %d Mode:%i Active:%i)\n",
1252 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1253 irq
, trigger
, polarity
);
1256 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1257 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1259 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1260 mp_ioapics
[apic
].mp_apicid
, pin
);
1261 __clear_irq_vector(irq
);
1265 ioapic_register_intr(irq
, trigger
);
1267 disable_8259A_irq(irq
);
1269 ioapic_write_entry(apic
, pin
, entry
);
1272 static void __init
setup_IO_APIC_irqs(void)
1274 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1276 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1278 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1279 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1281 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1284 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1287 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1290 if (!first_notcon
) {
1291 apic_printk(APIC_VERBOSE
, " not connected.\n");
1295 irq
= pin_2_irq(idx
, apic
, pin
);
1296 add_pin_to_irq(irq
, apic
, pin
);
1298 setup_IO_APIC_irq(apic
, pin
, irq
,
1299 irq_trigger(idx
), irq_polarity(idx
));
1304 apic_printk(APIC_VERBOSE
, " not connected.\n");
1308 * Set up the timer pin, possibly with the 8259A-master behind.
1310 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1313 struct IO_APIC_route_entry entry
;
1315 #ifdef CONFIG_INTR_REMAP
1316 if (intr_remapping_enabled
)
1320 memset(&entry
, 0, sizeof(entry
));
1323 * We use logical delivery to get the timer IRQ
1326 entry
.dest_mode
= INT_DEST_MODE
;
1327 entry
.mask
= 1; /* mask IRQ now */
1328 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1329 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1332 entry
.vector
= vector
;
1335 * The timer IRQ doesn't have to know that behind the
1336 * scene we may have a 8259A-master in AEOI mode ...
1338 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1341 * Add it to the IO-APIC irq-routing table:
1343 ioapic_write_entry(apic
, pin
, entry
);
1347 __apicdebuginit(void) print_IO_APIC(void)
1350 union IO_APIC_reg_00 reg_00
;
1351 union IO_APIC_reg_01 reg_01
;
1352 union IO_APIC_reg_02 reg_02
;
1353 unsigned long flags
;
1354 struct irq_cfg
*cfg
;
1356 if (apic_verbosity
== APIC_QUIET
)
1359 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1360 for (i
= 0; i
< nr_ioapics
; i
++)
1361 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1362 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1365 * We are a bit conservative about what we expect. We have to
1366 * know about every hardware change ASAP.
1368 printk(KERN_INFO
"testing the IO APIC.......................\n");
1370 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1372 spin_lock_irqsave(&ioapic_lock
, flags
);
1373 reg_00
.raw
= io_apic_read(apic
, 0);
1374 reg_01
.raw
= io_apic_read(apic
, 1);
1375 if (reg_01
.bits
.version
>= 0x10)
1376 reg_02
.raw
= io_apic_read(apic
, 2);
1377 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1380 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1381 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1382 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1383 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1384 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1386 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1387 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1389 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1390 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1392 if (reg_01
.bits
.version
>= 0x10) {
1393 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1394 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1397 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1399 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1400 " Stat Dmod Deli Vect: \n");
1402 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1403 struct IO_APIC_route_entry entry
;
1405 entry
= ioapic_read_entry(apic
, i
);
1407 printk(KERN_DEBUG
" %02x %03X ",
1412 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1417 entry
.delivery_status
,
1419 entry
.delivery_mode
,
1424 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1425 for_each_irq_cfg(cfg
) {
1426 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1429 printk(KERN_DEBUG
"IRQ%d ", cfg
->irq
);
1431 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1434 entry
= entry
->next
;
1439 printk(KERN_INFO
".................................... done.\n");
1444 __apicdebuginit(void) print_APIC_bitfield(int base
)
1449 if (apic_verbosity
== APIC_QUIET
)
1452 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1453 for (i
= 0; i
< 8; i
++) {
1454 v
= apic_read(base
+ i
*0x10);
1455 for (j
= 0; j
< 32; j
++) {
1465 __apicdebuginit(void) print_local_APIC(void *dummy
)
1467 unsigned int v
, ver
, maxlvt
;
1470 if (apic_verbosity
== APIC_QUIET
)
1473 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1474 smp_processor_id(), hard_smp_processor_id());
1475 v
= apic_read(APIC_ID
);
1476 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1477 v
= apic_read(APIC_LVR
);
1478 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1479 ver
= GET_APIC_VERSION(v
);
1480 maxlvt
= lapic_get_maxlvt();
1482 v
= apic_read(APIC_TASKPRI
);
1483 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1485 v
= apic_read(APIC_ARBPRI
);
1486 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1487 v
& APIC_ARBPRI_MASK
);
1488 v
= apic_read(APIC_PROCPRI
);
1489 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1491 v
= apic_read(APIC_EOI
);
1492 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1493 v
= apic_read(APIC_RRR
);
1494 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1495 v
= apic_read(APIC_LDR
);
1496 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1497 v
= apic_read(APIC_DFR
);
1498 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1499 v
= apic_read(APIC_SPIV
);
1500 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1502 printk(KERN_DEBUG
"... APIC ISR field:\n");
1503 print_APIC_bitfield(APIC_ISR
);
1504 printk(KERN_DEBUG
"... APIC TMR field:\n");
1505 print_APIC_bitfield(APIC_TMR
);
1506 printk(KERN_DEBUG
"... APIC IRR field:\n");
1507 print_APIC_bitfield(APIC_IRR
);
1509 v
= apic_read(APIC_ESR
);
1510 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1512 icr
= apic_icr_read();
1513 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1514 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1516 v
= apic_read(APIC_LVTT
);
1517 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1519 if (maxlvt
> 3) { /* PC is LVT#4. */
1520 v
= apic_read(APIC_LVTPC
);
1521 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1523 v
= apic_read(APIC_LVT0
);
1524 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1525 v
= apic_read(APIC_LVT1
);
1526 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1528 if (maxlvt
> 2) { /* ERR is LVT#3. */
1529 v
= apic_read(APIC_LVTERR
);
1530 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1533 v
= apic_read(APIC_TMICT
);
1534 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1535 v
= apic_read(APIC_TMCCT
);
1536 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1537 v
= apic_read(APIC_TDCR
);
1538 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1542 __apicdebuginit(void) print_all_local_APICs(void)
1544 on_each_cpu(print_local_APIC
, NULL
, 1);
1547 __apicdebuginit(void) print_PIC(void)
1550 unsigned long flags
;
1552 if (apic_verbosity
== APIC_QUIET
)
1555 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1557 spin_lock_irqsave(&i8259A_lock
, flags
);
1559 v
= inb(0xa1) << 8 | inb(0x21);
1560 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1562 v
= inb(0xa0) << 8 | inb(0x20);
1563 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1567 v
= inb(0xa0) << 8 | inb(0x20);
1571 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1573 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1575 v
= inb(0x4d1) << 8 | inb(0x4d0);
1576 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1579 __apicdebuginit(int) print_all_ICs(void)
1582 print_all_local_APICs();
1588 fs_initcall(print_all_ICs
);
1591 /* Where if anywhere is the i8259 connect in external int mode */
1592 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1594 void __init
enable_IO_APIC(void)
1596 union IO_APIC_reg_01 reg_01
;
1597 int i8259_apic
, i8259_pin
;
1599 unsigned long flags
;
1602 * The number of IO-APIC IRQ registers (== #pins):
1604 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1605 spin_lock_irqsave(&ioapic_lock
, flags
);
1606 reg_01
.raw
= io_apic_read(apic
, 1);
1607 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1608 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1610 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1612 /* See if any of the pins is in ExtINT mode */
1613 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1614 struct IO_APIC_route_entry entry
;
1615 entry
= ioapic_read_entry(apic
, pin
);
1617 /* If the interrupt line is enabled and in ExtInt mode
1618 * I have found the pin where the i8259 is connected.
1620 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1621 ioapic_i8259
.apic
= apic
;
1622 ioapic_i8259
.pin
= pin
;
1628 /* Look to see what if the MP table has reported the ExtINT */
1629 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1630 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1631 /* Trust the MP table if nothing is setup in the hardware */
1632 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1633 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1634 ioapic_i8259
.pin
= i8259_pin
;
1635 ioapic_i8259
.apic
= i8259_apic
;
1637 /* Complain if the MP table and the hardware disagree */
1638 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1639 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1641 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1645 * Do not trust the IO-APIC being empty at bootup
1651 * Not an __init, needed by the reboot code
1653 void disable_IO_APIC(void)
1656 * Clear the IO-APIC before rebooting:
1661 * If the i8259 is routed through an IOAPIC
1662 * Put that IOAPIC in virtual wire mode
1663 * so legacy interrupts can be delivered.
1665 if (ioapic_i8259
.pin
!= -1) {
1666 struct IO_APIC_route_entry entry
;
1668 memset(&entry
, 0, sizeof(entry
));
1669 entry
.mask
= 0; /* Enabled */
1670 entry
.trigger
= 0; /* Edge */
1672 entry
.polarity
= 0; /* High */
1673 entry
.delivery_status
= 0;
1674 entry
.dest_mode
= 0; /* Physical */
1675 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1677 entry
.dest
= read_apic_id();
1680 * Add it to the IO-APIC irq-routing table:
1682 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1685 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1688 static int no_timer_check
;
1690 static int __init
notimercheck(char *s
)
1695 __setup("no_timer_check", notimercheck
);
1698 * There is a nasty bug in some older SMP boards, their mptable lies
1699 * about the timer IRQ. We do the following to work around the situation:
1701 * - timer IRQ defaults to IO-APIC IRQ
1702 * - if this function detects that timer IRQs are defunct, then we fall
1703 * back to ISA timer IRQs
1705 static int __init
timer_irq_works(void)
1707 unsigned long t1
= jiffies
;
1708 unsigned long flags
;
1713 local_save_flags(flags
);
1715 /* Let ten ticks pass... */
1716 mdelay((10 * 1000) / HZ
);
1717 local_irq_restore(flags
);
1720 * Expect a few ticks at least, to be sure some possible
1721 * glue logic does not lock up after one or two first
1722 * ticks in a non-ExtINT mode. Also the local APIC
1723 * might have cached one ExtINT interrupt. Finally, at
1724 * least one tick may be lost due to delays.
1728 if (time_after(jiffies
, t1
+ 4))
1734 * In the SMP+IOAPIC case it might happen that there are an unspecified
1735 * number of pending IRQ events unhandled. These cases are very rare,
1736 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1737 * better to do it this way as thus we do not have to be aware of
1738 * 'pending' interrupts in the IRQ path, except at this point.
1741 * Edge triggered needs to resend any interrupt
1742 * that was delayed but this is now handled in the device
1747 * Starting up a edge-triggered IO-APIC interrupt is
1748 * nasty - we need to make sure that we get the edge.
1749 * If it is already asserted for some reason, we need
1750 * return 1 to indicate that is was pending.
1752 * This is not complete - we should be able to fake
1753 * an edge even if it isn't on the 8259A...
1756 static unsigned int startup_ioapic_irq(unsigned int irq
)
1758 int was_pending
= 0;
1759 unsigned long flags
;
1761 spin_lock_irqsave(&ioapic_lock
, flags
);
1763 disable_8259A_irq(irq
);
1764 if (i8259A_irq_pending(irq
))
1767 __unmask_IO_APIC_irq(irq
);
1768 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1773 static int ioapic_retrigger_irq(unsigned int irq
)
1775 struct irq_cfg
*cfg
= irq_cfg(irq
);
1776 unsigned long flags
;
1778 spin_lock_irqsave(&vector_lock
, flags
);
1779 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
1780 spin_unlock_irqrestore(&vector_lock
, flags
);
1786 * Level and edge triggered IO-APIC interrupts need different handling,
1787 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1788 * handled with the level-triggered descriptor, but that one has slightly
1789 * more overhead. Level-triggered interrupts cannot be handled with the
1790 * edge-triggered handler, without risking IRQ storms and other ugly
1796 #ifdef CONFIG_INTR_REMAP
1797 static void ir_irq_migration(struct work_struct
*work
);
1799 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
1802 * Migrate the IO-APIC irq in the presence of intr-remapping.
1804 * For edge triggered, irq migration is a simple atomic update(of vector
1805 * and cpu destination) of IRTE and flush the hardware cache.
1807 * For level triggered, we need to modify the io-apic RTE aswell with the update
1808 * vector information, along with modifying IRTE with vector and destination.
1809 * So irq migration for level triggered is little bit more complex compared to
1810 * edge triggered migration. But the good news is, we use the same algorithm
1811 * for level triggered migration as we have today, only difference being,
1812 * we now initiate the irq migration from process context instead of the
1813 * interrupt context.
1815 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1816 * suppression) to the IO-APIC, level triggered irq migration will also be
1817 * as simple as edge triggered migration and we can do the irq migration
1818 * with a simple atomic update to IO-APIC RTE.
1820 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
1822 struct irq_cfg
*cfg
;
1823 struct irq_desc
*desc
;
1824 cpumask_t tmp
, cleanup_mask
;
1826 int modify_ioapic_rte
;
1828 unsigned long flags
;
1830 cpus_and(tmp
, mask
, cpu_online_map
);
1831 if (cpus_empty(tmp
))
1834 if (get_irte(irq
, &irte
))
1837 if (assign_irq_vector(irq
, mask
))
1841 cpus_and(tmp
, cfg
->domain
, mask
);
1842 dest
= cpu_mask_to_apicid(tmp
);
1844 desc
= irq_to_desc(irq
);
1845 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
1846 if (modify_ioapic_rte
) {
1847 spin_lock_irqsave(&ioapic_lock
, flags
);
1848 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
1849 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1852 irte
.vector
= cfg
->vector
;
1853 irte
.dest_id
= IRTE_DEST(dest
);
1856 * Modified the IRTE and flushes the Interrupt entry cache.
1858 modify_irte(irq
, &irte
);
1860 if (cfg
->move_in_progress
) {
1861 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1862 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1863 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1864 cfg
->move_in_progress
= 0;
1867 desc
->affinity
= mask
;
1870 static int migrate_irq_remapped_level(int irq
)
1873 struct irq_desc
*desc
= irq_to_desc(irq
);
1875 mask_IO_APIC_irq(irq
);
1877 if (io_apic_level_ack_pending(irq
)) {
1879 * Interrupt in progress. Migrating irq now will change the
1880 * vector information in the IO-APIC RTE and that will confuse
1881 * the EOI broadcast performed by cpu.
1882 * So, delay the irq migration to the next instance.
1884 schedule_delayed_work(&ir_migration_work
, 1);
1888 /* everthing is clear. we have right of way */
1889 migrate_ioapic_irq(irq
, desc
->pending_mask
);
1892 desc
->status
&= ~IRQ_MOVE_PENDING
;
1893 cpus_clear(desc
->pending_mask
);
1896 unmask_IO_APIC_irq(irq
);
1900 static void ir_irq_migration(struct work_struct
*work
)
1903 struct irq_desc
*desc
;
1905 for_each_irq_desc(irq
, desc
) {
1906 if (desc
->status
& IRQ_MOVE_PENDING
) {
1907 unsigned long flags
;
1909 spin_lock_irqsave(&desc
->lock
, flags
);
1910 if (!desc
->chip
->set_affinity
||
1911 !(desc
->status
& IRQ_MOVE_PENDING
)) {
1912 desc
->status
&= ~IRQ_MOVE_PENDING
;
1913 spin_unlock_irqrestore(&desc
->lock
, flags
);
1917 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
1918 spin_unlock_irqrestore(&desc
->lock
, flags
);
1924 * Migrates the IRQ destination in the process context.
1926 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
1928 struct irq_desc
*desc
= irq_to_desc(irq
);
1930 if (desc
->status
& IRQ_LEVEL
) {
1931 desc
->status
|= IRQ_MOVE_PENDING
;
1932 desc
->pending_mask
= mask
;
1933 migrate_irq_remapped_level(irq
);
1937 migrate_ioapic_irq(irq
, mask
);
1941 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1943 unsigned vector
, me
;
1948 me
= smp_processor_id();
1949 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1951 struct irq_desc
*desc
;
1952 struct irq_cfg
*cfg
;
1953 irq
= __get_cpu_var(vector_irq
)[vector
];
1955 desc
= irq_to_desc(irq
);
1960 spin_lock(&desc
->lock
);
1961 if (!cfg
->move_cleanup_count
)
1964 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1967 __get_cpu_var(vector_irq
)[vector
] = -1;
1968 cfg
->move_cleanup_count
--;
1970 spin_unlock(&desc
->lock
);
1976 static void irq_complete_move(unsigned int irq
)
1978 struct irq_cfg
*cfg
= irq_cfg(irq
);
1979 unsigned vector
, me
;
1981 if (likely(!cfg
->move_in_progress
))
1984 vector
= ~get_irq_regs()->orig_ax
;
1985 me
= smp_processor_id();
1986 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1987 cpumask_t cleanup_mask
;
1989 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1990 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1991 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1992 cfg
->move_in_progress
= 0;
1996 static inline void irq_complete_move(unsigned int irq
) {}
1998 #ifdef CONFIG_INTR_REMAP
1999 static void ack_x2apic_level(unsigned int irq
)
2004 static void ack_x2apic_edge(unsigned int irq
)
2010 static void ack_apic_edge(unsigned int irq
)
2012 irq_complete_move(irq
);
2013 move_native_irq(irq
);
2017 static void ack_apic_level(unsigned int irq
)
2019 int do_unmask_irq
= 0;
2021 irq_complete_move(irq
);
2022 #ifdef CONFIG_GENERIC_PENDING_IRQ
2023 /* If we are moving the irq we need to mask it */
2024 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2026 mask_IO_APIC_irq(irq
);
2031 * We must acknowledge the irq before we move it or the acknowledge will
2032 * not propagate properly.
2036 /* Now we can move and renable the irq */
2037 if (unlikely(do_unmask_irq
)) {
2038 /* Only migrate the irq if the ack has been received.
2040 * On rare occasions the broadcast level triggered ack gets
2041 * delayed going to ioapics, and if we reprogram the
2042 * vector while Remote IRR is still set the irq will never
2045 * To prevent this scenario we read the Remote IRR bit
2046 * of the ioapic. This has two effects.
2047 * - On any sane system the read of the ioapic will
2048 * flush writes (and acks) going to the ioapic from
2050 * - We get to see if the ACK has actually been delivered.
2052 * Based on failed experiments of reprogramming the
2053 * ioapic entry from outside of irq context starting
2054 * with masking the ioapic entry and then polling until
2055 * Remote IRR was clear before reprogramming the
2056 * ioapic I don't trust the Remote IRR bit to be
2057 * completey accurate.
2059 * However there appears to be no other way to plug
2060 * this race, so if the Remote IRR bit is not
2061 * accurate and is causing problems then it is a hardware bug
2062 * and you can go talk to the chipset vendor about it.
2064 if (!io_apic_level_ack_pending(irq
))
2065 move_masked_irq(irq
);
2066 unmask_IO_APIC_irq(irq
);
2070 static struct irq_chip ioapic_chip __read_mostly
= {
2072 .startup
= startup_ioapic_irq
,
2073 .mask
= mask_IO_APIC_irq
,
2074 .unmask
= unmask_IO_APIC_irq
,
2075 .ack
= ack_apic_edge
,
2076 .eoi
= ack_apic_level
,
2078 .set_affinity
= set_ioapic_affinity_irq
,
2080 .retrigger
= ioapic_retrigger_irq
,
2083 #ifdef CONFIG_INTR_REMAP
2084 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2085 .name
= "IR-IO-APIC",
2086 .startup
= startup_ioapic_irq
,
2087 .mask
= mask_IO_APIC_irq
,
2088 .unmask
= unmask_IO_APIC_irq
,
2089 .ack
= ack_x2apic_edge
,
2090 .eoi
= ack_x2apic_level
,
2092 .set_affinity
= set_ir_ioapic_affinity_irq
,
2094 .retrigger
= ioapic_retrigger_irq
,
2098 static inline void init_IO_APIC_traps(void)
2101 struct irq_desc
*desc
;
2102 struct irq_cfg
*cfg
;
2105 * NOTE! The local APIC isn't very good at handling
2106 * multiple interrupts at the same interrupt level.
2107 * As the interrupt level is determined by taking the
2108 * vector number and shifting that right by 4, we
2109 * want to spread these out a bit so that they don't
2110 * all fall in the same interrupt level.
2112 * Also, we've got to be careful not to trash gate
2113 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2115 for_each_irq_cfg(cfg
) {
2117 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2119 * Hmm.. We don't have an entry for this,
2120 * so default to an old-fashioned 8259
2121 * interrupt if we can..
2124 make_8259A_irq(irq
);
2126 desc
= irq_to_desc(irq
);
2127 /* Strange. Oh, well.. */
2128 desc
->chip
= &no_irq_chip
;
2134 static void unmask_lapic_irq(unsigned int irq
)
2138 v
= apic_read(APIC_LVT0
);
2139 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2142 static void mask_lapic_irq(unsigned int irq
)
2146 v
= apic_read(APIC_LVT0
);
2147 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2150 static void ack_lapic_irq (unsigned int irq
)
2155 static struct irq_chip lapic_chip __read_mostly
= {
2156 .name
= "local-APIC",
2157 .mask
= mask_lapic_irq
,
2158 .unmask
= unmask_lapic_irq
,
2159 .ack
= ack_lapic_irq
,
2162 static void lapic_register_intr(int irq
)
2164 struct irq_desc
*desc
;
2166 desc
= irq_to_desc(irq
);
2167 desc
->status
&= ~IRQ_LEVEL
;
2168 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2172 static void __init
setup_nmi(void)
2175 * Dirty trick to enable the NMI watchdog ...
2176 * We put the 8259A master into AEOI mode and
2177 * unmask on all local APICs LVT0 as NMI.
2179 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2180 * is from Maciej W. Rozycki - so we do not have to EOI from
2181 * the NMI handler or the timer interrupt.
2183 printk(KERN_INFO
"activating NMI Watchdog ...");
2185 enable_NMI_through_LVT0();
2191 * This looks a bit hackish but it's about the only one way of sending
2192 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2193 * not support the ExtINT mode, unfortunately. We need to send these
2194 * cycles as some i82489DX-based boards have glue logic that keeps the
2195 * 8259A interrupt line asserted until INTA. --macro
2197 static inline void __init
unlock_ExtINT_logic(void)
2200 struct IO_APIC_route_entry entry0
, entry1
;
2201 unsigned char save_control
, save_freq_select
;
2203 pin
= find_isa_irq_pin(8, mp_INT
);
2204 apic
= find_isa_irq_apic(8, mp_INT
);
2208 entry0
= ioapic_read_entry(apic
, pin
);
2210 clear_IO_APIC_pin(apic
, pin
);
2212 memset(&entry1
, 0, sizeof(entry1
));
2214 entry1
.dest_mode
= 0; /* physical delivery */
2215 entry1
.mask
= 0; /* unmask IRQ now */
2216 entry1
.dest
= hard_smp_processor_id();
2217 entry1
.delivery_mode
= dest_ExtINT
;
2218 entry1
.polarity
= entry0
.polarity
;
2222 ioapic_write_entry(apic
, pin
, entry1
);
2224 save_control
= CMOS_READ(RTC_CONTROL
);
2225 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2226 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2228 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2233 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2237 CMOS_WRITE(save_control
, RTC_CONTROL
);
2238 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2239 clear_IO_APIC_pin(apic
, pin
);
2241 ioapic_write_entry(apic
, pin
, entry0
);
2244 static int disable_timer_pin_1 __initdata
;
2245 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2246 static int __init
disable_timer_pin_setup(char *arg
)
2248 disable_timer_pin_1
= 1;
2251 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2253 int timer_through_8259 __initdata
;
2256 * This code may look a bit paranoid, but it's supposed to cooperate with
2257 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2258 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2259 * fanatically on his truly buggy board.
2261 * FIXME: really need to revamp this for modern platforms only.
2263 static inline void __init
check_timer(void)
2265 struct irq_cfg
*cfg
= irq_cfg(0);
2266 int apic1
, pin1
, apic2
, pin2
;
2267 unsigned long flags
;
2270 local_irq_save(flags
);
2273 * get/set the timer IRQ vector:
2275 disable_8259A_irq(0);
2276 assign_irq_vector(0, TARGET_CPUS
);
2279 * As IRQ0 is to be enabled in the 8259A, the virtual
2280 * wire has to be disabled in the local APIC.
2282 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2285 pin1
= find_isa_irq_pin(0, mp_INT
);
2286 apic1
= find_isa_irq_apic(0, mp_INT
);
2287 pin2
= ioapic_i8259
.pin
;
2288 apic2
= ioapic_i8259
.apic
;
2290 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2291 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2292 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2295 * Some BIOS writers are clueless and report the ExtINTA
2296 * I/O APIC input from the cascaded 8259A as the timer
2297 * interrupt input. So just in case, if only one pin
2298 * was found above, try it both directly and through the
2302 #ifdef CONFIG_INTR_REMAP
2303 if (intr_remapping_enabled
)
2304 panic("BIOS bug: timer not connected to IO-APIC");
2309 } else if (pin2
== -1) {
2316 * Ok, does IRQ0 through the IOAPIC work?
2319 add_pin_to_irq(0, apic1
, pin1
);
2320 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2322 unmask_IO_APIC_irq(0);
2323 if (timer_irq_works()) {
2324 if (nmi_watchdog
== NMI_IO_APIC
) {
2326 enable_8259A_irq(0);
2328 if (disable_timer_pin_1
> 0)
2329 clear_IO_APIC_pin(0, pin1
);
2332 #ifdef CONFIG_INTR_REMAP
2333 if (intr_remapping_enabled
)
2334 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2336 clear_IO_APIC_pin(apic1
, pin1
);
2338 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2339 "8254 timer not connected to IO-APIC\n");
2341 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2342 "(IRQ0) through the 8259A ...\n");
2343 apic_printk(APIC_QUIET
, KERN_INFO
2344 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2346 * legacy devices should be connected to IO APIC #0
2348 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2349 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2350 unmask_IO_APIC_irq(0);
2351 enable_8259A_irq(0);
2352 if (timer_irq_works()) {
2353 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2354 timer_through_8259
= 1;
2355 if (nmi_watchdog
== NMI_IO_APIC
) {
2356 disable_8259A_irq(0);
2358 enable_8259A_irq(0);
2363 * Cleanup, just in case ...
2365 disable_8259A_irq(0);
2366 clear_IO_APIC_pin(apic2
, pin2
);
2367 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2370 if (nmi_watchdog
== NMI_IO_APIC
) {
2371 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2372 "through the IO-APIC - disabling NMI Watchdog!\n");
2373 nmi_watchdog
= NMI_NONE
;
2376 apic_printk(APIC_QUIET
, KERN_INFO
2377 "...trying to set up timer as Virtual Wire IRQ...\n");
2379 lapic_register_intr(0);
2380 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2381 enable_8259A_irq(0);
2383 if (timer_irq_works()) {
2384 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2387 disable_8259A_irq(0);
2388 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2389 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2391 apic_printk(APIC_QUIET
, KERN_INFO
2392 "...trying to set up timer as ExtINT IRQ...\n");
2396 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2398 unlock_ExtINT_logic();
2400 if (timer_irq_works()) {
2401 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2404 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2405 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2406 "report. Then try booting with the 'noapic' option.\n");
2408 local_irq_restore(flags
);
2412 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2413 * to devices. However there may be an I/O APIC pin available for
2414 * this interrupt regardless. The pin may be left unconnected, but
2415 * typically it will be reused as an ExtINT cascade interrupt for
2416 * the master 8259A. In the MPS case such a pin will normally be
2417 * reported as an ExtINT interrupt in the MP table. With ACPI
2418 * there is no provision for ExtINT interrupts, and in the absence
2419 * of an override it would be treated as an ordinary ISA I/O APIC
2420 * interrupt, that is edge-triggered and unmasked by default. We
2421 * used to do this, but it caused problems on some systems because
2422 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2423 * the same ExtINT cascade interrupt to drive the local APIC of the
2424 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2425 * the I/O APIC in all cases now. No actual device should request
2426 * it anyway. --macro
2428 #define PIC_IRQS (1<<2)
2430 void __init
setup_IO_APIC(void)
2434 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2437 io_apic_irqs
= ~PIC_IRQS
;
2439 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2442 setup_IO_APIC_irqs();
2443 init_IO_APIC_traps();
2447 struct sysfs_ioapic_data
{
2448 struct sys_device dev
;
2449 struct IO_APIC_route_entry entry
[0];
2451 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2453 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2455 struct IO_APIC_route_entry
*entry
;
2456 struct sysfs_ioapic_data
*data
;
2459 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2460 entry
= data
->entry
;
2461 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2462 *entry
= ioapic_read_entry(dev
->id
, i
);
2467 static int ioapic_resume(struct sys_device
*dev
)
2469 struct IO_APIC_route_entry
*entry
;
2470 struct sysfs_ioapic_data
*data
;
2471 unsigned long flags
;
2472 union IO_APIC_reg_00 reg_00
;
2475 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2476 entry
= data
->entry
;
2478 spin_lock_irqsave(&ioapic_lock
, flags
);
2479 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2480 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2481 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2482 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2484 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2485 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2486 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2491 static struct sysdev_class ioapic_sysdev_class
= {
2493 .suspend
= ioapic_suspend
,
2494 .resume
= ioapic_resume
,
2497 static int __init
ioapic_init_sysfs(void)
2499 struct sys_device
* dev
;
2502 error
= sysdev_class_register(&ioapic_sysdev_class
);
2506 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2507 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2508 * sizeof(struct IO_APIC_route_entry
);
2509 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2510 if (!mp_ioapic_data
[i
]) {
2511 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2514 dev
= &mp_ioapic_data
[i
]->dev
;
2516 dev
->cls
= &ioapic_sysdev_class
;
2517 error
= sysdev_register(dev
);
2519 kfree(mp_ioapic_data
[i
]);
2520 mp_ioapic_data
[i
] = NULL
;
2521 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2529 device_initcall(ioapic_init_sysfs
);
2532 * Dynamic irq allocate and deallocation
2534 unsigned int create_irq_nr(unsigned int irq_want
)
2536 /* Allocate an unused irq */
2539 unsigned long flags
;
2540 struct irq_cfg
*cfg_new
;
2542 #ifndef CONFIG_HAVE_SPARSE_IRQ
2543 irq_want
= nr_irqs
- 1;
2547 spin_lock_irqsave(&vector_lock
, flags
);
2548 for (new = irq_want
; new > 0; new--) {
2549 if (platform_legacy_irq(new))
2551 cfg_new
= irq_cfg(new);
2552 if (cfg_new
&& cfg_new
->vector
!= 0)
2554 /* check if need to create one */
2556 cfg_new
= irq_cfg_alloc(new);
2557 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2561 spin_unlock_irqrestore(&vector_lock
, flags
);
2564 dynamic_irq_init(irq
);
2569 int create_irq(void)
2573 irq
= create_irq_nr(nr_irqs
- 1);
2581 void destroy_irq(unsigned int irq
)
2583 unsigned long flags
;
2585 dynamic_irq_cleanup(irq
);
2587 #ifdef CONFIG_INTR_REMAP
2590 spin_lock_irqsave(&vector_lock
, flags
);
2591 __clear_irq_vector(irq
);
2592 spin_unlock_irqrestore(&vector_lock
, flags
);
2596 * MSI message composition
2598 #ifdef CONFIG_PCI_MSI
2599 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2601 struct irq_cfg
*cfg
;
2607 err
= assign_irq_vector(irq
, tmp
);
2612 cpus_and(tmp
, cfg
->domain
, tmp
);
2613 dest
= cpu_mask_to_apicid(tmp
);
2615 #ifdef CONFIG_INTR_REMAP
2616 if (irq_remapped(irq
)) {
2621 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
2622 BUG_ON(ir_index
== -1);
2624 memset (&irte
, 0, sizeof(irte
));
2627 irte
.dst_mode
= INT_DEST_MODE
;
2628 irte
.trigger_mode
= 0; /* edge */
2629 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
2630 irte
.vector
= cfg
->vector
;
2631 irte
.dest_id
= IRTE_DEST(dest
);
2633 modify_irte(irq
, &irte
);
2635 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2636 msg
->data
= sub_handle
;
2637 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
2639 MSI_ADDR_IR_INDEX1(ir_index
) |
2640 MSI_ADDR_IR_INDEX2(ir_index
);
2644 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2647 ((INT_DEST_MODE
== 0) ?
2648 MSI_ADDR_DEST_MODE_PHYSICAL
:
2649 MSI_ADDR_DEST_MODE_LOGICAL
) |
2650 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2651 MSI_ADDR_REDIRECTION_CPU
:
2652 MSI_ADDR_REDIRECTION_LOWPRI
) |
2653 MSI_ADDR_DEST_ID(dest
);
2656 MSI_DATA_TRIGGER_EDGE
|
2657 MSI_DATA_LEVEL_ASSERT
|
2658 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2659 MSI_DATA_DELIVERY_FIXED
:
2660 MSI_DATA_DELIVERY_LOWPRI
) |
2661 MSI_DATA_VECTOR(cfg
->vector
);
2667 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2669 struct irq_cfg
*cfg
;
2673 struct irq_desc
*desc
;
2675 cpus_and(tmp
, mask
, cpu_online_map
);
2676 if (cpus_empty(tmp
))
2679 if (assign_irq_vector(irq
, mask
))
2683 cpus_and(tmp
, cfg
->domain
, mask
);
2684 dest
= cpu_mask_to_apicid(tmp
);
2686 read_msi_msg(irq
, &msg
);
2688 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2689 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2690 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2691 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2693 write_msi_msg(irq
, &msg
);
2694 desc
= irq_to_desc(irq
);
2695 desc
->affinity
= mask
;
2698 #ifdef CONFIG_INTR_REMAP
2700 * Migrate the MSI irq to another cpumask. This migration is
2701 * done in the process context using interrupt-remapping hardware.
2703 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2705 struct irq_cfg
*cfg
;
2707 cpumask_t tmp
, cleanup_mask
;
2709 struct irq_desc
*desc
;
2711 cpus_and(tmp
, mask
, cpu_online_map
);
2712 if (cpus_empty(tmp
))
2715 if (get_irte(irq
, &irte
))
2718 if (assign_irq_vector(irq
, mask
))
2722 cpus_and(tmp
, cfg
->domain
, mask
);
2723 dest
= cpu_mask_to_apicid(tmp
);
2725 irte
.vector
= cfg
->vector
;
2726 irte
.dest_id
= IRTE_DEST(dest
);
2729 * atomically update the IRTE with the new destination and vector.
2731 modify_irte(irq
, &irte
);
2734 * After this point, all the interrupts will start arriving
2735 * at the new destination. So, time to cleanup the previous
2736 * vector allocation.
2738 if (cfg
->move_in_progress
) {
2739 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2740 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2741 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2742 cfg
->move_in_progress
= 0;
2745 desc
= irq_to_desc(irq
);
2746 desc
->affinity
= mask
;
2749 #endif /* CONFIG_SMP */
2752 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2753 * which implement the MSI or MSI-X Capability Structure.
2755 static struct irq_chip msi_chip
= {
2757 .unmask
= unmask_msi_irq
,
2758 .mask
= mask_msi_irq
,
2759 .ack
= ack_apic_edge
,
2761 .set_affinity
= set_msi_irq_affinity
,
2763 .retrigger
= ioapic_retrigger_irq
,
2766 #ifdef CONFIG_INTR_REMAP
2767 static struct irq_chip msi_ir_chip
= {
2768 .name
= "IR-PCI-MSI",
2769 .unmask
= unmask_msi_irq
,
2770 .mask
= mask_msi_irq
,
2771 .ack
= ack_x2apic_edge
,
2773 .set_affinity
= ir_set_msi_irq_affinity
,
2775 .retrigger
= ioapic_retrigger_irq
,
2779 * Map the PCI dev to the corresponding remapping hardware unit
2780 * and allocate 'nvec' consecutive interrupt-remapping table entries
2783 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
2785 struct intel_iommu
*iommu
;
2788 iommu
= map_dev_to_ir(dev
);
2791 "Unable to map PCI %s to iommu\n", pci_name(dev
));
2795 index
= alloc_irte(iommu
, irq
, nvec
);
2798 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
2806 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2811 ret
= msi_compose_msg(dev
, irq
, &msg
);
2815 set_irq_msi(irq
, desc
);
2816 write_msi_msg(irq
, &msg
);
2818 #ifdef CONFIG_INTR_REMAP
2819 if (irq_remapped(irq
)) {
2820 struct irq_desc
*desc
= irq_to_desc(irq
);
2822 * irq migration in process context
2824 desc
->status
|= IRQ_MOVE_PCNTXT
;
2825 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
2828 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2833 static unsigned int build_irq_for_pci_dev(struct pci_dev
*dev
)
2837 irq
= dev
->bus
->number
;
2845 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2849 unsigned int irq_want
;
2851 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
2853 irq
= create_irq_nr(irq_want
);
2857 #ifdef CONFIG_INTR_REMAP
2858 if (!intr_remapping_enabled
)
2861 ret
= msi_alloc_irte(dev
, irq
, 1);
2866 ret
= setup_msi_irq(dev
, desc
, irq
);
2873 #ifdef CONFIG_INTR_REMAP
2880 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
2883 int ret
, sub_handle
;
2884 struct msi_desc
*desc
;
2885 unsigned int irq_want
;
2887 #ifdef CONFIG_INTR_REMAP
2888 struct intel_iommu
*iommu
= 0;
2892 irq_want
= build_irq_for_pci_dev(dev
) + 0x100;
2894 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
2895 irq
= create_irq_nr(irq_want
--);
2898 #ifdef CONFIG_INTR_REMAP
2899 if (!intr_remapping_enabled
)
2904 * allocate the consecutive block of IRTE's
2907 index
= msi_alloc_irte(dev
, irq
, nvec
);
2913 iommu
= map_dev_to_ir(dev
);
2919 * setup the mapping between the irq and the IRTE
2920 * base index, the sub_handle pointing to the
2921 * appropriate interrupt remap table entry.
2923 set_irte_irq(irq
, iommu
, index
, sub_handle
);
2927 ret
= setup_msi_irq(dev
, desc
, irq
);
2939 void arch_teardown_msi_irq(unsigned int irq
)
2946 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2948 struct irq_cfg
*cfg
;
2952 struct irq_desc
*desc
;
2954 cpus_and(tmp
, mask
, cpu_online_map
);
2955 if (cpus_empty(tmp
))
2958 if (assign_irq_vector(irq
, mask
))
2962 cpus_and(tmp
, cfg
->domain
, mask
);
2963 dest
= cpu_mask_to_apicid(tmp
);
2965 dmar_msi_read(irq
, &msg
);
2967 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2968 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2969 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2970 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2972 dmar_msi_write(irq
, &msg
);
2973 desc
= irq_to_desc(irq
);
2974 desc
->affinity
= mask
;
2976 #endif /* CONFIG_SMP */
2978 struct irq_chip dmar_msi_type
= {
2980 .unmask
= dmar_msi_unmask
,
2981 .mask
= dmar_msi_mask
,
2982 .ack
= ack_apic_edge
,
2984 .set_affinity
= dmar_msi_set_affinity
,
2986 .retrigger
= ioapic_retrigger_irq
,
2989 int arch_setup_dmar_msi(unsigned int irq
)
2994 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2997 dmar_msi_write(irq
, &msg
);
2998 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3004 #endif /* CONFIG_PCI_MSI */
3006 * Hypertransport interrupt support
3008 #ifdef CONFIG_HT_IRQ
3012 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3014 struct ht_irq_msg msg
;
3015 fetch_ht_irq_msg(irq
, &msg
);
3017 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3018 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3020 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3021 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3023 write_ht_irq_msg(irq
, &msg
);
3026 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
3028 struct irq_cfg
*cfg
;
3031 struct irq_desc
*desc
;
3033 cpus_and(tmp
, mask
, cpu_online_map
);
3034 if (cpus_empty(tmp
))
3037 if (assign_irq_vector(irq
, mask
))
3041 cpus_and(tmp
, cfg
->domain
, mask
);
3042 dest
= cpu_mask_to_apicid(tmp
);
3044 target_ht_irq(irq
, dest
, cfg
->vector
);
3045 desc
= irq_to_desc(irq
);
3046 desc
->affinity
= mask
;
3050 static struct irq_chip ht_irq_chip
= {
3052 .mask
= mask_ht_irq
,
3053 .unmask
= unmask_ht_irq
,
3054 .ack
= ack_apic_edge
,
3056 .set_affinity
= set_ht_irq_affinity
,
3058 .retrigger
= ioapic_retrigger_irq
,
3061 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3063 struct irq_cfg
*cfg
;
3068 err
= assign_irq_vector(irq
, tmp
);
3070 struct ht_irq_msg msg
;
3074 cpus_and(tmp
, cfg
->domain
, tmp
);
3075 dest
= cpu_mask_to_apicid(tmp
);
3077 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3081 HT_IRQ_LOW_DEST_ID(dest
) |
3082 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3083 ((INT_DEST_MODE
== 0) ?
3084 HT_IRQ_LOW_DM_PHYSICAL
:
3085 HT_IRQ_LOW_DM_LOGICAL
) |
3086 HT_IRQ_LOW_RQEOI_EDGE
|
3087 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3088 HT_IRQ_LOW_MT_FIXED
:
3089 HT_IRQ_LOW_MT_ARBITRATED
) |
3090 HT_IRQ_LOW_IRQ_MASKED
;
3092 write_ht_irq_msg(irq
, &msg
);
3094 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3095 handle_edge_irq
, "edge");
3099 #endif /* CONFIG_HT_IRQ */
3101 /* --------------------------------------------------------------------------
3102 ACPI-based IOAPIC Configuration
3103 -------------------------------------------------------------------------- */
3107 #define IO_APIC_MAX_ID 0xFE
3109 int __init
io_apic_get_redir_entries (int ioapic
)
3111 union IO_APIC_reg_01 reg_01
;
3112 unsigned long flags
;
3114 spin_lock_irqsave(&ioapic_lock
, flags
);
3115 reg_01
.raw
= io_apic_read(ioapic
, 1);
3116 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3118 return reg_01
.bits
.entries
;
3122 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3124 if (!IO_APIC_IRQ(irq
)) {
3125 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3131 * IRQs < 16 are already in the irq_2_pin[] map
3134 add_pin_to_irq(irq
, ioapic
, pin
);
3136 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
3142 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3146 if (skip_ioapic_setup
)
3149 for (i
= 0; i
< mp_irq_entries
; i
++)
3150 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3151 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3153 if (i
>= mp_irq_entries
)
3156 *trigger
= irq_trigger(i
);
3157 *polarity
= irq_polarity(i
);
3161 #endif /* CONFIG_ACPI */
3164 * This function currently is only a helper for the i386 smp boot process where
3165 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3166 * so mask in all cases should simply be TARGET_CPUS
3169 void __init
setup_ioapic_dest(void)
3171 int pin
, ioapic
, irq
, irq_entry
;
3172 struct irq_cfg
*cfg
;
3174 if (skip_ioapic_setup
== 1)
3177 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3178 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3179 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3180 if (irq_entry
== -1)
3182 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3184 /* setup_IO_APIC_irqs could fail to get vector for some device
3185 * when you have too many devices, because at that time only boot
3190 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3191 irq_trigger(irq_entry
),
3192 irq_polarity(irq_entry
));
3193 #ifdef CONFIG_INTR_REMAP
3194 else if (intr_remapping_enabled
)
3195 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3198 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3205 #define IOAPIC_RESOURCE_NAME_SIZE 11
3207 static struct resource
*ioapic_resources
;
3209 static struct resource
* __init
ioapic_setup_resources(void)
3212 struct resource
*res
;
3216 if (nr_ioapics
<= 0)
3219 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3222 mem
= alloc_bootmem(n
);
3226 mem
+= sizeof(struct resource
) * nr_ioapics
;
3228 for (i
= 0; i
< nr_ioapics
; i
++) {
3230 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3231 sprintf(mem
, "IOAPIC %u", i
);
3232 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3236 ioapic_resources
= res
;
3241 void __init
ioapic_init_mappings(void)
3243 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3244 struct resource
*ioapic_res
;
3247 ioapic_res
= ioapic_setup_resources();
3248 for (i
= 0; i
< nr_ioapics
; i
++) {
3249 if (smp_found_config
) {
3250 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3252 ioapic_phys
= (unsigned long)
3253 alloc_bootmem_pages(PAGE_SIZE
);
3254 ioapic_phys
= __pa(ioapic_phys
);
3256 set_fixmap_nocache(idx
, ioapic_phys
);
3257 apic_printk(APIC_VERBOSE
,
3258 "mapped IOAPIC to %016lx (%016lx)\n",
3259 __fix_to_virt(idx
), ioapic_phys
);
3262 if (ioapic_res
!= NULL
) {
3263 ioapic_res
->start
= ioapic_phys
;
3264 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3270 static int __init
ioapic_insert_resources(void)
3273 struct resource
*r
= ioapic_resources
;
3277 "IO APIC resources could be not be allocated.\n");
3281 for (i
= 0; i
< nr_ioapics
; i
++) {
3282 insert_resource(&iomem_resource
, r
);
3289 /* Insert the IO APIC resources after PCI initialization has occured to handle
3290 * IO APICS that are mapped in on a BAR in PCI space. */
3291 late_initcall(ioapic_insert_resources
);