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x86: I/O APIC: Add a 64-bit variation of replace_pin_at_irq()
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40
41 #include <asm/idle.h>
42 #include <asm/io.h>
43 #include <asm/smp.h>
44 #include <asm/desc.h>
45 #include <asm/proto.h>
46 #include <asm/acpi.h>
47 #include <asm/dma.h>
48 #include <asm/nmi.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
51
52 #include <mach_ipi.h>
53 #include <mach_apic.h>
54
55 struct irq_cfg {
56 cpumask_t domain;
57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
59 u8 vector;
60 u8 move_in_progress : 1;
61 };
62
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
81 };
82
83 static int assign_irq_vector(int irq, cpumask_t mask);
84
85 int first_system_vector = 0xfe;
86
87 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
88
89 #define __apicdebuginit __init
90
91 int sis_apic_bug; /* not actually supported, dummy for compile */
92
93 static int no_timer_check;
94
95 static int disable_timer_pin_1 __initdata;
96
97 static bool mask_ioapic_irq_2 __initdata;
98
99 void __init force_mask_ioapic_irq_2(void)
100 {
101 mask_ioapic_irq_2 = true;
102 }
103
104 int timer_through_8259 __initdata;
105
106 /* Where if anywhere is the i8259 connect in external int mode */
107 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
108
109 static DEFINE_SPINLOCK(ioapic_lock);
110 DEFINE_SPINLOCK(vector_lock);
111
112 /*
113 * # of IRQ routing registers
114 */
115 int nr_ioapic_registers[MAX_IO_APICS];
116
117 /* I/O APIC entries */
118 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
119 int nr_ioapics;
120
121 /* MP IRQ source entries */
122 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
123
124 /* # of MP IRQ source entries */
125 int mp_irq_entries;
126
127 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
128
129 /*
130 * Rough estimation of how many shared IRQs there are, can
131 * be changed anytime.
132 */
133 #define MAX_PLUS_SHARED_IRQS NR_IRQS
134 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
135
136 /*
137 * This is performance-critical, we want to do it O(1)
138 *
139 * the indexing order of this array favors 1:1 mappings
140 * between pins and IRQs.
141 */
142
143 static struct irq_pin_list {
144 short apic, pin, next;
145 } irq_2_pin[PIN_MAP_SIZE];
146
147 struct io_apic {
148 unsigned int index;
149 unsigned int unused[3];
150 unsigned int data;
151 };
152
153 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
154 {
155 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
156 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
157 }
158
159 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
160 {
161 struct io_apic __iomem *io_apic = io_apic_base(apic);
162 writel(reg, &io_apic->index);
163 return readl(&io_apic->data);
164 }
165
166 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
167 {
168 struct io_apic __iomem *io_apic = io_apic_base(apic);
169 writel(reg, &io_apic->index);
170 writel(value, &io_apic->data);
171 }
172
173 /*
174 * Re-write a value: to be used for read-modify-write
175 * cycles where the read already set up the index register.
176 */
177 static inline void io_apic_modify(unsigned int apic, unsigned int value)
178 {
179 struct io_apic __iomem *io_apic = io_apic_base(apic);
180 writel(value, &io_apic->data);
181 }
182
183 static bool io_apic_level_ack_pending(unsigned int irq)
184 {
185 struct irq_pin_list *entry;
186 unsigned long flags;
187
188 spin_lock_irqsave(&ioapic_lock, flags);
189 entry = irq_2_pin + irq;
190 for (;;) {
191 unsigned int reg;
192 int pin;
193
194 pin = entry->pin;
195 if (pin == -1)
196 break;
197 reg = io_apic_read(entry->apic, 0x10 + pin*2);
198 /* Is the remote IRR bit set? */
199 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
200 spin_unlock_irqrestore(&ioapic_lock, flags);
201 return true;
202 }
203 if (!entry->next)
204 break;
205 entry = irq_2_pin + entry->next;
206 }
207 spin_unlock_irqrestore(&ioapic_lock, flags);
208
209 return false;
210 }
211
212 /*
213 * Synchronize the IO-APIC and the CPU by doing
214 * a dummy read from the IO-APIC
215 */
216 static inline void io_apic_sync(unsigned int apic)
217 {
218 struct io_apic __iomem *io_apic = io_apic_base(apic);
219 readl(&io_apic->data);
220 }
221
222 #define __DO_ACTION(R, ACTION, FINAL) \
223 \
224 { \
225 int pin; \
226 struct irq_pin_list *entry = irq_2_pin + irq; \
227 \
228 BUG_ON(irq >= NR_IRQS); \
229 for (;;) { \
230 unsigned int reg; \
231 pin = entry->pin; \
232 if (pin == -1) \
233 break; \
234 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
235 reg ACTION; \
236 io_apic_modify(entry->apic, reg); \
237 FINAL; \
238 if (!entry->next) \
239 break; \
240 entry = irq_2_pin + entry->next; \
241 } \
242 }
243
244 union entry_union {
245 struct { u32 w1, w2; };
246 struct IO_APIC_route_entry entry;
247 };
248
249 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
250 {
251 union entry_union eu;
252 unsigned long flags;
253 spin_lock_irqsave(&ioapic_lock, flags);
254 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
255 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
256 spin_unlock_irqrestore(&ioapic_lock, flags);
257 return eu.entry;
258 }
259
260 /*
261 * When we write a new IO APIC routing entry, we need to write the high
262 * word first! If the mask bit in the low word is clear, we will enable
263 * the interrupt, and we need to make sure the entry is fully populated
264 * before that happens.
265 */
266 static void
267 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
268 {
269 union entry_union eu;
270 eu.entry = e;
271 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
272 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
273 }
274
275 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
276 {
277 unsigned long flags;
278 spin_lock_irqsave(&ioapic_lock, flags);
279 __ioapic_write_entry(apic, pin, e);
280 spin_unlock_irqrestore(&ioapic_lock, flags);
281 }
282
283 /*
284 * When we mask an IO APIC routing entry, we need to write the low
285 * word first, in order to set the mask bit before we change the
286 * high bits!
287 */
288 static void ioapic_mask_entry(int apic, int pin)
289 {
290 unsigned long flags;
291 union entry_union eu = { .entry.mask = 1 };
292
293 spin_lock_irqsave(&ioapic_lock, flags);
294 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
295 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
296 spin_unlock_irqrestore(&ioapic_lock, flags);
297 }
298
299 #ifdef CONFIG_SMP
300 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
301 {
302 int apic, pin;
303 struct irq_pin_list *entry = irq_2_pin + irq;
304
305 BUG_ON(irq >= NR_IRQS);
306 for (;;) {
307 unsigned int reg;
308 apic = entry->apic;
309 pin = entry->pin;
310 if (pin == -1)
311 break;
312 io_apic_write(apic, 0x11 + pin*2, dest);
313 reg = io_apic_read(apic, 0x10 + pin*2);
314 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
315 reg |= vector;
316 io_apic_modify(apic, reg);
317 if (!entry->next)
318 break;
319 entry = irq_2_pin + entry->next;
320 }
321 }
322
323 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
324 {
325 struct irq_cfg *cfg = irq_cfg + irq;
326 unsigned long flags;
327 unsigned int dest;
328 cpumask_t tmp;
329
330 cpus_and(tmp, mask, cpu_online_map);
331 if (cpus_empty(tmp))
332 return;
333
334 if (assign_irq_vector(irq, mask))
335 return;
336
337 cpus_and(tmp, cfg->domain, mask);
338 dest = cpu_mask_to_apicid(tmp);
339
340 /*
341 * Only the high 8 bits are valid.
342 */
343 dest = SET_APIC_LOGICAL_ID(dest);
344
345 spin_lock_irqsave(&ioapic_lock, flags);
346 __target_IO_APIC_irq(irq, dest, cfg->vector);
347 irq_desc[irq].affinity = mask;
348 spin_unlock_irqrestore(&ioapic_lock, flags);
349 }
350 #endif
351
352 /*
353 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
354 * shared ISA-space IRQs, so we have to support them. We are super
355 * fast in the common case, and fast for shared ISA-space IRQs.
356 */
357 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
358 {
359 static int first_free_entry = NR_IRQS;
360 struct irq_pin_list *entry = irq_2_pin + irq;
361
362 BUG_ON(irq >= NR_IRQS);
363 while (entry->next)
364 entry = irq_2_pin + entry->next;
365
366 if (entry->pin != -1) {
367 entry->next = first_free_entry;
368 entry = irq_2_pin + entry->next;
369 if (++first_free_entry >= PIN_MAP_SIZE)
370 panic("io_apic.c: ran out of irq_2_pin entries!");
371 }
372 entry->apic = apic;
373 entry->pin = pin;
374 }
375
376 /*
377 * Reroute an IRQ to a different pin.
378 */
379 static void __init replace_pin_at_irq(unsigned int irq,
380 int oldapic, int oldpin,
381 int newapic, int newpin)
382 {
383 struct irq_pin_list *entry = irq_2_pin + irq;
384
385 while (1) {
386 if (entry->apic == oldapic && entry->pin == oldpin) {
387 entry->apic = newapic;
388 entry->pin = newpin;
389 }
390 if (!entry->next)
391 break;
392 entry = irq_2_pin + entry->next;
393 }
394 }
395
396
397 #define DO_ACTION(name,R,ACTION, FINAL) \
398 \
399 static void name##_IO_APIC_irq (unsigned int irq) \
400 __DO_ACTION(R, ACTION, FINAL)
401
402 /* mask = 1 */
403 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
404
405 /* mask = 0 */
406 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
407
408 static void mask_IO_APIC_irq (unsigned int irq)
409 {
410 unsigned long flags;
411
412 spin_lock_irqsave(&ioapic_lock, flags);
413 __mask_IO_APIC_irq(irq);
414 spin_unlock_irqrestore(&ioapic_lock, flags);
415 }
416
417 static void unmask_IO_APIC_irq (unsigned int irq)
418 {
419 unsigned long flags;
420
421 spin_lock_irqsave(&ioapic_lock, flags);
422 __unmask_IO_APIC_irq(irq);
423 spin_unlock_irqrestore(&ioapic_lock, flags);
424 }
425
426 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
427 {
428 struct IO_APIC_route_entry entry;
429
430 /* Check delivery_mode to be sure we're not clearing an SMI pin */
431 entry = ioapic_read_entry(apic, pin);
432 if (entry.delivery_mode == dest_SMI)
433 return;
434 /*
435 * Disable it in the IO-APIC irq-routing table:
436 */
437 ioapic_mask_entry(apic, pin);
438 }
439
440 static void clear_IO_APIC (void)
441 {
442 int apic, pin;
443
444 for (apic = 0; apic < nr_ioapics; apic++)
445 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
446 clear_IO_APIC_pin(apic, pin);
447 }
448
449 int skip_ioapic_setup;
450 int ioapic_force;
451
452 static int __init parse_noapic(char *str)
453 {
454 disable_ioapic_setup();
455 return 0;
456 }
457 early_param("noapic", parse_noapic);
458
459 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
460 static int __init disable_timer_pin_setup(char *arg)
461 {
462 disable_timer_pin_1 = 1;
463 return 1;
464 }
465 __setup("disable_timer_pin_1", disable_timer_pin_setup);
466
467
468 /*
469 * Find the IRQ entry number of a certain pin.
470 */
471 static int find_irq_entry(int apic, int pin, int type)
472 {
473 int i;
474
475 for (i = 0; i < mp_irq_entries; i++)
476 if (mp_irqs[i].mp_irqtype == type &&
477 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
478 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
479 mp_irqs[i].mp_dstirq == pin)
480 return i;
481
482 return -1;
483 }
484
485 /*
486 * Find the pin to which IRQ[irq] (ISA) is connected
487 */
488 static int __init find_isa_irq_pin(int irq, int type)
489 {
490 int i;
491
492 for (i = 0; i < mp_irq_entries; i++) {
493 int lbus = mp_irqs[i].mp_srcbus;
494
495 if (test_bit(lbus, mp_bus_not_pci) &&
496 (mp_irqs[i].mp_irqtype == type) &&
497 (mp_irqs[i].mp_srcbusirq == irq))
498
499 return mp_irqs[i].mp_dstirq;
500 }
501 return -1;
502 }
503
504 static int __init find_isa_irq_apic(int irq, int type)
505 {
506 int i;
507
508 for (i = 0; i < mp_irq_entries; i++) {
509 int lbus = mp_irqs[i].mp_srcbus;
510
511 if (test_bit(lbus, mp_bus_not_pci) &&
512 (mp_irqs[i].mp_irqtype == type) &&
513 (mp_irqs[i].mp_srcbusirq == irq))
514 break;
515 }
516 if (i < mp_irq_entries) {
517 int apic;
518 for(apic = 0; apic < nr_ioapics; apic++) {
519 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
520 return apic;
521 }
522 }
523
524 return -1;
525 }
526
527 /*
528 * Find a specific PCI IRQ entry.
529 * Not an __init, possibly needed by modules
530 */
531 static int pin_2_irq(int idx, int apic, int pin);
532
533 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
534 {
535 int apic, i, best_guess = -1;
536
537 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
538 bus, slot, pin);
539 if (test_bit(bus, mp_bus_not_pci)) {
540 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
541 return -1;
542 }
543 for (i = 0; i < mp_irq_entries; i++) {
544 int lbus = mp_irqs[i].mp_srcbus;
545
546 for (apic = 0; apic < nr_ioapics; apic++)
547 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
548 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
549 break;
550
551 if (!test_bit(lbus, mp_bus_not_pci) &&
552 !mp_irqs[i].mp_irqtype &&
553 (bus == lbus) &&
554 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
555 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
556
557 if (!(apic || IO_APIC_IRQ(irq)))
558 continue;
559
560 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
561 return irq;
562 /*
563 * Use the first all-but-pin matching entry as a
564 * best-guess fuzzy result for broken mptables.
565 */
566 if (best_guess < 0)
567 best_guess = irq;
568 }
569 }
570 BUG_ON(best_guess >= NR_IRQS);
571 return best_guess;
572 }
573
574 /* ISA interrupts are always polarity zero edge triggered,
575 * when listed as conforming in the MP table. */
576
577 #define default_ISA_trigger(idx) (0)
578 #define default_ISA_polarity(idx) (0)
579
580 /* PCI interrupts are always polarity one level triggered,
581 * when listed as conforming in the MP table. */
582
583 #define default_PCI_trigger(idx) (1)
584 #define default_PCI_polarity(idx) (1)
585
586 static int MPBIOS_polarity(int idx)
587 {
588 int bus = mp_irqs[idx].mp_srcbus;
589 int polarity;
590
591 /*
592 * Determine IRQ line polarity (high active or low active):
593 */
594 switch (mp_irqs[idx].mp_irqflag & 3)
595 {
596 case 0: /* conforms, ie. bus-type dependent polarity */
597 if (test_bit(bus, mp_bus_not_pci))
598 polarity = default_ISA_polarity(idx);
599 else
600 polarity = default_PCI_polarity(idx);
601 break;
602 case 1: /* high active */
603 {
604 polarity = 0;
605 break;
606 }
607 case 2: /* reserved */
608 {
609 printk(KERN_WARNING "broken BIOS!!\n");
610 polarity = 1;
611 break;
612 }
613 case 3: /* low active */
614 {
615 polarity = 1;
616 break;
617 }
618 default: /* invalid */
619 {
620 printk(KERN_WARNING "broken BIOS!!\n");
621 polarity = 1;
622 break;
623 }
624 }
625 return polarity;
626 }
627
628 static int MPBIOS_trigger(int idx)
629 {
630 int bus = mp_irqs[idx].mp_srcbus;
631 int trigger;
632
633 /*
634 * Determine IRQ trigger mode (edge or level sensitive):
635 */
636 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
637 {
638 case 0: /* conforms, ie. bus-type dependent */
639 if (test_bit(bus, mp_bus_not_pci))
640 trigger = default_ISA_trigger(idx);
641 else
642 trigger = default_PCI_trigger(idx);
643 break;
644 case 1: /* edge */
645 {
646 trigger = 0;
647 break;
648 }
649 case 2: /* reserved */
650 {
651 printk(KERN_WARNING "broken BIOS!!\n");
652 trigger = 1;
653 break;
654 }
655 case 3: /* level */
656 {
657 trigger = 1;
658 break;
659 }
660 default: /* invalid */
661 {
662 printk(KERN_WARNING "broken BIOS!!\n");
663 trigger = 0;
664 break;
665 }
666 }
667 return trigger;
668 }
669
670 static inline int irq_polarity(int idx)
671 {
672 return MPBIOS_polarity(idx);
673 }
674
675 static inline int irq_trigger(int idx)
676 {
677 return MPBIOS_trigger(idx);
678 }
679
680 static int pin_2_irq(int idx, int apic, int pin)
681 {
682 int irq, i;
683 int bus = mp_irqs[idx].mp_srcbus;
684
685 /*
686 * Debugging check, we are in big trouble if this message pops up!
687 */
688 if (mp_irqs[idx].mp_dstirq != pin)
689 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
690
691 if (test_bit(bus, mp_bus_not_pci)) {
692 irq = mp_irqs[idx].mp_srcbusirq;
693 } else {
694 /*
695 * PCI IRQs are mapped in order
696 */
697 i = irq = 0;
698 while (i < apic)
699 irq += nr_ioapic_registers[i++];
700 irq += pin;
701 }
702 BUG_ON(irq >= NR_IRQS);
703 return irq;
704 }
705
706 static int __assign_irq_vector(int irq, cpumask_t mask)
707 {
708 /*
709 * NOTE! The local APIC isn't very good at handling
710 * multiple interrupts at the same interrupt level.
711 * As the interrupt level is determined by taking the
712 * vector number and shifting that right by 4, we
713 * want to spread these out a bit so that they don't
714 * all fall in the same interrupt level.
715 *
716 * Also, we've got to be careful not to trash gate
717 * 0x80, because int 0x80 is hm, kind of importantish. ;)
718 */
719 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
720 unsigned int old_vector;
721 int cpu;
722 struct irq_cfg *cfg;
723
724 BUG_ON((unsigned)irq >= NR_IRQS);
725 cfg = &irq_cfg[irq];
726
727 /* Only try and allocate irqs on cpus that are present */
728 cpus_and(mask, mask, cpu_online_map);
729
730 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
731 return -EBUSY;
732
733 old_vector = cfg->vector;
734 if (old_vector) {
735 cpumask_t tmp;
736 cpus_and(tmp, cfg->domain, mask);
737 if (!cpus_empty(tmp))
738 return 0;
739 }
740
741 for_each_cpu_mask(cpu, mask) {
742 cpumask_t domain, new_mask;
743 int new_cpu;
744 int vector, offset;
745
746 domain = vector_allocation_domain(cpu);
747 cpus_and(new_mask, domain, cpu_online_map);
748
749 vector = current_vector;
750 offset = current_offset;
751 next:
752 vector += 8;
753 if (vector >= first_system_vector) {
754 /* If we run out of vectors on large boxen, must share them. */
755 offset = (offset + 1) % 8;
756 vector = FIRST_DEVICE_VECTOR + offset;
757 }
758 if (unlikely(current_vector == vector))
759 continue;
760 if (vector == IA32_SYSCALL_VECTOR)
761 goto next;
762 for_each_cpu_mask(new_cpu, new_mask)
763 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
764 goto next;
765 /* Found one! */
766 current_vector = vector;
767 current_offset = offset;
768 if (old_vector) {
769 cfg->move_in_progress = 1;
770 cfg->old_domain = cfg->domain;
771 }
772 for_each_cpu_mask(new_cpu, new_mask)
773 per_cpu(vector_irq, new_cpu)[vector] = irq;
774 cfg->vector = vector;
775 cfg->domain = domain;
776 return 0;
777 }
778 return -ENOSPC;
779 }
780
781 static int assign_irq_vector(int irq, cpumask_t mask)
782 {
783 int err;
784 unsigned long flags;
785
786 spin_lock_irqsave(&vector_lock, flags);
787 err = __assign_irq_vector(irq, mask);
788 spin_unlock_irqrestore(&vector_lock, flags);
789 return err;
790 }
791
792 static void __clear_irq_vector(int irq)
793 {
794 struct irq_cfg *cfg;
795 cpumask_t mask;
796 int cpu, vector;
797
798 BUG_ON((unsigned)irq >= NR_IRQS);
799 cfg = &irq_cfg[irq];
800 BUG_ON(!cfg->vector);
801
802 vector = cfg->vector;
803 cpus_and(mask, cfg->domain, cpu_online_map);
804 for_each_cpu_mask(cpu, mask)
805 per_cpu(vector_irq, cpu)[vector] = -1;
806
807 cfg->vector = 0;
808 cpus_clear(cfg->domain);
809 }
810
811 static void __setup_vector_irq(int cpu)
812 {
813 /* Initialize vector_irq on a new cpu */
814 /* This function must be called with vector_lock held */
815 int irq, vector;
816
817 /* Mark the inuse vectors */
818 for (irq = 0; irq < NR_IRQS; ++irq) {
819 if (!cpu_isset(cpu, irq_cfg[irq].domain))
820 continue;
821 vector = irq_cfg[irq].vector;
822 per_cpu(vector_irq, cpu)[vector] = irq;
823 }
824 /* Mark the free vectors */
825 for (vector = 0; vector < NR_VECTORS; ++vector) {
826 irq = per_cpu(vector_irq, cpu)[vector];
827 if (irq < 0)
828 continue;
829 if (!cpu_isset(cpu, irq_cfg[irq].domain))
830 per_cpu(vector_irq, cpu)[vector] = -1;
831 }
832 }
833
834 void setup_vector_irq(int cpu)
835 {
836 spin_lock(&vector_lock);
837 __setup_vector_irq(smp_processor_id());
838 spin_unlock(&vector_lock);
839 }
840
841
842 static struct irq_chip ioapic_chip;
843
844 static void ioapic_register_intr(int irq, unsigned long trigger)
845 {
846 if (trigger) {
847 irq_desc[irq].status |= IRQ_LEVEL;
848 set_irq_chip_and_handler_name(irq, &ioapic_chip,
849 handle_fasteoi_irq, "fasteoi");
850 } else {
851 irq_desc[irq].status &= ~IRQ_LEVEL;
852 set_irq_chip_and_handler_name(irq, &ioapic_chip,
853 handle_edge_irq, "edge");
854 }
855 }
856
857 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
858 int trigger, int polarity)
859 {
860 struct irq_cfg *cfg = irq_cfg + irq;
861 struct IO_APIC_route_entry entry;
862 cpumask_t mask;
863
864 if (!IO_APIC_IRQ(irq))
865 return;
866
867 mask = TARGET_CPUS;
868 if (assign_irq_vector(irq, mask))
869 return;
870
871 cpus_and(mask, cfg->domain, mask);
872
873 apic_printk(APIC_VERBOSE,KERN_DEBUG
874 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
875 "IRQ %d Mode:%i Active:%i)\n",
876 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
877 irq, trigger, polarity);
878
879 /*
880 * add it to the IO-APIC irq-routing table:
881 */
882 memset(&entry,0,sizeof(entry));
883
884 entry.delivery_mode = INT_DELIVERY_MODE;
885 entry.dest_mode = INT_DEST_MODE;
886 entry.dest = cpu_mask_to_apicid(mask);
887 entry.mask = 0; /* enable IRQ */
888 entry.trigger = trigger;
889 entry.polarity = polarity;
890 entry.vector = cfg->vector;
891
892 /* Mask level triggered irqs.
893 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
894 */
895 if (trigger)
896 entry.mask = 1;
897
898 ioapic_register_intr(irq, trigger);
899 if (irq < 16)
900 disable_8259A_irq(irq);
901
902 ioapic_write_entry(apic, pin, entry);
903 }
904
905 static void __init setup_IO_APIC_irqs(void)
906 {
907 int apic, pin, idx, irq, first_notcon = 1;
908
909 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
910
911 for (apic = 0; apic < nr_ioapics; apic++) {
912 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
913
914 idx = find_irq_entry(apic,pin,mp_INT);
915 if (idx == -1) {
916 if (first_notcon) {
917 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
918 first_notcon = 0;
919 } else
920 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
921 continue;
922 }
923 if (!first_notcon) {
924 apic_printk(APIC_VERBOSE, " not connected.\n");
925 first_notcon = 1;
926 }
927
928 irq = pin_2_irq(idx, apic, pin);
929 add_pin_to_irq(irq, apic, pin);
930
931 setup_IO_APIC_irq(apic, pin, irq,
932 irq_trigger(idx), irq_polarity(idx));
933 }
934 }
935
936 if (!first_notcon)
937 apic_printk(APIC_VERBOSE, " not connected.\n");
938 }
939
940 /*
941 * Set up the timer pin, possibly with the 8259A-master behind.
942 */
943 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
944 int vector)
945 {
946 struct IO_APIC_route_entry entry;
947
948 memset(&entry, 0, sizeof(entry));
949
950 /*
951 * We use logical delivery to get the timer IRQ
952 * to the first CPU.
953 */
954 entry.dest_mode = INT_DEST_MODE;
955 entry.mask = 1; /* mask IRQ now */
956 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
957 entry.delivery_mode = INT_DELIVERY_MODE;
958 entry.polarity = 0;
959 entry.trigger = 0;
960 entry.vector = vector;
961
962 /*
963 * The timer IRQ doesn't have to know that behind the
964 * scene we may have a 8259A-master in AEOI mode ...
965 */
966 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
967
968 /*
969 * Add it to the IO-APIC irq-routing table:
970 */
971 ioapic_write_entry(apic, pin, entry);
972 }
973
974 void __apicdebuginit print_IO_APIC(void)
975 {
976 int apic, i;
977 union IO_APIC_reg_00 reg_00;
978 union IO_APIC_reg_01 reg_01;
979 union IO_APIC_reg_02 reg_02;
980 unsigned long flags;
981
982 if (apic_verbosity == APIC_QUIET)
983 return;
984
985 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
986 for (i = 0; i < nr_ioapics; i++)
987 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
988 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
989
990 /*
991 * We are a bit conservative about what we expect. We have to
992 * know about every hardware change ASAP.
993 */
994 printk(KERN_INFO "testing the IO APIC.......................\n");
995
996 for (apic = 0; apic < nr_ioapics; apic++) {
997
998 spin_lock_irqsave(&ioapic_lock, flags);
999 reg_00.raw = io_apic_read(apic, 0);
1000 reg_01.raw = io_apic_read(apic, 1);
1001 if (reg_01.bits.version >= 0x10)
1002 reg_02.raw = io_apic_read(apic, 2);
1003 spin_unlock_irqrestore(&ioapic_lock, flags);
1004
1005 printk("\n");
1006 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1007 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1008 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1009
1010 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1011 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1012
1013 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1014 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1015
1016 if (reg_01.bits.version >= 0x10) {
1017 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1018 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1019 }
1020
1021 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1022
1023 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1024 " Stat Dmod Deli Vect: \n");
1025
1026 for (i = 0; i <= reg_01.bits.entries; i++) {
1027 struct IO_APIC_route_entry entry;
1028
1029 entry = ioapic_read_entry(apic, i);
1030
1031 printk(KERN_DEBUG " %02x %03X ",
1032 i,
1033 entry.dest
1034 );
1035
1036 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1037 entry.mask,
1038 entry.trigger,
1039 entry.irr,
1040 entry.polarity,
1041 entry.delivery_status,
1042 entry.dest_mode,
1043 entry.delivery_mode,
1044 entry.vector
1045 );
1046 }
1047 }
1048 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1049 for (i = 0; i < NR_IRQS; i++) {
1050 struct irq_pin_list *entry = irq_2_pin + i;
1051 if (entry->pin < 0)
1052 continue;
1053 printk(KERN_DEBUG "IRQ%d ", i);
1054 for (;;) {
1055 printk("-> %d:%d", entry->apic, entry->pin);
1056 if (!entry->next)
1057 break;
1058 entry = irq_2_pin + entry->next;
1059 }
1060 printk("\n");
1061 }
1062
1063 printk(KERN_INFO ".................................... done.\n");
1064
1065 return;
1066 }
1067
1068 #if 0
1069
1070 static __apicdebuginit void print_APIC_bitfield (int base)
1071 {
1072 unsigned int v;
1073 int i, j;
1074
1075 if (apic_verbosity == APIC_QUIET)
1076 return;
1077
1078 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1079 for (i = 0; i < 8; i++) {
1080 v = apic_read(base + i*0x10);
1081 for (j = 0; j < 32; j++) {
1082 if (v & (1<<j))
1083 printk("1");
1084 else
1085 printk("0");
1086 }
1087 printk("\n");
1088 }
1089 }
1090
1091 void __apicdebuginit print_local_APIC(void * dummy)
1092 {
1093 unsigned int v, ver, maxlvt;
1094
1095 if (apic_verbosity == APIC_QUIET)
1096 return;
1097
1098 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1099 smp_processor_id(), hard_smp_processor_id());
1100 v = apic_read(APIC_ID);
1101 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1102 v = apic_read(APIC_LVR);
1103 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1104 ver = GET_APIC_VERSION(v);
1105 maxlvt = lapic_get_maxlvt();
1106
1107 v = apic_read(APIC_TASKPRI);
1108 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1109
1110 v = apic_read(APIC_ARBPRI);
1111 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1112 v & APIC_ARBPRI_MASK);
1113 v = apic_read(APIC_PROCPRI);
1114 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1115
1116 v = apic_read(APIC_EOI);
1117 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1118 v = apic_read(APIC_RRR);
1119 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1120 v = apic_read(APIC_LDR);
1121 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1122 v = apic_read(APIC_DFR);
1123 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1124 v = apic_read(APIC_SPIV);
1125 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1126
1127 printk(KERN_DEBUG "... APIC ISR field:\n");
1128 print_APIC_bitfield(APIC_ISR);
1129 printk(KERN_DEBUG "... APIC TMR field:\n");
1130 print_APIC_bitfield(APIC_TMR);
1131 printk(KERN_DEBUG "... APIC IRR field:\n");
1132 print_APIC_bitfield(APIC_IRR);
1133
1134 v = apic_read(APIC_ESR);
1135 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1136
1137 v = apic_read(APIC_ICR);
1138 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1139 v = apic_read(APIC_ICR2);
1140 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1141
1142 v = apic_read(APIC_LVTT);
1143 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1144
1145 if (maxlvt > 3) { /* PC is LVT#4. */
1146 v = apic_read(APIC_LVTPC);
1147 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1148 }
1149 v = apic_read(APIC_LVT0);
1150 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1151 v = apic_read(APIC_LVT1);
1152 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1153
1154 if (maxlvt > 2) { /* ERR is LVT#3. */
1155 v = apic_read(APIC_LVTERR);
1156 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1157 }
1158
1159 v = apic_read(APIC_TMICT);
1160 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1161 v = apic_read(APIC_TMCCT);
1162 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1163 v = apic_read(APIC_TDCR);
1164 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1165 printk("\n");
1166 }
1167
1168 void print_all_local_APICs (void)
1169 {
1170 on_each_cpu(print_local_APIC, NULL, 1, 1);
1171 }
1172
1173 void __apicdebuginit print_PIC(void)
1174 {
1175 unsigned int v;
1176 unsigned long flags;
1177
1178 if (apic_verbosity == APIC_QUIET)
1179 return;
1180
1181 printk(KERN_DEBUG "\nprinting PIC contents\n");
1182
1183 spin_lock_irqsave(&i8259A_lock, flags);
1184
1185 v = inb(0xa1) << 8 | inb(0x21);
1186 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1187
1188 v = inb(0xa0) << 8 | inb(0x20);
1189 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1190
1191 outb(0x0b,0xa0);
1192 outb(0x0b,0x20);
1193 v = inb(0xa0) << 8 | inb(0x20);
1194 outb(0x0a,0xa0);
1195 outb(0x0a,0x20);
1196
1197 spin_unlock_irqrestore(&i8259A_lock, flags);
1198
1199 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1200
1201 v = inb(0x4d1) << 8 | inb(0x4d0);
1202 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1203 }
1204
1205 #endif /* 0 */
1206
1207 void __init enable_IO_APIC(void)
1208 {
1209 union IO_APIC_reg_01 reg_01;
1210 int i8259_apic, i8259_pin;
1211 int i, apic;
1212 unsigned long flags;
1213
1214 for (i = 0; i < PIN_MAP_SIZE; i++) {
1215 irq_2_pin[i].pin = -1;
1216 irq_2_pin[i].next = 0;
1217 }
1218
1219 /*
1220 * The number of IO-APIC IRQ registers (== #pins):
1221 */
1222 for (apic = 0; apic < nr_ioapics; apic++) {
1223 spin_lock_irqsave(&ioapic_lock, flags);
1224 reg_01.raw = io_apic_read(apic, 1);
1225 spin_unlock_irqrestore(&ioapic_lock, flags);
1226 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1227 }
1228 for(apic = 0; apic < nr_ioapics; apic++) {
1229 int pin;
1230 /* See if any of the pins is in ExtINT mode */
1231 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1232 struct IO_APIC_route_entry entry;
1233 entry = ioapic_read_entry(apic, pin);
1234
1235 /* If the interrupt line is enabled and in ExtInt mode
1236 * I have found the pin where the i8259 is connected.
1237 */
1238 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1239 ioapic_i8259.apic = apic;
1240 ioapic_i8259.pin = pin;
1241 goto found_i8259;
1242 }
1243 }
1244 }
1245 found_i8259:
1246 /* Look to see what if the MP table has reported the ExtINT */
1247 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1248 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1249 /* Trust the MP table if nothing is setup in the hardware */
1250 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1251 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1252 ioapic_i8259.pin = i8259_pin;
1253 ioapic_i8259.apic = i8259_apic;
1254 }
1255 /* Complain if the MP table and the hardware disagree */
1256 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1257 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1258 {
1259 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1260 }
1261
1262 /*
1263 * Do not trust the IO-APIC being empty at bootup
1264 */
1265 clear_IO_APIC();
1266 }
1267
1268 /*
1269 * Not an __init, needed by the reboot code
1270 */
1271 void disable_IO_APIC(void)
1272 {
1273 /*
1274 * Clear the IO-APIC before rebooting:
1275 */
1276 clear_IO_APIC();
1277
1278 /*
1279 * If the i8259 is routed through an IOAPIC
1280 * Put that IOAPIC in virtual wire mode
1281 * so legacy interrupts can be delivered.
1282 */
1283 if (ioapic_i8259.pin != -1) {
1284 struct IO_APIC_route_entry entry;
1285
1286 memset(&entry, 0, sizeof(entry));
1287 entry.mask = 0; /* Enabled */
1288 entry.trigger = 0; /* Edge */
1289 entry.irr = 0;
1290 entry.polarity = 0; /* High */
1291 entry.delivery_status = 0;
1292 entry.dest_mode = 0; /* Physical */
1293 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1294 entry.vector = 0;
1295 entry.dest = GET_APIC_ID(read_apic_id());
1296
1297 /*
1298 * Add it to the IO-APIC irq-routing table:
1299 */
1300 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1301 }
1302
1303 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1304 }
1305
1306 /*
1307 * There is a nasty bug in some older SMP boards, their mptable lies
1308 * about the timer IRQ. We do the following to work around the situation:
1309 *
1310 * - timer IRQ defaults to IO-APIC IRQ
1311 * - if this function detects that timer IRQs are defunct, then we fall
1312 * back to ISA timer IRQs
1313 */
1314 static int __init timer_irq_works(void)
1315 {
1316 unsigned long t1 = jiffies;
1317 unsigned long flags;
1318
1319 local_save_flags(flags);
1320 local_irq_enable();
1321 /* Let ten ticks pass... */
1322 mdelay((10 * 1000) / HZ);
1323 local_irq_restore(flags);
1324
1325 /*
1326 * Expect a few ticks at least, to be sure some possible
1327 * glue logic does not lock up after one or two first
1328 * ticks in a non-ExtINT mode. Also the local APIC
1329 * might have cached one ExtINT interrupt. Finally, at
1330 * least one tick may be lost due to delays.
1331 */
1332
1333 /* jiffies wrap? */
1334 if (time_after(jiffies, t1 + 4))
1335 return 1;
1336 return 0;
1337 }
1338
1339 /*
1340 * In the SMP+IOAPIC case it might happen that there are an unspecified
1341 * number of pending IRQ events unhandled. These cases are very rare,
1342 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1343 * better to do it this way as thus we do not have to be aware of
1344 * 'pending' interrupts in the IRQ path, except at this point.
1345 */
1346 /*
1347 * Edge triggered needs to resend any interrupt
1348 * that was delayed but this is now handled in the device
1349 * independent code.
1350 */
1351
1352 /*
1353 * Starting up a edge-triggered IO-APIC interrupt is
1354 * nasty - we need to make sure that we get the edge.
1355 * If it is already asserted for some reason, we need
1356 * return 1 to indicate that is was pending.
1357 *
1358 * This is not complete - we should be able to fake
1359 * an edge even if it isn't on the 8259A...
1360 */
1361
1362 static unsigned int startup_ioapic_irq(unsigned int irq)
1363 {
1364 int was_pending = 0;
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&ioapic_lock, flags);
1368 if (irq < 16) {
1369 disable_8259A_irq(irq);
1370 if (i8259A_irq_pending(irq))
1371 was_pending = 1;
1372 }
1373 __unmask_IO_APIC_irq(irq);
1374 spin_unlock_irqrestore(&ioapic_lock, flags);
1375
1376 return was_pending;
1377 }
1378
1379 static int ioapic_retrigger_irq(unsigned int irq)
1380 {
1381 struct irq_cfg *cfg = &irq_cfg[irq];
1382 cpumask_t mask;
1383 unsigned long flags;
1384
1385 spin_lock_irqsave(&vector_lock, flags);
1386 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1387 send_IPI_mask(mask, cfg->vector);
1388 spin_unlock_irqrestore(&vector_lock, flags);
1389
1390 return 1;
1391 }
1392
1393 /*
1394 * Level and edge triggered IO-APIC interrupts need different handling,
1395 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1396 * handled with the level-triggered descriptor, but that one has slightly
1397 * more overhead. Level-triggered interrupts cannot be handled with the
1398 * edge-triggered handler, without risking IRQ storms and other ugly
1399 * races.
1400 */
1401
1402 #ifdef CONFIG_SMP
1403 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1404 {
1405 unsigned vector, me;
1406 ack_APIC_irq();
1407 exit_idle();
1408 irq_enter();
1409
1410 me = smp_processor_id();
1411 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1412 unsigned int irq;
1413 struct irq_desc *desc;
1414 struct irq_cfg *cfg;
1415 irq = __get_cpu_var(vector_irq)[vector];
1416 if (irq >= NR_IRQS)
1417 continue;
1418
1419 desc = irq_desc + irq;
1420 cfg = irq_cfg + irq;
1421 spin_lock(&desc->lock);
1422 if (!cfg->move_cleanup_count)
1423 goto unlock;
1424
1425 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1426 goto unlock;
1427
1428 __get_cpu_var(vector_irq)[vector] = -1;
1429 cfg->move_cleanup_count--;
1430 unlock:
1431 spin_unlock(&desc->lock);
1432 }
1433
1434 irq_exit();
1435 }
1436
1437 static void irq_complete_move(unsigned int irq)
1438 {
1439 struct irq_cfg *cfg = irq_cfg + irq;
1440 unsigned vector, me;
1441
1442 if (likely(!cfg->move_in_progress))
1443 return;
1444
1445 vector = ~get_irq_regs()->orig_ax;
1446 me = smp_processor_id();
1447 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1448 cpumask_t cleanup_mask;
1449
1450 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1451 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1452 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1453 cfg->move_in_progress = 0;
1454 }
1455 }
1456 #else
1457 static inline void irq_complete_move(unsigned int irq) {}
1458 #endif
1459
1460 static void ack_apic_edge(unsigned int irq)
1461 {
1462 irq_complete_move(irq);
1463 move_native_irq(irq);
1464 ack_APIC_irq();
1465 }
1466
1467 static void ack_apic_level(unsigned int irq)
1468 {
1469 int do_unmask_irq = 0;
1470
1471 irq_complete_move(irq);
1472 #ifdef CONFIG_GENERIC_PENDING_IRQ
1473 /* If we are moving the irq we need to mask it */
1474 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1475 do_unmask_irq = 1;
1476 mask_IO_APIC_irq(irq);
1477 }
1478 #endif
1479
1480 /*
1481 * We must acknowledge the irq before we move it or the acknowledge will
1482 * not propagate properly.
1483 */
1484 ack_APIC_irq();
1485
1486 /* Now we can move and renable the irq */
1487 if (unlikely(do_unmask_irq)) {
1488 /* Only migrate the irq if the ack has been received.
1489 *
1490 * On rare occasions the broadcast level triggered ack gets
1491 * delayed going to ioapics, and if we reprogram the
1492 * vector while Remote IRR is still set the irq will never
1493 * fire again.
1494 *
1495 * To prevent this scenario we read the Remote IRR bit
1496 * of the ioapic. This has two effects.
1497 * - On any sane system the read of the ioapic will
1498 * flush writes (and acks) going to the ioapic from
1499 * this cpu.
1500 * - We get to see if the ACK has actually been delivered.
1501 *
1502 * Based on failed experiments of reprogramming the
1503 * ioapic entry from outside of irq context starting
1504 * with masking the ioapic entry and then polling until
1505 * Remote IRR was clear before reprogramming the
1506 * ioapic I don't trust the Remote IRR bit to be
1507 * completey accurate.
1508 *
1509 * However there appears to be no other way to plug
1510 * this race, so if the Remote IRR bit is not
1511 * accurate and is causing problems then it is a hardware bug
1512 * and you can go talk to the chipset vendor about it.
1513 */
1514 if (!io_apic_level_ack_pending(irq))
1515 move_masked_irq(irq);
1516 unmask_IO_APIC_irq(irq);
1517 }
1518 }
1519
1520 static struct irq_chip ioapic_chip __read_mostly = {
1521 .name = "IO-APIC",
1522 .startup = startup_ioapic_irq,
1523 .mask = mask_IO_APIC_irq,
1524 .unmask = unmask_IO_APIC_irq,
1525 .ack = ack_apic_edge,
1526 .eoi = ack_apic_level,
1527 #ifdef CONFIG_SMP
1528 .set_affinity = set_ioapic_affinity_irq,
1529 #endif
1530 .retrigger = ioapic_retrigger_irq,
1531 };
1532
1533 static inline void init_IO_APIC_traps(void)
1534 {
1535 int irq;
1536
1537 /*
1538 * NOTE! The local APIC isn't very good at handling
1539 * multiple interrupts at the same interrupt level.
1540 * As the interrupt level is determined by taking the
1541 * vector number and shifting that right by 4, we
1542 * want to spread these out a bit so that they don't
1543 * all fall in the same interrupt level.
1544 *
1545 * Also, we've got to be careful not to trash gate
1546 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1547 */
1548 for (irq = 0; irq < NR_IRQS ; irq++) {
1549 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1550 /*
1551 * Hmm.. We don't have an entry for this,
1552 * so default to an old-fashioned 8259
1553 * interrupt if we can..
1554 */
1555 if (irq < 16)
1556 make_8259A_irq(irq);
1557 else
1558 /* Strange. Oh, well.. */
1559 irq_desc[irq].chip = &no_irq_chip;
1560 }
1561 }
1562 }
1563
1564 static void enable_lapic_irq (unsigned int irq)
1565 {
1566 unsigned long v;
1567
1568 v = apic_read(APIC_LVT0);
1569 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1570 }
1571
1572 static void disable_lapic_irq (unsigned int irq)
1573 {
1574 unsigned long v;
1575
1576 v = apic_read(APIC_LVT0);
1577 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1578 }
1579
1580 static void ack_lapic_irq (unsigned int irq)
1581 {
1582 ack_APIC_irq();
1583 }
1584
1585 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1586
1587 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1588 .name = "local-APIC",
1589 .typename = "local-APIC-edge",
1590 .startup = NULL, /* startup_irq() not used for IRQ0 */
1591 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1592 .enable = enable_lapic_irq,
1593 .disable = disable_lapic_irq,
1594 .ack = ack_lapic_irq,
1595 .end = end_lapic_irq,
1596 };
1597
1598 static void __init setup_nmi(void)
1599 {
1600 /*
1601 * Dirty trick to enable the NMI watchdog ...
1602 * We put the 8259A master into AEOI mode and
1603 * unmask on all local APICs LVT0 as NMI.
1604 *
1605 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1606 * is from Maciej W. Rozycki - so we do not have to EOI from
1607 * the NMI handler or the timer interrupt.
1608 */
1609 printk(KERN_INFO "activating NMI Watchdog ...");
1610
1611 enable_NMI_through_LVT0();
1612
1613 printk(" done.\n");
1614 }
1615
1616 /*
1617 * This looks a bit hackish but it's about the only one way of sending
1618 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1619 * not support the ExtINT mode, unfortunately. We need to send these
1620 * cycles as some i82489DX-based boards have glue logic that keeps the
1621 * 8259A interrupt line asserted until INTA. --macro
1622 */
1623 static inline void __init unlock_ExtINT_logic(void)
1624 {
1625 int apic, pin, i;
1626 struct IO_APIC_route_entry entry0, entry1;
1627 unsigned char save_control, save_freq_select;
1628
1629 pin = find_isa_irq_pin(8, mp_INT);
1630 apic = find_isa_irq_apic(8, mp_INT);
1631 if (pin == -1)
1632 return;
1633
1634 entry0 = ioapic_read_entry(apic, pin);
1635
1636 clear_IO_APIC_pin(apic, pin);
1637
1638 memset(&entry1, 0, sizeof(entry1));
1639
1640 entry1.dest_mode = 0; /* physical delivery */
1641 entry1.mask = 0; /* unmask IRQ now */
1642 entry1.dest = hard_smp_processor_id();
1643 entry1.delivery_mode = dest_ExtINT;
1644 entry1.polarity = entry0.polarity;
1645 entry1.trigger = 0;
1646 entry1.vector = 0;
1647
1648 ioapic_write_entry(apic, pin, entry1);
1649
1650 save_control = CMOS_READ(RTC_CONTROL);
1651 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1652 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1653 RTC_FREQ_SELECT);
1654 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1655
1656 i = 100;
1657 while (i-- > 0) {
1658 mdelay(10);
1659 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1660 i -= 10;
1661 }
1662
1663 CMOS_WRITE(save_control, RTC_CONTROL);
1664 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1665 clear_IO_APIC_pin(apic, pin);
1666
1667 ioapic_write_entry(apic, pin, entry0);
1668 }
1669
1670 /*
1671 * This code may look a bit paranoid, but it's supposed to cooperate with
1672 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1673 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1674 * fanatically on his truly buggy board.
1675 *
1676 * FIXME: really need to revamp this for modern platforms only.
1677 */
1678 static inline void __init check_timer(void)
1679 {
1680 struct irq_cfg *cfg = irq_cfg + 0;
1681 int apic1, pin1, apic2, pin2;
1682 unsigned long flags;
1683 int no_pin1 = 0;
1684
1685 local_irq_save(flags);
1686
1687 /*
1688 * get/set the timer IRQ vector:
1689 */
1690 disable_8259A_irq(0);
1691 assign_irq_vector(0, TARGET_CPUS);
1692
1693 /*
1694 * As IRQ0 is to be enabled in the 8259A, the virtual
1695 * wire has to be disabled in the local APIC.
1696 */
1697 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1698 init_8259A(1);
1699
1700 pin1 = find_isa_irq_pin(0, mp_INT);
1701 apic1 = find_isa_irq_apic(0, mp_INT);
1702 pin2 = ioapic_i8259.pin;
1703 apic2 = ioapic_i8259.apic;
1704
1705 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1706 cfg->vector, apic1, pin1, apic2, pin2);
1707
1708 if (mask_ioapic_irq_2)
1709 mask_IO_APIC_irq(2);
1710
1711 /*
1712 * Some BIOS writers are clueless and report the ExtINTA
1713 * I/O APIC input from the cascaded 8259A as the timer
1714 * interrupt input. So just in case, if only one pin
1715 * was found above, try it both directly and through the
1716 * 8259A.
1717 */
1718 if (pin1 == -1) {
1719 pin1 = pin2;
1720 apic1 = apic2;
1721 no_pin1 = 1;
1722 } else if (pin2 == -1) {
1723 pin2 = pin1;
1724 apic2 = apic1;
1725 }
1726
1727 if (pin1 != -1) {
1728 /*
1729 * Ok, does IRQ0 through the IOAPIC work?
1730 */
1731 if (no_pin1) {
1732 add_pin_to_irq(0, apic1, pin1);
1733 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1734 }
1735 unmask_IO_APIC_irq(0);
1736 if (!no_timer_check && timer_irq_works()) {
1737 if (nmi_watchdog == NMI_IO_APIC) {
1738 setup_nmi();
1739 enable_8259A_irq(0);
1740 }
1741 if (disable_timer_pin_1 > 0)
1742 clear_IO_APIC_pin(0, pin1);
1743 goto out;
1744 }
1745 clear_IO_APIC_pin(apic1, pin1);
1746 if (!no_pin1)
1747 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1748 "8254 timer not connected to IO-APIC\n");
1749
1750 apic_printk(APIC_VERBOSE,KERN_INFO
1751 "...trying to set up timer (IRQ0) "
1752 "through the 8259A ... ");
1753 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1754 apic2, pin2);
1755 /*
1756 * legacy devices should be connected to IO APIC #0
1757 */
1758 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1759 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1760 unmask_IO_APIC_irq(0);
1761 enable_8259A_irq(0);
1762 if (timer_irq_works()) {
1763 apic_printk(APIC_VERBOSE," works.\n");
1764 timer_through_8259 = 1;
1765 if (nmi_watchdog == NMI_IO_APIC) {
1766 disable_8259A_irq(0);
1767 setup_nmi();
1768 enable_8259A_irq(0);
1769 }
1770 goto out;
1771 }
1772 /*
1773 * Cleanup, just in case ...
1774 */
1775 disable_8259A_irq(0);
1776 clear_IO_APIC_pin(apic2, pin2);
1777 apic_printk(APIC_VERBOSE," failed.\n");
1778 }
1779
1780 if (nmi_watchdog == NMI_IO_APIC) {
1781 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1782 nmi_watchdog = NMI_NONE;
1783 }
1784
1785 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1786
1787 irq_desc[0].chip = &lapic_irq_type;
1788 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1789 enable_8259A_irq(0);
1790
1791 if (timer_irq_works()) {
1792 apic_printk(APIC_VERBOSE," works.\n");
1793 goto out;
1794 }
1795 disable_8259A_irq(0);
1796 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1797 apic_printk(APIC_VERBOSE," failed.\n");
1798
1799 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1800
1801 init_8259A(0);
1802 make_8259A_irq(0);
1803 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1804
1805 unlock_ExtINT_logic();
1806
1807 if (timer_irq_works()) {
1808 apic_printk(APIC_VERBOSE," works.\n");
1809 goto out;
1810 }
1811 apic_printk(APIC_VERBOSE," failed :(.\n");
1812 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1813 out:
1814 local_irq_restore(flags);
1815 }
1816
1817 static int __init notimercheck(char *s)
1818 {
1819 no_timer_check = 1;
1820 return 1;
1821 }
1822 __setup("no_timer_check", notimercheck);
1823
1824 /*
1825 *
1826 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1827 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1828 * Linux doesn't really care, as it's not actually used
1829 * for any interrupt handling anyway.
1830 */
1831 #define PIC_IRQS (1<<2)
1832
1833 void __init setup_IO_APIC(void)
1834 {
1835
1836 /*
1837 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1838 */
1839
1840 if (acpi_ioapic)
1841 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1842 else
1843 io_apic_irqs = ~PIC_IRQS;
1844
1845 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1846
1847 sync_Arb_IDs();
1848 setup_IO_APIC_irqs();
1849 init_IO_APIC_traps();
1850 check_timer();
1851 if (!acpi_ioapic)
1852 print_IO_APIC();
1853 }
1854
1855 struct sysfs_ioapic_data {
1856 struct sys_device dev;
1857 struct IO_APIC_route_entry entry[0];
1858 };
1859 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1860
1861 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1862 {
1863 struct IO_APIC_route_entry *entry;
1864 struct sysfs_ioapic_data *data;
1865 int i;
1866
1867 data = container_of(dev, struct sysfs_ioapic_data, dev);
1868 entry = data->entry;
1869 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1870 *entry = ioapic_read_entry(dev->id, i);
1871
1872 return 0;
1873 }
1874
1875 static int ioapic_resume(struct sys_device *dev)
1876 {
1877 struct IO_APIC_route_entry *entry;
1878 struct sysfs_ioapic_data *data;
1879 unsigned long flags;
1880 union IO_APIC_reg_00 reg_00;
1881 int i;
1882
1883 data = container_of(dev, struct sysfs_ioapic_data, dev);
1884 entry = data->entry;
1885
1886 spin_lock_irqsave(&ioapic_lock, flags);
1887 reg_00.raw = io_apic_read(dev->id, 0);
1888 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
1889 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1890 io_apic_write(dev->id, 0, reg_00.raw);
1891 }
1892 spin_unlock_irqrestore(&ioapic_lock, flags);
1893 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1894 ioapic_write_entry(dev->id, i, entry[i]);
1895
1896 return 0;
1897 }
1898
1899 static struct sysdev_class ioapic_sysdev_class = {
1900 .name = "ioapic",
1901 .suspend = ioapic_suspend,
1902 .resume = ioapic_resume,
1903 };
1904
1905 static int __init ioapic_init_sysfs(void)
1906 {
1907 struct sys_device * dev;
1908 int i, size, error;
1909
1910 error = sysdev_class_register(&ioapic_sysdev_class);
1911 if (error)
1912 return error;
1913
1914 for (i = 0; i < nr_ioapics; i++ ) {
1915 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1916 * sizeof(struct IO_APIC_route_entry);
1917 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1918 if (!mp_ioapic_data[i]) {
1919 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1920 continue;
1921 }
1922 dev = &mp_ioapic_data[i]->dev;
1923 dev->id = i;
1924 dev->cls = &ioapic_sysdev_class;
1925 error = sysdev_register(dev);
1926 if (error) {
1927 kfree(mp_ioapic_data[i]);
1928 mp_ioapic_data[i] = NULL;
1929 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1930 continue;
1931 }
1932 }
1933
1934 return 0;
1935 }
1936
1937 device_initcall(ioapic_init_sysfs);
1938
1939 /*
1940 * Dynamic irq allocate and deallocation
1941 */
1942 int create_irq(void)
1943 {
1944 /* Allocate an unused irq */
1945 int irq;
1946 int new;
1947 unsigned long flags;
1948
1949 irq = -ENOSPC;
1950 spin_lock_irqsave(&vector_lock, flags);
1951 for (new = (NR_IRQS - 1); new >= 0; new--) {
1952 if (platform_legacy_irq(new))
1953 continue;
1954 if (irq_cfg[new].vector != 0)
1955 continue;
1956 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1957 irq = new;
1958 break;
1959 }
1960 spin_unlock_irqrestore(&vector_lock, flags);
1961
1962 if (irq >= 0) {
1963 dynamic_irq_init(irq);
1964 }
1965 return irq;
1966 }
1967
1968 void destroy_irq(unsigned int irq)
1969 {
1970 unsigned long flags;
1971
1972 dynamic_irq_cleanup(irq);
1973
1974 spin_lock_irqsave(&vector_lock, flags);
1975 __clear_irq_vector(irq);
1976 spin_unlock_irqrestore(&vector_lock, flags);
1977 }
1978
1979 /*
1980 * MSI message composition
1981 */
1982 #ifdef CONFIG_PCI_MSI
1983 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1984 {
1985 struct irq_cfg *cfg = irq_cfg + irq;
1986 int err;
1987 unsigned dest;
1988 cpumask_t tmp;
1989
1990 tmp = TARGET_CPUS;
1991 err = assign_irq_vector(irq, tmp);
1992 if (!err) {
1993 cpus_and(tmp, cfg->domain, tmp);
1994 dest = cpu_mask_to_apicid(tmp);
1995
1996 msg->address_hi = MSI_ADDR_BASE_HI;
1997 msg->address_lo =
1998 MSI_ADDR_BASE_LO |
1999 ((INT_DEST_MODE == 0) ?
2000 MSI_ADDR_DEST_MODE_PHYSICAL:
2001 MSI_ADDR_DEST_MODE_LOGICAL) |
2002 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2003 MSI_ADDR_REDIRECTION_CPU:
2004 MSI_ADDR_REDIRECTION_LOWPRI) |
2005 MSI_ADDR_DEST_ID(dest);
2006
2007 msg->data =
2008 MSI_DATA_TRIGGER_EDGE |
2009 MSI_DATA_LEVEL_ASSERT |
2010 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2011 MSI_DATA_DELIVERY_FIXED:
2012 MSI_DATA_DELIVERY_LOWPRI) |
2013 MSI_DATA_VECTOR(cfg->vector);
2014 }
2015 return err;
2016 }
2017
2018 #ifdef CONFIG_SMP
2019 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2020 {
2021 struct irq_cfg *cfg = irq_cfg + irq;
2022 struct msi_msg msg;
2023 unsigned int dest;
2024 cpumask_t tmp;
2025
2026 cpus_and(tmp, mask, cpu_online_map);
2027 if (cpus_empty(tmp))
2028 return;
2029
2030 if (assign_irq_vector(irq, mask))
2031 return;
2032
2033 cpus_and(tmp, cfg->domain, mask);
2034 dest = cpu_mask_to_apicid(tmp);
2035
2036 read_msi_msg(irq, &msg);
2037
2038 msg.data &= ~MSI_DATA_VECTOR_MASK;
2039 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2040 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2041 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2042
2043 write_msi_msg(irq, &msg);
2044 irq_desc[irq].affinity = mask;
2045 }
2046 #endif /* CONFIG_SMP */
2047
2048 /*
2049 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2050 * which implement the MSI or MSI-X Capability Structure.
2051 */
2052 static struct irq_chip msi_chip = {
2053 .name = "PCI-MSI",
2054 .unmask = unmask_msi_irq,
2055 .mask = mask_msi_irq,
2056 .ack = ack_apic_edge,
2057 #ifdef CONFIG_SMP
2058 .set_affinity = set_msi_irq_affinity,
2059 #endif
2060 .retrigger = ioapic_retrigger_irq,
2061 };
2062
2063 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2064 {
2065 struct msi_msg msg;
2066 int irq, ret;
2067 irq = create_irq();
2068 if (irq < 0)
2069 return irq;
2070
2071 ret = msi_compose_msg(dev, irq, &msg);
2072 if (ret < 0) {
2073 destroy_irq(irq);
2074 return ret;
2075 }
2076
2077 set_irq_msi(irq, desc);
2078 write_msi_msg(irq, &msg);
2079
2080 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2081
2082 return 0;
2083 }
2084
2085 void arch_teardown_msi_irq(unsigned int irq)
2086 {
2087 destroy_irq(irq);
2088 }
2089
2090 #ifdef CONFIG_DMAR
2091 #ifdef CONFIG_SMP
2092 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2093 {
2094 struct irq_cfg *cfg = irq_cfg + irq;
2095 struct msi_msg msg;
2096 unsigned int dest;
2097 cpumask_t tmp;
2098
2099 cpus_and(tmp, mask, cpu_online_map);
2100 if (cpus_empty(tmp))
2101 return;
2102
2103 if (assign_irq_vector(irq, mask))
2104 return;
2105
2106 cpus_and(tmp, cfg->domain, mask);
2107 dest = cpu_mask_to_apicid(tmp);
2108
2109 dmar_msi_read(irq, &msg);
2110
2111 msg.data &= ~MSI_DATA_VECTOR_MASK;
2112 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2113 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2114 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2115
2116 dmar_msi_write(irq, &msg);
2117 irq_desc[irq].affinity = mask;
2118 }
2119 #endif /* CONFIG_SMP */
2120
2121 struct irq_chip dmar_msi_type = {
2122 .name = "DMAR_MSI",
2123 .unmask = dmar_msi_unmask,
2124 .mask = dmar_msi_mask,
2125 .ack = ack_apic_edge,
2126 #ifdef CONFIG_SMP
2127 .set_affinity = dmar_msi_set_affinity,
2128 #endif
2129 .retrigger = ioapic_retrigger_irq,
2130 };
2131
2132 int arch_setup_dmar_msi(unsigned int irq)
2133 {
2134 int ret;
2135 struct msi_msg msg;
2136
2137 ret = msi_compose_msg(NULL, irq, &msg);
2138 if (ret < 0)
2139 return ret;
2140 dmar_msi_write(irq, &msg);
2141 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2142 "edge");
2143 return 0;
2144 }
2145 #endif
2146
2147 #endif /* CONFIG_PCI_MSI */
2148 /*
2149 * Hypertransport interrupt support
2150 */
2151 #ifdef CONFIG_HT_IRQ
2152
2153 #ifdef CONFIG_SMP
2154
2155 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2156 {
2157 struct ht_irq_msg msg;
2158 fetch_ht_irq_msg(irq, &msg);
2159
2160 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2161 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2162
2163 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2164 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2165
2166 write_ht_irq_msg(irq, &msg);
2167 }
2168
2169 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2170 {
2171 struct irq_cfg *cfg = irq_cfg + irq;
2172 unsigned int dest;
2173 cpumask_t tmp;
2174
2175 cpus_and(tmp, mask, cpu_online_map);
2176 if (cpus_empty(tmp))
2177 return;
2178
2179 if (assign_irq_vector(irq, mask))
2180 return;
2181
2182 cpus_and(tmp, cfg->domain, mask);
2183 dest = cpu_mask_to_apicid(tmp);
2184
2185 target_ht_irq(irq, dest, cfg->vector);
2186 irq_desc[irq].affinity = mask;
2187 }
2188 #endif
2189
2190 static struct irq_chip ht_irq_chip = {
2191 .name = "PCI-HT",
2192 .mask = mask_ht_irq,
2193 .unmask = unmask_ht_irq,
2194 .ack = ack_apic_edge,
2195 #ifdef CONFIG_SMP
2196 .set_affinity = set_ht_irq_affinity,
2197 #endif
2198 .retrigger = ioapic_retrigger_irq,
2199 };
2200
2201 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2202 {
2203 struct irq_cfg *cfg = irq_cfg + irq;
2204 int err;
2205 cpumask_t tmp;
2206
2207 tmp = TARGET_CPUS;
2208 err = assign_irq_vector(irq, tmp);
2209 if (!err) {
2210 struct ht_irq_msg msg;
2211 unsigned dest;
2212
2213 cpus_and(tmp, cfg->domain, tmp);
2214 dest = cpu_mask_to_apicid(tmp);
2215
2216 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2217
2218 msg.address_lo =
2219 HT_IRQ_LOW_BASE |
2220 HT_IRQ_LOW_DEST_ID(dest) |
2221 HT_IRQ_LOW_VECTOR(cfg->vector) |
2222 ((INT_DEST_MODE == 0) ?
2223 HT_IRQ_LOW_DM_PHYSICAL :
2224 HT_IRQ_LOW_DM_LOGICAL) |
2225 HT_IRQ_LOW_RQEOI_EDGE |
2226 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2227 HT_IRQ_LOW_MT_FIXED :
2228 HT_IRQ_LOW_MT_ARBITRATED) |
2229 HT_IRQ_LOW_IRQ_MASKED;
2230
2231 write_ht_irq_msg(irq, &msg);
2232
2233 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2234 handle_edge_irq, "edge");
2235 }
2236 return err;
2237 }
2238 #endif /* CONFIG_HT_IRQ */
2239
2240 /* --------------------------------------------------------------------------
2241 ACPI-based IOAPIC Configuration
2242 -------------------------------------------------------------------------- */
2243
2244 #ifdef CONFIG_ACPI
2245
2246 #define IO_APIC_MAX_ID 0xFE
2247
2248 int __init io_apic_get_redir_entries (int ioapic)
2249 {
2250 union IO_APIC_reg_01 reg_01;
2251 unsigned long flags;
2252
2253 spin_lock_irqsave(&ioapic_lock, flags);
2254 reg_01.raw = io_apic_read(ioapic, 1);
2255 spin_unlock_irqrestore(&ioapic_lock, flags);
2256
2257 return reg_01.bits.entries;
2258 }
2259
2260
2261 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2262 {
2263 if (!IO_APIC_IRQ(irq)) {
2264 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2265 ioapic);
2266 return -EINVAL;
2267 }
2268
2269 /*
2270 * IRQs < 16 are already in the irq_2_pin[] map
2271 */
2272 if (irq >= 16)
2273 add_pin_to_irq(irq, ioapic, pin);
2274
2275 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2276
2277 return 0;
2278 }
2279
2280
2281 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2282 {
2283 int i;
2284
2285 if (skip_ioapic_setup)
2286 return -1;
2287
2288 for (i = 0; i < mp_irq_entries; i++)
2289 if (mp_irqs[i].mp_irqtype == mp_INT &&
2290 mp_irqs[i].mp_srcbusirq == bus_irq)
2291 break;
2292 if (i >= mp_irq_entries)
2293 return -1;
2294
2295 *trigger = irq_trigger(i);
2296 *polarity = irq_polarity(i);
2297 return 0;
2298 }
2299
2300 #endif /* CONFIG_ACPI */
2301
2302 /*
2303 * This function currently is only a helper for the i386 smp boot process where
2304 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2305 * so mask in all cases should simply be TARGET_CPUS
2306 */
2307 #ifdef CONFIG_SMP
2308 void __init setup_ioapic_dest(void)
2309 {
2310 int pin, ioapic, irq, irq_entry;
2311
2312 if (skip_ioapic_setup == 1)
2313 return;
2314
2315 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2316 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2317 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2318 if (irq_entry == -1)
2319 continue;
2320 irq = pin_2_irq(irq_entry, ioapic, pin);
2321
2322 /* setup_IO_APIC_irqs could fail to get vector for some device
2323 * when you have too many devices, because at that time only boot
2324 * cpu is online.
2325 */
2326 if (!irq_cfg[irq].vector)
2327 setup_IO_APIC_irq(ioapic, pin, irq,
2328 irq_trigger(irq_entry),
2329 irq_polarity(irq_entry));
2330 else
2331 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2332 }
2333
2334 }
2335 }
2336 #endif
2337
2338 #define IOAPIC_RESOURCE_NAME_SIZE 11
2339
2340 static struct resource *ioapic_resources;
2341
2342 static struct resource * __init ioapic_setup_resources(void)
2343 {
2344 unsigned long n;
2345 struct resource *res;
2346 char *mem;
2347 int i;
2348
2349 if (nr_ioapics <= 0)
2350 return NULL;
2351
2352 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2353 n *= nr_ioapics;
2354
2355 mem = alloc_bootmem(n);
2356 res = (void *)mem;
2357
2358 if (mem != NULL) {
2359 mem += sizeof(struct resource) * nr_ioapics;
2360
2361 for (i = 0; i < nr_ioapics; i++) {
2362 res[i].name = mem;
2363 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2364 sprintf(mem, "IOAPIC %u", i);
2365 mem += IOAPIC_RESOURCE_NAME_SIZE;
2366 }
2367 }
2368
2369 ioapic_resources = res;
2370
2371 return res;
2372 }
2373
2374 void __init ioapic_init_mappings(void)
2375 {
2376 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2377 struct resource *ioapic_res;
2378 int i;
2379
2380 ioapic_res = ioapic_setup_resources();
2381 for (i = 0; i < nr_ioapics; i++) {
2382 if (smp_found_config) {
2383 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2384 } else {
2385 ioapic_phys = (unsigned long)
2386 alloc_bootmem_pages(PAGE_SIZE);
2387 ioapic_phys = __pa(ioapic_phys);
2388 }
2389 set_fixmap_nocache(idx, ioapic_phys);
2390 apic_printk(APIC_VERBOSE,
2391 "mapped IOAPIC to %016lx (%016lx)\n",
2392 __fix_to_virt(idx), ioapic_phys);
2393 idx++;
2394
2395 if (ioapic_res != NULL) {
2396 ioapic_res->start = ioapic_phys;
2397 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2398 ioapic_res++;
2399 }
2400 }
2401 }
2402
2403 static int __init ioapic_insert_resources(void)
2404 {
2405 int i;
2406 struct resource *r = ioapic_resources;
2407
2408 if (!r) {
2409 printk(KERN_ERR
2410 "IO APIC resources could be not be allocated.\n");
2411 return -1;
2412 }
2413
2414 for (i = 0; i < nr_ioapics; i++) {
2415 insert_resource(&iomem_resource, r);
2416 r++;
2417 }
2418
2419 return 0;
2420 }
2421
2422 /* Insert the IO APIC resources after PCI initialization has occured to handle
2423 * IO APICS that are mapped in on a BAR in PCI space. */
2424 late_initcall(ioapic_insert_resources);
2425
Linux kernel - Deliverables
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