2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
49 #include <asm/i8259.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
56 #include <mach_apic.h>
58 #define __apicdebuginit(type) static type __init
67 unsigned move_cleanup_count
;
69 u8 move_in_progress
: 1;
72 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
73 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
74 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
75 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
76 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
77 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
78 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
79 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
80 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
81 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
82 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
83 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
84 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
85 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
86 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
87 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
88 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
89 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
92 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
93 /* need to be biger than size of irq_cfg_legacy */
94 static int nr_irq_cfg
= 32;
96 static int __init
parse_nr_irq_cfg(char *arg
)
99 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
106 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
108 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
110 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
113 static void __init
init_work(void *data
)
115 struct dyn_array
*da
= data
;
121 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
123 i
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
124 for (; i
< *da
->nr
; i
++)
125 init_one_irq_cfg(&cfg
[i
]);
127 for (i
= 1; i
< *da
->nr
; i
++)
128 cfg
[i
-1].next
= &cfg
[i
];
131 static struct irq_cfg
*irq_cfgx
;
132 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
134 static struct irq_cfg
*irq_cfg(unsigned int irq
)
154 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
156 struct irq_cfg
*cfg
, *cfg_pri
;
162 cfg_pri
= cfg
= &irq_cfgx
[0];
167 if (cfg
->irq
== -1U) {
177 * we run out of pre-allocate ones, allocate more
179 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
182 cfg
= kzalloc(sizeof(struct irq_cfg
)*nr_irq_cfg
, GFP_ATOMIC
);
184 cfg
= __alloc_bootmem_nopanic(sizeof(struct irq_cfg
)*nr_irq_cfg
, PAGE_SIZE
, 0);
187 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
189 for (i
= 0; i
< nr_irq_cfg
; i
++)
190 init_one_irq_cfg(&cfg
[i
]);
192 for (i
= 1; i
< nr_irq_cfg
; i
++)
193 cfg
[i
-1].next
= &cfg
[i
];
201 static int assign_irq_vector(int irq
, cpumask_t mask
);
203 int first_system_vector
= 0xfe;
205 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
207 int sis_apic_bug
; /* not actually supported, dummy for compile */
209 static int no_timer_check
;
211 static int disable_timer_pin_1 __initdata
;
213 int timer_through_8259 __initdata
;
215 /* Where if anywhere is the i8259 connect in external int mode */
216 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
218 static DEFINE_SPINLOCK(ioapic_lock
);
219 static DEFINE_SPINLOCK(vector_lock
);
222 * # of IRQ routing registers
224 int nr_ioapic_registers
[MAX_IO_APICS
];
226 /* I/O APIC RTE contents at the OS boot up */
227 struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
229 /* I/O APIC entries */
230 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
233 /* MP IRQ source entries */
234 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
236 /* # of MP IRQ source entries */
239 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
242 * Rough estimation of how many shared IRQs there are, can
243 * be changed anytime.
249 * This is performance-critical, we want to do it O(1)
251 * the indexing order of this array favors 1:1 mappings
252 * between pins and IRQs.
255 static struct irq_pin_list
{
260 DEFINE_DYN_ARRAY(irq_2_pin
, sizeof(struct irq_pin_list
), pin_map_size
, sizeof(struct irq_pin_list
), NULL
);
265 unsigned int unused
[3];
269 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
271 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
272 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
275 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
277 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
278 writel(reg
, &io_apic
->index
);
279 return readl(&io_apic
->data
);
282 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
284 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
285 writel(reg
, &io_apic
->index
);
286 writel(value
, &io_apic
->data
);
290 * Re-write a value: to be used for read-modify-write
291 * cycles where the read already set up the index register.
293 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
295 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
296 writel(value
, &io_apic
->data
);
299 static bool io_apic_level_ack_pending(unsigned int irq
)
301 struct irq_pin_list
*entry
;
304 spin_lock_irqsave(&ioapic_lock
, flags
);
305 entry
= irq_2_pin
+ irq
;
313 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
314 /* Is the remote IRR bit set? */
315 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
316 spin_unlock_irqrestore(&ioapic_lock
, flags
);
321 entry
= irq_2_pin
+ entry
->next
;
323 spin_unlock_irqrestore(&ioapic_lock
, flags
);
329 * Synchronize the IO-APIC and the CPU by doing
330 * a dummy read from the IO-APIC
332 static inline void io_apic_sync(unsigned int apic
)
334 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
335 readl(&io_apic
->data
);
338 #define __DO_ACTION(R, ACTION, FINAL) \
342 struct irq_pin_list *entry = irq_2_pin + irq; \
344 BUG_ON(irq >= nr_irqs); \
350 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
352 io_apic_modify(entry->apic, reg); \
356 entry = irq_2_pin + entry->next; \
361 struct { u32 w1
, w2
; };
362 struct IO_APIC_route_entry entry
;
365 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
367 union entry_union eu
;
369 spin_lock_irqsave(&ioapic_lock
, flags
);
370 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
371 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
372 spin_unlock_irqrestore(&ioapic_lock
, flags
);
377 * When we write a new IO APIC routing entry, we need to write the high
378 * word first! If the mask bit in the low word is clear, we will enable
379 * the interrupt, and we need to make sure the entry is fully populated
380 * before that happens.
383 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
385 union entry_union eu
;
387 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
388 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
391 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
394 spin_lock_irqsave(&ioapic_lock
, flags
);
395 __ioapic_write_entry(apic
, pin
, e
);
396 spin_unlock_irqrestore(&ioapic_lock
, flags
);
400 * When we mask an IO APIC routing entry, we need to write the low
401 * word first, in order to set the mask bit before we change the
404 static void ioapic_mask_entry(int apic
, int pin
)
407 union entry_union eu
= { .entry
.mask
= 1 };
409 spin_lock_irqsave(&ioapic_lock
, flags
);
410 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
411 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
412 spin_unlock_irqrestore(&ioapic_lock
, flags
);
416 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
419 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
421 BUG_ON(irq
>= nr_irqs
);
429 * With interrupt-remapping, destination information comes
430 * from interrupt-remapping table entry.
432 if (!irq_remapped(irq
))
433 io_apic_write(apic
, 0x11 + pin
*2, dest
);
434 reg
= io_apic_read(apic
, 0x10 + pin
*2);
435 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
437 io_apic_modify(apic
, reg
);
440 entry
= irq_2_pin
+ entry
->next
;
444 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
446 struct irq_cfg
*cfg
= irq_cfg(irq
);
450 struct irq_desc
*desc
;
452 cpus_and(tmp
, mask
, cpu_online_map
);
456 if (assign_irq_vector(irq
, mask
))
459 cpus_and(tmp
, cfg
->domain
, mask
);
460 dest
= cpu_mask_to_apicid(tmp
);
463 * Only the high 8 bits are valid.
465 dest
= SET_APIC_LOGICAL_ID(dest
);
467 desc
= irq_to_desc(irq
);
468 spin_lock_irqsave(&ioapic_lock
, flags
);
469 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
470 desc
->affinity
= mask
;
471 spin_unlock_irqrestore(&ioapic_lock
, flags
);
476 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
477 * shared ISA-space IRQs, so we have to support them. We are super
478 * fast in the common case, and fast for shared ISA-space IRQs.
480 int first_free_entry
;
481 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
483 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
485 BUG_ON(irq
>= nr_irqs
);
489 entry
= irq_2_pin
+ entry
->next
;
491 if (entry
->pin
!= -1) {
492 entry
->next
= first_free_entry
;
493 entry
= irq_2_pin
+ entry
->next
;
494 if (++first_free_entry
>= pin_map_size
)
495 panic("io_apic.c: ran out of irq_2_pin entries!");
502 * Reroute an IRQ to a different pin.
504 static void __init
replace_pin_at_irq(unsigned int irq
,
505 int oldapic
, int oldpin
,
506 int newapic
, int newpin
)
508 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
511 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
512 entry
->apic
= newapic
;
517 entry
= irq_2_pin
+ entry
->next
;
522 #define DO_ACTION(name,R,ACTION, FINAL) \
524 static void name##_IO_APIC_irq (unsigned int irq) \
525 __DO_ACTION(R, ACTION, FINAL)
528 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, io_apic_sync(entry
->apic
))
531 DO_ACTION(__unmask
, 0, &= ~IO_APIC_REDIR_MASKED
, )
533 static void mask_IO_APIC_irq (unsigned int irq
)
537 spin_lock_irqsave(&ioapic_lock
, flags
);
538 __mask_IO_APIC_irq(irq
);
539 spin_unlock_irqrestore(&ioapic_lock
, flags
);
542 static void unmask_IO_APIC_irq (unsigned int irq
)
546 spin_lock_irqsave(&ioapic_lock
, flags
);
547 __unmask_IO_APIC_irq(irq
);
548 spin_unlock_irqrestore(&ioapic_lock
, flags
);
551 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
553 struct IO_APIC_route_entry entry
;
555 /* Check delivery_mode to be sure we're not clearing an SMI pin */
556 entry
= ioapic_read_entry(apic
, pin
);
557 if (entry
.delivery_mode
== dest_SMI
)
560 * Disable it in the IO-APIC irq-routing table:
562 ioapic_mask_entry(apic
, pin
);
565 static void clear_IO_APIC (void)
569 for (apic
= 0; apic
< nr_ioapics
; apic
++)
570 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
571 clear_IO_APIC_pin(apic
, pin
);
575 * Saves and masks all the unmasked IO-APIC RTE's
577 int save_mask_IO_APIC_setup(void)
579 union IO_APIC_reg_01 reg_01
;
584 * The number of IO-APIC IRQ registers (== #pins):
586 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
587 spin_lock_irqsave(&ioapic_lock
, flags
);
588 reg_01
.raw
= io_apic_read(apic
, 1);
589 spin_unlock_irqrestore(&ioapic_lock
, flags
);
590 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
593 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
594 early_ioapic_entries
[apic
] =
595 kzalloc(sizeof(struct IO_APIC_route_entry
) *
596 nr_ioapic_registers
[apic
], GFP_KERNEL
);
597 if (!early_ioapic_entries
[apic
])
601 for (apic
= 0; apic
< nr_ioapics
; apic
++)
602 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
603 struct IO_APIC_route_entry entry
;
605 entry
= early_ioapic_entries
[apic
][pin
] =
606 ioapic_read_entry(apic
, pin
);
609 ioapic_write_entry(apic
, pin
, entry
);
615 void restore_IO_APIC_setup(void)
619 for (apic
= 0; apic
< nr_ioapics
; apic
++)
620 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
621 ioapic_write_entry(apic
, pin
,
622 early_ioapic_entries
[apic
][pin
]);
625 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
628 * for now plain restore of previous settings.
629 * TBD: In the case of OS enabling interrupt-remapping,
630 * IO-APIC RTE's need to be setup to point to interrupt-remapping
631 * table entries. for now, do a plain restore, and wait for
632 * the setup_IO_APIC_irqs() to do proper initialization.
634 restore_IO_APIC_setup();
637 int skip_ioapic_setup
;
640 static int __init
parse_noapic(char *str
)
642 disable_ioapic_setup();
645 early_param("noapic", parse_noapic
);
647 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
648 static int __init
disable_timer_pin_setup(char *arg
)
650 disable_timer_pin_1
= 1;
653 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
657 * Find the IRQ entry number of a certain pin.
659 static int find_irq_entry(int apic
, int pin
, int type
)
663 for (i
= 0; i
< mp_irq_entries
; i
++)
664 if (mp_irqs
[i
].mp_irqtype
== type
&&
665 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
666 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
667 mp_irqs
[i
].mp_dstirq
== pin
)
674 * Find the pin to which IRQ[irq] (ISA) is connected
676 static int __init
find_isa_irq_pin(int irq
, int type
)
680 for (i
= 0; i
< mp_irq_entries
; i
++) {
681 int lbus
= mp_irqs
[i
].mp_srcbus
;
683 if (test_bit(lbus
, mp_bus_not_pci
) &&
684 (mp_irqs
[i
].mp_irqtype
== type
) &&
685 (mp_irqs
[i
].mp_srcbusirq
== irq
))
687 return mp_irqs
[i
].mp_dstirq
;
692 static int __init
find_isa_irq_apic(int irq
, int type
)
696 for (i
= 0; i
< mp_irq_entries
; i
++) {
697 int lbus
= mp_irqs
[i
].mp_srcbus
;
699 if (test_bit(lbus
, mp_bus_not_pci
) &&
700 (mp_irqs
[i
].mp_irqtype
== type
) &&
701 (mp_irqs
[i
].mp_srcbusirq
== irq
))
704 if (i
< mp_irq_entries
) {
706 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
707 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
716 * Find a specific PCI IRQ entry.
717 * Not an __init, possibly needed by modules
719 static int pin_2_irq(int idx
, int apic
, int pin
);
721 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
723 int apic
, i
, best_guess
= -1;
725 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
727 if (test_bit(bus
, mp_bus_not_pci
)) {
728 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
731 for (i
= 0; i
< mp_irq_entries
; i
++) {
732 int lbus
= mp_irqs
[i
].mp_srcbus
;
734 for (apic
= 0; apic
< nr_ioapics
; apic
++)
735 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
736 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
739 if (!test_bit(lbus
, mp_bus_not_pci
) &&
740 !mp_irqs
[i
].mp_irqtype
&&
742 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
743 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
745 if (!(apic
|| IO_APIC_IRQ(irq
)))
748 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
751 * Use the first all-but-pin matching entry as a
752 * best-guess fuzzy result for broken mptables.
758 BUG_ON(best_guess
>= nr_irqs
);
762 /* ISA interrupts are always polarity zero edge triggered,
763 * when listed as conforming in the MP table. */
765 #define default_ISA_trigger(idx) (0)
766 #define default_ISA_polarity(idx) (0)
768 /* PCI interrupts are always polarity one level triggered,
769 * when listed as conforming in the MP table. */
771 #define default_PCI_trigger(idx) (1)
772 #define default_PCI_polarity(idx) (1)
774 static int MPBIOS_polarity(int idx
)
776 int bus
= mp_irqs
[idx
].mp_srcbus
;
780 * Determine IRQ line polarity (high active or low active):
782 switch (mp_irqs
[idx
].mp_irqflag
& 3)
784 case 0: /* conforms, ie. bus-type dependent polarity */
785 if (test_bit(bus
, mp_bus_not_pci
))
786 polarity
= default_ISA_polarity(idx
);
788 polarity
= default_PCI_polarity(idx
);
790 case 1: /* high active */
795 case 2: /* reserved */
797 printk(KERN_WARNING
"broken BIOS!!\n");
801 case 3: /* low active */
806 default: /* invalid */
808 printk(KERN_WARNING
"broken BIOS!!\n");
816 static int MPBIOS_trigger(int idx
)
818 int bus
= mp_irqs
[idx
].mp_srcbus
;
822 * Determine IRQ trigger mode (edge or level sensitive):
824 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
826 case 0: /* conforms, ie. bus-type dependent */
827 if (test_bit(bus
, mp_bus_not_pci
))
828 trigger
= default_ISA_trigger(idx
);
830 trigger
= default_PCI_trigger(idx
);
837 case 2: /* reserved */
839 printk(KERN_WARNING
"broken BIOS!!\n");
848 default: /* invalid */
850 printk(KERN_WARNING
"broken BIOS!!\n");
858 static inline int irq_polarity(int idx
)
860 return MPBIOS_polarity(idx
);
863 static inline int irq_trigger(int idx
)
865 return MPBIOS_trigger(idx
);
868 static int pin_2_irq(int idx
, int apic
, int pin
)
871 int bus
= mp_irqs
[idx
].mp_srcbus
;
874 * Debugging check, we are in big trouble if this message pops up!
876 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
877 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
879 if (test_bit(bus
, mp_bus_not_pci
)) {
880 irq
= mp_irqs
[idx
].mp_srcbusirq
;
883 * PCI IRQs are mapped in order
887 irq
+= nr_ioapic_registers
[i
++];
890 BUG_ON(irq
>= nr_irqs
);
894 void lock_vector_lock(void)
896 /* Used to the online set of cpus does not change
897 * during assign_irq_vector.
899 spin_lock(&vector_lock
);
902 void unlock_vector_lock(void)
904 spin_unlock(&vector_lock
);
907 static int __assign_irq_vector(int irq
, cpumask_t mask
)
910 * NOTE! The local APIC isn't very good at handling
911 * multiple interrupts at the same interrupt level.
912 * As the interrupt level is determined by taking the
913 * vector number and shifting that right by 4, we
914 * want to spread these out a bit so that they don't
915 * all fall in the same interrupt level.
917 * Also, we've got to be careful not to trash gate
918 * 0x80, because int 0x80 is hm, kind of importantish. ;)
920 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
921 unsigned int old_vector
;
925 BUG_ON((unsigned)irq
>= nr_irqs
);
928 /* Only try and allocate irqs on cpus that are present */
929 cpus_and(mask
, mask
, cpu_online_map
);
931 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
934 old_vector
= cfg
->vector
;
937 cpus_and(tmp
, cfg
->domain
, mask
);
938 if (!cpus_empty(tmp
))
942 for_each_cpu_mask_nr(cpu
, mask
) {
943 cpumask_t domain
, new_mask
;
947 domain
= vector_allocation_domain(cpu
);
948 cpus_and(new_mask
, domain
, cpu_online_map
);
950 vector
= current_vector
;
951 offset
= current_offset
;
954 if (vector
>= first_system_vector
) {
955 /* If we run out of vectors on large boxen, must share them. */
956 offset
= (offset
+ 1) % 8;
957 vector
= FIRST_DEVICE_VECTOR
+ offset
;
959 if (unlikely(current_vector
== vector
))
961 if (vector
== IA32_SYSCALL_VECTOR
)
963 for_each_cpu_mask_nr(new_cpu
, new_mask
)
964 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
967 current_vector
= vector
;
968 current_offset
= offset
;
970 cfg
->move_in_progress
= 1;
971 cfg
->old_domain
= cfg
->domain
;
973 for_each_cpu_mask_nr(new_cpu
, new_mask
)
974 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
975 cfg
->vector
= vector
;
976 cfg
->domain
= domain
;
982 static int assign_irq_vector(int irq
, cpumask_t mask
)
987 spin_lock_irqsave(&vector_lock
, flags
);
988 err
= __assign_irq_vector(irq
, mask
);
989 spin_unlock_irqrestore(&vector_lock
, flags
);
993 static void __clear_irq_vector(int irq
)
999 BUG_ON((unsigned)irq
>= nr_irqs
);
1001 BUG_ON(!cfg
->vector
);
1003 vector
= cfg
->vector
;
1004 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1005 for_each_cpu_mask_nr(cpu
, mask
)
1006 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1009 cpus_clear(cfg
->domain
);
1012 void __setup_vector_irq(int cpu
)
1014 /* Initialize vector_irq on a new cpu */
1015 /* This function must be called with vector_lock held */
1018 /* Mark the inuse vectors */
1019 for (irq
= 0; irq
< nr_irqs
; ++irq
) {
1020 struct irq_cfg
*cfg
= irq_cfg(irq
);
1022 if (!cpu_isset(cpu
, cfg
->domain
))
1024 vector
= cfg
->vector
;
1025 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1027 /* Mark the free vectors */
1028 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1029 struct irq_cfg
*cfg
;
1031 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1036 if (!cpu_isset(cpu
, cfg
->domain
))
1037 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1041 static struct irq_chip ioapic_chip
;
1042 #ifdef CONFIG_INTR_REMAP
1043 static struct irq_chip ir_ioapic_chip
;
1046 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1048 struct irq_desc
*desc
;
1050 desc
= irq_to_desc(irq
);
1052 desc
->status
|= IRQ_LEVEL
;
1054 desc
->status
&= ~IRQ_LEVEL
;
1056 #ifdef CONFIG_INTR_REMAP
1057 if (irq_remapped(irq
)) {
1058 desc
->status
|= IRQ_MOVE_PCNTXT
;
1060 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1064 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1065 handle_edge_irq
, "edge");
1070 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1074 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1075 handle_edge_irq
, "edge");
1078 static int setup_ioapic_entry(int apic
, int irq
,
1079 struct IO_APIC_route_entry
*entry
,
1080 unsigned int destination
, int trigger
,
1081 int polarity
, int vector
)
1084 * add it to the IO-APIC irq-routing table:
1086 memset(entry
,0,sizeof(*entry
));
1088 #ifdef CONFIG_INTR_REMAP
1089 if (intr_remapping_enabled
) {
1090 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1092 struct IR_IO_APIC_route_entry
*ir_entry
=
1093 (struct IR_IO_APIC_route_entry
*) entry
;
1097 panic("No mapping iommu for ioapic %d\n", apic
);
1099 index
= alloc_irte(iommu
, irq
, 1);
1101 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1103 memset(&irte
, 0, sizeof(irte
));
1106 irte
.dst_mode
= INT_DEST_MODE
;
1107 irte
.trigger_mode
= trigger
;
1108 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1109 irte
.vector
= vector
;
1110 irte
.dest_id
= IRTE_DEST(destination
);
1112 modify_irte(irq
, &irte
);
1114 ir_entry
->index2
= (index
>> 15) & 0x1;
1116 ir_entry
->format
= 1;
1117 ir_entry
->index
= (index
& 0x7fff);
1121 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1122 entry
->dest_mode
= INT_DEST_MODE
;
1123 entry
->dest
= destination
;
1126 entry
->mask
= 0; /* enable IRQ */
1127 entry
->trigger
= trigger
;
1128 entry
->polarity
= polarity
;
1129 entry
->vector
= vector
;
1131 /* Mask level triggered irqs.
1132 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1139 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1140 int trigger
, int polarity
)
1142 struct irq_cfg
*cfg
;
1143 struct IO_APIC_route_entry entry
;
1146 if (!IO_APIC_IRQ(irq
))
1152 if (assign_irq_vector(irq
, mask
))
1155 cpus_and(mask
, cfg
->domain
, mask
);
1157 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1158 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1159 "IRQ %d Mode:%i Active:%i)\n",
1160 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1161 irq
, trigger
, polarity
);
1164 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1165 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1167 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1168 mp_ioapics
[apic
].mp_apicid
, pin
);
1169 __clear_irq_vector(irq
);
1173 ioapic_register_intr(irq
, trigger
);
1175 disable_8259A_irq(irq
);
1177 ioapic_write_entry(apic
, pin
, entry
);
1180 static void __init
setup_IO_APIC_irqs(void)
1182 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1184 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1186 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1187 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1189 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1192 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1195 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1198 if (!first_notcon
) {
1199 apic_printk(APIC_VERBOSE
, " not connected.\n");
1203 irq
= pin_2_irq(idx
, apic
, pin
);
1204 add_pin_to_irq(irq
, apic
, pin
);
1206 setup_IO_APIC_irq(apic
, pin
, irq
,
1207 irq_trigger(idx
), irq_polarity(idx
));
1212 apic_printk(APIC_VERBOSE
, " not connected.\n");
1216 * Set up the timer pin, possibly with the 8259A-master behind.
1218 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1221 struct IO_APIC_route_entry entry
;
1223 if (intr_remapping_enabled
)
1226 memset(&entry
, 0, sizeof(entry
));
1229 * We use logical delivery to get the timer IRQ
1232 entry
.dest_mode
= INT_DEST_MODE
;
1233 entry
.mask
= 1; /* mask IRQ now */
1234 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1235 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1238 entry
.vector
= vector
;
1241 * The timer IRQ doesn't have to know that behind the
1242 * scene we may have a 8259A-master in AEOI mode ...
1244 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1247 * Add it to the IO-APIC irq-routing table:
1249 ioapic_write_entry(apic
, pin
, entry
);
1253 __apicdebuginit(void) print_IO_APIC(void)
1256 union IO_APIC_reg_00 reg_00
;
1257 union IO_APIC_reg_01 reg_01
;
1258 union IO_APIC_reg_02 reg_02
;
1259 unsigned long flags
;
1261 if (apic_verbosity
== APIC_QUIET
)
1264 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1265 for (i
= 0; i
< nr_ioapics
; i
++)
1266 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1267 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1270 * We are a bit conservative about what we expect. We have to
1271 * know about every hardware change ASAP.
1273 printk(KERN_INFO
"testing the IO APIC.......................\n");
1275 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1277 spin_lock_irqsave(&ioapic_lock
, flags
);
1278 reg_00
.raw
= io_apic_read(apic
, 0);
1279 reg_01
.raw
= io_apic_read(apic
, 1);
1280 if (reg_01
.bits
.version
>= 0x10)
1281 reg_02
.raw
= io_apic_read(apic
, 2);
1282 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1285 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1286 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1287 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1289 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1290 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1292 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1293 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1295 if (reg_01
.bits
.version
>= 0x10) {
1296 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1297 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1300 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1302 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1303 " Stat Dmod Deli Vect: \n");
1305 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1306 struct IO_APIC_route_entry entry
;
1308 entry
= ioapic_read_entry(apic
, i
);
1310 printk(KERN_DEBUG
" %02x %03X ",
1315 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1320 entry
.delivery_status
,
1322 entry
.delivery_mode
,
1327 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1328 for (i
= 0; i
< nr_irqs
; i
++) {
1329 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1332 printk(KERN_DEBUG
"IRQ%d ", i
);
1334 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1337 entry
= irq_2_pin
+ entry
->next
;
1342 printk(KERN_INFO
".................................... done.\n");
1347 __apicdebuginit(void) print_APIC_bitfield(int base
)
1352 if (apic_verbosity
== APIC_QUIET
)
1355 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1356 for (i
= 0; i
< 8; i
++) {
1357 v
= apic_read(base
+ i
*0x10);
1358 for (j
= 0; j
< 32; j
++) {
1368 __apicdebuginit(void) print_local_APIC(void *dummy
)
1370 unsigned int v
, ver
, maxlvt
;
1373 if (apic_verbosity
== APIC_QUIET
)
1376 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1377 smp_processor_id(), hard_smp_processor_id());
1378 v
= apic_read(APIC_ID
);
1379 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1380 v
= apic_read(APIC_LVR
);
1381 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1382 ver
= GET_APIC_VERSION(v
);
1383 maxlvt
= lapic_get_maxlvt();
1385 v
= apic_read(APIC_TASKPRI
);
1386 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1388 v
= apic_read(APIC_ARBPRI
);
1389 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1390 v
& APIC_ARBPRI_MASK
);
1391 v
= apic_read(APIC_PROCPRI
);
1392 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1394 v
= apic_read(APIC_EOI
);
1395 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1396 v
= apic_read(APIC_RRR
);
1397 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1398 v
= apic_read(APIC_LDR
);
1399 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1400 v
= apic_read(APIC_DFR
);
1401 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1402 v
= apic_read(APIC_SPIV
);
1403 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1405 printk(KERN_DEBUG
"... APIC ISR field:\n");
1406 print_APIC_bitfield(APIC_ISR
);
1407 printk(KERN_DEBUG
"... APIC TMR field:\n");
1408 print_APIC_bitfield(APIC_TMR
);
1409 printk(KERN_DEBUG
"... APIC IRR field:\n");
1410 print_APIC_bitfield(APIC_IRR
);
1412 v
= apic_read(APIC_ESR
);
1413 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1415 icr
= apic_icr_read();
1416 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1417 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1419 v
= apic_read(APIC_LVTT
);
1420 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1422 if (maxlvt
> 3) { /* PC is LVT#4. */
1423 v
= apic_read(APIC_LVTPC
);
1424 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1426 v
= apic_read(APIC_LVT0
);
1427 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1428 v
= apic_read(APIC_LVT1
);
1429 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1431 if (maxlvt
> 2) { /* ERR is LVT#3. */
1432 v
= apic_read(APIC_LVTERR
);
1433 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1436 v
= apic_read(APIC_TMICT
);
1437 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1438 v
= apic_read(APIC_TMCCT
);
1439 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1440 v
= apic_read(APIC_TDCR
);
1441 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1445 __apicdebuginit(void) print_all_local_APICs(void)
1447 on_each_cpu(print_local_APIC
, NULL
, 1);
1450 __apicdebuginit(void) print_PIC(void)
1453 unsigned long flags
;
1455 if (apic_verbosity
== APIC_QUIET
)
1458 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1460 spin_lock_irqsave(&i8259A_lock
, flags
);
1462 v
= inb(0xa1) << 8 | inb(0x21);
1463 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1465 v
= inb(0xa0) << 8 | inb(0x20);
1466 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1470 v
= inb(0xa0) << 8 | inb(0x20);
1474 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1476 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1478 v
= inb(0x4d1) << 8 | inb(0x4d0);
1479 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1482 __apicdebuginit(int) print_all_ICs(void)
1485 print_all_local_APICs();
1491 fs_initcall(print_all_ICs
);
1494 void __init
enable_IO_APIC(void)
1496 union IO_APIC_reg_01 reg_01
;
1497 int i8259_apic
, i8259_pin
;
1499 unsigned long flags
;
1501 for (i
= 0; i
< pin_map_size
; i
++) {
1502 irq_2_pin
[i
].pin
= -1;
1503 irq_2_pin
[i
].next
= 0;
1507 * The number of IO-APIC IRQ registers (== #pins):
1509 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1510 spin_lock_irqsave(&ioapic_lock
, flags
);
1511 reg_01
.raw
= io_apic_read(apic
, 1);
1512 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1513 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1515 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1517 /* See if any of the pins is in ExtINT mode */
1518 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1519 struct IO_APIC_route_entry entry
;
1520 entry
= ioapic_read_entry(apic
, pin
);
1522 /* If the interrupt line is enabled and in ExtInt mode
1523 * I have found the pin where the i8259 is connected.
1525 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1526 ioapic_i8259
.apic
= apic
;
1527 ioapic_i8259
.pin
= pin
;
1533 /* Look to see what if the MP table has reported the ExtINT */
1534 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1535 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1536 /* Trust the MP table if nothing is setup in the hardware */
1537 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1538 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1539 ioapic_i8259
.pin
= i8259_pin
;
1540 ioapic_i8259
.apic
= i8259_apic
;
1542 /* Complain if the MP table and the hardware disagree */
1543 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1544 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1546 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1550 * Do not trust the IO-APIC being empty at bootup
1556 * Not an __init, needed by the reboot code
1558 void disable_IO_APIC(void)
1561 * Clear the IO-APIC before rebooting:
1566 * If the i8259 is routed through an IOAPIC
1567 * Put that IOAPIC in virtual wire mode
1568 * so legacy interrupts can be delivered.
1570 if (ioapic_i8259
.pin
!= -1) {
1571 struct IO_APIC_route_entry entry
;
1573 memset(&entry
, 0, sizeof(entry
));
1574 entry
.mask
= 0; /* Enabled */
1575 entry
.trigger
= 0; /* Edge */
1577 entry
.polarity
= 0; /* High */
1578 entry
.delivery_status
= 0;
1579 entry
.dest_mode
= 0; /* Physical */
1580 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1582 entry
.dest
= read_apic_id();
1585 * Add it to the IO-APIC irq-routing table:
1587 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1590 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1594 * There is a nasty bug in some older SMP boards, their mptable lies
1595 * about the timer IRQ. We do the following to work around the situation:
1597 * - timer IRQ defaults to IO-APIC IRQ
1598 * - if this function detects that timer IRQs are defunct, then we fall
1599 * back to ISA timer IRQs
1601 static int __init
timer_irq_works(void)
1603 unsigned long t1
= jiffies
;
1604 unsigned long flags
;
1606 local_save_flags(flags
);
1608 /* Let ten ticks pass... */
1609 mdelay((10 * 1000) / HZ
);
1610 local_irq_restore(flags
);
1613 * Expect a few ticks at least, to be sure some possible
1614 * glue logic does not lock up after one or two first
1615 * ticks in a non-ExtINT mode. Also the local APIC
1616 * might have cached one ExtINT interrupt. Finally, at
1617 * least one tick may be lost due to delays.
1621 if (time_after(jiffies
, t1
+ 4))
1627 * In the SMP+IOAPIC case it might happen that there are an unspecified
1628 * number of pending IRQ events unhandled. These cases are very rare,
1629 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1630 * better to do it this way as thus we do not have to be aware of
1631 * 'pending' interrupts in the IRQ path, except at this point.
1634 * Edge triggered needs to resend any interrupt
1635 * that was delayed but this is now handled in the device
1640 * Starting up a edge-triggered IO-APIC interrupt is
1641 * nasty - we need to make sure that we get the edge.
1642 * If it is already asserted for some reason, we need
1643 * return 1 to indicate that is was pending.
1645 * This is not complete - we should be able to fake
1646 * an edge even if it isn't on the 8259A...
1649 static unsigned int startup_ioapic_irq(unsigned int irq
)
1651 int was_pending
= 0;
1652 unsigned long flags
;
1654 spin_lock_irqsave(&ioapic_lock
, flags
);
1656 disable_8259A_irq(irq
);
1657 if (i8259A_irq_pending(irq
))
1660 __unmask_IO_APIC_irq(irq
);
1661 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1666 static int ioapic_retrigger_irq(unsigned int irq
)
1668 struct irq_cfg
*cfg
= irq_cfg(irq
);
1669 unsigned long flags
;
1671 spin_lock_irqsave(&vector_lock
, flags
);
1672 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
1673 spin_unlock_irqrestore(&vector_lock
, flags
);
1679 * Level and edge triggered IO-APIC interrupts need different handling,
1680 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1681 * handled with the level-triggered descriptor, but that one has slightly
1682 * more overhead. Level-triggered interrupts cannot be handled with the
1683 * edge-triggered handler, without risking IRQ storms and other ugly
1689 #ifdef CONFIG_INTR_REMAP
1690 static void ir_irq_migration(struct work_struct
*work
);
1692 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
1695 * Migrate the IO-APIC irq in the presence of intr-remapping.
1697 * For edge triggered, irq migration is a simple atomic update(of vector
1698 * and cpu destination) of IRTE and flush the hardware cache.
1700 * For level triggered, we need to modify the io-apic RTE aswell with the update
1701 * vector information, along with modifying IRTE with vector and destination.
1702 * So irq migration for level triggered is little bit more complex compared to
1703 * edge triggered migration. But the good news is, we use the same algorithm
1704 * for level triggered migration as we have today, only difference being,
1705 * we now initiate the irq migration from process context instead of the
1706 * interrupt context.
1708 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1709 * suppression) to the IO-APIC, level triggered irq migration will also be
1710 * as simple as edge triggered migration and we can do the irq migration
1711 * with a simple atomic update to IO-APIC RTE.
1713 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
1715 struct irq_cfg
*cfg
;
1716 struct irq_desc
*desc
;
1717 cpumask_t tmp
, cleanup_mask
;
1719 int modify_ioapic_rte
;
1721 unsigned long flags
;
1723 cpus_and(tmp
, mask
, cpu_online_map
);
1724 if (cpus_empty(tmp
))
1727 if (get_irte(irq
, &irte
))
1730 if (assign_irq_vector(irq
, mask
))
1734 cpus_and(tmp
, cfg
->domain
, mask
);
1735 dest
= cpu_mask_to_apicid(tmp
);
1737 desc
= irq_to_desc(irq
);
1738 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
1739 if (modify_ioapic_rte
) {
1740 spin_lock_irqsave(&ioapic_lock
, flags
);
1741 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
1742 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1745 irte
.vector
= cfg
->vector
;
1746 irte
.dest_id
= IRTE_DEST(dest
);
1749 * Modified the IRTE and flushes the Interrupt entry cache.
1751 modify_irte(irq
, &irte
);
1753 if (cfg
->move_in_progress
) {
1754 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1755 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1756 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1757 cfg
->move_in_progress
= 0;
1760 desc
->affinity
= mask
;
1763 static int migrate_irq_remapped_level(int irq
)
1766 struct irq_desc
*desc
= irq_to_desc(irq
);
1768 mask_IO_APIC_irq(irq
);
1770 if (io_apic_level_ack_pending(irq
)) {
1772 * Interrupt in progress. Migrating irq now will change the
1773 * vector information in the IO-APIC RTE and that will confuse
1774 * the EOI broadcast performed by cpu.
1775 * So, delay the irq migration to the next instance.
1777 schedule_delayed_work(&ir_migration_work
, 1);
1781 /* everthing is clear. we have right of way */
1782 migrate_ioapic_irq(irq
, desc
->pending_mask
);
1785 desc
->status
&= ~IRQ_MOVE_PENDING
;
1786 cpus_clear(desc
->pending_mask
);
1789 unmask_IO_APIC_irq(irq
);
1793 static void ir_irq_migration(struct work_struct
*work
)
1797 for (irq
= 0; irq
< nr_irqs
; irq
++) {
1798 struct irq_desc
*desc
= irq_to_desc(irq
);
1799 if (desc
->status
& IRQ_MOVE_PENDING
) {
1800 unsigned long flags
;
1802 spin_lock_irqsave(&desc
->lock
, flags
);
1803 if (!desc
->chip
->set_affinity
||
1804 !(desc
->status
& IRQ_MOVE_PENDING
)) {
1805 desc
->status
&= ~IRQ_MOVE_PENDING
;
1806 spin_unlock_irqrestore(&desc
->lock
, flags
);
1810 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
1811 spin_unlock_irqrestore(&desc
->lock
, flags
);
1817 * Migrates the IRQ destination in the process context.
1819 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
1821 struct irq_desc
*desc
= irq_to_desc(irq
);
1823 if (desc
->status
& IRQ_LEVEL
) {
1824 desc
->status
|= IRQ_MOVE_PENDING
;
1825 desc
->pending_mask
= mask
;
1826 migrate_irq_remapped_level(irq
);
1830 migrate_ioapic_irq(irq
, mask
);
1834 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1836 unsigned vector
, me
;
1841 me
= smp_processor_id();
1842 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1844 struct irq_desc
*desc
;
1845 struct irq_cfg
*cfg
;
1846 irq
= __get_cpu_var(vector_irq
)[vector
];
1850 desc
= irq_to_desc(irq
);
1852 spin_lock(&desc
->lock
);
1853 if (!cfg
->move_cleanup_count
)
1856 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1859 __get_cpu_var(vector_irq
)[vector
] = -1;
1860 cfg
->move_cleanup_count
--;
1862 spin_unlock(&desc
->lock
);
1868 static void irq_complete_move(unsigned int irq
)
1870 struct irq_cfg
*cfg
= irq_cfg(irq
);
1871 unsigned vector
, me
;
1873 if (likely(!cfg
->move_in_progress
))
1876 vector
= ~get_irq_regs()->orig_ax
;
1877 me
= smp_processor_id();
1878 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1879 cpumask_t cleanup_mask
;
1881 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1882 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1883 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1884 cfg
->move_in_progress
= 0;
1888 static inline void irq_complete_move(unsigned int irq
) {}
1890 #ifdef CONFIG_INTR_REMAP
1891 static void ack_x2apic_level(unsigned int irq
)
1896 static void ack_x2apic_edge(unsigned int irq
)
1902 static void ack_apic_edge(unsigned int irq
)
1904 irq_complete_move(irq
);
1905 move_native_irq(irq
);
1909 static void ack_apic_level(unsigned int irq
)
1911 int do_unmask_irq
= 0;
1913 irq_complete_move(irq
);
1914 #ifdef CONFIG_GENERIC_PENDING_IRQ
1915 /* If we are moving the irq we need to mask it */
1916 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
1918 mask_IO_APIC_irq(irq
);
1923 * We must acknowledge the irq before we move it or the acknowledge will
1924 * not propagate properly.
1928 /* Now we can move and renable the irq */
1929 if (unlikely(do_unmask_irq
)) {
1930 /* Only migrate the irq if the ack has been received.
1932 * On rare occasions the broadcast level triggered ack gets
1933 * delayed going to ioapics, and if we reprogram the
1934 * vector while Remote IRR is still set the irq will never
1937 * To prevent this scenario we read the Remote IRR bit
1938 * of the ioapic. This has two effects.
1939 * - On any sane system the read of the ioapic will
1940 * flush writes (and acks) going to the ioapic from
1942 * - We get to see if the ACK has actually been delivered.
1944 * Based on failed experiments of reprogramming the
1945 * ioapic entry from outside of irq context starting
1946 * with masking the ioapic entry and then polling until
1947 * Remote IRR was clear before reprogramming the
1948 * ioapic I don't trust the Remote IRR bit to be
1949 * completey accurate.
1951 * However there appears to be no other way to plug
1952 * this race, so if the Remote IRR bit is not
1953 * accurate and is causing problems then it is a hardware bug
1954 * and you can go talk to the chipset vendor about it.
1956 if (!io_apic_level_ack_pending(irq
))
1957 move_masked_irq(irq
);
1958 unmask_IO_APIC_irq(irq
);
1962 static struct irq_chip ioapic_chip __read_mostly
= {
1964 .startup
= startup_ioapic_irq
,
1965 .mask
= mask_IO_APIC_irq
,
1966 .unmask
= unmask_IO_APIC_irq
,
1967 .ack
= ack_apic_edge
,
1968 .eoi
= ack_apic_level
,
1970 .set_affinity
= set_ioapic_affinity_irq
,
1972 .retrigger
= ioapic_retrigger_irq
,
1975 #ifdef CONFIG_INTR_REMAP
1976 static struct irq_chip ir_ioapic_chip __read_mostly
= {
1977 .name
= "IR-IO-APIC",
1978 .startup
= startup_ioapic_irq
,
1979 .mask
= mask_IO_APIC_irq
,
1980 .unmask
= unmask_IO_APIC_irq
,
1981 .ack
= ack_x2apic_edge
,
1982 .eoi
= ack_x2apic_level
,
1984 .set_affinity
= set_ir_ioapic_affinity_irq
,
1986 .retrigger
= ioapic_retrigger_irq
,
1990 static inline void init_IO_APIC_traps(void)
1993 struct irq_desc
*desc
;
1996 * NOTE! The local APIC isn't very good at handling
1997 * multiple interrupts at the same interrupt level.
1998 * As the interrupt level is determined by taking the
1999 * vector number and shifting that right by 4, we
2000 * want to spread these out a bit so that they don't
2001 * all fall in the same interrupt level.
2003 * Also, we've got to be careful not to trash gate
2004 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2006 for (irq
= 0; irq
< nr_irqs
; irq
++) {
2007 struct irq_cfg
*cfg
;
2010 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2012 * Hmm.. We don't have an entry for this,
2013 * so default to an old-fashioned 8259
2014 * interrupt if we can..
2017 make_8259A_irq(irq
);
2019 desc
= irq_to_desc(irq
);
2020 /* Strange. Oh, well.. */
2021 desc
->chip
= &no_irq_chip
;
2027 static void unmask_lapic_irq(unsigned int irq
)
2031 v
= apic_read(APIC_LVT0
);
2032 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2035 static void mask_lapic_irq(unsigned int irq
)
2039 v
= apic_read(APIC_LVT0
);
2040 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2043 static void ack_lapic_irq (unsigned int irq
)
2048 static struct irq_chip lapic_chip __read_mostly
= {
2049 .name
= "local-APIC",
2050 .mask
= mask_lapic_irq
,
2051 .unmask
= unmask_lapic_irq
,
2052 .ack
= ack_lapic_irq
,
2055 static void lapic_register_intr(int irq
)
2057 struct irq_desc
*desc
;
2059 desc
= irq_to_desc(irq
);
2060 desc
->status
&= ~IRQ_LEVEL
;
2061 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2065 static void __init
setup_nmi(void)
2068 * Dirty trick to enable the NMI watchdog ...
2069 * We put the 8259A master into AEOI mode and
2070 * unmask on all local APICs LVT0 as NMI.
2072 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2073 * is from Maciej W. Rozycki - so we do not have to EOI from
2074 * the NMI handler or the timer interrupt.
2076 printk(KERN_INFO
"activating NMI Watchdog ...");
2078 enable_NMI_through_LVT0();
2084 * This looks a bit hackish but it's about the only one way of sending
2085 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2086 * not support the ExtINT mode, unfortunately. We need to send these
2087 * cycles as some i82489DX-based boards have glue logic that keeps the
2088 * 8259A interrupt line asserted until INTA. --macro
2090 static inline void __init
unlock_ExtINT_logic(void)
2093 struct IO_APIC_route_entry entry0
, entry1
;
2094 unsigned char save_control
, save_freq_select
;
2096 pin
= find_isa_irq_pin(8, mp_INT
);
2097 apic
= find_isa_irq_apic(8, mp_INT
);
2101 entry0
= ioapic_read_entry(apic
, pin
);
2103 clear_IO_APIC_pin(apic
, pin
);
2105 memset(&entry1
, 0, sizeof(entry1
));
2107 entry1
.dest_mode
= 0; /* physical delivery */
2108 entry1
.mask
= 0; /* unmask IRQ now */
2109 entry1
.dest
= hard_smp_processor_id();
2110 entry1
.delivery_mode
= dest_ExtINT
;
2111 entry1
.polarity
= entry0
.polarity
;
2115 ioapic_write_entry(apic
, pin
, entry1
);
2117 save_control
= CMOS_READ(RTC_CONTROL
);
2118 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2119 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2121 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2126 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2130 CMOS_WRITE(save_control
, RTC_CONTROL
);
2131 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2132 clear_IO_APIC_pin(apic
, pin
);
2134 ioapic_write_entry(apic
, pin
, entry0
);
2138 * This code may look a bit paranoid, but it's supposed to cooperate with
2139 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2140 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2141 * fanatically on his truly buggy board.
2143 * FIXME: really need to revamp this for modern platforms only.
2145 static inline void __init
check_timer(void)
2147 struct irq_cfg
*cfg
= irq_cfg(0);
2148 int apic1
, pin1
, apic2
, pin2
;
2149 unsigned long flags
;
2152 local_irq_save(flags
);
2155 * get/set the timer IRQ vector:
2157 disable_8259A_irq(0);
2158 assign_irq_vector(0, TARGET_CPUS
);
2161 * As IRQ0 is to be enabled in the 8259A, the virtual
2162 * wire has to be disabled in the local APIC.
2164 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2167 pin1
= find_isa_irq_pin(0, mp_INT
);
2168 apic1
= find_isa_irq_apic(0, mp_INT
);
2169 pin2
= ioapic_i8259
.pin
;
2170 apic2
= ioapic_i8259
.apic
;
2172 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2173 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2174 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2177 * Some BIOS writers are clueless and report the ExtINTA
2178 * I/O APIC input from the cascaded 8259A as the timer
2179 * interrupt input. So just in case, if only one pin
2180 * was found above, try it both directly and through the
2184 if (intr_remapping_enabled
)
2185 panic("BIOS bug: timer not connected to IO-APIC");
2189 } else if (pin2
== -1) {
2196 * Ok, does IRQ0 through the IOAPIC work?
2199 add_pin_to_irq(0, apic1
, pin1
);
2200 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2202 unmask_IO_APIC_irq(0);
2203 if (!no_timer_check
&& timer_irq_works()) {
2204 if (nmi_watchdog
== NMI_IO_APIC
) {
2206 enable_8259A_irq(0);
2208 if (disable_timer_pin_1
> 0)
2209 clear_IO_APIC_pin(0, pin1
);
2212 if (intr_remapping_enabled
)
2213 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2214 clear_IO_APIC_pin(apic1
, pin1
);
2216 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2217 "8254 timer not connected to IO-APIC\n");
2219 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2220 "(IRQ0) through the 8259A ...\n");
2221 apic_printk(APIC_QUIET
, KERN_INFO
2222 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2224 * legacy devices should be connected to IO APIC #0
2226 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2227 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2228 unmask_IO_APIC_irq(0);
2229 enable_8259A_irq(0);
2230 if (timer_irq_works()) {
2231 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2232 timer_through_8259
= 1;
2233 if (nmi_watchdog
== NMI_IO_APIC
) {
2234 disable_8259A_irq(0);
2236 enable_8259A_irq(0);
2241 * Cleanup, just in case ...
2243 disable_8259A_irq(0);
2244 clear_IO_APIC_pin(apic2
, pin2
);
2245 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2248 if (nmi_watchdog
== NMI_IO_APIC
) {
2249 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2250 "through the IO-APIC - disabling NMI Watchdog!\n");
2251 nmi_watchdog
= NMI_NONE
;
2254 apic_printk(APIC_QUIET
, KERN_INFO
2255 "...trying to set up timer as Virtual Wire IRQ...\n");
2257 lapic_register_intr(0);
2258 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2259 enable_8259A_irq(0);
2261 if (timer_irq_works()) {
2262 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2265 disable_8259A_irq(0);
2266 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2267 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2269 apic_printk(APIC_QUIET
, KERN_INFO
2270 "...trying to set up timer as ExtINT IRQ...\n");
2274 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2276 unlock_ExtINT_logic();
2278 if (timer_irq_works()) {
2279 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2282 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2283 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2284 "report. Then try booting with the 'noapic' option.\n");
2286 local_irq_restore(flags
);
2289 static int __init
notimercheck(char *s
)
2294 __setup("no_timer_check", notimercheck
);
2297 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2298 * to devices. However there may be an I/O APIC pin available for
2299 * this interrupt regardless. The pin may be left unconnected, but
2300 * typically it will be reused as an ExtINT cascade interrupt for
2301 * the master 8259A. In the MPS case such a pin will normally be
2302 * reported as an ExtINT interrupt in the MP table. With ACPI
2303 * there is no provision for ExtINT interrupts, and in the absence
2304 * of an override it would be treated as an ordinary ISA I/O APIC
2305 * interrupt, that is edge-triggered and unmasked by default. We
2306 * used to do this, but it caused problems on some systems because
2307 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2308 * the same ExtINT cascade interrupt to drive the local APIC of the
2309 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2310 * the I/O APIC in all cases now. No actual device should request
2311 * it anyway. --macro
2313 #define PIC_IRQS (1<<2)
2315 void __init
setup_IO_APIC(void)
2319 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2322 io_apic_irqs
= ~PIC_IRQS
;
2324 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2327 setup_IO_APIC_irqs();
2328 init_IO_APIC_traps();
2332 struct sysfs_ioapic_data
{
2333 struct sys_device dev
;
2334 struct IO_APIC_route_entry entry
[0];
2336 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2338 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2340 struct IO_APIC_route_entry
*entry
;
2341 struct sysfs_ioapic_data
*data
;
2344 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2345 entry
= data
->entry
;
2346 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2347 *entry
= ioapic_read_entry(dev
->id
, i
);
2352 static int ioapic_resume(struct sys_device
*dev
)
2354 struct IO_APIC_route_entry
*entry
;
2355 struct sysfs_ioapic_data
*data
;
2356 unsigned long flags
;
2357 union IO_APIC_reg_00 reg_00
;
2360 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2361 entry
= data
->entry
;
2363 spin_lock_irqsave(&ioapic_lock
, flags
);
2364 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2365 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2366 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2367 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2369 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2370 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2371 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2376 static struct sysdev_class ioapic_sysdev_class
= {
2378 .suspend
= ioapic_suspend
,
2379 .resume
= ioapic_resume
,
2382 static int __init
ioapic_init_sysfs(void)
2384 struct sys_device
* dev
;
2387 error
= sysdev_class_register(&ioapic_sysdev_class
);
2391 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2392 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2393 * sizeof(struct IO_APIC_route_entry
);
2394 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2395 if (!mp_ioapic_data
[i
]) {
2396 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2399 dev
= &mp_ioapic_data
[i
]->dev
;
2401 dev
->cls
= &ioapic_sysdev_class
;
2402 error
= sysdev_register(dev
);
2404 kfree(mp_ioapic_data
[i
]);
2405 mp_ioapic_data
[i
] = NULL
;
2406 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2414 device_initcall(ioapic_init_sysfs
);
2417 * Dynamic irq allocate and deallocation
2419 int create_irq(void)
2421 /* Allocate an unused irq */
2424 unsigned long flags
;
2425 struct irq_cfg
*cfg_new
;
2428 spin_lock_irqsave(&vector_lock
, flags
);
2429 for (new = (nr_irqs
- 1); new >= 0; new--) {
2430 if (platform_legacy_irq(new))
2432 cfg_new
= irq_cfg(new);
2433 if (cfg_new
&& cfg_new
->vector
!= 0)
2435 /* check if need to create one */
2437 cfg_new
= irq_cfg_alloc(new);
2438 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2442 spin_unlock_irqrestore(&vector_lock
, flags
);
2445 dynamic_irq_init(irq
);
2450 void destroy_irq(unsigned int irq
)
2452 unsigned long flags
;
2454 dynamic_irq_cleanup(irq
);
2456 #ifdef CONFIG_INTR_REMAP
2459 spin_lock_irqsave(&vector_lock
, flags
);
2460 __clear_irq_vector(irq
);
2461 spin_unlock_irqrestore(&vector_lock
, flags
);
2465 * MSI message composition
2467 #ifdef CONFIG_PCI_MSI
2468 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2470 struct irq_cfg
*cfg
;
2476 err
= assign_irq_vector(irq
, tmp
);
2481 cpus_and(tmp
, cfg
->domain
, tmp
);
2482 dest
= cpu_mask_to_apicid(tmp
);
2484 #ifdef CONFIG_INTR_REMAP
2485 if (irq_remapped(irq
)) {
2490 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
2491 BUG_ON(ir_index
== -1);
2493 memset (&irte
, 0, sizeof(irte
));
2496 irte
.dst_mode
= INT_DEST_MODE
;
2497 irte
.trigger_mode
= 0; /* edge */
2498 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
2499 irte
.vector
= cfg
->vector
;
2500 irte
.dest_id
= IRTE_DEST(dest
);
2502 modify_irte(irq
, &irte
);
2504 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2505 msg
->data
= sub_handle
;
2506 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
2508 MSI_ADDR_IR_INDEX1(ir_index
) |
2509 MSI_ADDR_IR_INDEX2(ir_index
);
2513 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2516 ((INT_DEST_MODE
== 0) ?
2517 MSI_ADDR_DEST_MODE_PHYSICAL
:
2518 MSI_ADDR_DEST_MODE_LOGICAL
) |
2519 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2520 MSI_ADDR_REDIRECTION_CPU
:
2521 MSI_ADDR_REDIRECTION_LOWPRI
) |
2522 MSI_ADDR_DEST_ID(dest
);
2525 MSI_DATA_TRIGGER_EDGE
|
2526 MSI_DATA_LEVEL_ASSERT
|
2527 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2528 MSI_DATA_DELIVERY_FIXED
:
2529 MSI_DATA_DELIVERY_LOWPRI
) |
2530 MSI_DATA_VECTOR(cfg
->vector
);
2536 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2538 struct irq_cfg
*cfg
;
2542 struct irq_desc
*desc
;
2544 cpus_and(tmp
, mask
, cpu_online_map
);
2545 if (cpus_empty(tmp
))
2548 if (assign_irq_vector(irq
, mask
))
2552 cpus_and(tmp
, cfg
->domain
, mask
);
2553 dest
= cpu_mask_to_apicid(tmp
);
2555 read_msi_msg(irq
, &msg
);
2557 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2558 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2559 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2560 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2562 write_msi_msg(irq
, &msg
);
2563 desc
= irq_to_desc(irq
);
2564 desc
->affinity
= mask
;
2567 #ifdef CONFIG_INTR_REMAP
2569 * Migrate the MSI irq to another cpumask. This migration is
2570 * done in the process context using interrupt-remapping hardware.
2572 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2574 struct irq_cfg
*cfg
;
2576 cpumask_t tmp
, cleanup_mask
;
2578 struct irq_desc
*desc
;
2580 cpus_and(tmp
, mask
, cpu_online_map
);
2581 if (cpus_empty(tmp
))
2584 if (get_irte(irq
, &irte
))
2587 if (assign_irq_vector(irq
, mask
))
2591 cpus_and(tmp
, cfg
->domain
, mask
);
2592 dest
= cpu_mask_to_apicid(tmp
);
2594 irte
.vector
= cfg
->vector
;
2595 irte
.dest_id
= IRTE_DEST(dest
);
2598 * atomically update the IRTE with the new destination and vector.
2600 modify_irte(irq
, &irte
);
2603 * After this point, all the interrupts will start arriving
2604 * at the new destination. So, time to cleanup the previous
2605 * vector allocation.
2607 if (cfg
->move_in_progress
) {
2608 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2609 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2610 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2611 cfg
->move_in_progress
= 0;
2614 desc
= irq_to_desc(irq
);
2615 desc
->affinity
= mask
;
2618 #endif /* CONFIG_SMP */
2621 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2622 * which implement the MSI or MSI-X Capability Structure.
2624 static struct irq_chip msi_chip
= {
2626 .unmask
= unmask_msi_irq
,
2627 .mask
= mask_msi_irq
,
2628 .ack
= ack_apic_edge
,
2630 .set_affinity
= set_msi_irq_affinity
,
2632 .retrigger
= ioapic_retrigger_irq
,
2635 #ifdef CONFIG_INTR_REMAP
2636 static struct irq_chip msi_ir_chip
= {
2637 .name
= "IR-PCI-MSI",
2638 .unmask
= unmask_msi_irq
,
2639 .mask
= mask_msi_irq
,
2640 .ack
= ack_x2apic_edge
,
2642 .set_affinity
= ir_set_msi_irq_affinity
,
2644 .retrigger
= ioapic_retrigger_irq
,
2648 * Map the PCI dev to the corresponding remapping hardware unit
2649 * and allocate 'nvec' consecutive interrupt-remapping table entries
2652 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
2654 struct intel_iommu
*iommu
;
2657 iommu
= map_dev_to_ir(dev
);
2660 "Unable to map PCI %s to iommu\n", pci_name(dev
));
2664 index
= alloc_irte(iommu
, irq
, nvec
);
2667 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
2675 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2680 ret
= msi_compose_msg(dev
, irq
, &msg
);
2684 set_irq_msi(irq
, desc
);
2685 write_msi_msg(irq
, &msg
);
2687 #ifdef CONFIG_INTR_REMAP
2688 if (irq_remapped(irq
)) {
2689 struct irq_desc
*desc
= irq_to_desc(irq
);
2691 * irq migration in process context
2693 desc
->status
|= IRQ_MOVE_PCNTXT
;
2694 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
2697 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2702 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2710 #ifdef CONFIG_INTR_REMAP
2711 if (!intr_remapping_enabled
)
2714 ret
= msi_alloc_irte(dev
, irq
, 1);
2719 ret
= setup_msi_irq(dev
, desc
, irq
);
2726 #ifdef CONFIG_INTR_REMAP
2733 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
2735 int irq
, ret
, sub_handle
;
2736 struct msi_desc
*desc
;
2737 #ifdef CONFIG_INTR_REMAP
2738 struct intel_iommu
*iommu
= 0;
2743 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
2747 #ifdef CONFIG_INTR_REMAP
2748 if (!intr_remapping_enabled
)
2753 * allocate the consecutive block of IRTE's
2756 index
= msi_alloc_irte(dev
, irq
, nvec
);
2762 iommu
= map_dev_to_ir(dev
);
2768 * setup the mapping between the irq and the IRTE
2769 * base index, the sub_handle pointing to the
2770 * appropriate interrupt remap table entry.
2772 set_irte_irq(irq
, iommu
, index
, sub_handle
);
2776 ret
= setup_msi_irq(dev
, desc
, irq
);
2788 void arch_teardown_msi_irq(unsigned int irq
)
2795 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2797 struct irq_cfg
*cfg
;
2801 struct irq_desc
*desc
;
2803 cpus_and(tmp
, mask
, cpu_online_map
);
2804 if (cpus_empty(tmp
))
2807 if (assign_irq_vector(irq
, mask
))
2811 cpus_and(tmp
, cfg
->domain
, mask
);
2812 dest
= cpu_mask_to_apicid(tmp
);
2814 dmar_msi_read(irq
, &msg
);
2816 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2817 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2818 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2819 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2821 dmar_msi_write(irq
, &msg
);
2822 desc
= irq_to_desc(irq
);
2823 desc
->affinity
= mask
;
2825 #endif /* CONFIG_SMP */
2827 struct irq_chip dmar_msi_type
= {
2829 .unmask
= dmar_msi_unmask
,
2830 .mask
= dmar_msi_mask
,
2831 .ack
= ack_apic_edge
,
2833 .set_affinity
= dmar_msi_set_affinity
,
2835 .retrigger
= ioapic_retrigger_irq
,
2838 int arch_setup_dmar_msi(unsigned int irq
)
2843 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2846 dmar_msi_write(irq
, &msg
);
2847 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2853 #endif /* CONFIG_PCI_MSI */
2855 * Hypertransport interrupt support
2857 #ifdef CONFIG_HT_IRQ
2861 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2863 struct ht_irq_msg msg
;
2864 fetch_ht_irq_msg(irq
, &msg
);
2866 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2867 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2869 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2870 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2872 write_ht_irq_msg(irq
, &msg
);
2875 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2877 struct irq_cfg
*cfg
;
2880 struct irq_desc
*desc
;
2882 cpus_and(tmp
, mask
, cpu_online_map
);
2883 if (cpus_empty(tmp
))
2886 if (assign_irq_vector(irq
, mask
))
2890 cpus_and(tmp
, cfg
->domain
, mask
);
2891 dest
= cpu_mask_to_apicid(tmp
);
2893 target_ht_irq(irq
, dest
, cfg
->vector
);
2894 desc
= irq_to_desc(irq
);
2895 desc
->affinity
= mask
;
2899 static struct irq_chip ht_irq_chip
= {
2901 .mask
= mask_ht_irq
,
2902 .unmask
= unmask_ht_irq
,
2903 .ack
= ack_apic_edge
,
2905 .set_affinity
= set_ht_irq_affinity
,
2907 .retrigger
= ioapic_retrigger_irq
,
2910 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2912 struct irq_cfg
*cfg
;
2917 err
= assign_irq_vector(irq
, tmp
);
2919 struct ht_irq_msg msg
;
2923 cpus_and(tmp
, cfg
->domain
, tmp
);
2924 dest
= cpu_mask_to_apicid(tmp
);
2926 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2930 HT_IRQ_LOW_DEST_ID(dest
) |
2931 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
2932 ((INT_DEST_MODE
== 0) ?
2933 HT_IRQ_LOW_DM_PHYSICAL
:
2934 HT_IRQ_LOW_DM_LOGICAL
) |
2935 HT_IRQ_LOW_RQEOI_EDGE
|
2936 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2937 HT_IRQ_LOW_MT_FIXED
:
2938 HT_IRQ_LOW_MT_ARBITRATED
) |
2939 HT_IRQ_LOW_IRQ_MASKED
;
2941 write_ht_irq_msg(irq
, &msg
);
2943 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2944 handle_edge_irq
, "edge");
2948 #endif /* CONFIG_HT_IRQ */
2950 /* --------------------------------------------------------------------------
2951 ACPI-based IOAPIC Configuration
2952 -------------------------------------------------------------------------- */
2956 #define IO_APIC_MAX_ID 0xFE
2958 int __init
io_apic_get_redir_entries (int ioapic
)
2960 union IO_APIC_reg_01 reg_01
;
2961 unsigned long flags
;
2963 spin_lock_irqsave(&ioapic_lock
, flags
);
2964 reg_01
.raw
= io_apic_read(ioapic
, 1);
2965 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2967 return reg_01
.bits
.entries
;
2971 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
2973 if (!IO_APIC_IRQ(irq
)) {
2974 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2980 * IRQs < 16 are already in the irq_2_pin[] map
2983 add_pin_to_irq(irq
, ioapic
, pin
);
2985 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
2991 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2995 if (skip_ioapic_setup
)
2998 for (i
= 0; i
< mp_irq_entries
; i
++)
2999 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3000 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3002 if (i
>= mp_irq_entries
)
3005 *trigger
= irq_trigger(i
);
3006 *polarity
= irq_polarity(i
);
3010 #endif /* CONFIG_ACPI */
3013 * This function currently is only a helper for the i386 smp boot process where
3014 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3015 * so mask in all cases should simply be TARGET_CPUS
3018 void __init
setup_ioapic_dest(void)
3020 int pin
, ioapic
, irq
, irq_entry
;
3021 struct irq_cfg
*cfg
;
3023 if (skip_ioapic_setup
== 1)
3026 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3027 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3028 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3029 if (irq_entry
== -1)
3031 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3033 /* setup_IO_APIC_irqs could fail to get vector for some device
3034 * when you have too many devices, because at that time only boot
3039 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3040 irq_trigger(irq_entry
),
3041 irq_polarity(irq_entry
));
3042 #ifdef CONFIG_INTR_REMAP
3043 else if (intr_remapping_enabled
)
3044 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3047 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3054 #define IOAPIC_RESOURCE_NAME_SIZE 11
3056 static struct resource
*ioapic_resources
;
3058 static struct resource
* __init
ioapic_setup_resources(void)
3061 struct resource
*res
;
3065 if (nr_ioapics
<= 0)
3068 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3071 mem
= alloc_bootmem(n
);
3075 mem
+= sizeof(struct resource
) * nr_ioapics
;
3077 for (i
= 0; i
< nr_ioapics
; i
++) {
3079 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3080 sprintf(mem
, "IOAPIC %u", i
);
3081 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3085 ioapic_resources
= res
;
3090 void __init
ioapic_init_mappings(void)
3092 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3093 struct resource
*ioapic_res
;
3096 ioapic_res
= ioapic_setup_resources();
3097 for (i
= 0; i
< nr_ioapics
; i
++) {
3098 if (smp_found_config
) {
3099 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3101 ioapic_phys
= (unsigned long)
3102 alloc_bootmem_pages(PAGE_SIZE
);
3103 ioapic_phys
= __pa(ioapic_phys
);
3105 set_fixmap_nocache(idx
, ioapic_phys
);
3106 apic_printk(APIC_VERBOSE
,
3107 "mapped IOAPIC to %016lx (%016lx)\n",
3108 __fix_to_virt(idx
), ioapic_phys
);
3111 if (ioapic_res
!= NULL
) {
3112 ioapic_res
->start
= ioapic_phys
;
3113 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3119 static int __init
ioapic_insert_resources(void)
3122 struct resource
*r
= ioapic_resources
;
3126 "IO APIC resources could be not be allocated.\n");
3130 for (i
= 0; i
< nr_ioapics
; i
++) {
3131 insert_resource(&iomem_resource
, r
);
3138 /* Insert the IO APIC resources after PCI initialization has occured to handle
3139 * IO APICS that are mapped in on a BAR in PCI space. */
3140 late_initcall(ioapic_insert_resources
);