2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
46 #include <asm/proto.h>
49 #include <asm/i8259.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
56 #include <mach_apic.h>
58 #define __apicdebuginit(type) static type __init
65 struct irq_pin_list
*irq_2_pin
;
68 unsigned move_cleanup_count
;
70 u8 move_in_progress
: 1;
73 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
74 static struct irq_cfg irq_cfg_legacy
[] __initdata
= {
75 [0] = { .irq
= 0, .domain
= CPU_MASK_ALL
, .vector
= IRQ0_VECTOR
, },
76 [1] = { .irq
= 1, .domain
= CPU_MASK_ALL
, .vector
= IRQ1_VECTOR
, },
77 [2] = { .irq
= 2, .domain
= CPU_MASK_ALL
, .vector
= IRQ2_VECTOR
, },
78 [3] = { .irq
= 3, .domain
= CPU_MASK_ALL
, .vector
= IRQ3_VECTOR
, },
79 [4] = { .irq
= 4, .domain
= CPU_MASK_ALL
, .vector
= IRQ4_VECTOR
, },
80 [5] = { .irq
= 5, .domain
= CPU_MASK_ALL
, .vector
= IRQ5_VECTOR
, },
81 [6] = { .irq
= 6, .domain
= CPU_MASK_ALL
, .vector
= IRQ6_VECTOR
, },
82 [7] = { .irq
= 7, .domain
= CPU_MASK_ALL
, .vector
= IRQ7_VECTOR
, },
83 [8] = { .irq
= 8, .domain
= CPU_MASK_ALL
, .vector
= IRQ8_VECTOR
, },
84 [9] = { .irq
= 9, .domain
= CPU_MASK_ALL
, .vector
= IRQ9_VECTOR
, },
85 [10] = { .irq
= 10, .domain
= CPU_MASK_ALL
, .vector
= IRQ10_VECTOR
, },
86 [11] = { .irq
= 11, .domain
= CPU_MASK_ALL
, .vector
= IRQ11_VECTOR
, },
87 [12] = { .irq
= 12, .domain
= CPU_MASK_ALL
, .vector
= IRQ12_VECTOR
, },
88 [13] = { .irq
= 13, .domain
= CPU_MASK_ALL
, .vector
= IRQ13_VECTOR
, },
89 [14] = { .irq
= 14, .domain
= CPU_MASK_ALL
, .vector
= IRQ14_VECTOR
, },
90 [15] = { .irq
= 15, .domain
= CPU_MASK_ALL
, .vector
= IRQ15_VECTOR
, },
93 static struct irq_cfg irq_cfg_init
= { .irq
= -1U, };
94 /* need to be biger than size of irq_cfg_legacy */
95 static int nr_irq_cfg
= 32;
97 static int __init
parse_nr_irq_cfg(char *arg
)
100 nr_irq_cfg
= simple_strtoul(arg
, NULL
, 0);
107 early_param("nr_irq_cfg", parse_nr_irq_cfg
);
109 static void init_one_irq_cfg(struct irq_cfg
*cfg
)
111 memcpy(cfg
, &irq_cfg_init
, sizeof(struct irq_cfg
));
114 static struct irq_cfg
*irq_cfgx
;
115 static struct irq_cfg
*irq_cfgx_free
;
116 static void __init
init_work(void *data
)
118 struct dyn_array
*da
= data
;
125 memcpy(cfg
, irq_cfg_legacy
, sizeof(irq_cfg_legacy
));
127 legacy_count
= sizeof(irq_cfg_legacy
)/sizeof(irq_cfg_legacy
[0]);
128 for (i
= legacy_count
; i
< *da
->nr
; i
++)
129 init_one_irq_cfg(&cfg
[i
]);
131 for (i
= 1; i
< *da
->nr
; i
++)
132 cfg
[i
-1].next
= &cfg
[i
];
134 irq_cfgx_free
= &irq_cfgx
[legacy_count
];
135 irq_cfgx
[legacy_count
- 1].next
= NULL
;
138 #define for_each_irq_cfg(cfg) \
139 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
141 DEFINE_DYN_ARRAY(irq_cfgx
, sizeof(struct irq_cfg
), nr_irq_cfg
, PAGE_SIZE
, init_work
);
143 static struct irq_cfg
*irq_cfg(unsigned int irq
)
158 static struct irq_cfg
*irq_cfg_alloc(unsigned int irq
)
160 struct irq_cfg
*cfg
, *cfg_pri
;
164 cfg_pri
= cfg
= irq_cfgx
;
174 if (!irq_cfgx_free
) {
176 unsigned long total_bytes
;
178 * we run out of pre-allocate ones, allocate more
180 printk(KERN_DEBUG
"try to get more irq_cfg %d\n", nr_irq_cfg
);
182 total_bytes
= sizeof(struct irq_cfg
) * nr_irq_cfg
;
184 cfg
= kzalloc(total_bytes
, GFP_ATOMIC
);
186 cfg
= __alloc_bootmem_nopanic(total_bytes
, PAGE_SIZE
, 0);
189 panic("please boot with nr_irq_cfg= %d\n", count
* 2);
192 printk(KERN_DEBUG
"irq_irq ==> [%#lx - %#lx]\n", phys
, phys
+ total_bytes
);
194 for (i
= 0; i
< nr_irq_cfg
; i
++)
195 init_one_irq_cfg(&cfg
[i
]);
197 for (i
= 1; i
< nr_irq_cfg
; i
++)
198 cfg
[i
-1].next
= &cfg
[i
];
204 irq_cfgx_free
= irq_cfgx_free
->next
;
211 printk(KERN_DEBUG
"found new irq_cfg for irq %d\n", cfg
->irq
);
212 #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
214 /* dump the results */
217 unsigned long bytes
= sizeof(struct irq_cfg
);
219 printk(KERN_DEBUG
"=========================== %d\n", irq
);
220 printk(KERN_DEBUG
"irq_cfg dump after get that for %d\n", irq
);
221 for_each_irq_cfg(cfg
) {
223 printk(KERN_DEBUG
"irq_cfg %d ==> [%#lx - %#lx]\n", cfg
->irq
, phys
, phys
+ bytes
);
225 printk(KERN_DEBUG
"===========================\n");
231 static int assign_irq_vector(int irq
, cpumask_t mask
);
233 int first_system_vector
= 0xfe;
235 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
237 int sis_apic_bug
; /* not actually supported, dummy for compile */
239 static int no_timer_check
;
241 static int disable_timer_pin_1 __initdata
;
243 int timer_through_8259 __initdata
;
245 /* Where if anywhere is the i8259 connect in external int mode */
246 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
248 static DEFINE_SPINLOCK(ioapic_lock
);
249 static DEFINE_SPINLOCK(vector_lock
);
252 * # of IRQ routing registers
254 int nr_ioapic_registers
[MAX_IO_APICS
];
256 /* I/O APIC RTE contents at the OS boot up */
257 struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
259 /* I/O APIC entries */
260 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
263 /* MP IRQ source entries */
264 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
266 /* # of MP IRQ source entries */
269 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
272 * Rough estimation of how many shared IRQs there are, can
273 * be changed anytime.
279 * This is performance-critical, we want to do it O(1)
281 * the indexing order of this array favors 1:1 mappings
282 * between pins and IRQs.
285 struct irq_pin_list
{
287 struct irq_pin_list
*next
;
290 static struct irq_pin_list
*irq_2_pin_head
;
291 /* fill one page ? */
292 static int nr_irq_2_pin
= 0x100;
293 static struct irq_pin_list
*irq_2_pin_ptr
;
294 static void __init
irq_2_pin_init_work(void *data
)
296 struct dyn_array
*da
= data
;
297 struct irq_pin_list
*pin
;
302 for (i
= 1; i
< *da
->nr
; i
++)
303 pin
[i
-1].next
= &pin
[i
];
305 irq_2_pin_ptr
= &pin
[0];
307 DEFINE_DYN_ARRAY(irq_2_pin_head
, sizeof(struct irq_pin_list
), nr_irq_2_pin
, PAGE_SIZE
, irq_2_pin_init_work
);
309 static struct irq_pin_list
*get_one_free_irq_2_pin(void)
311 struct irq_pin_list
*pin
;
317 irq_2_pin_ptr
= pin
->next
;
323 * we run out of pre-allocate ones, allocate more
325 printk(KERN_DEBUG
"try to get more irq_2_pin %d\n", nr_irq_2_pin
);
328 pin
= kzalloc(sizeof(struct irq_pin_list
)*nr_irq_2_pin
,
331 pin
= __alloc_bootmem_nopanic(sizeof(struct irq_pin_list
) *
332 nr_irq_2_pin
, PAGE_SIZE
, 0);
335 panic("can not get more irq_2_pin\n");
337 for (i
= 1; i
< nr_irq_2_pin
; i
++)
338 pin
[i
-1].next
= &pin
[i
];
340 irq_2_pin_ptr
= pin
->next
;
348 unsigned int unused
[3];
352 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
354 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
355 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
358 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
360 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
361 writel(reg
, &io_apic
->index
);
362 return readl(&io_apic
->data
);
365 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
367 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
368 writel(reg
, &io_apic
->index
);
369 writel(value
, &io_apic
->data
);
373 * Re-write a value: to be used for read-modify-write
374 * cycles where the read already set up the index register.
376 static inline void io_apic_modify(unsigned int apic
, unsigned int value
)
378 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
379 writel(value
, &io_apic
->data
);
382 static bool io_apic_level_ack_pending(unsigned int irq
)
384 struct irq_pin_list
*entry
;
386 struct irq_cfg
*cfg
= irq_cfg(irq
);
388 spin_lock_irqsave(&ioapic_lock
, flags
);
389 entry
= cfg
->irq_2_pin
;
397 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
398 /* Is the remote IRR bit set? */
399 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
400 spin_unlock_irqrestore(&ioapic_lock
, flags
);
407 spin_unlock_irqrestore(&ioapic_lock
, flags
);
413 * Synchronize the IO-APIC and the CPU by doing
414 * a dummy read from the IO-APIC
416 static inline void io_apic_sync(unsigned int apic
)
418 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
419 readl(&io_apic
->data
);
422 #define __DO_ACTION(R, ACTION, FINAL) \
426 struct irq_cfg *cfg; \
427 struct irq_pin_list *entry; \
429 cfg = irq_cfg(irq); \
430 entry = cfg->irq_2_pin; \
436 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
438 io_apic_modify(entry->apic, reg); \
442 entry = entry->next; \
447 struct { u32 w1
, w2
; };
448 struct IO_APIC_route_entry entry
;
451 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
453 union entry_union eu
;
455 spin_lock_irqsave(&ioapic_lock
, flags
);
456 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
457 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
458 spin_unlock_irqrestore(&ioapic_lock
, flags
);
463 * When we write a new IO APIC routing entry, we need to write the high
464 * word first! If the mask bit in the low word is clear, we will enable
465 * the interrupt, and we need to make sure the entry is fully populated
466 * before that happens.
469 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
471 union entry_union eu
;
473 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
474 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
477 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
480 spin_lock_irqsave(&ioapic_lock
, flags
);
481 __ioapic_write_entry(apic
, pin
, e
);
482 spin_unlock_irqrestore(&ioapic_lock
, flags
);
486 * When we mask an IO APIC routing entry, we need to write the low
487 * word first, in order to set the mask bit before we change the
490 static void ioapic_mask_entry(int apic
, int pin
)
493 union entry_union eu
= { .entry
.mask
= 1 };
495 spin_lock_irqsave(&ioapic_lock
, flags
);
496 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
497 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
498 spin_unlock_irqrestore(&ioapic_lock
, flags
);
502 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
506 struct irq_pin_list
*entry
;
509 entry
= cfg
->irq_2_pin
;
519 * With interrupt-remapping, destination information comes
520 * from interrupt-remapping table entry.
522 if (!irq_remapped(irq
))
523 io_apic_write(apic
, 0x11 + pin
*2, dest
);
524 reg
= io_apic_read(apic
, 0x10 + pin
*2);
525 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
527 io_apic_modify(apic
, reg
);
534 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
536 struct irq_cfg
*cfg
= irq_cfg(irq
);
540 struct irq_desc
*desc
;
542 cpus_and(tmp
, mask
, cpu_online_map
);
546 if (assign_irq_vector(irq
, mask
))
549 cpus_and(tmp
, cfg
->domain
, mask
);
550 dest
= cpu_mask_to_apicid(tmp
);
553 * Only the high 8 bits are valid.
555 dest
= SET_APIC_LOGICAL_ID(dest
);
557 desc
= irq_to_desc(irq
);
558 spin_lock_irqsave(&ioapic_lock
, flags
);
559 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
560 desc
->affinity
= mask
;
561 spin_unlock_irqrestore(&ioapic_lock
, flags
);
566 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
567 * shared ISA-space IRQs, so we have to support them. We are super
568 * fast in the common case, and fast for shared ISA-space IRQs.
570 int first_free_entry
;
571 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
574 struct irq_pin_list
*entry
;
576 /* first time to refer irq_cfg, so with new */
577 cfg
= irq_cfg_alloc(irq
);
578 entry
= cfg
->irq_2_pin
;
580 entry
= get_one_free_irq_2_pin();
581 cfg
->irq_2_pin
= entry
;
584 printk(KERN_DEBUG
" 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
588 while (entry
->next
) {
589 /* not again, please */
590 if (entry
->apic
== apic
&& entry
->pin
== pin
)
596 entry
->next
= get_one_free_irq_2_pin();
600 printk(KERN_DEBUG
" x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq
, apic
, pin
);
604 * Reroute an IRQ to a different pin.
606 static void __init
replace_pin_at_irq(unsigned int irq
,
607 int oldapic
, int oldpin
,
608 int newapic
, int newpin
)
610 struct irq_cfg
*cfg
= irq_cfg(irq
);
611 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
615 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
616 entry
->apic
= newapic
;
619 /* every one is different, right? */
625 /* why? call replace before add? */
627 add_pin_to_irq(irq
, newapic
, newpin
);
631 #define DO_ACTION(name,R,ACTION, FINAL) \
633 static void name##_IO_APIC_irq (unsigned int irq) \
634 __DO_ACTION(R, ACTION, FINAL)
637 DO_ACTION(__mask
, 0, |= IO_APIC_REDIR_MASKED
, io_apic_sync(entry
->apic
))
640 DO_ACTION(__unmask
, 0, &= ~IO_APIC_REDIR_MASKED
, )
642 static void mask_IO_APIC_irq (unsigned int irq
)
646 spin_lock_irqsave(&ioapic_lock
, flags
);
647 __mask_IO_APIC_irq(irq
);
648 spin_unlock_irqrestore(&ioapic_lock
, flags
);
651 static void unmask_IO_APIC_irq (unsigned int irq
)
655 spin_lock_irqsave(&ioapic_lock
, flags
);
656 __unmask_IO_APIC_irq(irq
);
657 spin_unlock_irqrestore(&ioapic_lock
, flags
);
660 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
662 struct IO_APIC_route_entry entry
;
664 /* Check delivery_mode to be sure we're not clearing an SMI pin */
665 entry
= ioapic_read_entry(apic
, pin
);
666 if (entry
.delivery_mode
== dest_SMI
)
669 * Disable it in the IO-APIC irq-routing table:
671 ioapic_mask_entry(apic
, pin
);
674 static void clear_IO_APIC (void)
678 for (apic
= 0; apic
< nr_ioapics
; apic
++)
679 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
680 clear_IO_APIC_pin(apic
, pin
);
684 * Saves and masks all the unmasked IO-APIC RTE's
686 int save_mask_IO_APIC_setup(void)
688 union IO_APIC_reg_01 reg_01
;
693 * The number of IO-APIC IRQ registers (== #pins):
695 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
696 spin_lock_irqsave(&ioapic_lock
, flags
);
697 reg_01
.raw
= io_apic_read(apic
, 1);
698 spin_unlock_irqrestore(&ioapic_lock
, flags
);
699 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
702 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
703 early_ioapic_entries
[apic
] =
704 kzalloc(sizeof(struct IO_APIC_route_entry
) *
705 nr_ioapic_registers
[apic
], GFP_KERNEL
);
706 if (!early_ioapic_entries
[apic
])
710 for (apic
= 0; apic
< nr_ioapics
; apic
++)
711 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
712 struct IO_APIC_route_entry entry
;
714 entry
= early_ioapic_entries
[apic
][pin
] =
715 ioapic_read_entry(apic
, pin
);
718 ioapic_write_entry(apic
, pin
, entry
);
724 void restore_IO_APIC_setup(void)
728 for (apic
= 0; apic
< nr_ioapics
; apic
++)
729 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
730 ioapic_write_entry(apic
, pin
,
731 early_ioapic_entries
[apic
][pin
]);
734 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
737 * for now plain restore of previous settings.
738 * TBD: In the case of OS enabling interrupt-remapping,
739 * IO-APIC RTE's need to be setup to point to interrupt-remapping
740 * table entries. for now, do a plain restore, and wait for
741 * the setup_IO_APIC_irqs() to do proper initialization.
743 restore_IO_APIC_setup();
746 int skip_ioapic_setup
;
749 static int __init
parse_noapic(char *str
)
751 disable_ioapic_setup();
754 early_param("noapic", parse_noapic
);
756 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
757 static int __init
disable_timer_pin_setup(char *arg
)
759 disable_timer_pin_1
= 1;
762 __setup("disable_timer_pin_1", disable_timer_pin_setup
);
766 * Find the IRQ entry number of a certain pin.
768 static int find_irq_entry(int apic
, int pin
, int type
)
772 for (i
= 0; i
< mp_irq_entries
; i
++)
773 if (mp_irqs
[i
].mp_irqtype
== type
&&
774 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
775 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
776 mp_irqs
[i
].mp_dstirq
== pin
)
783 * Find the pin to which IRQ[irq] (ISA) is connected
785 static int __init
find_isa_irq_pin(int irq
, int type
)
789 for (i
= 0; i
< mp_irq_entries
; i
++) {
790 int lbus
= mp_irqs
[i
].mp_srcbus
;
792 if (test_bit(lbus
, mp_bus_not_pci
) &&
793 (mp_irqs
[i
].mp_irqtype
== type
) &&
794 (mp_irqs
[i
].mp_srcbusirq
== irq
))
796 return mp_irqs
[i
].mp_dstirq
;
801 static int __init
find_isa_irq_apic(int irq
, int type
)
805 for (i
= 0; i
< mp_irq_entries
; i
++) {
806 int lbus
= mp_irqs
[i
].mp_srcbus
;
808 if (test_bit(lbus
, mp_bus_not_pci
) &&
809 (mp_irqs
[i
].mp_irqtype
== type
) &&
810 (mp_irqs
[i
].mp_srcbusirq
== irq
))
813 if (i
< mp_irq_entries
) {
815 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
816 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
825 * Find a specific PCI IRQ entry.
826 * Not an __init, possibly needed by modules
828 static int pin_2_irq(int idx
, int apic
, int pin
);
830 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
832 int apic
, i
, best_guess
= -1;
834 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
836 if (test_bit(bus
, mp_bus_not_pci
)) {
837 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
840 for (i
= 0; i
< mp_irq_entries
; i
++) {
841 int lbus
= mp_irqs
[i
].mp_srcbus
;
843 for (apic
= 0; apic
< nr_ioapics
; apic
++)
844 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
845 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
848 if (!test_bit(lbus
, mp_bus_not_pci
) &&
849 !mp_irqs
[i
].mp_irqtype
&&
851 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
852 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
854 if (!(apic
|| IO_APIC_IRQ(irq
)))
857 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
860 * Use the first all-but-pin matching entry as a
861 * best-guess fuzzy result for broken mptables.
870 /* ISA interrupts are always polarity zero edge triggered,
871 * when listed as conforming in the MP table. */
873 #define default_ISA_trigger(idx) (0)
874 #define default_ISA_polarity(idx) (0)
876 /* PCI interrupts are always polarity one level triggered,
877 * when listed as conforming in the MP table. */
879 #define default_PCI_trigger(idx) (1)
880 #define default_PCI_polarity(idx) (1)
882 static int MPBIOS_polarity(int idx
)
884 int bus
= mp_irqs
[idx
].mp_srcbus
;
888 * Determine IRQ line polarity (high active or low active):
890 switch (mp_irqs
[idx
].mp_irqflag
& 3)
892 case 0: /* conforms, ie. bus-type dependent polarity */
893 if (test_bit(bus
, mp_bus_not_pci
))
894 polarity
= default_ISA_polarity(idx
);
896 polarity
= default_PCI_polarity(idx
);
898 case 1: /* high active */
903 case 2: /* reserved */
905 printk(KERN_WARNING
"broken BIOS!!\n");
909 case 3: /* low active */
914 default: /* invalid */
916 printk(KERN_WARNING
"broken BIOS!!\n");
924 static int MPBIOS_trigger(int idx
)
926 int bus
= mp_irqs
[idx
].mp_srcbus
;
930 * Determine IRQ trigger mode (edge or level sensitive):
932 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
934 case 0: /* conforms, ie. bus-type dependent */
935 if (test_bit(bus
, mp_bus_not_pci
))
936 trigger
= default_ISA_trigger(idx
);
938 trigger
= default_PCI_trigger(idx
);
945 case 2: /* reserved */
947 printk(KERN_WARNING
"broken BIOS!!\n");
956 default: /* invalid */
958 printk(KERN_WARNING
"broken BIOS!!\n");
966 static inline int irq_polarity(int idx
)
968 return MPBIOS_polarity(idx
);
971 static inline int irq_trigger(int idx
)
973 return MPBIOS_trigger(idx
);
976 static int pin_2_irq(int idx
, int apic
, int pin
)
979 int bus
= mp_irqs
[idx
].mp_srcbus
;
982 * Debugging check, we are in big trouble if this message pops up!
984 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
985 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
987 if (test_bit(bus
, mp_bus_not_pci
)) {
988 irq
= mp_irqs
[idx
].mp_srcbusirq
;
991 * PCI IRQs are mapped in order
995 irq
+= nr_ioapic_registers
[i
++];
1001 void lock_vector_lock(void)
1003 /* Used to the online set of cpus does not change
1004 * during assign_irq_vector.
1006 spin_lock(&vector_lock
);
1009 void unlock_vector_lock(void)
1011 spin_unlock(&vector_lock
);
1014 static int __assign_irq_vector(int irq
, cpumask_t mask
)
1017 * NOTE! The local APIC isn't very good at handling
1018 * multiple interrupts at the same interrupt level.
1019 * As the interrupt level is determined by taking the
1020 * vector number and shifting that right by 4, we
1021 * want to spread these out a bit so that they don't
1022 * all fall in the same interrupt level.
1024 * Also, we've got to be careful not to trash gate
1025 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1027 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1028 unsigned int old_vector
;
1030 struct irq_cfg
*cfg
;
1034 /* Only try and allocate irqs on cpus that are present */
1035 cpus_and(mask
, mask
, cpu_online_map
);
1037 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1040 old_vector
= cfg
->vector
;
1043 cpus_and(tmp
, cfg
->domain
, mask
);
1044 if (!cpus_empty(tmp
))
1048 for_each_cpu_mask_nr(cpu
, mask
) {
1049 cpumask_t domain
, new_mask
;
1053 domain
= vector_allocation_domain(cpu
);
1054 cpus_and(new_mask
, domain
, cpu_online_map
);
1056 vector
= current_vector
;
1057 offset
= current_offset
;
1060 if (vector
>= first_system_vector
) {
1061 /* If we run out of vectors on large boxen, must share them. */
1062 offset
= (offset
+ 1) % 8;
1063 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1065 if (unlikely(current_vector
== vector
))
1067 if (vector
== IA32_SYSCALL_VECTOR
)
1069 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1070 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1073 current_vector
= vector
;
1074 current_offset
= offset
;
1076 cfg
->move_in_progress
= 1;
1077 cfg
->old_domain
= cfg
->domain
;
1079 for_each_cpu_mask_nr(new_cpu
, new_mask
)
1080 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1081 cfg
->vector
= vector
;
1082 cfg
->domain
= domain
;
1088 static int assign_irq_vector(int irq
, cpumask_t mask
)
1091 unsigned long flags
;
1093 spin_lock_irqsave(&vector_lock
, flags
);
1094 err
= __assign_irq_vector(irq
, mask
);
1095 spin_unlock_irqrestore(&vector_lock
, flags
);
1099 static void __clear_irq_vector(int irq
)
1101 struct irq_cfg
*cfg
;
1106 BUG_ON(!cfg
->vector
);
1108 vector
= cfg
->vector
;
1109 cpus_and(mask
, cfg
->domain
, cpu_online_map
);
1110 for_each_cpu_mask_nr(cpu
, mask
)
1111 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1114 cpus_clear(cfg
->domain
);
1117 void __setup_vector_irq(int cpu
)
1119 /* Initialize vector_irq on a new cpu */
1120 /* This function must be called with vector_lock held */
1122 struct irq_cfg
*cfg
;
1124 /* Mark the inuse vectors */
1125 for_each_irq_cfg(cfg
) {
1126 if (!cpu_isset(cpu
, cfg
->domain
))
1128 vector
= cfg
->vector
;
1130 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1132 /* Mark the free vectors */
1133 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1134 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1139 if (!cpu_isset(cpu
, cfg
->domain
))
1140 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1144 static struct irq_chip ioapic_chip
;
1145 #ifdef CONFIG_INTR_REMAP
1146 static struct irq_chip ir_ioapic_chip
;
1149 static void ioapic_register_intr(int irq
, unsigned long trigger
)
1151 struct irq_desc
*desc
;
1153 /* first time to use this irq_desc */
1155 desc
= irq_to_desc(irq
);
1157 desc
= irq_to_desc_alloc(irq
);
1160 desc
->status
|= IRQ_LEVEL
;
1162 desc
->status
&= ~IRQ_LEVEL
;
1164 #ifdef CONFIG_INTR_REMAP
1165 if (irq_remapped(irq
)) {
1166 desc
->status
|= IRQ_MOVE_PCNTXT
;
1168 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1172 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1173 handle_edge_irq
, "edge");
1178 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1182 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1183 handle_edge_irq
, "edge");
1186 static int setup_ioapic_entry(int apic
, int irq
,
1187 struct IO_APIC_route_entry
*entry
,
1188 unsigned int destination
, int trigger
,
1189 int polarity
, int vector
)
1192 * add it to the IO-APIC irq-routing table:
1194 memset(entry
,0,sizeof(*entry
));
1196 #ifdef CONFIG_INTR_REMAP
1197 if (intr_remapping_enabled
) {
1198 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1200 struct IR_IO_APIC_route_entry
*ir_entry
=
1201 (struct IR_IO_APIC_route_entry
*) entry
;
1205 panic("No mapping iommu for ioapic %d\n", apic
);
1207 index
= alloc_irte(iommu
, irq
, 1);
1209 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1211 memset(&irte
, 0, sizeof(irte
));
1214 irte
.dst_mode
= INT_DEST_MODE
;
1215 irte
.trigger_mode
= trigger
;
1216 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1217 irte
.vector
= vector
;
1218 irte
.dest_id
= IRTE_DEST(destination
);
1220 modify_irte(irq
, &irte
);
1222 ir_entry
->index2
= (index
>> 15) & 0x1;
1224 ir_entry
->format
= 1;
1225 ir_entry
->index
= (index
& 0x7fff);
1229 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1230 entry
->dest_mode
= INT_DEST_MODE
;
1231 entry
->dest
= destination
;
1234 entry
->mask
= 0; /* enable IRQ */
1235 entry
->trigger
= trigger
;
1236 entry
->polarity
= polarity
;
1237 entry
->vector
= vector
;
1239 /* Mask level triggered irqs.
1240 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1247 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
,
1248 int trigger
, int polarity
)
1250 struct irq_cfg
*cfg
;
1251 struct IO_APIC_route_entry entry
;
1254 if (!IO_APIC_IRQ(irq
))
1260 if (assign_irq_vector(irq
, mask
))
1263 cpus_and(mask
, cfg
->domain
, mask
);
1265 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1266 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1267 "IRQ %d Mode:%i Active:%i)\n",
1268 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1269 irq
, trigger
, polarity
);
1272 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1273 cpu_mask_to_apicid(mask
), trigger
, polarity
,
1275 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1276 mp_ioapics
[apic
].mp_apicid
, pin
);
1277 __clear_irq_vector(irq
);
1281 ioapic_register_intr(irq
, trigger
);
1283 disable_8259A_irq(irq
);
1285 ioapic_write_entry(apic
, pin
, entry
);
1288 static void __init
setup_IO_APIC_irqs(void)
1290 int apic
, pin
, idx
, irq
, first_notcon
= 1;
1292 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1294 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1295 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1297 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1300 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1303 apic_printk(APIC_VERBOSE
, ", %d-%d", mp_ioapics
[apic
].mp_apicid
, pin
);
1306 if (!first_notcon
) {
1307 apic_printk(APIC_VERBOSE
, " not connected.\n");
1311 irq
= pin_2_irq(idx
, apic
, pin
);
1312 add_pin_to_irq(irq
, apic
, pin
);
1314 setup_IO_APIC_irq(apic
, pin
, irq
,
1315 irq_trigger(idx
), irq_polarity(idx
));
1320 apic_printk(APIC_VERBOSE
, " not connected.\n");
1324 * Set up the timer pin, possibly with the 8259A-master behind.
1326 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1329 struct IO_APIC_route_entry entry
;
1331 if (intr_remapping_enabled
)
1334 memset(&entry
, 0, sizeof(entry
));
1337 * We use logical delivery to get the timer IRQ
1340 entry
.dest_mode
= INT_DEST_MODE
;
1341 entry
.mask
= 1; /* mask IRQ now */
1342 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1343 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1346 entry
.vector
= vector
;
1349 * The timer IRQ doesn't have to know that behind the
1350 * scene we may have a 8259A-master in AEOI mode ...
1352 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1355 * Add it to the IO-APIC irq-routing table:
1357 ioapic_write_entry(apic
, pin
, entry
);
1361 __apicdebuginit(void) print_IO_APIC(void)
1364 union IO_APIC_reg_00 reg_00
;
1365 union IO_APIC_reg_01 reg_01
;
1366 union IO_APIC_reg_02 reg_02
;
1367 unsigned long flags
;
1368 struct irq_cfg
*cfg
;
1370 if (apic_verbosity
== APIC_QUIET
)
1373 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1374 for (i
= 0; i
< nr_ioapics
; i
++)
1375 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1376 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1379 * We are a bit conservative about what we expect. We have to
1380 * know about every hardware change ASAP.
1382 printk(KERN_INFO
"testing the IO APIC.......................\n");
1384 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1386 spin_lock_irqsave(&ioapic_lock
, flags
);
1387 reg_00
.raw
= io_apic_read(apic
, 0);
1388 reg_01
.raw
= io_apic_read(apic
, 1);
1389 if (reg_01
.bits
.version
>= 0x10)
1390 reg_02
.raw
= io_apic_read(apic
, 2);
1391 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1394 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1395 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1396 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1398 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1399 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1401 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1402 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1404 if (reg_01
.bits
.version
>= 0x10) {
1405 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1406 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1409 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1411 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1412 " Stat Dmod Deli Vect: \n");
1414 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1415 struct IO_APIC_route_entry entry
;
1417 entry
= ioapic_read_entry(apic
, i
);
1419 printk(KERN_DEBUG
" %02x %03X ",
1424 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1429 entry
.delivery_status
,
1431 entry
.delivery_mode
,
1436 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1437 for_each_irq_cfg(cfg
) {
1438 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
1441 printk(KERN_DEBUG
"IRQ%d ", cfg
->irq
);
1443 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1446 entry
= entry
->next
;
1451 printk(KERN_INFO
".................................... done.\n");
1456 __apicdebuginit(void) print_APIC_bitfield(int base
)
1461 if (apic_verbosity
== APIC_QUIET
)
1464 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1465 for (i
= 0; i
< 8; i
++) {
1466 v
= apic_read(base
+ i
*0x10);
1467 for (j
= 0; j
< 32; j
++) {
1477 __apicdebuginit(void) print_local_APIC(void *dummy
)
1479 unsigned int v
, ver
, maxlvt
;
1482 if (apic_verbosity
== APIC_QUIET
)
1485 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1486 smp_processor_id(), hard_smp_processor_id());
1487 v
= apic_read(APIC_ID
);
1488 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1489 v
= apic_read(APIC_LVR
);
1490 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1491 ver
= GET_APIC_VERSION(v
);
1492 maxlvt
= lapic_get_maxlvt();
1494 v
= apic_read(APIC_TASKPRI
);
1495 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1497 v
= apic_read(APIC_ARBPRI
);
1498 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1499 v
& APIC_ARBPRI_MASK
);
1500 v
= apic_read(APIC_PROCPRI
);
1501 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1503 v
= apic_read(APIC_EOI
);
1504 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1505 v
= apic_read(APIC_RRR
);
1506 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1507 v
= apic_read(APIC_LDR
);
1508 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1509 v
= apic_read(APIC_DFR
);
1510 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1511 v
= apic_read(APIC_SPIV
);
1512 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1514 printk(KERN_DEBUG
"... APIC ISR field:\n");
1515 print_APIC_bitfield(APIC_ISR
);
1516 printk(KERN_DEBUG
"... APIC TMR field:\n");
1517 print_APIC_bitfield(APIC_TMR
);
1518 printk(KERN_DEBUG
"... APIC IRR field:\n");
1519 print_APIC_bitfield(APIC_IRR
);
1521 v
= apic_read(APIC_ESR
);
1522 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1524 icr
= apic_icr_read();
1525 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1526 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1528 v
= apic_read(APIC_LVTT
);
1529 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1531 if (maxlvt
> 3) { /* PC is LVT#4. */
1532 v
= apic_read(APIC_LVTPC
);
1533 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1535 v
= apic_read(APIC_LVT0
);
1536 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1537 v
= apic_read(APIC_LVT1
);
1538 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1540 if (maxlvt
> 2) { /* ERR is LVT#3. */
1541 v
= apic_read(APIC_LVTERR
);
1542 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1545 v
= apic_read(APIC_TMICT
);
1546 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1547 v
= apic_read(APIC_TMCCT
);
1548 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1549 v
= apic_read(APIC_TDCR
);
1550 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1554 __apicdebuginit(void) print_all_local_APICs(void)
1556 on_each_cpu(print_local_APIC
, NULL
, 1);
1559 __apicdebuginit(void) print_PIC(void)
1562 unsigned long flags
;
1564 if (apic_verbosity
== APIC_QUIET
)
1567 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1569 spin_lock_irqsave(&i8259A_lock
, flags
);
1571 v
= inb(0xa1) << 8 | inb(0x21);
1572 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1574 v
= inb(0xa0) << 8 | inb(0x20);
1575 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1579 v
= inb(0xa0) << 8 | inb(0x20);
1583 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1585 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1587 v
= inb(0x4d1) << 8 | inb(0x4d0);
1588 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1591 __apicdebuginit(int) print_all_ICs(void)
1594 print_all_local_APICs();
1600 fs_initcall(print_all_ICs
);
1603 void __init
enable_IO_APIC(void)
1605 union IO_APIC_reg_01 reg_01
;
1606 int i8259_apic
, i8259_pin
;
1608 unsigned long flags
;
1611 * The number of IO-APIC IRQ registers (== #pins):
1613 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1614 spin_lock_irqsave(&ioapic_lock
, flags
);
1615 reg_01
.raw
= io_apic_read(apic
, 1);
1616 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1617 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1619 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1621 /* See if any of the pins is in ExtINT mode */
1622 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1623 struct IO_APIC_route_entry entry
;
1624 entry
= ioapic_read_entry(apic
, pin
);
1626 /* If the interrupt line is enabled and in ExtInt mode
1627 * I have found the pin where the i8259 is connected.
1629 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1630 ioapic_i8259
.apic
= apic
;
1631 ioapic_i8259
.pin
= pin
;
1637 /* Look to see what if the MP table has reported the ExtINT */
1638 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1639 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1640 /* Trust the MP table if nothing is setup in the hardware */
1641 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1642 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1643 ioapic_i8259
.pin
= i8259_pin
;
1644 ioapic_i8259
.apic
= i8259_apic
;
1646 /* Complain if the MP table and the hardware disagree */
1647 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1648 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1650 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1654 * Do not trust the IO-APIC being empty at bootup
1660 * Not an __init, needed by the reboot code
1662 void disable_IO_APIC(void)
1665 * Clear the IO-APIC before rebooting:
1670 * If the i8259 is routed through an IOAPIC
1671 * Put that IOAPIC in virtual wire mode
1672 * so legacy interrupts can be delivered.
1674 if (ioapic_i8259
.pin
!= -1) {
1675 struct IO_APIC_route_entry entry
;
1677 memset(&entry
, 0, sizeof(entry
));
1678 entry
.mask
= 0; /* Enabled */
1679 entry
.trigger
= 0; /* Edge */
1681 entry
.polarity
= 0; /* High */
1682 entry
.delivery_status
= 0;
1683 entry
.dest_mode
= 0; /* Physical */
1684 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1686 entry
.dest
= read_apic_id();
1689 * Add it to the IO-APIC irq-routing table:
1691 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1694 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1698 * There is a nasty bug in some older SMP boards, their mptable lies
1699 * about the timer IRQ. We do the following to work around the situation:
1701 * - timer IRQ defaults to IO-APIC IRQ
1702 * - if this function detects that timer IRQs are defunct, then we fall
1703 * back to ISA timer IRQs
1705 static int __init
timer_irq_works(void)
1707 unsigned long t1
= jiffies
;
1708 unsigned long flags
;
1710 local_save_flags(flags
);
1712 /* Let ten ticks pass... */
1713 mdelay((10 * 1000) / HZ
);
1714 local_irq_restore(flags
);
1717 * Expect a few ticks at least, to be sure some possible
1718 * glue logic does not lock up after one or two first
1719 * ticks in a non-ExtINT mode. Also the local APIC
1720 * might have cached one ExtINT interrupt. Finally, at
1721 * least one tick may be lost due to delays.
1725 if (time_after(jiffies
, t1
+ 4))
1731 * In the SMP+IOAPIC case it might happen that there are an unspecified
1732 * number of pending IRQ events unhandled. These cases are very rare,
1733 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1734 * better to do it this way as thus we do not have to be aware of
1735 * 'pending' interrupts in the IRQ path, except at this point.
1738 * Edge triggered needs to resend any interrupt
1739 * that was delayed but this is now handled in the device
1744 * Starting up a edge-triggered IO-APIC interrupt is
1745 * nasty - we need to make sure that we get the edge.
1746 * If it is already asserted for some reason, we need
1747 * return 1 to indicate that is was pending.
1749 * This is not complete - we should be able to fake
1750 * an edge even if it isn't on the 8259A...
1753 static unsigned int startup_ioapic_irq(unsigned int irq
)
1755 int was_pending
= 0;
1756 unsigned long flags
;
1758 spin_lock_irqsave(&ioapic_lock
, flags
);
1760 disable_8259A_irq(irq
);
1761 if (i8259A_irq_pending(irq
))
1764 __unmask_IO_APIC_irq(irq
);
1765 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1770 static int ioapic_retrigger_irq(unsigned int irq
)
1772 struct irq_cfg
*cfg
= irq_cfg(irq
);
1773 unsigned long flags
;
1775 spin_lock_irqsave(&vector_lock
, flags
);
1776 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg
->domain
)), cfg
->vector
);
1777 spin_unlock_irqrestore(&vector_lock
, flags
);
1783 * Level and edge triggered IO-APIC interrupts need different handling,
1784 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1785 * handled with the level-triggered descriptor, but that one has slightly
1786 * more overhead. Level-triggered interrupts cannot be handled with the
1787 * edge-triggered handler, without risking IRQ storms and other ugly
1793 #ifdef CONFIG_INTR_REMAP
1794 static void ir_irq_migration(struct work_struct
*work
);
1796 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
1799 * Migrate the IO-APIC irq in the presence of intr-remapping.
1801 * For edge triggered, irq migration is a simple atomic update(of vector
1802 * and cpu destination) of IRTE and flush the hardware cache.
1804 * For level triggered, we need to modify the io-apic RTE aswell with the update
1805 * vector information, along with modifying IRTE with vector and destination.
1806 * So irq migration for level triggered is little bit more complex compared to
1807 * edge triggered migration. But the good news is, we use the same algorithm
1808 * for level triggered migration as we have today, only difference being,
1809 * we now initiate the irq migration from process context instead of the
1810 * interrupt context.
1812 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1813 * suppression) to the IO-APIC, level triggered irq migration will also be
1814 * as simple as edge triggered migration and we can do the irq migration
1815 * with a simple atomic update to IO-APIC RTE.
1817 static void migrate_ioapic_irq(int irq
, cpumask_t mask
)
1819 struct irq_cfg
*cfg
;
1820 struct irq_desc
*desc
;
1821 cpumask_t tmp
, cleanup_mask
;
1823 int modify_ioapic_rte
;
1825 unsigned long flags
;
1827 cpus_and(tmp
, mask
, cpu_online_map
);
1828 if (cpus_empty(tmp
))
1831 if (get_irte(irq
, &irte
))
1834 if (assign_irq_vector(irq
, mask
))
1838 cpus_and(tmp
, cfg
->domain
, mask
);
1839 dest
= cpu_mask_to_apicid(tmp
);
1841 desc
= irq_to_desc(irq
);
1842 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
1843 if (modify_ioapic_rte
) {
1844 spin_lock_irqsave(&ioapic_lock
, flags
);
1845 __target_IO_APIC_irq(irq
, dest
, cfg
->vector
);
1846 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1849 irte
.vector
= cfg
->vector
;
1850 irte
.dest_id
= IRTE_DEST(dest
);
1853 * Modified the IRTE and flushes the Interrupt entry cache.
1855 modify_irte(irq
, &irte
);
1857 if (cfg
->move_in_progress
) {
1858 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1859 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1860 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1861 cfg
->move_in_progress
= 0;
1864 desc
->affinity
= mask
;
1867 static int migrate_irq_remapped_level(int irq
)
1870 struct irq_desc
*desc
= irq_to_desc(irq
);
1872 mask_IO_APIC_irq(irq
);
1874 if (io_apic_level_ack_pending(irq
)) {
1876 * Interrupt in progress. Migrating irq now will change the
1877 * vector information in the IO-APIC RTE and that will confuse
1878 * the EOI broadcast performed by cpu.
1879 * So, delay the irq migration to the next instance.
1881 schedule_delayed_work(&ir_migration_work
, 1);
1885 /* everthing is clear. we have right of way */
1886 migrate_ioapic_irq(irq
, desc
->pending_mask
);
1889 desc
->status
&= ~IRQ_MOVE_PENDING
;
1890 cpus_clear(desc
->pending_mask
);
1893 unmask_IO_APIC_irq(irq
);
1897 static void ir_irq_migration(struct work_struct
*work
)
1900 struct irq_desc
*desc
;
1902 for_each_irq_desc(irq
, desc
) {
1903 if (desc
->status
& IRQ_MOVE_PENDING
) {
1904 unsigned long flags
;
1906 spin_lock_irqsave(&desc
->lock
, flags
);
1907 if (!desc
->chip
->set_affinity
||
1908 !(desc
->status
& IRQ_MOVE_PENDING
)) {
1909 desc
->status
&= ~IRQ_MOVE_PENDING
;
1910 spin_unlock_irqrestore(&desc
->lock
, flags
);
1914 desc
->chip
->set_affinity(irq
, desc
->pending_mask
);
1915 spin_unlock_irqrestore(&desc
->lock
, flags
);
1921 * Migrates the IRQ destination in the process context.
1923 static void set_ir_ioapic_affinity_irq(unsigned int irq
, cpumask_t mask
)
1925 struct irq_desc
*desc
= irq_to_desc(irq
);
1927 if (desc
->status
& IRQ_LEVEL
) {
1928 desc
->status
|= IRQ_MOVE_PENDING
;
1929 desc
->pending_mask
= mask
;
1930 migrate_irq_remapped_level(irq
);
1934 migrate_ioapic_irq(irq
, mask
);
1938 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
1940 unsigned vector
, me
;
1945 me
= smp_processor_id();
1946 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
1948 struct irq_desc
*desc
;
1949 struct irq_cfg
*cfg
;
1950 irq
= __get_cpu_var(vector_irq
)[vector
];
1952 desc
= irq_to_desc(irq
);
1957 spin_lock(&desc
->lock
);
1958 if (!cfg
->move_cleanup_count
)
1961 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
))
1964 __get_cpu_var(vector_irq
)[vector
] = -1;
1965 cfg
->move_cleanup_count
--;
1967 spin_unlock(&desc
->lock
);
1973 static void irq_complete_move(unsigned int irq
)
1975 struct irq_cfg
*cfg
= irq_cfg(irq
);
1976 unsigned vector
, me
;
1978 if (likely(!cfg
->move_in_progress
))
1981 vector
= ~get_irq_regs()->orig_ax
;
1982 me
= smp_processor_id();
1983 if ((vector
== cfg
->vector
) && cpu_isset(me
, cfg
->domain
)) {
1984 cpumask_t cleanup_mask
;
1986 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
1987 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
1988 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
1989 cfg
->move_in_progress
= 0;
1993 static inline void irq_complete_move(unsigned int irq
) {}
1995 #ifdef CONFIG_INTR_REMAP
1996 static void ack_x2apic_level(unsigned int irq
)
2001 static void ack_x2apic_edge(unsigned int irq
)
2007 static void ack_apic_edge(unsigned int irq
)
2009 irq_complete_move(irq
);
2010 move_native_irq(irq
);
2014 static void ack_apic_level(unsigned int irq
)
2016 int do_unmask_irq
= 0;
2018 irq_complete_move(irq
);
2019 #ifdef CONFIG_GENERIC_PENDING_IRQ
2020 /* If we are moving the irq we need to mask it */
2021 if (unlikely(irq_to_desc(irq
)->status
& IRQ_MOVE_PENDING
)) {
2023 mask_IO_APIC_irq(irq
);
2028 * We must acknowledge the irq before we move it or the acknowledge will
2029 * not propagate properly.
2033 /* Now we can move and renable the irq */
2034 if (unlikely(do_unmask_irq
)) {
2035 /* Only migrate the irq if the ack has been received.
2037 * On rare occasions the broadcast level triggered ack gets
2038 * delayed going to ioapics, and if we reprogram the
2039 * vector while Remote IRR is still set the irq will never
2042 * To prevent this scenario we read the Remote IRR bit
2043 * of the ioapic. This has two effects.
2044 * - On any sane system the read of the ioapic will
2045 * flush writes (and acks) going to the ioapic from
2047 * - We get to see if the ACK has actually been delivered.
2049 * Based on failed experiments of reprogramming the
2050 * ioapic entry from outside of irq context starting
2051 * with masking the ioapic entry and then polling until
2052 * Remote IRR was clear before reprogramming the
2053 * ioapic I don't trust the Remote IRR bit to be
2054 * completey accurate.
2056 * However there appears to be no other way to plug
2057 * this race, so if the Remote IRR bit is not
2058 * accurate and is causing problems then it is a hardware bug
2059 * and you can go talk to the chipset vendor about it.
2061 if (!io_apic_level_ack_pending(irq
))
2062 move_masked_irq(irq
);
2063 unmask_IO_APIC_irq(irq
);
2067 static struct irq_chip ioapic_chip __read_mostly
= {
2069 .startup
= startup_ioapic_irq
,
2070 .mask
= mask_IO_APIC_irq
,
2071 .unmask
= unmask_IO_APIC_irq
,
2072 .ack
= ack_apic_edge
,
2073 .eoi
= ack_apic_level
,
2075 .set_affinity
= set_ioapic_affinity_irq
,
2077 .retrigger
= ioapic_retrigger_irq
,
2080 #ifdef CONFIG_INTR_REMAP
2081 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2082 .name
= "IR-IO-APIC",
2083 .startup
= startup_ioapic_irq
,
2084 .mask
= mask_IO_APIC_irq
,
2085 .unmask
= unmask_IO_APIC_irq
,
2086 .ack
= ack_x2apic_edge
,
2087 .eoi
= ack_x2apic_level
,
2089 .set_affinity
= set_ir_ioapic_affinity_irq
,
2091 .retrigger
= ioapic_retrigger_irq
,
2095 static inline void init_IO_APIC_traps(void)
2098 struct irq_desc
*desc
;
2099 struct irq_cfg
*cfg
;
2102 * NOTE! The local APIC isn't very good at handling
2103 * multiple interrupts at the same interrupt level.
2104 * As the interrupt level is determined by taking the
2105 * vector number and shifting that right by 4, we
2106 * want to spread these out a bit so that they don't
2107 * all fall in the same interrupt level.
2109 * Also, we've got to be careful not to trash gate
2110 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2112 for_each_irq_cfg(cfg
) {
2114 if (IO_APIC_IRQ(irq
) && !cfg
->vector
) {
2116 * Hmm.. We don't have an entry for this,
2117 * so default to an old-fashioned 8259
2118 * interrupt if we can..
2121 make_8259A_irq(irq
);
2123 desc
= irq_to_desc(irq
);
2124 /* Strange. Oh, well.. */
2125 desc
->chip
= &no_irq_chip
;
2131 static void unmask_lapic_irq(unsigned int irq
)
2135 v
= apic_read(APIC_LVT0
);
2136 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2139 static void mask_lapic_irq(unsigned int irq
)
2143 v
= apic_read(APIC_LVT0
);
2144 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2147 static void ack_lapic_irq (unsigned int irq
)
2152 static struct irq_chip lapic_chip __read_mostly
= {
2153 .name
= "local-APIC",
2154 .mask
= mask_lapic_irq
,
2155 .unmask
= unmask_lapic_irq
,
2156 .ack
= ack_lapic_irq
,
2159 static void lapic_register_intr(int irq
)
2161 struct irq_desc
*desc
;
2163 desc
= irq_to_desc(irq
);
2164 desc
->status
&= ~IRQ_LEVEL
;
2165 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2169 static void __init
setup_nmi(void)
2172 * Dirty trick to enable the NMI watchdog ...
2173 * We put the 8259A master into AEOI mode and
2174 * unmask on all local APICs LVT0 as NMI.
2176 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2177 * is from Maciej W. Rozycki - so we do not have to EOI from
2178 * the NMI handler or the timer interrupt.
2180 printk(KERN_INFO
"activating NMI Watchdog ...");
2182 enable_NMI_through_LVT0();
2188 * This looks a bit hackish but it's about the only one way of sending
2189 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2190 * not support the ExtINT mode, unfortunately. We need to send these
2191 * cycles as some i82489DX-based boards have glue logic that keeps the
2192 * 8259A interrupt line asserted until INTA. --macro
2194 static inline void __init
unlock_ExtINT_logic(void)
2197 struct IO_APIC_route_entry entry0
, entry1
;
2198 unsigned char save_control
, save_freq_select
;
2200 pin
= find_isa_irq_pin(8, mp_INT
);
2201 apic
= find_isa_irq_apic(8, mp_INT
);
2205 entry0
= ioapic_read_entry(apic
, pin
);
2207 clear_IO_APIC_pin(apic
, pin
);
2209 memset(&entry1
, 0, sizeof(entry1
));
2211 entry1
.dest_mode
= 0; /* physical delivery */
2212 entry1
.mask
= 0; /* unmask IRQ now */
2213 entry1
.dest
= hard_smp_processor_id();
2214 entry1
.delivery_mode
= dest_ExtINT
;
2215 entry1
.polarity
= entry0
.polarity
;
2219 ioapic_write_entry(apic
, pin
, entry1
);
2221 save_control
= CMOS_READ(RTC_CONTROL
);
2222 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2223 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2225 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2230 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2234 CMOS_WRITE(save_control
, RTC_CONTROL
);
2235 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2236 clear_IO_APIC_pin(apic
, pin
);
2238 ioapic_write_entry(apic
, pin
, entry0
);
2242 * This code may look a bit paranoid, but it's supposed to cooperate with
2243 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2244 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2245 * fanatically on his truly buggy board.
2247 * FIXME: really need to revamp this for modern platforms only.
2249 static inline void __init
check_timer(void)
2251 struct irq_cfg
*cfg
= irq_cfg(0);
2252 int apic1
, pin1
, apic2
, pin2
;
2253 unsigned long flags
;
2256 local_irq_save(flags
);
2259 * get/set the timer IRQ vector:
2261 disable_8259A_irq(0);
2262 assign_irq_vector(0, TARGET_CPUS
);
2265 * As IRQ0 is to be enabled in the 8259A, the virtual
2266 * wire has to be disabled in the local APIC.
2268 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2271 pin1
= find_isa_irq_pin(0, mp_INT
);
2272 apic1
= find_isa_irq_apic(0, mp_INT
);
2273 pin2
= ioapic_i8259
.pin
;
2274 apic2
= ioapic_i8259
.apic
;
2276 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2277 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2278 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2281 * Some BIOS writers are clueless and report the ExtINTA
2282 * I/O APIC input from the cascaded 8259A as the timer
2283 * interrupt input. So just in case, if only one pin
2284 * was found above, try it both directly and through the
2288 if (intr_remapping_enabled
)
2289 panic("BIOS bug: timer not connected to IO-APIC");
2293 } else if (pin2
== -1) {
2300 * Ok, does IRQ0 through the IOAPIC work?
2303 add_pin_to_irq(0, apic1
, pin1
);
2304 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2306 unmask_IO_APIC_irq(0);
2307 if (!no_timer_check
&& timer_irq_works()) {
2308 if (nmi_watchdog
== NMI_IO_APIC
) {
2310 enable_8259A_irq(0);
2312 if (disable_timer_pin_1
> 0)
2313 clear_IO_APIC_pin(0, pin1
);
2316 if (intr_remapping_enabled
)
2317 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2318 clear_IO_APIC_pin(apic1
, pin1
);
2320 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2321 "8254 timer not connected to IO-APIC\n");
2323 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2324 "(IRQ0) through the 8259A ...\n");
2325 apic_printk(APIC_QUIET
, KERN_INFO
2326 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2328 * legacy devices should be connected to IO APIC #0
2330 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2331 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2332 unmask_IO_APIC_irq(0);
2333 enable_8259A_irq(0);
2334 if (timer_irq_works()) {
2335 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2336 timer_through_8259
= 1;
2337 if (nmi_watchdog
== NMI_IO_APIC
) {
2338 disable_8259A_irq(0);
2340 enable_8259A_irq(0);
2345 * Cleanup, just in case ...
2347 disable_8259A_irq(0);
2348 clear_IO_APIC_pin(apic2
, pin2
);
2349 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2352 if (nmi_watchdog
== NMI_IO_APIC
) {
2353 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2354 "through the IO-APIC - disabling NMI Watchdog!\n");
2355 nmi_watchdog
= NMI_NONE
;
2358 apic_printk(APIC_QUIET
, KERN_INFO
2359 "...trying to set up timer as Virtual Wire IRQ...\n");
2361 lapic_register_intr(0);
2362 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2363 enable_8259A_irq(0);
2365 if (timer_irq_works()) {
2366 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2369 disable_8259A_irq(0);
2370 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2371 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2373 apic_printk(APIC_QUIET
, KERN_INFO
2374 "...trying to set up timer as ExtINT IRQ...\n");
2378 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2380 unlock_ExtINT_logic();
2382 if (timer_irq_works()) {
2383 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2386 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2387 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2388 "report. Then try booting with the 'noapic' option.\n");
2390 local_irq_restore(flags
);
2393 static int __init
notimercheck(char *s
)
2398 __setup("no_timer_check", notimercheck
);
2401 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2402 * to devices. However there may be an I/O APIC pin available for
2403 * this interrupt regardless. The pin may be left unconnected, but
2404 * typically it will be reused as an ExtINT cascade interrupt for
2405 * the master 8259A. In the MPS case such a pin will normally be
2406 * reported as an ExtINT interrupt in the MP table. With ACPI
2407 * there is no provision for ExtINT interrupts, and in the absence
2408 * of an override it would be treated as an ordinary ISA I/O APIC
2409 * interrupt, that is edge-triggered and unmasked by default. We
2410 * used to do this, but it caused problems on some systems because
2411 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2412 * the same ExtINT cascade interrupt to drive the local APIC of the
2413 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2414 * the I/O APIC in all cases now. No actual device should request
2415 * it anyway. --macro
2417 #define PIC_IRQS (1<<2)
2419 void __init
setup_IO_APIC(void)
2423 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2426 io_apic_irqs
= ~PIC_IRQS
;
2428 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2431 setup_IO_APIC_irqs();
2432 init_IO_APIC_traps();
2436 struct sysfs_ioapic_data
{
2437 struct sys_device dev
;
2438 struct IO_APIC_route_entry entry
[0];
2440 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2442 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2444 struct IO_APIC_route_entry
*entry
;
2445 struct sysfs_ioapic_data
*data
;
2448 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2449 entry
= data
->entry
;
2450 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
2451 *entry
= ioapic_read_entry(dev
->id
, i
);
2456 static int ioapic_resume(struct sys_device
*dev
)
2458 struct IO_APIC_route_entry
*entry
;
2459 struct sysfs_ioapic_data
*data
;
2460 unsigned long flags
;
2461 union IO_APIC_reg_00 reg_00
;
2464 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2465 entry
= data
->entry
;
2467 spin_lock_irqsave(&ioapic_lock
, flags
);
2468 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2469 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
2470 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
2471 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2473 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2474 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2475 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2480 static struct sysdev_class ioapic_sysdev_class
= {
2482 .suspend
= ioapic_suspend
,
2483 .resume
= ioapic_resume
,
2486 static int __init
ioapic_init_sysfs(void)
2488 struct sys_device
* dev
;
2491 error
= sysdev_class_register(&ioapic_sysdev_class
);
2495 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2496 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2497 * sizeof(struct IO_APIC_route_entry
);
2498 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
2499 if (!mp_ioapic_data
[i
]) {
2500 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2503 dev
= &mp_ioapic_data
[i
]->dev
;
2505 dev
->cls
= &ioapic_sysdev_class
;
2506 error
= sysdev_register(dev
);
2508 kfree(mp_ioapic_data
[i
]);
2509 mp_ioapic_data
[i
] = NULL
;
2510 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2518 device_initcall(ioapic_init_sysfs
);
2521 * Dynamic irq allocate and deallocation
2523 int create_irq(void)
2525 /* Allocate an unused irq */
2528 unsigned long flags
;
2529 struct irq_cfg
*cfg_new
;
2532 spin_lock_irqsave(&vector_lock
, flags
);
2533 for (new = (nr_irqs
- 1); new >= 0; new--) {
2534 if (platform_legacy_irq(new))
2536 cfg_new
= irq_cfg(new);
2537 if (cfg_new
&& cfg_new
->vector
!= 0)
2539 /* check if need to create one */
2541 cfg_new
= irq_cfg_alloc(new);
2542 if (__assign_irq_vector(new, TARGET_CPUS
) == 0)
2546 spin_unlock_irqrestore(&vector_lock
, flags
);
2549 dynamic_irq_init(irq
);
2554 void destroy_irq(unsigned int irq
)
2556 unsigned long flags
;
2558 dynamic_irq_cleanup(irq
);
2560 #ifdef CONFIG_INTR_REMAP
2563 spin_lock_irqsave(&vector_lock
, flags
);
2564 __clear_irq_vector(irq
);
2565 spin_unlock_irqrestore(&vector_lock
, flags
);
2569 * MSI message composition
2571 #ifdef CONFIG_PCI_MSI
2572 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2574 struct irq_cfg
*cfg
;
2580 err
= assign_irq_vector(irq
, tmp
);
2585 cpus_and(tmp
, cfg
->domain
, tmp
);
2586 dest
= cpu_mask_to_apicid(tmp
);
2588 #ifdef CONFIG_INTR_REMAP
2589 if (irq_remapped(irq
)) {
2594 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
2595 BUG_ON(ir_index
== -1);
2597 memset (&irte
, 0, sizeof(irte
));
2600 irte
.dst_mode
= INT_DEST_MODE
;
2601 irte
.trigger_mode
= 0; /* edge */
2602 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
2603 irte
.vector
= cfg
->vector
;
2604 irte
.dest_id
= IRTE_DEST(dest
);
2606 modify_irte(irq
, &irte
);
2608 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2609 msg
->data
= sub_handle
;
2610 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
2612 MSI_ADDR_IR_INDEX1(ir_index
) |
2613 MSI_ADDR_IR_INDEX2(ir_index
);
2617 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2620 ((INT_DEST_MODE
== 0) ?
2621 MSI_ADDR_DEST_MODE_PHYSICAL
:
2622 MSI_ADDR_DEST_MODE_LOGICAL
) |
2623 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2624 MSI_ADDR_REDIRECTION_CPU
:
2625 MSI_ADDR_REDIRECTION_LOWPRI
) |
2626 MSI_ADDR_DEST_ID(dest
);
2629 MSI_DATA_TRIGGER_EDGE
|
2630 MSI_DATA_LEVEL_ASSERT
|
2631 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2632 MSI_DATA_DELIVERY_FIXED
:
2633 MSI_DATA_DELIVERY_LOWPRI
) |
2634 MSI_DATA_VECTOR(cfg
->vector
);
2640 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2642 struct irq_cfg
*cfg
;
2646 struct irq_desc
*desc
;
2648 cpus_and(tmp
, mask
, cpu_online_map
);
2649 if (cpus_empty(tmp
))
2652 if (assign_irq_vector(irq
, mask
))
2656 cpus_and(tmp
, cfg
->domain
, mask
);
2657 dest
= cpu_mask_to_apicid(tmp
);
2659 read_msi_msg(irq
, &msg
);
2661 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2662 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2663 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2664 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2666 write_msi_msg(irq
, &msg
);
2667 desc
= irq_to_desc(irq
);
2668 desc
->affinity
= mask
;
2671 #ifdef CONFIG_INTR_REMAP
2673 * Migrate the MSI irq to another cpumask. This migration is
2674 * done in the process context using interrupt-remapping hardware.
2676 static void ir_set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2678 struct irq_cfg
*cfg
;
2680 cpumask_t tmp
, cleanup_mask
;
2682 struct irq_desc
*desc
;
2684 cpus_and(tmp
, mask
, cpu_online_map
);
2685 if (cpus_empty(tmp
))
2688 if (get_irte(irq
, &irte
))
2691 if (assign_irq_vector(irq
, mask
))
2695 cpus_and(tmp
, cfg
->domain
, mask
);
2696 dest
= cpu_mask_to_apicid(tmp
);
2698 irte
.vector
= cfg
->vector
;
2699 irte
.dest_id
= IRTE_DEST(dest
);
2702 * atomically update the IRTE with the new destination and vector.
2704 modify_irte(irq
, &irte
);
2707 * After this point, all the interrupts will start arriving
2708 * at the new destination. So, time to cleanup the previous
2709 * vector allocation.
2711 if (cfg
->move_in_progress
) {
2712 cpus_and(cleanup_mask
, cfg
->old_domain
, cpu_online_map
);
2713 cfg
->move_cleanup_count
= cpus_weight(cleanup_mask
);
2714 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2715 cfg
->move_in_progress
= 0;
2718 desc
= irq_to_desc(irq
);
2719 desc
->affinity
= mask
;
2722 #endif /* CONFIG_SMP */
2725 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2726 * which implement the MSI or MSI-X Capability Structure.
2728 static struct irq_chip msi_chip
= {
2730 .unmask
= unmask_msi_irq
,
2731 .mask
= mask_msi_irq
,
2732 .ack
= ack_apic_edge
,
2734 .set_affinity
= set_msi_irq_affinity
,
2736 .retrigger
= ioapic_retrigger_irq
,
2739 #ifdef CONFIG_INTR_REMAP
2740 static struct irq_chip msi_ir_chip
= {
2741 .name
= "IR-PCI-MSI",
2742 .unmask
= unmask_msi_irq
,
2743 .mask
= mask_msi_irq
,
2744 .ack
= ack_x2apic_edge
,
2746 .set_affinity
= ir_set_msi_irq_affinity
,
2748 .retrigger
= ioapic_retrigger_irq
,
2752 * Map the PCI dev to the corresponding remapping hardware unit
2753 * and allocate 'nvec' consecutive interrupt-remapping table entries
2756 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
2758 struct intel_iommu
*iommu
;
2761 iommu
= map_dev_to_ir(dev
);
2764 "Unable to map PCI %s to iommu\n", pci_name(dev
));
2768 index
= alloc_irte(iommu
, irq
, nvec
);
2771 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
2779 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
, int irq
)
2784 ret
= msi_compose_msg(dev
, irq
, &msg
);
2788 set_irq_msi(irq
, desc
);
2789 write_msi_msg(irq
, &msg
);
2791 #ifdef CONFIG_INTR_REMAP
2792 if (irq_remapped(irq
)) {
2793 struct irq_desc
*desc
= irq_to_desc(irq
);
2795 * irq migration in process context
2797 desc
->status
|= IRQ_MOVE_PCNTXT
;
2798 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
2801 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
2806 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2814 #ifdef CONFIG_INTR_REMAP
2815 if (!intr_remapping_enabled
)
2818 ret
= msi_alloc_irte(dev
, irq
, 1);
2823 ret
= setup_msi_irq(dev
, desc
, irq
);
2830 #ifdef CONFIG_INTR_REMAP
2837 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
2839 int irq
, ret
, sub_handle
;
2840 struct msi_desc
*desc
;
2841 #ifdef CONFIG_INTR_REMAP
2842 struct intel_iommu
*iommu
= 0;
2847 list_for_each_entry(desc
, &dev
->msi_list
, list
) {
2851 #ifdef CONFIG_INTR_REMAP
2852 if (!intr_remapping_enabled
)
2857 * allocate the consecutive block of IRTE's
2860 index
= msi_alloc_irte(dev
, irq
, nvec
);
2866 iommu
= map_dev_to_ir(dev
);
2872 * setup the mapping between the irq and the IRTE
2873 * base index, the sub_handle pointing to the
2874 * appropriate interrupt remap table entry.
2876 set_irte_irq(irq
, iommu
, index
, sub_handle
);
2880 ret
= setup_msi_irq(dev
, desc
, irq
);
2892 void arch_teardown_msi_irq(unsigned int irq
)
2899 static void dmar_msi_set_affinity(unsigned int irq
, cpumask_t mask
)
2901 struct irq_cfg
*cfg
;
2905 struct irq_desc
*desc
;
2907 cpus_and(tmp
, mask
, cpu_online_map
);
2908 if (cpus_empty(tmp
))
2911 if (assign_irq_vector(irq
, mask
))
2915 cpus_and(tmp
, cfg
->domain
, mask
);
2916 dest
= cpu_mask_to_apicid(tmp
);
2918 dmar_msi_read(irq
, &msg
);
2920 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2921 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
2922 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2923 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2925 dmar_msi_write(irq
, &msg
);
2926 desc
= irq_to_desc(irq
);
2927 desc
->affinity
= mask
;
2929 #endif /* CONFIG_SMP */
2931 struct irq_chip dmar_msi_type
= {
2933 .unmask
= dmar_msi_unmask
,
2934 .mask
= dmar_msi_mask
,
2935 .ack
= ack_apic_edge
,
2937 .set_affinity
= dmar_msi_set_affinity
,
2939 .retrigger
= ioapic_retrigger_irq
,
2942 int arch_setup_dmar_msi(unsigned int irq
)
2947 ret
= msi_compose_msg(NULL
, irq
, &msg
);
2950 dmar_msi_write(irq
, &msg
);
2951 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
2957 #endif /* CONFIG_PCI_MSI */
2959 * Hypertransport interrupt support
2961 #ifdef CONFIG_HT_IRQ
2965 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
2967 struct ht_irq_msg msg
;
2968 fetch_ht_irq_msg(irq
, &msg
);
2970 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
2971 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2973 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
2974 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2976 write_ht_irq_msg(irq
, &msg
);
2979 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2981 struct irq_cfg
*cfg
;
2984 struct irq_desc
*desc
;
2986 cpus_and(tmp
, mask
, cpu_online_map
);
2987 if (cpus_empty(tmp
))
2990 if (assign_irq_vector(irq
, mask
))
2994 cpus_and(tmp
, cfg
->domain
, mask
);
2995 dest
= cpu_mask_to_apicid(tmp
);
2997 target_ht_irq(irq
, dest
, cfg
->vector
);
2998 desc
= irq_to_desc(irq
);
2999 desc
->affinity
= mask
;
3003 static struct irq_chip ht_irq_chip
= {
3005 .mask
= mask_ht_irq
,
3006 .unmask
= unmask_ht_irq
,
3007 .ack
= ack_apic_edge
,
3009 .set_affinity
= set_ht_irq_affinity
,
3011 .retrigger
= ioapic_retrigger_irq
,
3014 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3016 struct irq_cfg
*cfg
;
3021 err
= assign_irq_vector(irq
, tmp
);
3023 struct ht_irq_msg msg
;
3027 cpus_and(tmp
, cfg
->domain
, tmp
);
3028 dest
= cpu_mask_to_apicid(tmp
);
3030 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3034 HT_IRQ_LOW_DEST_ID(dest
) |
3035 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3036 ((INT_DEST_MODE
== 0) ?
3037 HT_IRQ_LOW_DM_PHYSICAL
:
3038 HT_IRQ_LOW_DM_LOGICAL
) |
3039 HT_IRQ_LOW_RQEOI_EDGE
|
3040 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3041 HT_IRQ_LOW_MT_FIXED
:
3042 HT_IRQ_LOW_MT_ARBITRATED
) |
3043 HT_IRQ_LOW_IRQ_MASKED
;
3045 write_ht_irq_msg(irq
, &msg
);
3047 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3048 handle_edge_irq
, "edge");
3052 #endif /* CONFIG_HT_IRQ */
3054 /* --------------------------------------------------------------------------
3055 ACPI-based IOAPIC Configuration
3056 -------------------------------------------------------------------------- */
3060 #define IO_APIC_MAX_ID 0xFE
3062 int __init
io_apic_get_redir_entries (int ioapic
)
3064 union IO_APIC_reg_01 reg_01
;
3065 unsigned long flags
;
3067 spin_lock_irqsave(&ioapic_lock
, flags
);
3068 reg_01
.raw
= io_apic_read(ioapic
, 1);
3069 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3071 return reg_01
.bits
.entries
;
3075 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3077 if (!IO_APIC_IRQ(irq
)) {
3078 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3084 * IRQs < 16 are already in the irq_2_pin[] map
3087 add_pin_to_irq(irq
, ioapic
, pin
);
3089 setup_IO_APIC_irq(ioapic
, pin
, irq
, triggering
, polarity
);
3095 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3099 if (skip_ioapic_setup
)
3102 for (i
= 0; i
< mp_irq_entries
; i
++)
3103 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3104 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3106 if (i
>= mp_irq_entries
)
3109 *trigger
= irq_trigger(i
);
3110 *polarity
= irq_polarity(i
);
3114 #endif /* CONFIG_ACPI */
3117 * This function currently is only a helper for the i386 smp boot process where
3118 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3119 * so mask in all cases should simply be TARGET_CPUS
3122 void __init
setup_ioapic_dest(void)
3124 int pin
, ioapic
, irq
, irq_entry
;
3125 struct irq_cfg
*cfg
;
3127 if (skip_ioapic_setup
== 1)
3130 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
3131 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
3132 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3133 if (irq_entry
== -1)
3135 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3137 /* setup_IO_APIC_irqs could fail to get vector for some device
3138 * when you have too many devices, because at that time only boot
3143 setup_IO_APIC_irq(ioapic
, pin
, irq
,
3144 irq_trigger(irq_entry
),
3145 irq_polarity(irq_entry
));
3146 #ifdef CONFIG_INTR_REMAP
3147 else if (intr_remapping_enabled
)
3148 set_ir_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3151 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
3158 #define IOAPIC_RESOURCE_NAME_SIZE 11
3160 static struct resource
*ioapic_resources
;
3162 static struct resource
* __init
ioapic_setup_resources(void)
3165 struct resource
*res
;
3169 if (nr_ioapics
<= 0)
3172 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3175 mem
= alloc_bootmem(n
);
3179 mem
+= sizeof(struct resource
) * nr_ioapics
;
3181 for (i
= 0; i
< nr_ioapics
; i
++) {
3183 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3184 sprintf(mem
, "IOAPIC %u", i
);
3185 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3189 ioapic_resources
= res
;
3194 void __init
ioapic_init_mappings(void)
3196 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3197 struct resource
*ioapic_res
;
3200 ioapic_res
= ioapic_setup_resources();
3201 for (i
= 0; i
< nr_ioapics
; i
++) {
3202 if (smp_found_config
) {
3203 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
3205 ioapic_phys
= (unsigned long)
3206 alloc_bootmem_pages(PAGE_SIZE
);
3207 ioapic_phys
= __pa(ioapic_phys
);
3209 set_fixmap_nocache(idx
, ioapic_phys
);
3210 apic_printk(APIC_VERBOSE
,
3211 "mapped IOAPIC to %016lx (%016lx)\n",
3212 __fix_to_virt(idx
), ioapic_phys
);
3215 if (ioapic_res
!= NULL
) {
3216 ioapic_res
->start
= ioapic_phys
;
3217 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
3223 static int __init
ioapic_insert_resources(void)
3226 struct resource
*r
= ioapic_resources
;
3230 "IO APIC resources could be not be allocated.\n");
3234 for (i
= 0; i
< nr_ioapics
; i
++) {
3235 insert_resource(&iomem_resource
, r
);
3242 /* Insert the IO APIC resources after PCI initialization has occured to handle
3243 * IO APICS that are mapped in on a BAR in PCI space. */
3244 late_initcall(ioapic_insert_resources
);