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x86: use dyn_array in io_apic_xx.c
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
41
42 #include <asm/idle.h>
43 #include <asm/io.h>
44 #include <asm/smp.h>
45 #include <asm/desc.h>
46 #include <asm/proto.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/i8259.h>
50 #include <asm/nmi.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
54
55 #include <mach_ipi.h>
56 #include <mach_apic.h>
57
58 #define __apicdebuginit(type) static type __init
59
60 struct irq_cfg {
61 cpumask_t domain;
62 cpumask_t old_domain;
63 unsigned move_cleanup_count;
64 u8 vector;
65 u8 move_in_progress : 1;
66 };
67
68 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
69 static struct irq_cfg irq_cfg_legacy[] __initdata = {
70 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
71 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
72 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
73 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
74 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
75 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
76 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
77 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
78 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
79 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
80 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
81 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
82 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
83 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
84 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
85 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
86 };
87
88 static struct irq_cfg *irq_cfg;
89
90 static void __init init_work(void *data)
91 {
92 struct dyn_array *da = data;
93
94 memcpy(*da->name, irq_cfg_legacy, sizeof(irq_cfg_legacy));
95 }
96
97 DEFINE_DYN_ARRAY(irq_cfg, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work);
98
99 static int assign_irq_vector(int irq, cpumask_t mask);
100
101 int first_system_vector = 0xfe;
102
103 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
104
105 int sis_apic_bug; /* not actually supported, dummy for compile */
106
107 static int no_timer_check;
108
109 static int disable_timer_pin_1 __initdata;
110
111 int timer_through_8259 __initdata;
112
113 /* Where if anywhere is the i8259 connect in external int mode */
114 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
115
116 static DEFINE_SPINLOCK(ioapic_lock);
117 static DEFINE_SPINLOCK(vector_lock);
118
119 /*
120 * # of IRQ routing registers
121 */
122 int nr_ioapic_registers[MAX_IO_APICS];
123
124 /* I/O APIC RTE contents at the OS boot up */
125 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
126
127 /* I/O APIC entries */
128 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
129 int nr_ioapics;
130
131 /* MP IRQ source entries */
132 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
133
134 /* # of MP IRQ source entries */
135 int mp_irq_entries;
136
137 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
138
139 /*
140 * Rough estimation of how many shared IRQs there are, can
141 * be changed anytime.
142 */
143
144 int pin_map_size;
145
146 /*
147 * This is performance-critical, we want to do it O(1)
148 *
149 * the indexing order of this array favors 1:1 mappings
150 * between pins and IRQs.
151 */
152
153 static struct irq_pin_list {
154 short apic, pin;
155 int next;
156 } *irq_2_pin;
157
158 DEFINE_DYN_ARRAY(irq_2_pin, sizeof(struct irq_pin_list), pin_map_size, sizeof(struct irq_pin_list), NULL);
159
160
161 struct io_apic {
162 unsigned int index;
163 unsigned int unused[3];
164 unsigned int data;
165 };
166
167 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
168 {
169 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
170 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
171 }
172
173 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
174 {
175 struct io_apic __iomem *io_apic = io_apic_base(apic);
176 writel(reg, &io_apic->index);
177 return readl(&io_apic->data);
178 }
179
180 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
181 {
182 struct io_apic __iomem *io_apic = io_apic_base(apic);
183 writel(reg, &io_apic->index);
184 writel(value, &io_apic->data);
185 }
186
187 /*
188 * Re-write a value: to be used for read-modify-write
189 * cycles where the read already set up the index register.
190 */
191 static inline void io_apic_modify(unsigned int apic, unsigned int value)
192 {
193 struct io_apic __iomem *io_apic = io_apic_base(apic);
194 writel(value, &io_apic->data);
195 }
196
197 static bool io_apic_level_ack_pending(unsigned int irq)
198 {
199 struct irq_pin_list *entry;
200 unsigned long flags;
201
202 spin_lock_irqsave(&ioapic_lock, flags);
203 entry = irq_2_pin + irq;
204 for (;;) {
205 unsigned int reg;
206 int pin;
207
208 pin = entry->pin;
209 if (pin == -1)
210 break;
211 reg = io_apic_read(entry->apic, 0x10 + pin*2);
212 /* Is the remote IRR bit set? */
213 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
214 spin_unlock_irqrestore(&ioapic_lock, flags);
215 return true;
216 }
217 if (!entry->next)
218 break;
219 entry = irq_2_pin + entry->next;
220 }
221 spin_unlock_irqrestore(&ioapic_lock, flags);
222
223 return false;
224 }
225
226 /*
227 * Synchronize the IO-APIC and the CPU by doing
228 * a dummy read from the IO-APIC
229 */
230 static inline void io_apic_sync(unsigned int apic)
231 {
232 struct io_apic __iomem *io_apic = io_apic_base(apic);
233 readl(&io_apic->data);
234 }
235
236 #define __DO_ACTION(R, ACTION, FINAL) \
237 \
238 { \
239 int pin; \
240 struct irq_pin_list *entry = irq_2_pin + irq; \
241 \
242 BUG_ON(irq >= nr_irqs); \
243 for (;;) { \
244 unsigned int reg; \
245 pin = entry->pin; \
246 if (pin == -1) \
247 break; \
248 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
249 reg ACTION; \
250 io_apic_modify(entry->apic, reg); \
251 FINAL; \
252 if (!entry->next) \
253 break; \
254 entry = irq_2_pin + entry->next; \
255 } \
256 }
257
258 union entry_union {
259 struct { u32 w1, w2; };
260 struct IO_APIC_route_entry entry;
261 };
262
263 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
264 {
265 union entry_union eu;
266 unsigned long flags;
267 spin_lock_irqsave(&ioapic_lock, flags);
268 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
269 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
270 spin_unlock_irqrestore(&ioapic_lock, flags);
271 return eu.entry;
272 }
273
274 /*
275 * When we write a new IO APIC routing entry, we need to write the high
276 * word first! If the mask bit in the low word is clear, we will enable
277 * the interrupt, and we need to make sure the entry is fully populated
278 * before that happens.
279 */
280 static void
281 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
282 {
283 union entry_union eu;
284 eu.entry = e;
285 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
286 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
287 }
288
289 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
290 {
291 unsigned long flags;
292 spin_lock_irqsave(&ioapic_lock, flags);
293 __ioapic_write_entry(apic, pin, e);
294 spin_unlock_irqrestore(&ioapic_lock, flags);
295 }
296
297 /*
298 * When we mask an IO APIC routing entry, we need to write the low
299 * word first, in order to set the mask bit before we change the
300 * high bits!
301 */
302 static void ioapic_mask_entry(int apic, int pin)
303 {
304 unsigned long flags;
305 union entry_union eu = { .entry.mask = 1 };
306
307 spin_lock_irqsave(&ioapic_lock, flags);
308 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
309 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
310 spin_unlock_irqrestore(&ioapic_lock, flags);
311 }
312
313 #ifdef CONFIG_SMP
314 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
315 {
316 int apic, pin;
317 struct irq_pin_list *entry = irq_2_pin + irq;
318
319 BUG_ON(irq >= nr_irqs);
320 for (;;) {
321 unsigned int reg;
322 apic = entry->apic;
323 pin = entry->pin;
324 if (pin == -1)
325 break;
326 /*
327 * With interrupt-remapping, destination information comes
328 * from interrupt-remapping table entry.
329 */
330 if (!irq_remapped(irq))
331 io_apic_write(apic, 0x11 + pin*2, dest);
332 reg = io_apic_read(apic, 0x10 + pin*2);
333 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
334 reg |= vector;
335 io_apic_modify(apic, reg);
336 if (!entry->next)
337 break;
338 entry = irq_2_pin + entry->next;
339 }
340 }
341
342 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
343 {
344 struct irq_cfg *cfg = irq_cfg + irq;
345 unsigned long flags;
346 unsigned int dest;
347 cpumask_t tmp;
348
349 cpus_and(tmp, mask, cpu_online_map);
350 if (cpus_empty(tmp))
351 return;
352
353 if (assign_irq_vector(irq, mask))
354 return;
355
356 cpus_and(tmp, cfg->domain, mask);
357 dest = cpu_mask_to_apicid(tmp);
358
359 /*
360 * Only the high 8 bits are valid.
361 */
362 dest = SET_APIC_LOGICAL_ID(dest);
363
364 spin_lock_irqsave(&ioapic_lock, flags);
365 __target_IO_APIC_irq(irq, dest, cfg->vector);
366 irq_desc[irq].affinity = mask;
367 spin_unlock_irqrestore(&ioapic_lock, flags);
368 }
369 #endif
370
371 /*
372 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
373 * shared ISA-space IRQs, so we have to support them. We are super
374 * fast in the common case, and fast for shared ISA-space IRQs.
375 */
376 int first_free_entry;
377 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
378 {
379 struct irq_pin_list *entry = irq_2_pin + irq;
380
381 BUG_ON(irq >= nr_irqs);
382 while (entry->next)
383 entry = irq_2_pin + entry->next;
384
385 if (entry->pin != -1) {
386 entry->next = first_free_entry;
387 entry = irq_2_pin + entry->next;
388 if (++first_free_entry >= pin_map_size)
389 panic("io_apic.c: ran out of irq_2_pin entries!");
390 }
391 entry->apic = apic;
392 entry->pin = pin;
393 }
394
395 /*
396 * Reroute an IRQ to a different pin.
397 */
398 static void __init replace_pin_at_irq(unsigned int irq,
399 int oldapic, int oldpin,
400 int newapic, int newpin)
401 {
402 struct irq_pin_list *entry = irq_2_pin + irq;
403
404 while (1) {
405 if (entry->apic == oldapic && entry->pin == oldpin) {
406 entry->apic = newapic;
407 entry->pin = newpin;
408 }
409 if (!entry->next)
410 break;
411 entry = irq_2_pin + entry->next;
412 }
413 }
414
415
416 #define DO_ACTION(name,R,ACTION, FINAL) \
417 \
418 static void name##_IO_APIC_irq (unsigned int irq) \
419 __DO_ACTION(R, ACTION, FINAL)
420
421 /* mask = 1 */
422 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
423
424 /* mask = 0 */
425 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
426
427 static void mask_IO_APIC_irq (unsigned int irq)
428 {
429 unsigned long flags;
430
431 spin_lock_irqsave(&ioapic_lock, flags);
432 __mask_IO_APIC_irq(irq);
433 spin_unlock_irqrestore(&ioapic_lock, flags);
434 }
435
436 static void unmask_IO_APIC_irq (unsigned int irq)
437 {
438 unsigned long flags;
439
440 spin_lock_irqsave(&ioapic_lock, flags);
441 __unmask_IO_APIC_irq(irq);
442 spin_unlock_irqrestore(&ioapic_lock, flags);
443 }
444
445 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
446 {
447 struct IO_APIC_route_entry entry;
448
449 /* Check delivery_mode to be sure we're not clearing an SMI pin */
450 entry = ioapic_read_entry(apic, pin);
451 if (entry.delivery_mode == dest_SMI)
452 return;
453 /*
454 * Disable it in the IO-APIC irq-routing table:
455 */
456 ioapic_mask_entry(apic, pin);
457 }
458
459 static void clear_IO_APIC (void)
460 {
461 int apic, pin;
462
463 for (apic = 0; apic < nr_ioapics; apic++)
464 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
465 clear_IO_APIC_pin(apic, pin);
466 }
467
468 /*
469 * Saves and masks all the unmasked IO-APIC RTE's
470 */
471 int save_mask_IO_APIC_setup(void)
472 {
473 union IO_APIC_reg_01 reg_01;
474 unsigned long flags;
475 int apic, pin;
476
477 /*
478 * The number of IO-APIC IRQ registers (== #pins):
479 */
480 for (apic = 0; apic < nr_ioapics; apic++) {
481 spin_lock_irqsave(&ioapic_lock, flags);
482 reg_01.raw = io_apic_read(apic, 1);
483 spin_unlock_irqrestore(&ioapic_lock, flags);
484 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
485 }
486
487 for (apic = 0; apic < nr_ioapics; apic++) {
488 early_ioapic_entries[apic] =
489 kzalloc(sizeof(struct IO_APIC_route_entry) *
490 nr_ioapic_registers[apic], GFP_KERNEL);
491 if (!early_ioapic_entries[apic])
492 return -ENOMEM;
493 }
494
495 for (apic = 0; apic < nr_ioapics; apic++)
496 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
497 struct IO_APIC_route_entry entry;
498
499 entry = early_ioapic_entries[apic][pin] =
500 ioapic_read_entry(apic, pin);
501 if (!entry.mask) {
502 entry.mask = 1;
503 ioapic_write_entry(apic, pin, entry);
504 }
505 }
506 return 0;
507 }
508
509 void restore_IO_APIC_setup(void)
510 {
511 int apic, pin;
512
513 for (apic = 0; apic < nr_ioapics; apic++)
514 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
515 ioapic_write_entry(apic, pin,
516 early_ioapic_entries[apic][pin]);
517 }
518
519 void reinit_intr_remapped_IO_APIC(int intr_remapping)
520 {
521 /*
522 * for now plain restore of previous settings.
523 * TBD: In the case of OS enabling interrupt-remapping,
524 * IO-APIC RTE's need to be setup to point to interrupt-remapping
525 * table entries. for now, do a plain restore, and wait for
526 * the setup_IO_APIC_irqs() to do proper initialization.
527 */
528 restore_IO_APIC_setup();
529 }
530
531 int skip_ioapic_setup;
532 int ioapic_force;
533
534 static int __init parse_noapic(char *str)
535 {
536 disable_ioapic_setup();
537 return 0;
538 }
539 early_param("noapic", parse_noapic);
540
541 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
542 static int __init disable_timer_pin_setup(char *arg)
543 {
544 disable_timer_pin_1 = 1;
545 return 1;
546 }
547 __setup("disable_timer_pin_1", disable_timer_pin_setup);
548
549
550 /*
551 * Find the IRQ entry number of a certain pin.
552 */
553 static int find_irq_entry(int apic, int pin, int type)
554 {
555 int i;
556
557 for (i = 0; i < mp_irq_entries; i++)
558 if (mp_irqs[i].mp_irqtype == type &&
559 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
560 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
561 mp_irqs[i].mp_dstirq == pin)
562 return i;
563
564 return -1;
565 }
566
567 /*
568 * Find the pin to which IRQ[irq] (ISA) is connected
569 */
570 static int __init find_isa_irq_pin(int irq, int type)
571 {
572 int i;
573
574 for (i = 0; i < mp_irq_entries; i++) {
575 int lbus = mp_irqs[i].mp_srcbus;
576
577 if (test_bit(lbus, mp_bus_not_pci) &&
578 (mp_irqs[i].mp_irqtype == type) &&
579 (mp_irqs[i].mp_srcbusirq == irq))
580
581 return mp_irqs[i].mp_dstirq;
582 }
583 return -1;
584 }
585
586 static int __init find_isa_irq_apic(int irq, int type)
587 {
588 int i;
589
590 for (i = 0; i < mp_irq_entries; i++) {
591 int lbus = mp_irqs[i].mp_srcbus;
592
593 if (test_bit(lbus, mp_bus_not_pci) &&
594 (mp_irqs[i].mp_irqtype == type) &&
595 (mp_irqs[i].mp_srcbusirq == irq))
596 break;
597 }
598 if (i < mp_irq_entries) {
599 int apic;
600 for(apic = 0; apic < nr_ioapics; apic++) {
601 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
602 return apic;
603 }
604 }
605
606 return -1;
607 }
608
609 /*
610 * Find a specific PCI IRQ entry.
611 * Not an __init, possibly needed by modules
612 */
613 static int pin_2_irq(int idx, int apic, int pin);
614
615 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
616 {
617 int apic, i, best_guess = -1;
618
619 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
620 bus, slot, pin);
621 if (test_bit(bus, mp_bus_not_pci)) {
622 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
623 return -1;
624 }
625 for (i = 0; i < mp_irq_entries; i++) {
626 int lbus = mp_irqs[i].mp_srcbus;
627
628 for (apic = 0; apic < nr_ioapics; apic++)
629 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
630 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
631 break;
632
633 if (!test_bit(lbus, mp_bus_not_pci) &&
634 !mp_irqs[i].mp_irqtype &&
635 (bus == lbus) &&
636 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
637 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
638
639 if (!(apic || IO_APIC_IRQ(irq)))
640 continue;
641
642 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
643 return irq;
644 /*
645 * Use the first all-but-pin matching entry as a
646 * best-guess fuzzy result for broken mptables.
647 */
648 if (best_guess < 0)
649 best_guess = irq;
650 }
651 }
652 BUG_ON(best_guess >= nr_irqs);
653 return best_guess;
654 }
655
656 /* ISA interrupts are always polarity zero edge triggered,
657 * when listed as conforming in the MP table. */
658
659 #define default_ISA_trigger(idx) (0)
660 #define default_ISA_polarity(idx) (0)
661
662 /* PCI interrupts are always polarity one level triggered,
663 * when listed as conforming in the MP table. */
664
665 #define default_PCI_trigger(idx) (1)
666 #define default_PCI_polarity(idx) (1)
667
668 static int MPBIOS_polarity(int idx)
669 {
670 int bus = mp_irqs[idx].mp_srcbus;
671 int polarity;
672
673 /*
674 * Determine IRQ line polarity (high active or low active):
675 */
676 switch (mp_irqs[idx].mp_irqflag & 3)
677 {
678 case 0: /* conforms, ie. bus-type dependent polarity */
679 if (test_bit(bus, mp_bus_not_pci))
680 polarity = default_ISA_polarity(idx);
681 else
682 polarity = default_PCI_polarity(idx);
683 break;
684 case 1: /* high active */
685 {
686 polarity = 0;
687 break;
688 }
689 case 2: /* reserved */
690 {
691 printk(KERN_WARNING "broken BIOS!!\n");
692 polarity = 1;
693 break;
694 }
695 case 3: /* low active */
696 {
697 polarity = 1;
698 break;
699 }
700 default: /* invalid */
701 {
702 printk(KERN_WARNING "broken BIOS!!\n");
703 polarity = 1;
704 break;
705 }
706 }
707 return polarity;
708 }
709
710 static int MPBIOS_trigger(int idx)
711 {
712 int bus = mp_irqs[idx].mp_srcbus;
713 int trigger;
714
715 /*
716 * Determine IRQ trigger mode (edge or level sensitive):
717 */
718 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
719 {
720 case 0: /* conforms, ie. bus-type dependent */
721 if (test_bit(bus, mp_bus_not_pci))
722 trigger = default_ISA_trigger(idx);
723 else
724 trigger = default_PCI_trigger(idx);
725 break;
726 case 1: /* edge */
727 {
728 trigger = 0;
729 break;
730 }
731 case 2: /* reserved */
732 {
733 printk(KERN_WARNING "broken BIOS!!\n");
734 trigger = 1;
735 break;
736 }
737 case 3: /* level */
738 {
739 trigger = 1;
740 break;
741 }
742 default: /* invalid */
743 {
744 printk(KERN_WARNING "broken BIOS!!\n");
745 trigger = 0;
746 break;
747 }
748 }
749 return trigger;
750 }
751
752 static inline int irq_polarity(int idx)
753 {
754 return MPBIOS_polarity(idx);
755 }
756
757 static inline int irq_trigger(int idx)
758 {
759 return MPBIOS_trigger(idx);
760 }
761
762 static int pin_2_irq(int idx, int apic, int pin)
763 {
764 int irq, i;
765 int bus = mp_irqs[idx].mp_srcbus;
766
767 /*
768 * Debugging check, we are in big trouble if this message pops up!
769 */
770 if (mp_irqs[idx].mp_dstirq != pin)
771 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
772
773 if (test_bit(bus, mp_bus_not_pci)) {
774 irq = mp_irqs[idx].mp_srcbusirq;
775 } else {
776 /*
777 * PCI IRQs are mapped in order
778 */
779 i = irq = 0;
780 while (i < apic)
781 irq += nr_ioapic_registers[i++];
782 irq += pin;
783 }
784 BUG_ON(irq >= nr_irqs);
785 return irq;
786 }
787
788 void lock_vector_lock(void)
789 {
790 /* Used to the online set of cpus does not change
791 * during assign_irq_vector.
792 */
793 spin_lock(&vector_lock);
794 }
795
796 void unlock_vector_lock(void)
797 {
798 spin_unlock(&vector_lock);
799 }
800
801 static int __assign_irq_vector(int irq, cpumask_t mask)
802 {
803 /*
804 * NOTE! The local APIC isn't very good at handling
805 * multiple interrupts at the same interrupt level.
806 * As the interrupt level is determined by taking the
807 * vector number and shifting that right by 4, we
808 * want to spread these out a bit so that they don't
809 * all fall in the same interrupt level.
810 *
811 * Also, we've got to be careful not to trash gate
812 * 0x80, because int 0x80 is hm, kind of importantish. ;)
813 */
814 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
815 unsigned int old_vector;
816 int cpu;
817 struct irq_cfg *cfg;
818
819 BUG_ON((unsigned)irq >= nr_irqs);
820 cfg = &irq_cfg[irq];
821
822 /* Only try and allocate irqs on cpus that are present */
823 cpus_and(mask, mask, cpu_online_map);
824
825 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
826 return -EBUSY;
827
828 old_vector = cfg->vector;
829 if (old_vector) {
830 cpumask_t tmp;
831 cpus_and(tmp, cfg->domain, mask);
832 if (!cpus_empty(tmp))
833 return 0;
834 }
835
836 for_each_cpu_mask_nr(cpu, mask) {
837 cpumask_t domain, new_mask;
838 int new_cpu;
839 int vector, offset;
840
841 domain = vector_allocation_domain(cpu);
842 cpus_and(new_mask, domain, cpu_online_map);
843
844 vector = current_vector;
845 offset = current_offset;
846 next:
847 vector += 8;
848 if (vector >= first_system_vector) {
849 /* If we run out of vectors on large boxen, must share them. */
850 offset = (offset + 1) % 8;
851 vector = FIRST_DEVICE_VECTOR + offset;
852 }
853 if (unlikely(current_vector == vector))
854 continue;
855 if (vector == IA32_SYSCALL_VECTOR)
856 goto next;
857 for_each_cpu_mask_nr(new_cpu, new_mask)
858 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
859 goto next;
860 /* Found one! */
861 current_vector = vector;
862 current_offset = offset;
863 if (old_vector) {
864 cfg->move_in_progress = 1;
865 cfg->old_domain = cfg->domain;
866 }
867 for_each_cpu_mask_nr(new_cpu, new_mask)
868 per_cpu(vector_irq, new_cpu)[vector] = irq;
869 cfg->vector = vector;
870 cfg->domain = domain;
871 return 0;
872 }
873 return -ENOSPC;
874 }
875
876 static int assign_irq_vector(int irq, cpumask_t mask)
877 {
878 int err;
879 unsigned long flags;
880
881 spin_lock_irqsave(&vector_lock, flags);
882 err = __assign_irq_vector(irq, mask);
883 spin_unlock_irqrestore(&vector_lock, flags);
884 return err;
885 }
886
887 static void __clear_irq_vector(int irq)
888 {
889 struct irq_cfg *cfg;
890 cpumask_t mask;
891 int cpu, vector;
892
893 BUG_ON((unsigned)irq >= nr_irqs);
894 cfg = &irq_cfg[irq];
895 BUG_ON(!cfg->vector);
896
897 vector = cfg->vector;
898 cpus_and(mask, cfg->domain, cpu_online_map);
899 for_each_cpu_mask_nr(cpu, mask)
900 per_cpu(vector_irq, cpu)[vector] = -1;
901
902 cfg->vector = 0;
903 cpus_clear(cfg->domain);
904 }
905
906 void __setup_vector_irq(int cpu)
907 {
908 /* Initialize vector_irq on a new cpu */
909 /* This function must be called with vector_lock held */
910 int irq, vector;
911
912 /* Mark the inuse vectors */
913 for (irq = 0; irq < nr_irqs; ++irq) {
914 if (!cpu_isset(cpu, irq_cfg[irq].domain))
915 continue;
916 vector = irq_cfg[irq].vector;
917 per_cpu(vector_irq, cpu)[vector] = irq;
918 }
919 /* Mark the free vectors */
920 for (vector = 0; vector < NR_VECTORS; ++vector) {
921 irq = per_cpu(vector_irq, cpu)[vector];
922 if (irq < 0)
923 continue;
924 if (!cpu_isset(cpu, irq_cfg[irq].domain))
925 per_cpu(vector_irq, cpu)[vector] = -1;
926 }
927 }
928
929 static struct irq_chip ioapic_chip;
930 #ifdef CONFIG_INTR_REMAP
931 static struct irq_chip ir_ioapic_chip;
932 #endif
933
934 static void ioapic_register_intr(int irq, unsigned long trigger)
935 {
936 if (trigger)
937 irq_desc[irq].status |= IRQ_LEVEL;
938 else
939 irq_desc[irq].status &= ~IRQ_LEVEL;
940
941 #ifdef CONFIG_INTR_REMAP
942 if (irq_remapped(irq)) {
943 irq_desc[irq].status |= IRQ_MOVE_PCNTXT;
944 if (trigger)
945 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
946 handle_fasteoi_irq,
947 "fasteoi");
948 else
949 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
950 handle_edge_irq, "edge");
951 return;
952 }
953 #endif
954 if (trigger)
955 set_irq_chip_and_handler_name(irq, &ioapic_chip,
956 handle_fasteoi_irq,
957 "fasteoi");
958 else
959 set_irq_chip_and_handler_name(irq, &ioapic_chip,
960 handle_edge_irq, "edge");
961 }
962
963 static int setup_ioapic_entry(int apic, int irq,
964 struct IO_APIC_route_entry *entry,
965 unsigned int destination, int trigger,
966 int polarity, int vector)
967 {
968 /*
969 * add it to the IO-APIC irq-routing table:
970 */
971 memset(entry,0,sizeof(*entry));
972
973 #ifdef CONFIG_INTR_REMAP
974 if (intr_remapping_enabled) {
975 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
976 struct irte irte;
977 struct IR_IO_APIC_route_entry *ir_entry =
978 (struct IR_IO_APIC_route_entry *) entry;
979 int index;
980
981 if (!iommu)
982 panic("No mapping iommu for ioapic %d\n", apic);
983
984 index = alloc_irte(iommu, irq, 1);
985 if (index < 0)
986 panic("Failed to allocate IRTE for ioapic %d\n", apic);
987
988 memset(&irte, 0, sizeof(irte));
989
990 irte.present = 1;
991 irte.dst_mode = INT_DEST_MODE;
992 irte.trigger_mode = trigger;
993 irte.dlvry_mode = INT_DELIVERY_MODE;
994 irte.vector = vector;
995 irte.dest_id = IRTE_DEST(destination);
996
997 modify_irte(irq, &irte);
998
999 ir_entry->index2 = (index >> 15) & 0x1;
1000 ir_entry->zero = 0;
1001 ir_entry->format = 1;
1002 ir_entry->index = (index & 0x7fff);
1003 } else
1004 #endif
1005 {
1006 entry->delivery_mode = INT_DELIVERY_MODE;
1007 entry->dest_mode = INT_DEST_MODE;
1008 entry->dest = destination;
1009 }
1010
1011 entry->mask = 0; /* enable IRQ */
1012 entry->trigger = trigger;
1013 entry->polarity = polarity;
1014 entry->vector = vector;
1015
1016 /* Mask level triggered irqs.
1017 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1018 */
1019 if (trigger)
1020 entry->mask = 1;
1021 return 0;
1022 }
1023
1024 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1025 int trigger, int polarity)
1026 {
1027 struct irq_cfg *cfg = irq_cfg + irq;
1028 struct IO_APIC_route_entry entry;
1029 cpumask_t mask;
1030
1031 if (!IO_APIC_IRQ(irq))
1032 return;
1033
1034 mask = TARGET_CPUS;
1035 if (assign_irq_vector(irq, mask))
1036 return;
1037
1038 cpus_and(mask, cfg->domain, mask);
1039
1040 apic_printk(APIC_VERBOSE,KERN_DEBUG
1041 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1042 "IRQ %d Mode:%i Active:%i)\n",
1043 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1044 irq, trigger, polarity);
1045
1046
1047 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1048 cpu_mask_to_apicid(mask), trigger, polarity,
1049 cfg->vector)) {
1050 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1051 mp_ioapics[apic].mp_apicid, pin);
1052 __clear_irq_vector(irq);
1053 return;
1054 }
1055
1056 ioapic_register_intr(irq, trigger);
1057 if (irq < 16)
1058 disable_8259A_irq(irq);
1059
1060 ioapic_write_entry(apic, pin, entry);
1061 }
1062
1063 static void __init setup_IO_APIC_irqs(void)
1064 {
1065 int apic, pin, idx, irq, first_notcon = 1;
1066
1067 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1068
1069 for (apic = 0; apic < nr_ioapics; apic++) {
1070 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1071
1072 idx = find_irq_entry(apic,pin,mp_INT);
1073 if (idx == -1) {
1074 if (first_notcon) {
1075 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1076 first_notcon = 0;
1077 } else
1078 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1079 continue;
1080 }
1081 if (!first_notcon) {
1082 apic_printk(APIC_VERBOSE, " not connected.\n");
1083 first_notcon = 1;
1084 }
1085
1086 irq = pin_2_irq(idx, apic, pin);
1087 add_pin_to_irq(irq, apic, pin);
1088
1089 setup_IO_APIC_irq(apic, pin, irq,
1090 irq_trigger(idx), irq_polarity(idx));
1091 }
1092 }
1093
1094 if (!first_notcon)
1095 apic_printk(APIC_VERBOSE, " not connected.\n");
1096 }
1097
1098 /*
1099 * Set up the timer pin, possibly with the 8259A-master behind.
1100 */
1101 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1102 int vector)
1103 {
1104 struct IO_APIC_route_entry entry;
1105
1106 if (intr_remapping_enabled)
1107 return;
1108
1109 memset(&entry, 0, sizeof(entry));
1110
1111 /*
1112 * We use logical delivery to get the timer IRQ
1113 * to the first CPU.
1114 */
1115 entry.dest_mode = INT_DEST_MODE;
1116 entry.mask = 1; /* mask IRQ now */
1117 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1118 entry.delivery_mode = INT_DELIVERY_MODE;
1119 entry.polarity = 0;
1120 entry.trigger = 0;
1121 entry.vector = vector;
1122
1123 /*
1124 * The timer IRQ doesn't have to know that behind the
1125 * scene we may have a 8259A-master in AEOI mode ...
1126 */
1127 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1128
1129 /*
1130 * Add it to the IO-APIC irq-routing table:
1131 */
1132 ioapic_write_entry(apic, pin, entry);
1133 }
1134
1135
1136 __apicdebuginit(void) print_IO_APIC(void)
1137 {
1138 int apic, i;
1139 union IO_APIC_reg_00 reg_00;
1140 union IO_APIC_reg_01 reg_01;
1141 union IO_APIC_reg_02 reg_02;
1142 unsigned long flags;
1143
1144 if (apic_verbosity == APIC_QUIET)
1145 return;
1146
1147 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1148 for (i = 0; i < nr_ioapics; i++)
1149 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1150 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1151
1152 /*
1153 * We are a bit conservative about what we expect. We have to
1154 * know about every hardware change ASAP.
1155 */
1156 printk(KERN_INFO "testing the IO APIC.......................\n");
1157
1158 for (apic = 0; apic < nr_ioapics; apic++) {
1159
1160 spin_lock_irqsave(&ioapic_lock, flags);
1161 reg_00.raw = io_apic_read(apic, 0);
1162 reg_01.raw = io_apic_read(apic, 1);
1163 if (reg_01.bits.version >= 0x10)
1164 reg_02.raw = io_apic_read(apic, 2);
1165 spin_unlock_irqrestore(&ioapic_lock, flags);
1166
1167 printk("\n");
1168 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1169 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1170 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1171
1172 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1173 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1174
1175 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1176 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1177
1178 if (reg_01.bits.version >= 0x10) {
1179 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1180 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1181 }
1182
1183 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1184
1185 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1186 " Stat Dmod Deli Vect: \n");
1187
1188 for (i = 0; i <= reg_01.bits.entries; i++) {
1189 struct IO_APIC_route_entry entry;
1190
1191 entry = ioapic_read_entry(apic, i);
1192
1193 printk(KERN_DEBUG " %02x %03X ",
1194 i,
1195 entry.dest
1196 );
1197
1198 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1199 entry.mask,
1200 entry.trigger,
1201 entry.irr,
1202 entry.polarity,
1203 entry.delivery_status,
1204 entry.dest_mode,
1205 entry.delivery_mode,
1206 entry.vector
1207 );
1208 }
1209 }
1210 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1211 for (i = 0; i < nr_irqs; i++) {
1212 struct irq_pin_list *entry = irq_2_pin + i;
1213 if (entry->pin < 0)
1214 continue;
1215 printk(KERN_DEBUG "IRQ%d ", i);
1216 for (;;) {
1217 printk("-> %d:%d", entry->apic, entry->pin);
1218 if (!entry->next)
1219 break;
1220 entry = irq_2_pin + entry->next;
1221 }
1222 printk("\n");
1223 }
1224
1225 printk(KERN_INFO ".................................... done.\n");
1226
1227 return;
1228 }
1229
1230 __apicdebuginit(void) print_APIC_bitfield(int base)
1231 {
1232 unsigned int v;
1233 int i, j;
1234
1235 if (apic_verbosity == APIC_QUIET)
1236 return;
1237
1238 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1239 for (i = 0; i < 8; i++) {
1240 v = apic_read(base + i*0x10);
1241 for (j = 0; j < 32; j++) {
1242 if (v & (1<<j))
1243 printk("1");
1244 else
1245 printk("0");
1246 }
1247 printk("\n");
1248 }
1249 }
1250
1251 __apicdebuginit(void) print_local_APIC(void *dummy)
1252 {
1253 unsigned int v, ver, maxlvt;
1254 unsigned long icr;
1255
1256 if (apic_verbosity == APIC_QUIET)
1257 return;
1258
1259 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1260 smp_processor_id(), hard_smp_processor_id());
1261 v = apic_read(APIC_ID);
1262 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1263 v = apic_read(APIC_LVR);
1264 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1265 ver = GET_APIC_VERSION(v);
1266 maxlvt = lapic_get_maxlvt();
1267
1268 v = apic_read(APIC_TASKPRI);
1269 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1270
1271 v = apic_read(APIC_ARBPRI);
1272 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1273 v & APIC_ARBPRI_MASK);
1274 v = apic_read(APIC_PROCPRI);
1275 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1276
1277 v = apic_read(APIC_EOI);
1278 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1279 v = apic_read(APIC_RRR);
1280 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1281 v = apic_read(APIC_LDR);
1282 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1283 v = apic_read(APIC_DFR);
1284 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1285 v = apic_read(APIC_SPIV);
1286 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1287
1288 printk(KERN_DEBUG "... APIC ISR field:\n");
1289 print_APIC_bitfield(APIC_ISR);
1290 printk(KERN_DEBUG "... APIC TMR field:\n");
1291 print_APIC_bitfield(APIC_TMR);
1292 printk(KERN_DEBUG "... APIC IRR field:\n");
1293 print_APIC_bitfield(APIC_IRR);
1294
1295 v = apic_read(APIC_ESR);
1296 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1297
1298 icr = apic_icr_read();
1299 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1300 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1301
1302 v = apic_read(APIC_LVTT);
1303 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1304
1305 if (maxlvt > 3) { /* PC is LVT#4. */
1306 v = apic_read(APIC_LVTPC);
1307 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1308 }
1309 v = apic_read(APIC_LVT0);
1310 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1311 v = apic_read(APIC_LVT1);
1312 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1313
1314 if (maxlvt > 2) { /* ERR is LVT#3. */
1315 v = apic_read(APIC_LVTERR);
1316 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1317 }
1318
1319 v = apic_read(APIC_TMICT);
1320 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1321 v = apic_read(APIC_TMCCT);
1322 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1323 v = apic_read(APIC_TDCR);
1324 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1325 printk("\n");
1326 }
1327
1328 __apicdebuginit(void) print_all_local_APICs(void)
1329 {
1330 on_each_cpu(print_local_APIC, NULL, 1);
1331 }
1332
1333 __apicdebuginit(void) print_PIC(void)
1334 {
1335 unsigned int v;
1336 unsigned long flags;
1337
1338 if (apic_verbosity == APIC_QUIET)
1339 return;
1340
1341 printk(KERN_DEBUG "\nprinting PIC contents\n");
1342
1343 spin_lock_irqsave(&i8259A_lock, flags);
1344
1345 v = inb(0xa1) << 8 | inb(0x21);
1346 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1347
1348 v = inb(0xa0) << 8 | inb(0x20);
1349 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1350
1351 outb(0x0b,0xa0);
1352 outb(0x0b,0x20);
1353 v = inb(0xa0) << 8 | inb(0x20);
1354 outb(0x0a,0xa0);
1355 outb(0x0a,0x20);
1356
1357 spin_unlock_irqrestore(&i8259A_lock, flags);
1358
1359 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1360
1361 v = inb(0x4d1) << 8 | inb(0x4d0);
1362 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1363 }
1364
1365 __apicdebuginit(int) print_all_ICs(void)
1366 {
1367 print_PIC();
1368 print_all_local_APICs();
1369 print_IO_APIC();
1370
1371 return 0;
1372 }
1373
1374 fs_initcall(print_all_ICs);
1375
1376
1377 void __init enable_IO_APIC(void)
1378 {
1379 union IO_APIC_reg_01 reg_01;
1380 int i8259_apic, i8259_pin;
1381 int i, apic;
1382 unsigned long flags;
1383
1384 for (i = 0; i < pin_map_size; i++) {
1385 irq_2_pin[i].pin = -1;
1386 irq_2_pin[i].next = 0;
1387 }
1388
1389 /*
1390 * The number of IO-APIC IRQ registers (== #pins):
1391 */
1392 for (apic = 0; apic < nr_ioapics; apic++) {
1393 spin_lock_irqsave(&ioapic_lock, flags);
1394 reg_01.raw = io_apic_read(apic, 1);
1395 spin_unlock_irqrestore(&ioapic_lock, flags);
1396 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1397 }
1398 for(apic = 0; apic < nr_ioapics; apic++) {
1399 int pin;
1400 /* See if any of the pins is in ExtINT mode */
1401 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1402 struct IO_APIC_route_entry entry;
1403 entry = ioapic_read_entry(apic, pin);
1404
1405 /* If the interrupt line is enabled and in ExtInt mode
1406 * I have found the pin where the i8259 is connected.
1407 */
1408 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1409 ioapic_i8259.apic = apic;
1410 ioapic_i8259.pin = pin;
1411 goto found_i8259;
1412 }
1413 }
1414 }
1415 found_i8259:
1416 /* Look to see what if the MP table has reported the ExtINT */
1417 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1418 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1419 /* Trust the MP table if nothing is setup in the hardware */
1420 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1421 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1422 ioapic_i8259.pin = i8259_pin;
1423 ioapic_i8259.apic = i8259_apic;
1424 }
1425 /* Complain if the MP table and the hardware disagree */
1426 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1427 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1428 {
1429 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1430 }
1431
1432 /*
1433 * Do not trust the IO-APIC being empty at bootup
1434 */
1435 clear_IO_APIC();
1436 }
1437
1438 /*
1439 * Not an __init, needed by the reboot code
1440 */
1441 void disable_IO_APIC(void)
1442 {
1443 /*
1444 * Clear the IO-APIC before rebooting:
1445 */
1446 clear_IO_APIC();
1447
1448 /*
1449 * If the i8259 is routed through an IOAPIC
1450 * Put that IOAPIC in virtual wire mode
1451 * so legacy interrupts can be delivered.
1452 */
1453 if (ioapic_i8259.pin != -1) {
1454 struct IO_APIC_route_entry entry;
1455
1456 memset(&entry, 0, sizeof(entry));
1457 entry.mask = 0; /* Enabled */
1458 entry.trigger = 0; /* Edge */
1459 entry.irr = 0;
1460 entry.polarity = 0; /* High */
1461 entry.delivery_status = 0;
1462 entry.dest_mode = 0; /* Physical */
1463 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1464 entry.vector = 0;
1465 entry.dest = read_apic_id();
1466
1467 /*
1468 * Add it to the IO-APIC irq-routing table:
1469 */
1470 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1471 }
1472
1473 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1474 }
1475
1476 /*
1477 * There is a nasty bug in some older SMP boards, their mptable lies
1478 * about the timer IRQ. We do the following to work around the situation:
1479 *
1480 * - timer IRQ defaults to IO-APIC IRQ
1481 * - if this function detects that timer IRQs are defunct, then we fall
1482 * back to ISA timer IRQs
1483 */
1484 static int __init timer_irq_works(void)
1485 {
1486 unsigned long t1 = jiffies;
1487 unsigned long flags;
1488
1489 local_save_flags(flags);
1490 local_irq_enable();
1491 /* Let ten ticks pass... */
1492 mdelay((10 * 1000) / HZ);
1493 local_irq_restore(flags);
1494
1495 /*
1496 * Expect a few ticks at least, to be sure some possible
1497 * glue logic does not lock up after one or two first
1498 * ticks in a non-ExtINT mode. Also the local APIC
1499 * might have cached one ExtINT interrupt. Finally, at
1500 * least one tick may be lost due to delays.
1501 */
1502
1503 /* jiffies wrap? */
1504 if (time_after(jiffies, t1 + 4))
1505 return 1;
1506 return 0;
1507 }
1508
1509 /*
1510 * In the SMP+IOAPIC case it might happen that there are an unspecified
1511 * number of pending IRQ events unhandled. These cases are very rare,
1512 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1513 * better to do it this way as thus we do not have to be aware of
1514 * 'pending' interrupts in the IRQ path, except at this point.
1515 */
1516 /*
1517 * Edge triggered needs to resend any interrupt
1518 * that was delayed but this is now handled in the device
1519 * independent code.
1520 */
1521
1522 /*
1523 * Starting up a edge-triggered IO-APIC interrupt is
1524 * nasty - we need to make sure that we get the edge.
1525 * If it is already asserted for some reason, we need
1526 * return 1 to indicate that is was pending.
1527 *
1528 * This is not complete - we should be able to fake
1529 * an edge even if it isn't on the 8259A...
1530 */
1531
1532 static unsigned int startup_ioapic_irq(unsigned int irq)
1533 {
1534 int was_pending = 0;
1535 unsigned long flags;
1536
1537 spin_lock_irqsave(&ioapic_lock, flags);
1538 if (irq < 16) {
1539 disable_8259A_irq(irq);
1540 if (i8259A_irq_pending(irq))
1541 was_pending = 1;
1542 }
1543 __unmask_IO_APIC_irq(irq);
1544 spin_unlock_irqrestore(&ioapic_lock, flags);
1545
1546 return was_pending;
1547 }
1548
1549 static int ioapic_retrigger_irq(unsigned int irq)
1550 {
1551 struct irq_cfg *cfg = &irq_cfg[irq];
1552 unsigned long flags;
1553
1554 spin_lock_irqsave(&vector_lock, flags);
1555 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1556 spin_unlock_irqrestore(&vector_lock, flags);
1557
1558 return 1;
1559 }
1560
1561 /*
1562 * Level and edge triggered IO-APIC interrupts need different handling,
1563 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1564 * handled with the level-triggered descriptor, but that one has slightly
1565 * more overhead. Level-triggered interrupts cannot be handled with the
1566 * edge-triggered handler, without risking IRQ storms and other ugly
1567 * races.
1568 */
1569
1570 #ifdef CONFIG_SMP
1571
1572 #ifdef CONFIG_INTR_REMAP
1573 static void ir_irq_migration(struct work_struct *work);
1574
1575 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1576
1577 /*
1578 * Migrate the IO-APIC irq in the presence of intr-remapping.
1579 *
1580 * For edge triggered, irq migration is a simple atomic update(of vector
1581 * and cpu destination) of IRTE and flush the hardware cache.
1582 *
1583 * For level triggered, we need to modify the io-apic RTE aswell with the update
1584 * vector information, along with modifying IRTE with vector and destination.
1585 * So irq migration for level triggered is little bit more complex compared to
1586 * edge triggered migration. But the good news is, we use the same algorithm
1587 * for level triggered migration as we have today, only difference being,
1588 * we now initiate the irq migration from process context instead of the
1589 * interrupt context.
1590 *
1591 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1592 * suppression) to the IO-APIC, level triggered irq migration will also be
1593 * as simple as edge triggered migration and we can do the irq migration
1594 * with a simple atomic update to IO-APIC RTE.
1595 */
1596 static void migrate_ioapic_irq(int irq, cpumask_t mask)
1597 {
1598 struct irq_cfg *cfg = irq_cfg + irq;
1599 struct irq_desc *desc = irq_desc + irq;
1600 cpumask_t tmp, cleanup_mask;
1601 struct irte irte;
1602 int modify_ioapic_rte = desc->status & IRQ_LEVEL;
1603 unsigned int dest;
1604 unsigned long flags;
1605
1606 cpus_and(tmp, mask, cpu_online_map);
1607 if (cpus_empty(tmp))
1608 return;
1609
1610 if (get_irte(irq, &irte))
1611 return;
1612
1613 if (assign_irq_vector(irq, mask))
1614 return;
1615
1616 cpus_and(tmp, cfg->domain, mask);
1617 dest = cpu_mask_to_apicid(tmp);
1618
1619 if (modify_ioapic_rte) {
1620 spin_lock_irqsave(&ioapic_lock, flags);
1621 __target_IO_APIC_irq(irq, dest, cfg->vector);
1622 spin_unlock_irqrestore(&ioapic_lock, flags);
1623 }
1624
1625 irte.vector = cfg->vector;
1626 irte.dest_id = IRTE_DEST(dest);
1627
1628 /*
1629 * Modified the IRTE and flushes the Interrupt entry cache.
1630 */
1631 modify_irte(irq, &irte);
1632
1633 if (cfg->move_in_progress) {
1634 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1635 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1636 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1637 cfg->move_in_progress = 0;
1638 }
1639
1640 irq_desc[irq].affinity = mask;
1641 }
1642
1643 static int migrate_irq_remapped_level(int irq)
1644 {
1645 int ret = -1;
1646
1647 mask_IO_APIC_irq(irq);
1648
1649 if (io_apic_level_ack_pending(irq)) {
1650 /*
1651 * Interrupt in progress. Migrating irq now will change the
1652 * vector information in the IO-APIC RTE and that will confuse
1653 * the EOI broadcast performed by cpu.
1654 * So, delay the irq migration to the next instance.
1655 */
1656 schedule_delayed_work(&ir_migration_work, 1);
1657 goto unmask;
1658 }
1659
1660 /* everthing is clear. we have right of way */
1661 migrate_ioapic_irq(irq, irq_desc[irq].pending_mask);
1662
1663 ret = 0;
1664 irq_desc[irq].status &= ~IRQ_MOVE_PENDING;
1665 cpus_clear(irq_desc[irq].pending_mask);
1666
1667 unmask:
1668 unmask_IO_APIC_irq(irq);
1669 return ret;
1670 }
1671
1672 static void ir_irq_migration(struct work_struct *work)
1673 {
1674 int irq;
1675
1676 for (irq = 0; irq < nr_irqs; irq++) {
1677 struct irq_desc *desc = irq_desc + irq;
1678 if (desc->status & IRQ_MOVE_PENDING) {
1679 unsigned long flags;
1680
1681 spin_lock_irqsave(&desc->lock, flags);
1682 if (!desc->chip->set_affinity ||
1683 !(desc->status & IRQ_MOVE_PENDING)) {
1684 desc->status &= ~IRQ_MOVE_PENDING;
1685 spin_unlock_irqrestore(&desc->lock, flags);
1686 continue;
1687 }
1688
1689 desc->chip->set_affinity(irq,
1690 irq_desc[irq].pending_mask);
1691 spin_unlock_irqrestore(&desc->lock, flags);
1692 }
1693 }
1694 }
1695
1696 /*
1697 * Migrates the IRQ destination in the process context.
1698 */
1699 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1700 {
1701 if (irq_desc[irq].status & IRQ_LEVEL) {
1702 irq_desc[irq].status |= IRQ_MOVE_PENDING;
1703 irq_desc[irq].pending_mask = mask;
1704 migrate_irq_remapped_level(irq);
1705 return;
1706 }
1707
1708 migrate_ioapic_irq(irq, mask);
1709 }
1710 #endif
1711
1712 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1713 {
1714 unsigned vector, me;
1715 ack_APIC_irq();
1716 exit_idle();
1717 irq_enter();
1718
1719 me = smp_processor_id();
1720 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1721 unsigned int irq;
1722 struct irq_desc *desc;
1723 struct irq_cfg *cfg;
1724 irq = __get_cpu_var(vector_irq)[vector];
1725 if (irq >= nr_irqs)
1726 continue;
1727
1728 desc = irq_desc + irq;
1729 cfg = irq_cfg + irq;
1730 spin_lock(&desc->lock);
1731 if (!cfg->move_cleanup_count)
1732 goto unlock;
1733
1734 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1735 goto unlock;
1736
1737 __get_cpu_var(vector_irq)[vector] = -1;
1738 cfg->move_cleanup_count--;
1739 unlock:
1740 spin_unlock(&desc->lock);
1741 }
1742
1743 irq_exit();
1744 }
1745
1746 static void irq_complete_move(unsigned int irq)
1747 {
1748 struct irq_cfg *cfg = irq_cfg + irq;
1749 unsigned vector, me;
1750
1751 if (likely(!cfg->move_in_progress))
1752 return;
1753
1754 vector = ~get_irq_regs()->orig_ax;
1755 me = smp_processor_id();
1756 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1757 cpumask_t cleanup_mask;
1758
1759 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1760 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1761 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1762 cfg->move_in_progress = 0;
1763 }
1764 }
1765 #else
1766 static inline void irq_complete_move(unsigned int irq) {}
1767 #endif
1768 #ifdef CONFIG_INTR_REMAP
1769 static void ack_x2apic_level(unsigned int irq)
1770 {
1771 ack_x2APIC_irq();
1772 }
1773
1774 static void ack_x2apic_edge(unsigned int irq)
1775 {
1776 ack_x2APIC_irq();
1777 }
1778 #endif
1779
1780 static void ack_apic_edge(unsigned int irq)
1781 {
1782 irq_complete_move(irq);
1783 move_native_irq(irq);
1784 ack_APIC_irq();
1785 }
1786
1787 static void ack_apic_level(unsigned int irq)
1788 {
1789 int do_unmask_irq = 0;
1790
1791 irq_complete_move(irq);
1792 #ifdef CONFIG_GENERIC_PENDING_IRQ
1793 /* If we are moving the irq we need to mask it */
1794 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1795 do_unmask_irq = 1;
1796 mask_IO_APIC_irq(irq);
1797 }
1798 #endif
1799
1800 /*
1801 * We must acknowledge the irq before we move it or the acknowledge will
1802 * not propagate properly.
1803 */
1804 ack_APIC_irq();
1805
1806 /* Now we can move and renable the irq */
1807 if (unlikely(do_unmask_irq)) {
1808 /* Only migrate the irq if the ack has been received.
1809 *
1810 * On rare occasions the broadcast level triggered ack gets
1811 * delayed going to ioapics, and if we reprogram the
1812 * vector while Remote IRR is still set the irq will never
1813 * fire again.
1814 *
1815 * To prevent this scenario we read the Remote IRR bit
1816 * of the ioapic. This has two effects.
1817 * - On any sane system the read of the ioapic will
1818 * flush writes (and acks) going to the ioapic from
1819 * this cpu.
1820 * - We get to see if the ACK has actually been delivered.
1821 *
1822 * Based on failed experiments of reprogramming the
1823 * ioapic entry from outside of irq context starting
1824 * with masking the ioapic entry and then polling until
1825 * Remote IRR was clear before reprogramming the
1826 * ioapic I don't trust the Remote IRR bit to be
1827 * completey accurate.
1828 *
1829 * However there appears to be no other way to plug
1830 * this race, so if the Remote IRR bit is not
1831 * accurate and is causing problems then it is a hardware bug
1832 * and you can go talk to the chipset vendor about it.
1833 */
1834 if (!io_apic_level_ack_pending(irq))
1835 move_masked_irq(irq);
1836 unmask_IO_APIC_irq(irq);
1837 }
1838 }
1839
1840 static struct irq_chip ioapic_chip __read_mostly = {
1841 .name = "IO-APIC",
1842 .startup = startup_ioapic_irq,
1843 .mask = mask_IO_APIC_irq,
1844 .unmask = unmask_IO_APIC_irq,
1845 .ack = ack_apic_edge,
1846 .eoi = ack_apic_level,
1847 #ifdef CONFIG_SMP
1848 .set_affinity = set_ioapic_affinity_irq,
1849 #endif
1850 .retrigger = ioapic_retrigger_irq,
1851 };
1852
1853 #ifdef CONFIG_INTR_REMAP
1854 static struct irq_chip ir_ioapic_chip __read_mostly = {
1855 .name = "IR-IO-APIC",
1856 .startup = startup_ioapic_irq,
1857 .mask = mask_IO_APIC_irq,
1858 .unmask = unmask_IO_APIC_irq,
1859 .ack = ack_x2apic_edge,
1860 .eoi = ack_x2apic_level,
1861 #ifdef CONFIG_SMP
1862 .set_affinity = set_ir_ioapic_affinity_irq,
1863 #endif
1864 .retrigger = ioapic_retrigger_irq,
1865 };
1866 #endif
1867
1868 static inline void init_IO_APIC_traps(void)
1869 {
1870 int irq;
1871
1872 /*
1873 * NOTE! The local APIC isn't very good at handling
1874 * multiple interrupts at the same interrupt level.
1875 * As the interrupt level is determined by taking the
1876 * vector number and shifting that right by 4, we
1877 * want to spread these out a bit so that they don't
1878 * all fall in the same interrupt level.
1879 *
1880 * Also, we've got to be careful not to trash gate
1881 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1882 */
1883 for (irq = 0; irq < nr_irqs ; irq++) {
1884 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1885 /*
1886 * Hmm.. We don't have an entry for this,
1887 * so default to an old-fashioned 8259
1888 * interrupt if we can..
1889 */
1890 if (irq < 16)
1891 make_8259A_irq(irq);
1892 else
1893 /* Strange. Oh, well.. */
1894 irq_desc[irq].chip = &no_irq_chip;
1895 }
1896 }
1897 }
1898
1899 static void unmask_lapic_irq(unsigned int irq)
1900 {
1901 unsigned long v;
1902
1903 v = apic_read(APIC_LVT0);
1904 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1905 }
1906
1907 static void mask_lapic_irq(unsigned int irq)
1908 {
1909 unsigned long v;
1910
1911 v = apic_read(APIC_LVT0);
1912 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1913 }
1914
1915 static void ack_lapic_irq (unsigned int irq)
1916 {
1917 ack_APIC_irq();
1918 }
1919
1920 static struct irq_chip lapic_chip __read_mostly = {
1921 .name = "local-APIC",
1922 .mask = mask_lapic_irq,
1923 .unmask = unmask_lapic_irq,
1924 .ack = ack_lapic_irq,
1925 };
1926
1927 static void lapic_register_intr(int irq)
1928 {
1929 irq_desc[irq].status &= ~IRQ_LEVEL;
1930 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1931 "edge");
1932 }
1933
1934 static void __init setup_nmi(void)
1935 {
1936 /*
1937 * Dirty trick to enable the NMI watchdog ...
1938 * We put the 8259A master into AEOI mode and
1939 * unmask on all local APICs LVT0 as NMI.
1940 *
1941 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1942 * is from Maciej W. Rozycki - so we do not have to EOI from
1943 * the NMI handler or the timer interrupt.
1944 */
1945 printk(KERN_INFO "activating NMI Watchdog ...");
1946
1947 enable_NMI_through_LVT0();
1948
1949 printk(" done.\n");
1950 }
1951
1952 /*
1953 * This looks a bit hackish but it's about the only one way of sending
1954 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1955 * not support the ExtINT mode, unfortunately. We need to send these
1956 * cycles as some i82489DX-based boards have glue logic that keeps the
1957 * 8259A interrupt line asserted until INTA. --macro
1958 */
1959 static inline void __init unlock_ExtINT_logic(void)
1960 {
1961 int apic, pin, i;
1962 struct IO_APIC_route_entry entry0, entry1;
1963 unsigned char save_control, save_freq_select;
1964
1965 pin = find_isa_irq_pin(8, mp_INT);
1966 apic = find_isa_irq_apic(8, mp_INT);
1967 if (pin == -1)
1968 return;
1969
1970 entry0 = ioapic_read_entry(apic, pin);
1971
1972 clear_IO_APIC_pin(apic, pin);
1973
1974 memset(&entry1, 0, sizeof(entry1));
1975
1976 entry1.dest_mode = 0; /* physical delivery */
1977 entry1.mask = 0; /* unmask IRQ now */
1978 entry1.dest = hard_smp_processor_id();
1979 entry1.delivery_mode = dest_ExtINT;
1980 entry1.polarity = entry0.polarity;
1981 entry1.trigger = 0;
1982 entry1.vector = 0;
1983
1984 ioapic_write_entry(apic, pin, entry1);
1985
1986 save_control = CMOS_READ(RTC_CONTROL);
1987 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1988 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1989 RTC_FREQ_SELECT);
1990 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1991
1992 i = 100;
1993 while (i-- > 0) {
1994 mdelay(10);
1995 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1996 i -= 10;
1997 }
1998
1999 CMOS_WRITE(save_control, RTC_CONTROL);
2000 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2001 clear_IO_APIC_pin(apic, pin);
2002
2003 ioapic_write_entry(apic, pin, entry0);
2004 }
2005
2006 /*
2007 * This code may look a bit paranoid, but it's supposed to cooperate with
2008 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2009 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2010 * fanatically on his truly buggy board.
2011 *
2012 * FIXME: really need to revamp this for modern platforms only.
2013 */
2014 static inline void __init check_timer(void)
2015 {
2016 struct irq_cfg *cfg = irq_cfg + 0;
2017 int apic1, pin1, apic2, pin2;
2018 unsigned long flags;
2019 int no_pin1 = 0;
2020
2021 local_irq_save(flags);
2022
2023 /*
2024 * get/set the timer IRQ vector:
2025 */
2026 disable_8259A_irq(0);
2027 assign_irq_vector(0, TARGET_CPUS);
2028
2029 /*
2030 * As IRQ0 is to be enabled in the 8259A, the virtual
2031 * wire has to be disabled in the local APIC.
2032 */
2033 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2034 init_8259A(1);
2035
2036 pin1 = find_isa_irq_pin(0, mp_INT);
2037 apic1 = find_isa_irq_apic(0, mp_INT);
2038 pin2 = ioapic_i8259.pin;
2039 apic2 = ioapic_i8259.apic;
2040
2041 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2042 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2043 cfg->vector, apic1, pin1, apic2, pin2);
2044
2045 /*
2046 * Some BIOS writers are clueless and report the ExtINTA
2047 * I/O APIC input from the cascaded 8259A as the timer
2048 * interrupt input. So just in case, if only one pin
2049 * was found above, try it both directly and through the
2050 * 8259A.
2051 */
2052 if (pin1 == -1) {
2053 if (intr_remapping_enabled)
2054 panic("BIOS bug: timer not connected to IO-APIC");
2055 pin1 = pin2;
2056 apic1 = apic2;
2057 no_pin1 = 1;
2058 } else if (pin2 == -1) {
2059 pin2 = pin1;
2060 apic2 = apic1;
2061 }
2062
2063 if (pin1 != -1) {
2064 /*
2065 * Ok, does IRQ0 through the IOAPIC work?
2066 */
2067 if (no_pin1) {
2068 add_pin_to_irq(0, apic1, pin1);
2069 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2070 }
2071 unmask_IO_APIC_irq(0);
2072 if (!no_timer_check && timer_irq_works()) {
2073 if (nmi_watchdog == NMI_IO_APIC) {
2074 setup_nmi();
2075 enable_8259A_irq(0);
2076 }
2077 if (disable_timer_pin_1 > 0)
2078 clear_IO_APIC_pin(0, pin1);
2079 goto out;
2080 }
2081 if (intr_remapping_enabled)
2082 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2083 clear_IO_APIC_pin(apic1, pin1);
2084 if (!no_pin1)
2085 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2086 "8254 timer not connected to IO-APIC\n");
2087
2088 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2089 "(IRQ0) through the 8259A ...\n");
2090 apic_printk(APIC_QUIET, KERN_INFO
2091 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2092 /*
2093 * legacy devices should be connected to IO APIC #0
2094 */
2095 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2096 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2097 unmask_IO_APIC_irq(0);
2098 enable_8259A_irq(0);
2099 if (timer_irq_works()) {
2100 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2101 timer_through_8259 = 1;
2102 if (nmi_watchdog == NMI_IO_APIC) {
2103 disable_8259A_irq(0);
2104 setup_nmi();
2105 enable_8259A_irq(0);
2106 }
2107 goto out;
2108 }
2109 /*
2110 * Cleanup, just in case ...
2111 */
2112 disable_8259A_irq(0);
2113 clear_IO_APIC_pin(apic2, pin2);
2114 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2115 }
2116
2117 if (nmi_watchdog == NMI_IO_APIC) {
2118 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2119 "through the IO-APIC - disabling NMI Watchdog!\n");
2120 nmi_watchdog = NMI_NONE;
2121 }
2122
2123 apic_printk(APIC_QUIET, KERN_INFO
2124 "...trying to set up timer as Virtual Wire IRQ...\n");
2125
2126 lapic_register_intr(0);
2127 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2128 enable_8259A_irq(0);
2129
2130 if (timer_irq_works()) {
2131 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2132 goto out;
2133 }
2134 disable_8259A_irq(0);
2135 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2136 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2137
2138 apic_printk(APIC_QUIET, KERN_INFO
2139 "...trying to set up timer as ExtINT IRQ...\n");
2140
2141 init_8259A(0);
2142 make_8259A_irq(0);
2143 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2144
2145 unlock_ExtINT_logic();
2146
2147 if (timer_irq_works()) {
2148 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2149 goto out;
2150 }
2151 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2152 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2153 "report. Then try booting with the 'noapic' option.\n");
2154 out:
2155 local_irq_restore(flags);
2156 }
2157
2158 static int __init notimercheck(char *s)
2159 {
2160 no_timer_check = 1;
2161 return 1;
2162 }
2163 __setup("no_timer_check", notimercheck);
2164
2165 /*
2166 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2167 * to devices. However there may be an I/O APIC pin available for
2168 * this interrupt regardless. The pin may be left unconnected, but
2169 * typically it will be reused as an ExtINT cascade interrupt for
2170 * the master 8259A. In the MPS case such a pin will normally be
2171 * reported as an ExtINT interrupt in the MP table. With ACPI
2172 * there is no provision for ExtINT interrupts, and in the absence
2173 * of an override it would be treated as an ordinary ISA I/O APIC
2174 * interrupt, that is edge-triggered and unmasked by default. We
2175 * used to do this, but it caused problems on some systems because
2176 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2177 * the same ExtINT cascade interrupt to drive the local APIC of the
2178 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2179 * the I/O APIC in all cases now. No actual device should request
2180 * it anyway. --macro
2181 */
2182 #define PIC_IRQS (1<<2)
2183
2184 void __init setup_IO_APIC(void)
2185 {
2186
2187 /*
2188 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2189 */
2190
2191 io_apic_irqs = ~PIC_IRQS;
2192
2193 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2194
2195 sync_Arb_IDs();
2196 setup_IO_APIC_irqs();
2197 init_IO_APIC_traps();
2198 check_timer();
2199 }
2200
2201 struct sysfs_ioapic_data {
2202 struct sys_device dev;
2203 struct IO_APIC_route_entry entry[0];
2204 };
2205 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2206
2207 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2208 {
2209 struct IO_APIC_route_entry *entry;
2210 struct sysfs_ioapic_data *data;
2211 int i;
2212
2213 data = container_of(dev, struct sysfs_ioapic_data, dev);
2214 entry = data->entry;
2215 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2216 *entry = ioapic_read_entry(dev->id, i);
2217
2218 return 0;
2219 }
2220
2221 static int ioapic_resume(struct sys_device *dev)
2222 {
2223 struct IO_APIC_route_entry *entry;
2224 struct sysfs_ioapic_data *data;
2225 unsigned long flags;
2226 union IO_APIC_reg_00 reg_00;
2227 int i;
2228
2229 data = container_of(dev, struct sysfs_ioapic_data, dev);
2230 entry = data->entry;
2231
2232 spin_lock_irqsave(&ioapic_lock, flags);
2233 reg_00.raw = io_apic_read(dev->id, 0);
2234 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2235 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2236 io_apic_write(dev->id, 0, reg_00.raw);
2237 }
2238 spin_unlock_irqrestore(&ioapic_lock, flags);
2239 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2240 ioapic_write_entry(dev->id, i, entry[i]);
2241
2242 return 0;
2243 }
2244
2245 static struct sysdev_class ioapic_sysdev_class = {
2246 .name = "ioapic",
2247 .suspend = ioapic_suspend,
2248 .resume = ioapic_resume,
2249 };
2250
2251 static int __init ioapic_init_sysfs(void)
2252 {
2253 struct sys_device * dev;
2254 int i, size, error;
2255
2256 error = sysdev_class_register(&ioapic_sysdev_class);
2257 if (error)
2258 return error;
2259
2260 for (i = 0; i < nr_ioapics; i++ ) {
2261 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2262 * sizeof(struct IO_APIC_route_entry);
2263 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2264 if (!mp_ioapic_data[i]) {
2265 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2266 continue;
2267 }
2268 dev = &mp_ioapic_data[i]->dev;
2269 dev->id = i;
2270 dev->cls = &ioapic_sysdev_class;
2271 error = sysdev_register(dev);
2272 if (error) {
2273 kfree(mp_ioapic_data[i]);
2274 mp_ioapic_data[i] = NULL;
2275 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2276 continue;
2277 }
2278 }
2279
2280 return 0;
2281 }
2282
2283 device_initcall(ioapic_init_sysfs);
2284
2285 /*
2286 * Dynamic irq allocate and deallocation
2287 */
2288 int create_irq(void)
2289 {
2290 /* Allocate an unused irq */
2291 int irq;
2292 int new;
2293 unsigned long flags;
2294
2295 irq = -ENOSPC;
2296 spin_lock_irqsave(&vector_lock, flags);
2297 for (new = (nr_irqs - 1); new >= 0; new--) {
2298 if (platform_legacy_irq(new))
2299 continue;
2300 if (irq_cfg[new].vector != 0)
2301 continue;
2302 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2303 irq = new;
2304 break;
2305 }
2306 spin_unlock_irqrestore(&vector_lock, flags);
2307
2308 if (irq >= 0) {
2309 dynamic_irq_init(irq);
2310 }
2311 return irq;
2312 }
2313
2314 void destroy_irq(unsigned int irq)
2315 {
2316 unsigned long flags;
2317
2318 dynamic_irq_cleanup(irq);
2319
2320 #ifdef CONFIG_INTR_REMAP
2321 free_irte(irq);
2322 #endif
2323 spin_lock_irqsave(&vector_lock, flags);
2324 __clear_irq_vector(irq);
2325 spin_unlock_irqrestore(&vector_lock, flags);
2326 }
2327
2328 /*
2329 * MSI message composition
2330 */
2331 #ifdef CONFIG_PCI_MSI
2332 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2333 {
2334 struct irq_cfg *cfg = irq_cfg + irq;
2335 int err;
2336 unsigned dest;
2337 cpumask_t tmp;
2338
2339 tmp = TARGET_CPUS;
2340 err = assign_irq_vector(irq, tmp);
2341 if (err)
2342 return err;
2343
2344 cpus_and(tmp, cfg->domain, tmp);
2345 dest = cpu_mask_to_apicid(tmp);
2346
2347 #ifdef CONFIG_INTR_REMAP
2348 if (irq_remapped(irq)) {
2349 struct irte irte;
2350 int ir_index;
2351 u16 sub_handle;
2352
2353 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2354 BUG_ON(ir_index == -1);
2355
2356 memset (&irte, 0, sizeof(irte));
2357
2358 irte.present = 1;
2359 irte.dst_mode = INT_DEST_MODE;
2360 irte.trigger_mode = 0; /* edge */
2361 irte.dlvry_mode = INT_DELIVERY_MODE;
2362 irte.vector = cfg->vector;
2363 irte.dest_id = IRTE_DEST(dest);
2364
2365 modify_irte(irq, &irte);
2366
2367 msg->address_hi = MSI_ADDR_BASE_HI;
2368 msg->data = sub_handle;
2369 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2370 MSI_ADDR_IR_SHV |
2371 MSI_ADDR_IR_INDEX1(ir_index) |
2372 MSI_ADDR_IR_INDEX2(ir_index);
2373 } else
2374 #endif
2375 {
2376 msg->address_hi = MSI_ADDR_BASE_HI;
2377 msg->address_lo =
2378 MSI_ADDR_BASE_LO |
2379 ((INT_DEST_MODE == 0) ?
2380 MSI_ADDR_DEST_MODE_PHYSICAL:
2381 MSI_ADDR_DEST_MODE_LOGICAL) |
2382 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2383 MSI_ADDR_REDIRECTION_CPU:
2384 MSI_ADDR_REDIRECTION_LOWPRI) |
2385 MSI_ADDR_DEST_ID(dest);
2386
2387 msg->data =
2388 MSI_DATA_TRIGGER_EDGE |
2389 MSI_DATA_LEVEL_ASSERT |
2390 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2391 MSI_DATA_DELIVERY_FIXED:
2392 MSI_DATA_DELIVERY_LOWPRI) |
2393 MSI_DATA_VECTOR(cfg->vector);
2394 }
2395 return err;
2396 }
2397
2398 #ifdef CONFIG_SMP
2399 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2400 {
2401 struct irq_cfg *cfg = irq_cfg + irq;
2402 struct msi_msg msg;
2403 unsigned int dest;
2404 cpumask_t tmp;
2405
2406 cpus_and(tmp, mask, cpu_online_map);
2407 if (cpus_empty(tmp))
2408 return;
2409
2410 if (assign_irq_vector(irq, mask))
2411 return;
2412
2413 cpus_and(tmp, cfg->domain, mask);
2414 dest = cpu_mask_to_apicid(tmp);
2415
2416 read_msi_msg(irq, &msg);
2417
2418 msg.data &= ~MSI_DATA_VECTOR_MASK;
2419 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2420 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2421 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2422
2423 write_msi_msg(irq, &msg);
2424 irq_desc[irq].affinity = mask;
2425 }
2426
2427 #ifdef CONFIG_INTR_REMAP
2428 /*
2429 * Migrate the MSI irq to another cpumask. This migration is
2430 * done in the process context using interrupt-remapping hardware.
2431 */
2432 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2433 {
2434 struct irq_cfg *cfg = irq_cfg + irq;
2435 unsigned int dest;
2436 cpumask_t tmp, cleanup_mask;
2437 struct irte irte;
2438
2439 cpus_and(tmp, mask, cpu_online_map);
2440 if (cpus_empty(tmp))
2441 return;
2442
2443 if (get_irte(irq, &irte))
2444 return;
2445
2446 if (assign_irq_vector(irq, mask))
2447 return;
2448
2449 cpus_and(tmp, cfg->domain, mask);
2450 dest = cpu_mask_to_apicid(tmp);
2451
2452 irte.vector = cfg->vector;
2453 irte.dest_id = IRTE_DEST(dest);
2454
2455 /*
2456 * atomically update the IRTE with the new destination and vector.
2457 */
2458 modify_irte(irq, &irte);
2459
2460 /*
2461 * After this point, all the interrupts will start arriving
2462 * at the new destination. So, time to cleanup the previous
2463 * vector allocation.
2464 */
2465 if (cfg->move_in_progress) {
2466 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2467 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2468 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2469 cfg->move_in_progress = 0;
2470 }
2471
2472 irq_desc[irq].affinity = mask;
2473 }
2474 #endif
2475 #endif /* CONFIG_SMP */
2476
2477 /*
2478 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2479 * which implement the MSI or MSI-X Capability Structure.
2480 */
2481 static struct irq_chip msi_chip = {
2482 .name = "PCI-MSI",
2483 .unmask = unmask_msi_irq,
2484 .mask = mask_msi_irq,
2485 .ack = ack_apic_edge,
2486 #ifdef CONFIG_SMP
2487 .set_affinity = set_msi_irq_affinity,
2488 #endif
2489 .retrigger = ioapic_retrigger_irq,
2490 };
2491
2492 #ifdef CONFIG_INTR_REMAP
2493 static struct irq_chip msi_ir_chip = {
2494 .name = "IR-PCI-MSI",
2495 .unmask = unmask_msi_irq,
2496 .mask = mask_msi_irq,
2497 .ack = ack_x2apic_edge,
2498 #ifdef CONFIG_SMP
2499 .set_affinity = ir_set_msi_irq_affinity,
2500 #endif
2501 .retrigger = ioapic_retrigger_irq,
2502 };
2503
2504 /*
2505 * Map the PCI dev to the corresponding remapping hardware unit
2506 * and allocate 'nvec' consecutive interrupt-remapping table entries
2507 * in it.
2508 */
2509 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
2510 {
2511 struct intel_iommu *iommu;
2512 int index;
2513
2514 iommu = map_dev_to_ir(dev);
2515 if (!iommu) {
2516 printk(KERN_ERR
2517 "Unable to map PCI %s to iommu\n", pci_name(dev));
2518 return -ENOENT;
2519 }
2520
2521 index = alloc_irte(iommu, irq, nvec);
2522 if (index < 0) {
2523 printk(KERN_ERR
2524 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2525 pci_name(dev));
2526 return -ENOSPC;
2527 }
2528 return index;
2529 }
2530 #endif
2531
2532 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2533 {
2534 int ret;
2535 struct msi_msg msg;
2536
2537 ret = msi_compose_msg(dev, irq, &msg);
2538 if (ret < 0)
2539 return ret;
2540
2541 set_irq_msi(irq, desc);
2542 write_msi_msg(irq, &msg);
2543
2544 #ifdef CONFIG_INTR_REMAP
2545 if (irq_remapped(irq)) {
2546 struct irq_desc *desc = irq_desc + irq;
2547 /*
2548 * irq migration in process context
2549 */
2550 desc->status |= IRQ_MOVE_PCNTXT;
2551 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2552 } else
2553 #endif
2554 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2555
2556 return 0;
2557 }
2558
2559 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2560 {
2561 int irq, ret;
2562
2563 irq = create_irq();
2564 if (irq < 0)
2565 return irq;
2566
2567 #ifdef CONFIG_INTR_REMAP
2568 if (!intr_remapping_enabled)
2569 goto no_ir;
2570
2571 ret = msi_alloc_irte(dev, irq, 1);
2572 if (ret < 0)
2573 goto error;
2574 no_ir:
2575 #endif
2576 ret = setup_msi_irq(dev, desc, irq);
2577 if (ret < 0) {
2578 destroy_irq(irq);
2579 return ret;
2580 }
2581 return 0;
2582
2583 #ifdef CONFIG_INTR_REMAP
2584 error:
2585 destroy_irq(irq);
2586 return ret;
2587 #endif
2588 }
2589
2590 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2591 {
2592 int irq, ret, sub_handle;
2593 struct msi_desc *desc;
2594 #ifdef CONFIG_INTR_REMAP
2595 struct intel_iommu *iommu = 0;
2596 int index = 0;
2597 #endif
2598
2599 sub_handle = 0;
2600 list_for_each_entry(desc, &dev->msi_list, list) {
2601 irq = create_irq();
2602 if (irq < 0)
2603 return irq;
2604 #ifdef CONFIG_INTR_REMAP
2605 if (!intr_remapping_enabled)
2606 goto no_ir;
2607
2608 if (!sub_handle) {
2609 /*
2610 * allocate the consecutive block of IRTE's
2611 * for 'nvec'
2612 */
2613 index = msi_alloc_irte(dev, irq, nvec);
2614 if (index < 0) {
2615 ret = index;
2616 goto error;
2617 }
2618 } else {
2619 iommu = map_dev_to_ir(dev);
2620 if (!iommu) {
2621 ret = -ENOENT;
2622 goto error;
2623 }
2624 /*
2625 * setup the mapping between the irq and the IRTE
2626 * base index, the sub_handle pointing to the
2627 * appropriate interrupt remap table entry.
2628 */
2629 set_irte_irq(irq, iommu, index, sub_handle);
2630 }
2631 no_ir:
2632 #endif
2633 ret = setup_msi_irq(dev, desc, irq);
2634 if (ret < 0)
2635 goto error;
2636 sub_handle++;
2637 }
2638 return 0;
2639
2640 error:
2641 destroy_irq(irq);
2642 return ret;
2643 }
2644
2645 void arch_teardown_msi_irq(unsigned int irq)
2646 {
2647 destroy_irq(irq);
2648 }
2649
2650 #ifdef CONFIG_DMAR
2651 #ifdef CONFIG_SMP
2652 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2653 {
2654 struct irq_cfg *cfg = irq_cfg + irq;
2655 struct msi_msg msg;
2656 unsigned int dest;
2657 cpumask_t tmp;
2658
2659 cpus_and(tmp, mask, cpu_online_map);
2660 if (cpus_empty(tmp))
2661 return;
2662
2663 if (assign_irq_vector(irq, mask))
2664 return;
2665
2666 cpus_and(tmp, cfg->domain, mask);
2667 dest = cpu_mask_to_apicid(tmp);
2668
2669 dmar_msi_read(irq, &msg);
2670
2671 msg.data &= ~MSI_DATA_VECTOR_MASK;
2672 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2673 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2674 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2675
2676 dmar_msi_write(irq, &msg);
2677 irq_desc[irq].affinity = mask;
2678 }
2679 #endif /* CONFIG_SMP */
2680
2681 struct irq_chip dmar_msi_type = {
2682 .name = "DMAR_MSI",
2683 .unmask = dmar_msi_unmask,
2684 .mask = dmar_msi_mask,
2685 .ack = ack_apic_edge,
2686 #ifdef CONFIG_SMP
2687 .set_affinity = dmar_msi_set_affinity,
2688 #endif
2689 .retrigger = ioapic_retrigger_irq,
2690 };
2691
2692 int arch_setup_dmar_msi(unsigned int irq)
2693 {
2694 int ret;
2695 struct msi_msg msg;
2696
2697 ret = msi_compose_msg(NULL, irq, &msg);
2698 if (ret < 0)
2699 return ret;
2700 dmar_msi_write(irq, &msg);
2701 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2702 "edge");
2703 return 0;
2704 }
2705 #endif
2706
2707 #endif /* CONFIG_PCI_MSI */
2708 /*
2709 * Hypertransport interrupt support
2710 */
2711 #ifdef CONFIG_HT_IRQ
2712
2713 #ifdef CONFIG_SMP
2714
2715 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2716 {
2717 struct ht_irq_msg msg;
2718 fetch_ht_irq_msg(irq, &msg);
2719
2720 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2721 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2722
2723 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2724 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2725
2726 write_ht_irq_msg(irq, &msg);
2727 }
2728
2729 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2730 {
2731 struct irq_cfg *cfg = irq_cfg + irq;
2732 unsigned int dest;
2733 cpumask_t tmp;
2734
2735 cpus_and(tmp, mask, cpu_online_map);
2736 if (cpus_empty(tmp))
2737 return;
2738
2739 if (assign_irq_vector(irq, mask))
2740 return;
2741
2742 cpus_and(tmp, cfg->domain, mask);
2743 dest = cpu_mask_to_apicid(tmp);
2744
2745 target_ht_irq(irq, dest, cfg->vector);
2746 irq_desc[irq].affinity = mask;
2747 }
2748 #endif
2749
2750 static struct irq_chip ht_irq_chip = {
2751 .name = "PCI-HT",
2752 .mask = mask_ht_irq,
2753 .unmask = unmask_ht_irq,
2754 .ack = ack_apic_edge,
2755 #ifdef CONFIG_SMP
2756 .set_affinity = set_ht_irq_affinity,
2757 #endif
2758 .retrigger = ioapic_retrigger_irq,
2759 };
2760
2761 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2762 {
2763 struct irq_cfg *cfg = irq_cfg + irq;
2764 int err;
2765 cpumask_t tmp;
2766
2767 tmp = TARGET_CPUS;
2768 err = assign_irq_vector(irq, tmp);
2769 if (!err) {
2770 struct ht_irq_msg msg;
2771 unsigned dest;
2772
2773 cpus_and(tmp, cfg->domain, tmp);
2774 dest = cpu_mask_to_apicid(tmp);
2775
2776 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2777
2778 msg.address_lo =
2779 HT_IRQ_LOW_BASE |
2780 HT_IRQ_LOW_DEST_ID(dest) |
2781 HT_IRQ_LOW_VECTOR(cfg->vector) |
2782 ((INT_DEST_MODE == 0) ?
2783 HT_IRQ_LOW_DM_PHYSICAL :
2784 HT_IRQ_LOW_DM_LOGICAL) |
2785 HT_IRQ_LOW_RQEOI_EDGE |
2786 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2787 HT_IRQ_LOW_MT_FIXED :
2788 HT_IRQ_LOW_MT_ARBITRATED) |
2789 HT_IRQ_LOW_IRQ_MASKED;
2790
2791 write_ht_irq_msg(irq, &msg);
2792
2793 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2794 handle_edge_irq, "edge");
2795 }
2796 return err;
2797 }
2798 #endif /* CONFIG_HT_IRQ */
2799
2800 /* --------------------------------------------------------------------------
2801 ACPI-based IOAPIC Configuration
2802 -------------------------------------------------------------------------- */
2803
2804 #ifdef CONFIG_ACPI
2805
2806 #define IO_APIC_MAX_ID 0xFE
2807
2808 int __init io_apic_get_redir_entries (int ioapic)
2809 {
2810 union IO_APIC_reg_01 reg_01;
2811 unsigned long flags;
2812
2813 spin_lock_irqsave(&ioapic_lock, flags);
2814 reg_01.raw = io_apic_read(ioapic, 1);
2815 spin_unlock_irqrestore(&ioapic_lock, flags);
2816
2817 return reg_01.bits.entries;
2818 }
2819
2820
2821 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2822 {
2823 if (!IO_APIC_IRQ(irq)) {
2824 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2825 ioapic);
2826 return -EINVAL;
2827 }
2828
2829 /*
2830 * IRQs < 16 are already in the irq_2_pin[] map
2831 */
2832 if (irq >= 16)
2833 add_pin_to_irq(irq, ioapic, pin);
2834
2835 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2836
2837 return 0;
2838 }
2839
2840
2841 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2842 {
2843 int i;
2844
2845 if (skip_ioapic_setup)
2846 return -1;
2847
2848 for (i = 0; i < mp_irq_entries; i++)
2849 if (mp_irqs[i].mp_irqtype == mp_INT &&
2850 mp_irqs[i].mp_srcbusirq == bus_irq)
2851 break;
2852 if (i >= mp_irq_entries)
2853 return -1;
2854
2855 *trigger = irq_trigger(i);
2856 *polarity = irq_polarity(i);
2857 return 0;
2858 }
2859
2860 #endif /* CONFIG_ACPI */
2861
2862 /*
2863 * This function currently is only a helper for the i386 smp boot process where
2864 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2865 * so mask in all cases should simply be TARGET_CPUS
2866 */
2867 #ifdef CONFIG_SMP
2868 void __init setup_ioapic_dest(void)
2869 {
2870 int pin, ioapic, irq, irq_entry;
2871
2872 if (skip_ioapic_setup == 1)
2873 return;
2874
2875 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2876 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2877 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2878 if (irq_entry == -1)
2879 continue;
2880 irq = pin_2_irq(irq_entry, ioapic, pin);
2881
2882 /* setup_IO_APIC_irqs could fail to get vector for some device
2883 * when you have too many devices, because at that time only boot
2884 * cpu is online.
2885 */
2886 if (!irq_cfg[irq].vector)
2887 setup_IO_APIC_irq(ioapic, pin, irq,
2888 irq_trigger(irq_entry),
2889 irq_polarity(irq_entry));
2890 #ifdef CONFIG_INTR_REMAP
2891 else if (intr_remapping_enabled)
2892 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
2893 #endif
2894 else
2895 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2896 }
2897
2898 }
2899 }
2900 #endif
2901
2902 #define IOAPIC_RESOURCE_NAME_SIZE 11
2903
2904 static struct resource *ioapic_resources;
2905
2906 static struct resource * __init ioapic_setup_resources(void)
2907 {
2908 unsigned long n;
2909 struct resource *res;
2910 char *mem;
2911 int i;
2912
2913 if (nr_ioapics <= 0)
2914 return NULL;
2915
2916 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2917 n *= nr_ioapics;
2918
2919 mem = alloc_bootmem(n);
2920 res = (void *)mem;
2921
2922 if (mem != NULL) {
2923 mem += sizeof(struct resource) * nr_ioapics;
2924
2925 for (i = 0; i < nr_ioapics; i++) {
2926 res[i].name = mem;
2927 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2928 sprintf(mem, "IOAPIC %u", i);
2929 mem += IOAPIC_RESOURCE_NAME_SIZE;
2930 }
2931 }
2932
2933 ioapic_resources = res;
2934
2935 return res;
2936 }
2937
2938 void __init ioapic_init_mappings(void)
2939 {
2940 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2941 struct resource *ioapic_res;
2942 int i;
2943
2944 ioapic_res = ioapic_setup_resources();
2945 for (i = 0; i < nr_ioapics; i++) {
2946 if (smp_found_config) {
2947 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2948 } else {
2949 ioapic_phys = (unsigned long)
2950 alloc_bootmem_pages(PAGE_SIZE);
2951 ioapic_phys = __pa(ioapic_phys);
2952 }
2953 set_fixmap_nocache(idx, ioapic_phys);
2954 apic_printk(APIC_VERBOSE,
2955 "mapped IOAPIC to %016lx (%016lx)\n",
2956 __fix_to_virt(idx), ioapic_phys);
2957 idx++;
2958
2959 if (ioapic_res != NULL) {
2960 ioapic_res->start = ioapic_phys;
2961 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2962 ioapic_res++;
2963 }
2964 }
2965 }
2966
2967 static int __init ioapic_insert_resources(void)
2968 {
2969 int i;
2970 struct resource *r = ioapic_resources;
2971
2972 if (!r) {
2973 printk(KERN_ERR
2974 "IO APIC resources could be not be allocated.\n");
2975 return -1;
2976 }
2977
2978 for (i = 0; i < nr_ioapics; i++) {
2979 insert_resource(&iomem_resource, r);
2980 r++;
2981 }
2982
2983 return 0;
2984 }
2985
2986 /* Insert the IO APIC resources after PCI initialization has occured to handle
2987 * IO APICS that are mapped in on a BAR in PCI space. */
2988 late_initcall(ioapic_insert_resources);
2989
Linux kernel - Deliverables
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